Semiconductor equipment

Abstract

To provide a semiconductor device with elements arranged in such a way as to prevent the adverse effects of DTI stress.SOLUTION: Provided is a semiconductor device comprising: a first semiconductor element 301, which is an N-channel MOSFET; a second semiconductor element 302, which is an N-channel MOSFET positioned next to the first semiconductor element; a DTI 101 enclosing the first and second semiconductor elements; the first semiconductor element is connected to a first circuit and the second semiconductor element is connected to a second circuit different from the first circuit.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This disclosure relates to a semiconductor device.

Background Art

[0002] Development has been made regarding deep trench isolation. Patent Document 1 describes a semiconductor device and a method of manufacturing the same in which malfunction of a semiconductor element due to a leakage current caused by variations in oxygen concentration in a semiconductor substrate is suppressed. Patent Document 1 describes a semiconductor device in which a high breakdown voltage NMOS transistor formation region defined by an element isolation insulating film (deep trench isolation), a CMOS transistor formation region defined by the element isolation insulating film, and a substrate contact portion are formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, due to the influence of the stress of DTI (Deep Trench Isolation), the performance of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may deteriorate. Therefore, an object of this disclosure is to provide a semiconductor device in which elements are arranged so as to prevent the adverse influence of the stress of DTI.

[0005] Other problems and novel features will become apparent from the description of this specification and the attached drawings.

Means for Solving the Problems

[0006] According to one embodiment, high-performance transistors are placed away from the DTI, making effective use of the available space. [Effects of the Invention]

[0007] According to the above embodiment, a semiconductor device can be provided in which elements are arranged in a way that prevents the adverse effects of DTI stress. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic plan view of a deep trench isolation according to an embodiment. [Figure 2] This figure shows the stress of the deep trench isolation according to the embodiment and the effect of the stress on the MOS transistor. [Figure 3] This is a layout diagram of the semiconductor device according to Embodiment 1. [Figure 4] This figure shows an example of the configuration of a pair of transistors according to Embodiment 1. [Figure 5] This figure shows the method for fabricating a pair of transistors according to Embodiment 1. [Figure 6] This is a layout diagram of the semiconductor device according to Embodiment 2. [Figure 7] This is a layout diagram of the semiconductor device according to Embodiment 3. [Figure 8] This is a layout diagram of the semiconductor device according to Embodiment 4. [Figure 9] This is a layout diagram of the semiconductor device according to Embodiment 5. [Figure 10] This is a layout diagram of the semiconductor device according to Embodiment 6. [Figure 11] This is a modified arrangement of the deep trench isolation according to the embodiment. [Modes for carrying out the invention]

[0009] Embodiment For clarity of explanation, the following descriptions and drawings have been omitted and simplified as appropriate. In each drawing, the same elements are denoted by the same reference numeral, and redundant explanations have been omitted where necessary.

[0010] (Description of deep trench isolation according to the embodiment) Figure 1 is a schematic plan view of the deep trench isolation according to the embodiment. Figure 2 is a diagram showing the stress in the deep trench isolation according to the embodiment and the effect of the stress on the MOS transistor. The deep trench isolation (DTI) according to the embodiment will be explained with reference to Figures 1 and 2.

[0011] The semiconductor device according to this embodiment includes, for example, a bipolar transistor, a CMOS (CMOSFET: Complementary Metal Oxide Semiconductor Field Effect Transistor), and a DMOS (DMOSFET: Double Diffused Metal Oxide Semiconductor Field Effect Transistor) as semiconductor elements. To form this semiconductor device, the semiconductor elements are isolated from each other using DTI. In this semiconductor device, in order to achieve high breakdown voltage and suppress the effects of noise, DTI is used not only for STI (Shallow Trench Isolation) but also for element isolation of the MOSFETs.

[0012] As shown in Figure 1, the semiconductor element 102 is surrounded by a normal element isolation STI 103. Furthermore, the multiple semiconductor elements 102 and the element isolation STI 103 are surrounded by a back gate 104. Furthermore, the multiple semiconductor elements 102, the element isolation STI 103 and the back gate 104 are surrounded by a DTI 101. The DTI 101 has a first and second portion extending in a first direction 107, and a third and fourth portion extending in a second direction 108. The first direction 107 and the second direction 108 are directions along the main surface of the semiconductor substrate. The first direction 107 and the second direction 108 intersect each other. The multiple semiconductor elements 102 are arranged in the second direction 108. The channel width direction, which will be described later, is the first direction 107, and the channel length direction, which will be described later, is the second direction 108.

[0013] As shown in the DTI cross-sectional view of Figure 1, the semiconductor substrate has a P+ semiconductor substrate and a semiconductor layer formed on the P+ semiconductor substrate. A DTI 101, a semiconductor element 102, an element isolation STI 103, and a back gate 104 are formed on the semiconductor substrate. The element isolation STI 103 is formed on the surface of the semiconductor layer (P- layer) that forms the semiconductor element 102. The bottom surface of the element isolation STI 103 is formed within a groove provided in the semiconductor substrate. The DTI 101 is formed from an oxide film 106 formed on the side surface and bottom surface of the groove and a cavity 105. The DTI 101 penetrates the P- layer, NBL (N+ Buried Layer), and P- layer on the surface of the semiconductor layer to reach the P+ semiconductor substrate. If the DTI 101 functions as an element isolation, the bottom surface of the DTI 101 may be located between the NBL and the P+ semiconductor substrate.

[0014] The upper part of Figure 2 shows the stress intensity of DTI101 with respect to the distance from DTI101 in the second direction 108. As shown in the upper part of Figure 2, compressive stress acts on the semiconductor substrate in the region from 2 to 3 μm from DTI101 (A). Tensile stress acts on the semiconductor substrate in the region where the distance from DTI101 is 3 μm to 10 μm (B). In the region more than 10 μm away from DTI101 (C), the tensile stress acting on the semiconductor substrate converges.

[0015] As shown in the lower figure of FIG. 2, the semiconductor element 102 is, for example, an N-channel type MOSFET 201. The N-channel type MOSFET 201 has a gate electrode, a source region, and a drain region. The source region and the drain region are formed in a semiconductor substrate. The source region and the drain region are regions into which N-type impurities are introduced. The gate electrode is formed on the semiconductor substrate located between the source region and the drain region via a gate insulating film. As shown in FIG. 1, the gate electrode, the source region, and the drain region extend in the first direction 107. In FIG. 1, a plurality of N-channel type MOSFETs 201 are arranged side by side in the second direction 108. Therefore, as shown in FIG. 1, the DTI 101, the gate electrode, the source region, and the drain region of the N-channel type MOSFET 201 are arranged along the second direction 108. The lower figure of FIG. 2 shows an example of the compressive stress acting on the N-channel type MOSFET 201. The stress of the DTI 101 mainly acts in the second direction 108. In the N-channel type MOSFET 201, when compressive stress acts on the channel region in the channel length direction (the second direction), the current flowing through the N-channel type MOSFET 201 becomes small. Similarly, in the N-channel type MOSFET 201, when tensile stress acts on the channel region in the channel length direction (the second direction), the current flowing through the N-channel type MOSFET 201 becomes small. Therefore, placing an N-channel type MOSFET in the region where stress acts causes variations in performance or deterioration of performance.

[0016] (Description of the semiconductor device according to Embodiment 1) FIG. 3 is a plan layout diagram of the element according to Embodiment 1. FIG. 4 is a diagram showing a configuration example of the pair transistor according to Embodiment 1. FIG. 5 is a diagram showing a manufacturing method of the pair transistor according to Embodiment 1. The semiconductor device according to Embodiment 1 will be described while referring to FIGS. 3 to 5.

[0017] As shown in Figure 3, the semiconductor device 300 according to Embodiment 1 comprises a first semiconductor element 301 of an N-channel MOSFET formed on a semiconductor substrate, and a second semiconductor element 302 of an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element 301. Furthermore, the semiconductor device 300 comprises a DTI 101 formed on the semiconductor substrate that surrounds the first semiconductor element 301 and the second semiconductor element 302 in a plan view.

[0018] The first semiconductor element 301 and the second semiconductor element 302 may each consist of one or more elements. The first semiconductor element 301 and the second semiconductor element 302 are arranged in parallel in the channel length direction. As shown in Figure 3, the DTI 101 closest to the second semiconductor element 302 in the second direction 108 extends in the first direction 107. In the second direction 108 along the main surface of the semiconductor substrate, the second semiconductor element 302 is positioned between the first semiconductor element 301 and the DTI 101. The DTI 101, the first gate electrode, first source region and first drain region of the first semiconductor element 301, and the second gate electrode, second source region and second drain region of the second semiconductor element 302 are arranged along the second direction 108. The first semiconductor element 301 is located at least 10 μm away from the nearest DTI 101 in the channel length direction. The second semiconductor element 302 is located within 10 μm of the nearest DTI in the channel length direction. Therefore, the first semiconductor element 301 is formed in a region that is not affected by the stress of DTI 101. The second semiconductor element 302 is formed in a region that is affected by the stress of DTI 101.

[0019] The second semiconductor element 302 has inferior electrical characteristics because it is affected by the stress of DTI 101. However, the first semiconductor element 301 is connected to the first circuit, and the second semiconductor element 302 is connected to a second circuit that is different from the first circuit. The first circuit and the second circuit are not directly connected. Therefore, the electrical characteristics of the second semiconductor element 302 do not affect the electrical characteristics of the first semiconductor element 301.

[0020] Furthermore, the first semiconductor element 301 has a first accuracy, and the second semiconductor element 302 has a second accuracy. Since the first semiconductor element 301 is not affected by the stress of DTI 101, its first accuracy is higher than its second accuracy. The first accuracy is, for example, a relative accuracy of 1% or less. The second accuracy is, for example, a relative accuracy of greater than 1%. Relative accuracy refers to the ratio of the current value of the target MOFET to the MOSFET furthest from DTI 101 in the second direction 108. The MOSFET furthest from DTI 101 in the second direction 108 is the MOSFET located in the center of the multiple MOSFETs lined up in the second direction 108 if the number of MOSFETs enclosed by DTI 101 is odd. The MOSFET furthest from DTI 101 in the second direction 108 is one of the two MOSFETs closest to the center of the multiple MOSFETs lined up in the second direction 108 if the number of MOSFETs enclosed by DTI 101 is even.

[0021] Analog circuits handle analog signals. Analog signals, whose values ​​are used directly, are more susceptible to noise than digital signals. Therefore, the first circuit, which uses high-precision semiconductor elements, can be used in analog circuits where high precision is required. On the other hand, digital circuits handle digital signals. Digital signals only need to be determined as either 0 or 1, so they are less susceptible to noise than analog signals. The second circuit, which is connected with low-precision semiconductor elements, has high noise and cannot be used in analog circuits; it is preferable to use it in digital circuits.

[0022] Furthermore, the highly accurate first semiconductor element 301 can form a pair of transistors. The first circuit described above can be constructed from pair of transistors. On the other hand, the less accurate second semiconductor element 302 cannot form a pair of transistors. Therefore, the second circuit described above is constructed from transistors different from pair of transistors. As shown in Figure 4, examples of paired transistors include gate-shared (I), drain-shared (II), source-shared (III), and drain and source-shared (IV).

[0023] As shown in Figure 5, the paired transistors are fabricated as follows. First, as shown in DTI etching, a MOSFET 503 is formed on the semiconductor substrate, and then a trench 501 for DTI and a trench 502 for the substrate contact electrodes are formed.

[0024] Next, an oxide film 504 is formed in the trench 501 for the DTI and the trench 502 for the substrate contact electrodes, and DTI is formed within the trench 502. The DTI electrically isolates the MOSFET 503 from other elements. Next, after contact holes are formed in the trench 502 for the substrate contact electrodes and the MOSFET 503, a metal or N-type semiconductor is embedded in the trench 502. This forms the substrate contact electrode 505 and the source / drain contact electrode 506 of the MOSFET within each trench 502. The metal can be tungsten, molybdenum, etc. The N-type semiconductor can be N-type polysilicon doped with phosphorus or arsenic.

[0025] Finally, a pair of transistors 507 is formed by creating wiring that connects adjacent MOSFETs 503 to each other.

[0026] In this way, the first semiconductor element 301 that constitutes a pair transistor can be formed.

[0027] (Description of the semiconductor device according to Embodiment 2) Figure 6 is a layout diagram of the semiconductor device according to Embodiment 2. The semiconductor device according to Embodiment 2 will be described with reference to Figure 6.

[0028] The semiconductor device 600 according to Embodiment 2 efficiently arranges high-precision semiconductor elements. As shown in Figure 6, the semiconductor device 600 comprises a semiconductor substrate, a first semiconductor element 301 which is an N-channel MOSFET formed on the semiconductor substrate, and a second semiconductor element 601 which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element 301. The semiconductor device 600 also comprises a DTI 101 formed on the semiconductor substrate that surrounds the first semiconductor element 301 and the second semiconductor element 601 in a plan view.

[0029] The first semiconductor element 301 and the second semiconductor element 601 may each consist of one or more elements. The second semiconductor element 601 is positioned such that its channel length direction is perpendicular to that of the first semiconductor element 301. The channel length direction of the second semiconductor element 601 is the direction in which the DTI 101 closest to the second semiconductor element 601 extends. That is, as shown in Figure 6, the DTI 101 closest to the second semiconductor element 601 in the second direction 108 extends in the first direction 107. In the second direction 108 along the main surface of the semiconductor substrate, the second semiconductor element 601 is positioned between the first semiconductor element 301 and the DTI 101. The first semiconductor element 301 is located at least 10 μm away from the nearest DTI 101 in the channel length direction. The second semiconductor element 601 is located at least 10 μm away from the nearest DTI in the channel length direction. Therefore, the first semiconductor element 301 and the second semiconductor element 601 are formed in regions that are not affected by the stress of DTI 101.

[0030] The second semiconductor element 601 is not affected by the stress of DTI101 and therefore does not have inferior electrical characteristics. Furthermore, the first semiconductor element 301 and the second semiconductor element 601 have a first level of accuracy. This first level of accuracy is, for example, a relative accuracy of 1% or less.

[0031] Such first semiconductor element 301 and second semiconductor element 601 are preferably used in analog circuits. Furthermore, the first semiconductor element 301 and second semiconductor element 601, which have high precision, can form a pair of transistors.

[0032] The second semiconductor element 601 is formed in a region affected by stress when viewed from the first semiconductor element 301, but by devising its arrangement, it can be made so as not to be affected by the stress of DTI101. Therefore, many high-precision semiconductor elements can be arranged.

[0033] (Description of the semiconductor device according to Embodiment 3) Figure 7 is a layout diagram of the semiconductor device according to Embodiment 3. The semiconductor device according to Embodiment 3 will be described with reference to Figure 7.

[0034] The semiconductor device 700 according to Embodiment 3 arranges elements other than an N-channel MOSFET, such as a resistive element, in a region affected by stress. As shown in Figure 7, the semiconductor device 700 comprises a semiconductor substrate, a first semiconductor element 301 which is an N-channel MOSFET formed on the semiconductor substrate, and a resistive element 701 formed on the semiconductor substrate and arranged next to the first semiconductor element 301. The semiconductor device 700 also comprises a DTI 101 formed on the semiconductor substrate that surrounds the first semiconductor element 301 and the resistive element 701 in a plan view.

[0035] The first semiconductor element 301 may be one or more. As shown in Figure 7, the DTI 101 closest to the resistive element 701 in the second direction 108 extends in the first direction 107. In the second direction 108 along the main surface of the semiconductor substrate, the resistive element 701 is positioned between the first semiconductor element 301 and the DTI 101. The first semiconductor element 301 is located at least 10 μm away from the nearest DTI 101 in the channel length direction. The resistive element 701 is formed within 10 μm of the nearest DTI 101 in the channel length direction of the first semiconductor element 301. Therefore, the first semiconductor element 301 is formed in a region that is not affected by the stress of the DTI 101. Also, the resistive element 701 is formed in a region that is affected by the stress of the DTI 101.

[0036] The resistive element 701 is formed in the same layer as the gate electrode of the first semiconductor element 301. Therefore, the resistive element 701 is not affected by the stress applied to the semiconductor layer. Consequently, the semiconductor device 700 can effectively utilize regions where a high-precision N-channel MOSFET cannot be formed.

[0037] (Description of the semiconductor device according to Embodiment 4) Figure 8 is a layout diagram of the semiconductor device according to Embodiment 4. The semiconductor device according to Embodiment 4 will be described with reference to Figure 8.

[0038] The semiconductor device 800 according to Embodiment 4 efficiently arranges high-precision semiconductor elements and places elements other than transistors, such as resistive elements, in areas affected by stress. As shown in Figure 8, the semiconductor device 800 comprises a semiconductor substrate, a first semiconductor element 301 which is an N-channel MOSFET formed on the semiconductor substrate, a second semiconductor element 601 which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element 301, and a resistive element 801 which is formed on the semiconductor substrate and positioned next to the first semiconductor element 301. The semiconductor device 800 also comprises a DTI 101 formed on the semiconductor substrate that surrounds the first semiconductor element 301, the second semiconductor element 601, and the resistive element 801 in a plan view.

[0039] The first semiconductor element 301 and the second semiconductor element 601 are the same as in Embodiment 2, so their description is omitted. The effect of arranging the second semiconductor element 601 is also the same as in Embodiment 2. Furthermore, the resistive element 801 is arranged next to the second semiconductor element 601 in the channel length direction (first direction 107) of the second semiconductor element 601. As shown in Figure 8, the DTI 101 closest to the second semiconductor element 601 in the first direction 107 extends in the second direction 108. Also, in the first direction 107 along the main surface of the semiconductor substrate, the resistive element 801 is arranged between the second semiconductor element 601 and the DTI 101. The resistive element 801 is arranged within 10 μm of the nearest DTI 101 in the channel length direction (first direction 107) of the second semiconductor element 601. For this reason, the resistive element 801 is formed in a region affected by the stress of the DTI 101.

[0040] The resistive element 801 is formed in the same layer as the gate electrodes of the first semiconductor element 301 and the second semiconductor element 601. Therefore, the resistive element 801 is not affected by the stress applied to the semiconductor layer. Consequently, the semiconductor device 800 can effectively utilize regions where a high-precision N-channel MOSFET cannot be formed. In other words, Embodiment 3 can be combined with Embodiment 2.

[0041] (Description of the semiconductor device according to Embodiment 5) Figure 9 is a layout diagram of the semiconductor device according to Embodiment 5. The semiconductor device according to Embodiment 5 will be described with reference to Figure 9.

[0042] The semiconductor device 900 according to Embodiment 5 has a P-channel MOSFET placed in a region affected by stress. The upper part of Figure 9 shows the variation in stress and the electrical characteristics of the P-channel MOSFET with respect to the distance from the DTI in the second direction 108. As shown in the upper part of Figure 9, the change in the electrical characteristics of the P-channel MOSFET is small with respect to the distance from the DTI 101. The variation in the electrical characteristics of the P-channel MOSFET is within 0.2% even in a region where the compressive stress is large in the channel length direction. Therefore, even if the P-channel MOSFET is placed in a region with large stress variations within 10 μm from the DTI 101, a high-precision semiconductor device 900 can be obtained.

[0043] As shown in the lower part of Figure 9, the semiconductor device 900 according to Embodiment 5 comprises a semiconductor substrate, a first semiconductor element 301 which is an N-channel type MOSFET formed on the semiconductor substrate, and a second semiconductor element 901 which is a P-channel type MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element 301. Furthermore, the semiconductor device 900 comprises a DTI 101 formed on the semiconductor substrate that surrounds the first semiconductor element 301 and the second semiconductor element 901 in a plan view.

[0044] A P-channel MOSFET has a gate electrode, a source region, and a drain region. The source region and drain region are formed within a semiconductor substrate. The source region and drain region are regions into which P-type impurities are introduced. The gate electrode is formed on the semiconductor substrate located between the source region and the drain region, via a gate insulating film. As shown in Figure 9, the gate electrode, source region, and drain region extend in the first direction 107. In Figure 9, multiple P-channel MOSFETs are aligned in the second direction 108. Therefore, as shown in Figure 9, the DTI 101, the gate electrode, source region, and drain region of the P-channel MOSFET are arranged along the second direction 108. Thus, the stress on DTI 101 acts mainly in the second direction 108.

[0045] The first semiconductor element 301 and the second semiconductor element 901 may each consist of one or more elements. The first semiconductor element 301 and the second semiconductor element 901 are arranged in parallel with their channel lengths aligned. As shown in Figure 9, the DTI 101 closest to the second semiconductor element 901 in the second direction 108 extends in the first direction 107. In the second direction 108 along the main surface of the semiconductor substrate, the second semiconductor element 901 is positioned between the first semiconductor element 301 and the DTI 101. The first semiconductor element 301 is located at least 10 μm away from its nearest DTI 101 in the channel length direction. The second semiconductor element 901 is located within 10 μm of its nearest DTI in the channel length direction. Therefore, the first semiconductor element 301 is formed in a region unaffected by the stress of the DTI 101. The second semiconductor element 901 is formed in the region of DTI101 that is affected by stress.

[0046] Even if the second semiconductor element 901 is formed in a region affected by the stress of DTI 101, the change in the electrical characteristics of the second semiconductor element 901 with respect to the distance from DTI 101 is small, making it possible to obtain a highly accurate semiconductor device 900.

[0047] (Description of the semiconductor device according to Embodiment 6) Figure 10 is a layout diagram of the semiconductor device according to Embodiment 6. The semiconductor device according to Embodiment 6 will be described with reference to Figure 10.

[0048] In the semiconductor device 1000 according to Embodiment 6, a P-channel MOSFET and a substrate contact electrode 1001 are provided. The substrate contact electrode 1001 is arranged in parallel with the P-channel MOSFET. Since the substrate contact electrode 1001 generates strong compressive stress, the semiconductor device 1000 according to Embodiment 6 can improve the electrical characteristics of the P-channel MOSFET. As shown in the upper left cross-sectional view of Figure 10, the substrate contact electrode 1001 is formed by filling the cavity of the DTI with a conductive material. Stress is generated in the substrate contact electrode 1001 due to the conductive material formed in the trench, so its compressive stress is stronger than that of the DTI. The upper right view of Figure 10 shows the stress with respect to distance from the DTI and the variation in the electrical characteristics of the P-channel MOSFET. As shown in the upper right view of Figure 10, in a P-channel MOSFET, the current driving capability is improved when compressive stress is applied in the direction of its channel length. Therefore, in the semiconductor device 1000, the P-channel MOSFET is arranged in parallel with the substrate contact electrode 1001 to improve the electrical characteristics of the P-channel MOSFET.

[0049] The semiconductor device 1000 according to Embodiment 6 comprises a semiconductor substrate, a first semiconductor element 1002 formed on the semiconductor substrate and being a P-channel type MOSFET, and a DTI 101 formed on the semiconductor substrate and surrounding the first semiconductor element 1002 in a plan view. As shown in Figure 10, the gate electrode, source region, and drain region of the first semiconductor element 1002 extend in the first direction 107. In Figure 10, the multiple P-channel type MOSFETs are arranged in the second direction 108. The semiconductor device 1000 also comprises a substrate contact electrode 1001 arranged parallel to the channel width direction of the first semiconductor element 1002 in the first direction 107. The length of the first direction 107 parallel to the channel width direction of the first semiconductor element 1002 in the substrate contact electrode 1001 is longer than the channel width of the first semiconductor element 1002. Therefore, the stress on the substrate contact electrode 1001 acts mainly in the second direction 108.

[0050] The first semiconductor element 1002 may be one or more. As shown in the upper left cross-sectional view of Figure 10, the substrate contact electrode 1001 undergoes part of the same formation process as the DTI 101, and therefore penetrates the P- layer, NBL (N+ Buried Layer), and P- layer on the semiconductor layer surface to reach the P+ semiconductor substrate. By making the length of the substrate contact electrode 1001 in the direction parallel to the channel width direction of the first semiconductor element 1002 longer than the channel width of the first semiconductor element 1002, stress can be applied to the entire channel formation region of the first semiconductor element 1002. The channel width of the first semiconductor element 1002 is between 0.4 μm and 100 μm. The distance from the substrate contact electrode 1001 to the first semiconductor element 1002 is preferably 5 to 6 μm.

[0051] The semiconductor device 1000 can be composed of high-performance P-channel MOSFETs.

[0052] (Description of variations in the arrangement of the deep trench isolation according to the embodiment) Figure 11 shows a modified configuration of the deep trench isolation according to the embodiment. A modified configuration of the deep trench isolation according to the embodiment will be described with reference to Figure 11.

[0053] As shown in Figure 11, in a modified arrangement of DTI1101 according to the embodiment, the planar shape of DTI1101 in plan view is rectangular. DTI101 had a rectangular shape with chamfered corners in plan view. DTI1101 has a rectangular shape with corners remaining in plan view.

[0054] Even in such cases, a region 1102 where DTI stress is applied is formed. Region 1102 is a region within 10 μm of DTI 1101 in the second direction 108, which is the channel length direction of the first semiconductor element 301. Therefore, the second semiconductor element 302, the second semiconductor element 601, the first semiconductor element 1002, the resistor element 701, or the resistor element 801 shown in embodiments 1 to 6 can be placed in region 1102. In that case, the same effects as those described in each embodiment can be obtained.

[0055] The present invention has been described in detail above based on embodiments, but it goes without saying that the present invention is not limited to the embodiments already described, and various modifications are possible without departing from the spirit of the invention. [Explanation of Symbols]

[0056] 101 DTI, 102 Semiconductor element, 103 Element isolation STI, 104 Back gate, 105 Cavity, 106 Oxide film, 107 First direction, 108 Second direction, 201 N-channel MOSFET, 300 Semiconductor device, 301 First semiconductor element, 302 Second semiconductor element, 501 Trench for DTI, 502 Trench for substrate contact electrode, 503 MOSFET, 504 Oxide film, 505 Substrate contact electrode, 506 Source-drain contact electrode, 507 Paired transistor, 600 Semiconductor device, 601 Second semiconductor element, 700 Semiconductor device, 701 Resistor element, 800 Semiconductor device, 801 Resistor element, 900 Semiconductor device, 901 Second semiconductor element, 1000 Semiconductor device, 1001 Substrate contact electrode, 1002 First semiconductor element, 1101 DTI, 1102 Region

Claims

1. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A second semiconductor element, which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element, The semiconductor substrate comprises a deep trench isolation formed thereon, which surrounds the first semiconductor element and the second semiconductor element in a plan view, The first semiconductor element is connected to the first circuit, The second semiconductor element is connected to a second circuit different from the first circuit. The first circuit has a first accuracy, The second circuit has a second accuracy, A semiconductor device wherein the first accuracy is higher than the second accuracy.

2. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A second semiconductor element, which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element, The semiconductor substrate comprises a deep trench isolation formed thereon, which surrounds the first semiconductor element and the second semiconductor element in a plan view, The first semiconductor element is connected to the first circuit, The second semiconductor element is connected to a second circuit different from the first circuit. The first circuit is an analog circuit, The second circuit is a digital circuit, a semiconductor device.

3. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A second semiconductor element, which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element, The semiconductor substrate comprises a deep trench isolation formed thereon, which surrounds the first semiconductor element and the second semiconductor element in a plan view, The first semiconductor element is connected to the first circuit, The second semiconductor element is connected to a second circuit different from the first circuit. The first circuit described above is composed of a pair of transistors, The second circuit is a semiconductor device composed of transistors different from the paired transistors.

4. In a first direction along the main surface of the semiconductor substrate, the second semiconductor element is positioned between the first semiconductor element and the deep trench isolation. The first semiconductor device is A first gate electrode extending along the main surface of the semiconductor substrate and in a second direction intersecting the first direction, The first source area and, The first drain region and It has, The second semiconductor element is The second gate electrode extending in the second direction, The second source area and, The second drain region and It has, The deep trench isolation extends in the first direction, The semiconductor device according to claim 1, wherein the deep trench isolation, the first gate electrode, the first source region, the first drain region, the second gate electrode, the second source region, and the second drain region are arranged along the second direction.

5. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A second semiconductor element, which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element, The semiconductor substrate comprises a deep trench isolation formed thereon, which surrounds the first semiconductor element and the second semiconductor element in a plan view, The second semiconductor element is arranged such that its channel length direction is perpendicular to that of the first semiconductor element. A semiconductor device wherein the channel length direction of the second semiconductor element is the direction in which the deep trench isolation closest to the second semiconductor element extends.

6. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A resistive element formed on the semiconductor substrate and positioned next to the first semiconductor element, A semiconductor device comprising a deep trench isolation formed on the semiconductor substrate, which surrounds the first semiconductor element and the resistive element in a plan view.

7. Semiconductor substrate and A first semiconductor element, which is an N-channel type MOSFET, is formed on the aforementioned semiconductor substrate. A second semiconductor element, which is an N-channel MOSFET formed on the semiconductor substrate and positioned next to the first semiconductor element, A resistive element formed on the semiconductor substrate and positioned next to the first semiconductor element, The semiconductor substrate is formed and comprises a deep trench isolation that surrounds the first semiconductor element, the second semiconductor element, and the resistive element in a plan view, The second semiconductor element is arranged such that its channel length direction is perpendicular to that of the first semiconductor element. The channel length direction of the second semiconductor element is the direction in which the deep trench isolation closest to the second semiconductor element extends. The resistive element is a semiconductor device in which the resistive element is arranged adjacent to the second semiconductor element in the channel length direction of the second semiconductor element.

8. The semiconductor device according to any one of claims 1 to 7, wherein, in a plan view, the planar shape of the deep trench isolation is rectangular.

9. The semiconductor device according to claim 1, 5, 6, or 7, wherein the first semiconductor element is located at a distance of 10 μm or more from the deep trench isolation.

10. The semiconductor device according to claim 1, 5, 6, or 7, wherein the first semiconductor element is formed in a region where compressive stress is not applied due to the deep trench isolation.

11. The semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device comprises a bipolar transistor, a CMOS, and a DMOS.

12. The semiconductor device according to any one of claims 1 to 7, wherein the deep trench isolation is formed in a trench that extends from the surface of the semiconductor layer to the semiconductor substrate.

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