Semiconductor device, and method for manufacturing a semiconductor device.

Abstract

The present invention suppresses a decline in the reliability of an insulated gate-type semiconductor device (100) which has a trench structure. A semiconductor device which is equipped with a source electrode (11) which is electrically connected to a source region adjacent to a trench (6) in a first region, and gate wiring (18) provided on the top surface of a gate electrode (8) provided inside a trench in a second region, wherein the radius of curvature (Re) of a gate insulated film provided in an upper corner section of the trench in the second region is greater than the radius of curvature (Rc) of a gate insulated film provided in an upper corner section of the trench in the first region.

Description

[Technical Field]

[0001] The technology disclosed in this specification relates to semiconductor technology. [Background technology]

[0002] In power electronics equipment, insulated-gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors) are widely used as switching elements to control the power supply to loads such as motors.

[0003] Some of these insulated-gate semiconductor devices have a trench structure in which the gate electrode is embedded in the semiconductor layer. Compared to insulated-gate semiconductor devices without a trench structure (planar type semiconductor devices) where the gate electrode is formed on the surface of the semiconductor layer, insulated-gate semiconductor devices with a trench structure can have a higher channel width density in the active region. Therefore, the electrical resistance per unit area can be lowered when the semiconductor device is in the ON state.

[0004] Conventionally, in insulated gate semiconductor devices with a trench structure, gate electrodes and gate insulating films are formed in the termination region surrounding the active region, specifically inside the trench opening on the active region side and around the upper corners. In this case, when a gate voltage is applied and the semiconductor device turns on, an electric field concentrates at the bottom of the trench and around the upper corners, causing insulation degradation of the gate insulating film at the bottom of the trench and around the upper corners. As a result, the reliability of the semiconductor device may decrease.

[0005] To solve this problem, a method is known in which a conductive electric field relaxation region is provided at the bottom of the trench to relax the electric field applied to the gate insulating film at the bottom of the trench (see, for example, Patent Document 1).

[0006] Furthermore, a method is known in which a structure is formed having a narrow, deep trench in the active region and a wide, shallow trench in the terminal region, and then, during a subsequent CMP (Chemical Mechanical Polishing) process, or a combination of the CMP process and the etch-back process, the gate electrodes formed in the trenches of the active and terminal regions are flattened so that the upper corners of the trenches are not covered by the gate electrodes (see, for example, Patent Document 2). [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Special table 2001-511315 publication [Patent Document 2] Special table 2006-520091 publication [Overview of the project] [Problems that the invention aims to solve]

[0008] As a method for setting the potential of the gate electrode, it is necessary to provide a gate contact (contact hole) to the gate electrode formed in the gate trench within the cell array. Since the gate trench of the cell array is formed with the minimum processing dimensions, there is a concern about misalignment with the contact mask. Therefore, to avoid providing a gate contact within the cell, the gate contact may be set on the upper surface of the polysilicon in the wider trench at the terminal region.

[0009] Even in such cases, it is impossible to avoid the upper corners of the trench being covered with polysilicon. As a result, the electric field concentrates on the gate insulating film at the polysilicon-covered upper corners of the trench, causing insulation degradation of the gate insulating film and reducing the reliability of the semiconductor device.

[0010] On the other hand, in the method of providing an electric field relaxation region at the bottom of the trench, it may not be possible to suppress insulation degradation around the upper corner of the trench. Further, in the method using a CMP process, it is necessary to minimize the influence of warping of the semiconductor substrate, unevenness on the substrate surface, in-plane thickness uniformity of the film formed on the semiconductor substrate, or unevenness of the film due to the influence of particles or the like, and it is difficult to adopt in reality.

[0011] Furthermore, when forming a wide trench in the termination region and continuously depositing the gate insulating film and the gate electrode, the exposed area of the gate electrode increases in the subsequent etch-back process, the gate electrode may be etched and its thickness may become thin, or the gate electrode may disappear. Therefore, the operation of the insulated gate semiconductor device may become unstable (the reliability of the semiconductor device may decrease). Also, it may not be possible to suppress insulation degradation around the upper corner of the trench.

[0012] The technology disclosed in the present specification has been made in view of the problems described above, and is a technology for suppressing a decrease in the reliability of a semiconductor device in an insulated gate semiconductor device having a trench structure.

Means for Solving the Problems

[0013] The semiconductor device according to the first aspect of the technology disclosed in the present specification includes a drift layer of a first conductivity type, a base region of a second conductivity type provided on the surface layer of the drift layer, a plurality of source regions of the first conductivity type provided on the surface layer of the base region, at least one trench reaching from the upper surface of the drift layer to the inside of the drift layer through the base region, a protection layer of the second conductivity type provided in the drift layer below the trench, a gate insulating film provided along the inside of the trench including the upper corner portion of the trench, a gate electrode provided in at least the trench surrounded by the gate insulating film, a source electrode electrically connected to the source region adjacent to the trench, and a gate wiring provided on the upper surface of the gate electrode provided in the trench. Among the regions partitioned in the plan view of the trench, the region where the source electrode is provided is defined as a first region, the region where the gate wiring is provided is defined as a second region, and the radius of curvature of the gate insulating film provided at the upper corner portion of the trench in the second region is larger than the radius of curvature of the gate insulating film provided at the upper corner portion of the trench in the first region.

Advantages of the Invention

[0014] According to at least the first aspect of the technology disclosed in the present specification, since the electric field concentration is suppressed even when a gate voltage is applied, the breakdown of the gate insulating film is suppressed.

[0015] In addition, the objects, features, aspects, and advantages related to the technology disclosed in the present specification will become more apparent from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0016] [Figure 1] It is a plan view schematically showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 2] It is a cross-sectional view showing a part of the configuration of a semiconductor device according to an embodiment. [Figure 3] It is a cross-sectional view showing a part of the configuration of a semiconductor device according to an embodiment. [Figure 4] This is a plan view showing a part of the configuration of a semiconductor device according to an embodiment. [Figure 5] This is a cross-sectional view showing an example of the configuration of the cell section in the figure. [Figure 6] Figure 3 is a cross-sectional view showing an example of the configuration of the gate contact portion in the active region 20. [Figure 7] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 9] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 10] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 11] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 12] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 13] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 14] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 15] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 16] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 17] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 18] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 19] This is a schematic plan view showing an example of the configuration of a semiconductor device according to this embodiment. [Figure 20] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 21] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 22] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 23] This is a schematic plan view showing an example of the configuration of a semiconductor device according to this embodiment. [Figure 24] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 25] This figure shows an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 26] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 27] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 28] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 29] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Figure 30] This is a schematic cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. [Modes for carrying out the invention]

[0017] The embodiments will be described below with reference to the attached drawings. In the following embodiments, detailed features will be shown for the purpose of explaining the technology, but these are illustrative, and not all of them are necessarily essential features for the embodiments to be implementable.

[0018] Please note that the drawings are for illustrative purposes only, and for the sake of clarity, some components may be omitted or simplified as appropriate. Furthermore, the relative sizes and positions of components shown in different drawings are not necessarily accurately represented and may be modified as appropriate. In addition, hatching may be used in drawings other than cross-sectional views, such as plan views, to facilitate understanding of the embodiment.

[0019] Furthermore, in the following explanations, similar components will be denoted by the same symbols, and their names and functions will also be the same. Therefore, detailed explanations of them may be omitted to avoid redundancy.

[0020] Furthermore, in the descriptions contained in this specification, when a certain component is described as "equipped with," "includes," or "has," unless otherwise specified, it is not an exclusive expression that excludes the existence of other components.

[0021] Furthermore, even if ordinal numbers such as "first" or "second" are used in the descriptions contained herein, these terms are used for convenience to facilitate understanding of the embodiments, and the contents of the embodiments are not limited to the order that may result from these ordinal numbers.

[0022] Furthermore, even if terms such as "top," "bottom," "left," "right," "side," "bottom," "front," or "back" are used in the descriptions of this specification to indicate a specific position or direction, these terms are used for convenience to facilitate understanding of the embodiments and are not related to the actual position or direction in which the embodiments are carried out.

[0023] Furthermore, in the descriptions contained herein, when a "top surface of..." or "bottom surface of..." is used, it includes not only the top surface or bottom surface of the component in question itself, but also the state in which other components are formed on the top surface or bottom surface of the component in question. That is, for example, when it is stated that "B is provided on the top surface of A", this does not preclude the presence of another component "C" between A and B.

[0024] <First Embodiment> The semiconductor device and the method for manufacturing the semiconductor device according to this embodiment will be described below. Note that, for the sake of brevity, details of the semiconductor layer and electrodes may be omitted in the drawings.

[0025] <About the configuration of semiconductor devices> Figure 1 is a schematic plan view showing an example of the configuration of a semiconductor device 100 according to this embodiment. As shown in the example in Figure 1, the semiconductor device 100 comprises an active region 20 and a termination region 30.

[0026] The active region 20 has multiple gate trenches 6 arranged in a plan view. The terminal region 30 has a terminal trench 16 and gate wiring 18 formed overlapping the terminal trench 16 in a plan view. In addition, a gate trench 26 is formed in the inner portion of the terminal region 30.

[0027] The active region 20 is located in the central part of the semiconductor device 100. The active region 20 is a region in which current flows through the semiconductor device 100 when a voltage is applied to the gate trenches 6 formed in a stripe pattern within the active region 20.

[0028] When the semiconductor device 100 is in the ON state, applying a positive voltage to the gate trench 6 induces electrons at the interface between the gate insulating film and the semiconductor layer, causing a current to flow.

[0029] The termination region 30 is formed around the active region 20 in a plan view. The termination region 30 includes a termination trench 16, a gate insulating film 17, a gate electrode 8, gate wiring 18, and a guard ring for electric field relaxation. The termination trench 16 is a trench provided in the termination region 30.

[0030] In this embodiment, the first conductivity type is described as n-type and the second conductivity type as p-type, but a semiconductor device may also be one in which the first conductivity type is p-type and the second conductivity type is n-type.

[0031] Furthermore, although this embodiment describes the case where the semiconductor device is a MOSFET, the semiconductor device may also be an IGBT. Also, although this embodiment describes the case where the drift layer included in the semiconductor layer is formed of silicon carbide (SiC), the drift layer may also be a wide-bandgap semiconductor with a larger bandgap compared to silicon, such as gallium nitride (GaN) or diamond.

[0032] In Figure 1, the semiconductor layer of the semiconductor device 100 has a gate trench 6 formed in the active region 20, and a gate trench 26 and a termination trench 16 formed in the termination region 30. The termination trench 16 surrounds the gate trench 6 and the gate trench 26 in a plan view and is formed at a distance from the gate trench 6 and the gate trench 26.

[0033] As shown in Figure 1, the gate trenches 6 are formed in a striped pattern in a plan view. Multiple cells (cell portions) are formed in each region partitioned by the gate trenches 6 within the active region 20, and these cells function as MOSFETs.

[0034] Figures 2 and 3 are cross-sectional views showing part of the configuration of a semiconductor device according to this embodiment. Figure 4 is a plan view showing part of the configuration of a semiconductor device according to this embodiment. The configurations shown in Figures 2, 3, and 4 correspond to the area 1000 enclosed by the dashed line in Figure 1. Also, the cross-section shown in Figure 2 corresponds to the A-A' cross-section shown in Figure 4. Similarly, the cross-section shown in Figure 3 corresponds to the B-B' cross-section shown in Figure 4.

[0035] As illustrated in Figures 2 and 3, the semiconductor device 100, which is a MOSFET, comprises an n-type silicon carbide semiconductor substrate 1 and a semiconductor layer 2 formed on the upper surface of the silicon carbide semiconductor substrate 1 by epitaxial growth. The semiconductor device 100 also includes a drain electrode 12 on the lower surface of the silicon carbide semiconductor substrate 1.

[0036] In the active region 20 of the semiconductor layer 2, there are formed a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided on the surface layer of the drift layer 3, an n-type source region 5 selectively provided on the surface layer of the base region 4, a gate trench 6 formed to penetrate through the source region 5 and the base region 4 and have a bottom surface located within the drift layer 3, and a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 6.

[0037] On the other hand, in the termination region 30 of the semiconductor layer 2, there are formed a drift layer 3 made of an n-type silicon carbide semiconductor, a p-type base region 4 provided on the surface layer of the drift layer 3, a gate trench 26 and a termination trench 16 formed such that the bottom surface is deeper than the base region 4 and located within the n-type drift layer 3, a p-type diffusion protection layer 9 provided below the bottom surface of the gate trench 26, and a p-type termination protection layer 19 provided below the bottom surface of the termination trench 16.

[0038] When the semiconductor device 100 is an IGBT, the conductivity type of the silicon carbide semiconductor substrate 1 may be p-type.

[0039] Here, the n-type impurity concentration of the drift layer 3 is, for example, 1×10 14 cm -3 or more and 1×10 17 cm -3 or less, and the thickness of the drift layer 3 may be, for example, 5 μm or more and 200 μm or less.

[0040] Also, the p-type impurity concentration of the base region 4 is, for example, 1×10 17 cm -3 or more and 1×10 20 cm -3 or less.

[0041] Also, the n-type impurity concentration of the source region 5 is not less than the p-type impurity concentration of the base region 4 and 1×10 21 cm -3 or less.

[0042] Furthermore, the p-type impurity concentration in the diffusion protection layer 9 and the p-type impurity concentration in the termination protection layer 19 are, for example, 1 × 10⁻⁶. 17 cm -3 The above, and 1 × 10 19 cm -3 The following is possible: The p-type impurity concentration of the diffusion protective layer 9 is preferably the same as, or greater than or equal to, the p-type impurity concentration of the termination protective layer 19.

[0043] Furthermore, as illustrated in Figures 2 and 3, gate insulating films 7 are formed on the sides and bottom of the gate trench 6, and a gate electrode 8 made of polysilicon is embedded within the gate trench 6 via the gate insulating film 7. However, in Figure 3, the gate insulating film 7 and gate electrode 8 within the gate trench 6, which overlap with the gate wiring 18 in a plan view, extend to the upper surface of the semiconductor layer 2 (the upper surface of the semiconductor layer 2 where the base region 4 or source region 5 is formed).

[0044] Similarly, gate insulating films 7 of the same thickness as those in gate trench 6 are formed on the sides and bottom of gate trench 26, and gate electrodes 8 made of polysilicon are embedded in gate trench 26 via the gate insulating films 7. The gate electrodes 8 in gate trench 26 are formed up to the upper surface of semiconductor layer 2. Gate wiring 18 is provided across the upper surfaces of the gate electrodes 8 provided in multiple gate trenches 6.

[0045] A gate electrode 8 is formed on the polysilicon that has been stretched to the upper surface of the semiconductor layer 2, via a contact hole (gate contact 34). The gate electrode 8 is stretched to the bonding pad for wire bonding connection during chip assembly.

[0046] As illustrated in Figures 2, 3, and 4, an electrically non-functional gate trench 26 is formed at the boundary between the terminal region 30 and the active region 20.

[0047] In the terminal region 30, a terminal trench 16 is formed, which is wider than the gate trenches 6 and 26. The bottom and sides of the terminal trench 16 are coated with a gate insulating film 7 of the same thickness as the gate insulating film 7 in the gate trench 6. An interlayer insulating film 13 (oxide film) is deposited in a portion of the terminal trench 16. A gate electrode 8 is formed in another portion of the terminal trench 16.

[0048] Furthermore, a gate electrode 8 is formed in the gate trench 6 of the cell portion. Polysilicon (gate electrode 8) is also deposited in the gate trench 26 at the boundary between the terminal region 30 and the active region 20.

[0049] Furthermore, the interlayer insulating film 13 is formed to cover the upper surface of the semiconductor layer 2, which includes the gate electrode 8. Then, gate wiring 18 is formed so as to contact the gate electrode 8, which is exposed through a gate contact 34, which is an opening formed in the interlayer insulating film 13. The gate contact 34 includes one that exposes the gate electrode 8 in the termination trench 16 in the termination region 30, and one that exposes the gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2 in the active region 20. In addition, a source electrode 11 is formed so as to contact the upper surface of the base region 4 and the upper surface of the source region 5, which are exposed through a source contact 31, which is an opening formed in the interlayer insulating film 13, via an ohmic electrode 32.

[0050] While an oxide film (interlayer insulating film 13) is formed in the terminal trench 16 of the terminal region 30, polysilicon is formed inside the gate trench 6 and gate trench 26, meaning that different materials are formed in each of these locations.

[0051] Furthermore, while the termination trenches 16 in the termination region 30 are machined with a wide dimension, the gate trenches 6 or 26 in the cell section are formed with the minimum machining line width. Due to the structural difference between the two, the thermal history during the wafer process results in different thermal expansion coefficients for the materials. This generates residual stress, which in turn causes differences in the electrical properties of the element and affects the reliability of the semiconductor device.

[0052] In each cell located in the active region 20, the stress increases towards the outermost edge of the gate trench. As a result, the failure rate of the gate insulating film 7 increases closer to the outermost edge of the gate trench. Therefore, by electrically isolating the outermost cells from the other cells and floating the gate potential, device failure can be suppressed.

[0053] Figure 5 is a cross-sectional view showing an example of the cell configuration in Figure 2. As shown in the example in Figure 5, the upper corner of the gate trench 6 is rounded.

[0054] Figure 6 is a cross-sectional view showing an example of the configuration of the gate contact area in the active region 20 of Figure 3. As shown in the example in Figure 6, the upper corner of the gate trench 6 has a rounded shape.

[0055] As shown in Figure 5, the upper corner of the semiconductor layer 2 in the cell portion where the gate electrode 8 is embedded in the gate trench 6 has a rounded shape, indicated by the radius of curvature Rc. Therefore, the shape of the gate insulating film 7 formed at that location is also a rounded shape, indicated by the radius of curvature Rc.

[0056] Furthermore, as shown in Figure 6, the upper corner of the semiconductor layer 2 of the gate contact portion, which includes a gate electrode 8 extending from the gate trench 6 to the upper surface of the semiconductor layer 2, has a rounded shape indicated by the radius of curvature Re. Therefore, the shape of the gate insulating film 7 formed at that location is also a rounded shape indicated by the radius of curvature Re.

[0057] Comparing the radii of curvature of the gate trench 6 directly beneath the gate insulating film 7, Re > Rc, indicating that the gate contact area has a gentler shape. The small radius of curvature Rc of the cell area is, for example, greater than 0 μm and 0.1 μm or less. The radius of curvature Re of the gate contact area is, for example, 0.1 μm or more and 2 μm or less. In particular, good characteristics can be obtained if the radius of curvature Re of the gate contact area is 0.5 μm or more and 2 μm or less.

[0058] A gate insulating film 7 and a gate electrode 8 are formed at the upper corner of the gate trench 6 in the gate contact area. Since the radius of curvature Re is larger than the radius of curvature Rc, it is possible to suppress the application of a high electric field to the gate insulating film 7 formed at the upper corner of the gate trench 6 when the MOSFET is turned on.

[0059] For example, when a gate voltage of 20V is applied, if the thickness of the gate insulating film 7 is 50nm, an electric field of 4MV / cm will be applied to the sidewall portion of the gate trench 6. In this case, if the gate contact portion is formed with a gate insulating film 7 having a rounded radius of curvature Re, it is possible to suppress the application of a high electric field to the gate insulating film 7 formed at the upper corner of the gate trench 6, thereby suppressing the breakdown of the insulating film.

[0060] From the standpoint of reliability of the gate insulating film 7, it is desirable to design a radius of curvature Re such that the electric field applied to the gate insulating film 7 near the gate trench 6 has a radius of curvature Re that suppresses the increase to 5% or less.

[0061] Although the gate contact portion shown in Figure 6 is assumed to be located in the active region 20, the gate contact portion in the termination region 30 (where the gate wiring 18 and the gate electrode 8 are connected via the gate contact 34) may have a rounded shape at the upper corner of the termination trench 16.

[0062] In this embodiment, when an ohmic electrode is provided between the source electrode and the semiconductor layer, the source electrode and the ohmic electrode may be referred to collectively as the source electrode without distinction. Similarly, when an ohmic electrode is provided between a gate bonding pad, which is a metal electrode, and a gate electrode made of a semiconductor or the like, the gate bonding pad and the ohmic electrode may be referred to collectively as the gate bonding pad without distinction.

[0063] In other words, in this embodiment, the source electrode and gate bonding pad are not limited to being composed of a single metal, but may be configured with a material suitable for bonding to the semiconductor layer at the junction with the semiconductor layer. Furthermore, the ohmic electrode is not limited to a metal, but may be a compound of metal and semiconductor, or a silicide. Also, the ohmic electrode may be composed of multiple layers of metal or a conductive material such as a semiconductor.

[0064] <Regarding the manufacturing method of semiconductor devices> Next, a method for manufacturing the semiconductor device 100 according to this embodiment will be described.

[0065] Figures 7 to 18 show examples of methods for manufacturing a semiconductor device according to this embodiment.

[0066] Figures 7 to 11 show examples of the process for forming a diffusion protective layer 9 below the bottom surface of the gate trench 6 and a terminal protective layer 19 below the bottom surface of the terminal trench 16. Figures 7 to 10 correspond to the A-A' section in Figure 11.

[0067] Figures 12 to 15 show examples of the process from forming the diffusion protective layer 9 and the termination protective layer 19 to forming the gate electrode 8. Figures 12 and 13 correspond to the A-A' section of Figure 15. Figure 14 corresponds to the B-B' section of Figure 15.

[0068] Figures 16 to 18 show an example of the process from forming the gate electrode 8 to completing the semiconductor device 100.

[0069] First, as shown in Figure 7, an n-type silicon carbide semiconductor substrate 1 having a 4H polytype is prepared, and an n-type semiconductor layer 2 is epitaxially grown on its upper surface by chemical vapor deposition (CVD).

[0070] In this case, the n-type impurity concentration of the n-type semiconductor layer 2 is, for example, 1 × 10⁻⁶ 14 cm -3 The above, and 1 × 10 17 cm -3 The following conditions apply, and the thickness of semiconductor layer 2 is, for example, 5 μm or more and 200 μm or less.

[0071] Next, as shown in Figure 7, a base region 4 is formed by ion implanting p-type impurities, such as aluminum (Al), into the surface layer of the epitaxially grown semiconductor layer 2. The ion implantation depth of Al is set to a range that does not exceed the thickness of the semiconductor layer 2, for example, between 0.3 μm and 3 μm. The impurity concentration of Al to be ion-implanted is set to be higher than the n-type impurity concentration of the epitaxially grown semiconductor layer 2, and the p-type impurity concentration of the base region 4 is set to, for example, 1 × 10⁻⁶ 17 cm -3 The above, and 1 × 10 20 cm -3 The following applies. As a result, the region of the semiconductor layer 2 other than the base region 4 which is deeper than the ion implantation depth of Al becomes the n-type drift layer 3.

[0072] The base region 4 may also be formed by epitaxial growth of a p-type semiconductor, in which case the p-type impurity concentration and thickness of the base region 4 may be the same as when the base region 4 is formed by ion implantation.

[0073] Next, as shown in Figure 7, source region 5 is formed by selectively ion-implanting nitrogen (N), an n-type impurity, into the surface layer of base region 4. Source region 5 is formed in a pattern corresponding to the layout of gate electrode 8, which will be formed in a later step. The ion implantation depth of N is made shallower than the thickness of base region 4. The impurity concentration of N to be ion-implanted is equal to or greater than the p-type impurity concentration of base region 4, and is 1 × 10⁻⁶ 21 cm -3 The following applies:

[0074] The order of the steps for ion implanting Al to form the base region 4 and ion implanting N to form the source region 5 may be reversed. Alternatively, after ion implanting N into the entire surface layer of the base region 4 to form an n-type semiconductor layer, the portion to be left as the source region 5 may be masked, and Al may be ion implanted again into the unmasked region (the region other than the source region 5) to return to a p-type base region 4. In this case, the impurity concentration of the Al to be ion implanted again may be made higher than the impurity concentration of Al in the base region 4 adjacent to the drift layer 3 to reduce the contact resistance with the source electrode.

[0075] Next, as shown in Figure 8, a silicon oxide film 41 is formed on the upper surface of the semiconductor layer 2, and then an etching mask 42 is formed on the upper surface of the silicon oxide film 41. The silicon oxide film 41 is formed by depositing it to a thickness of, for example, 1 μm or more and 2 μm or less, and then an etching mask 42 is formed on the upper surface of the silicon oxide film 41. A pattern having openings corresponding to the regions for forming the gate trench 6, gate trench 26, and termination trench 16 is formed on the etching mask 42 using photolithography techniques.

[0076] Next, reactive ion etching (RIE) is performed using the etching mask 42 as a mask to pattern the silicon oxide film 41. In other words, the pattern of the etching mask 42 is transferred to the silicon oxide film 41, and the silicon oxide film 41 becomes the etching mask for the semiconductor layer 2.

[0077] Next, as shown in Figure 9, using the patterned silicon oxide film 41 as a mask, gate trenches 6 and 26 penetrating the source region 5 and base region 4, and a termination trench 16 penetrating the base region 4 are formed in the semiconductor layer 2 during the RIE process.

[0078] The depths of the gate trench 6, gate trench 26, and termination trench 16 are greater than or equal to the depth of the base region 4 formed in the semiconductor layer 2 by ion implantation, and may be, for example, 1.0 μm or more and 6.0 μm or less.

[0079] Using a silicon oxide film 41 as a mask, gate trenches 6, 26, and terminal trenches 16 are formed. After forming gate trenches 6, 26, and 16, an implantation mask 43 having an opening pattern similar to that of the silicon oxide film 41 is formed, as shown in an example in Figure 10, and a p-type diffusion protective layer 9 is formed at the bottom of gate trenches 6 and 26 by Al ion implantation. Similarly, a p-type terminal protective layer 19 is formed at the bottom of terminal trench 16 by Al ion implantation. The impurity concentration of Al to be ion implanted is, for example, 1 × 10⁻⁶. 17 cm -3 The above, and 1 × 10 1 9 cm -3 The following conditions apply, and the ion implantation depth is preferably, for example, 0.1 μm or more and 2.0 μm or less. The impurity concentration of Al to be ion-implanted may be determined based on the electric field applied to the gate insulating film 7 when the same voltage as the breakdown voltage of the semiconductor device 100 is applied between the drain electrode 12 and the source electrode 11 of the semiconductor device 100.

[0080] Furthermore, by adjusting the thickness of the silicon oxide film 41 and the etching conditions so that the silicon oxide film 41 remains even after the gate trench 6 and terminal trench 16 are formed using the silicon oxide film 41 as a mask, the remaining silicon oxide film 41 can be used as a mask instead of the injection mask 43 when forming the diffusion protective layer 9 and terminal protective layer 19. This makes it possible to simplify the manufacturing process and reduce manufacturing costs.

[0081] Furthermore, when forming the diffusion protection layer 9, by ion implanting Al from an oblique direction into the opening of the gate trench 6, a p-type semiconductor layer can be formed within the drift layer 3 that is in contact with the side surface of the gate trench 6, thereby connecting the p-type diffusion protection layer 9 and the p-type base region 4 with the p-type semiconductor layer. This allows for an electrical connection between the diffusion protection layer 9 and the source electrode 11.

[0082] After forming the diffusion protective layer 9 and the termination protective layer 19, the implantation mask 43 used for ion implantation is removed, and an annealing treatment is performed using a heat treatment device to activate the ion-implanted impurities. The annealing treatment is carried out by heating in an inert gas atmosphere such as argon (Ar) or in a vacuum at a temperature of 1300°C or higher and 1900°C or lower for 30 seconds or more and 1 hour or less.

[0083] Next, as shown in Figure 12, the injection mask 43 is removed in the A-A' and B-B' sections of Figure 15, and the upper surface of the semiconductor layer 2 is oxidized. The thickness of the oxide film formed on the upper surface of the semiconductor layer 2 should be, for example, 5 nm or more and 100 nm or less. After that, the oxide film is removed by hydrofluoric acid-based wet etching. This process forms a rounded shape (radius of curvature Rc) at the upper corners of each trench.

[0084] Next, as shown in Figure 13, an oxide film 41A is deposited, and then, as shown in Figure 14, only the portion of the oxide film 41A corresponding to the region forming the gate contact of the active region 20 is opened.

[0085] Next, as shown in Figure 14, in the B-B' section of Figure 15, the oxide film 41A is etched to expose a portion of the semiconductor layer 2, and a rounded shape (radius of curvature Re) is formed at the upper corner of the gate trench 6 in the exposed semiconductor layer 2. In the B-B' section of Figure 15, a state is shown where the area spanning multiple gate trenches 6 is exposed from the oxide film 41A.

[0086] The round shape can be formed by CDE (chemical dry etching: isotropic etching) etching or by other etching treatments (such as heat treatment in a hydrogen atmosphere). After that, the oxide film 41A is removed.

[0087] In the process shown in Figure 12, a rounded shape (radius of curvature Rc) was formed at the upper corner of the trench. Further heat treatment in a CDE or hydrogen atmosphere in the process shown in Figure 14 allows for the formation of a rounded shape with an even larger radius of curvature at the upper corner of the gate trench 6.

[0088] As described above, the radius of curvature Re of the gate insulating film 7 provided at the upper corner of the gate trench 6 (or terminal trench 16) in the region where the gate wiring 18 is provided on the upper surface is larger than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the gate trench 6 in the region where the source electrode 11 is electrically connected to the adjacent source region 5. With this configuration, even if a gate voltage is applied to the gate insulating film 7 formed in a round shape with a larger radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field. As a result, the breakdown of the gate insulating film 7 is suppressed.

[0089] Next, the gate electrode 8 is formed. Note that Figure 16 corresponds to the A-A' section in Figure 18. Also, Figure 17 corresponds to the B-B' section in Figure 18.

[0090] As shown in the example in Figure 16, the gate insulating film 7 and the gate electrode 8 are formed in the gate trench 6, gate trench 26, and terminal trench 16, respectively. Specifically, the gate insulating film 7 is deposited first, and then the polysilicon that will become the gate electrode 8 is deposited. After that, the deposited polysilicon is etched back using the resist as a mask. In this way, the polysilicon is etched back in areas where there is no resist, and polysilicon is formed in the gate trench 6, gate trench 26, and terminal trench 16.

[0091] On the other hand, as shown in the example in Figure 17, the region covered with the resist is a region where a round shape (radius of curvature Re) is formed at the upper corner of the gate trench 6, and polysilicon is not etched back, and polysilicon remains in the mesa region (upper surface of semiconductor layer 2). Because the upper corner of the gate trench 6 has a large round shape (radius of curvature Re), it is not necessary to locally thicken the gate insulating film 7 to suppress electric field concentration at the upper corner of the gate trench 6. For this reason, a structure that can suppress electric field concentration at the upper corner of the gate trench 6 can be manufactured in a single gate insulating film 7 formation process, and the increase in manufacturing costs can be suppressed without increasing the number of manufacturing processes.

[0092] Next, an interlayer insulating film 13 is formed on the upper surface of the semiconductor layer 2 by a reduced-pressure CVD method, covering the gate electrode 8. Then, by patterning the interlayer insulating film 13, contact holes (gate contacts 34) reaching the source region 5 and the base region 4 are formed in the active region 20 and the termination region 30. In addition, a contact hole (source contact 31) reaching the gate electrode 8 is formed in the active region. Subsequently, an ohmic electrode 25 is formed within the gate contact 34 (see Figure 6). An ohmic electrode 32 is also formed within the source contact 31. Each ohmic electrode may be a silicide film formed by first depositing a metal film mainly composed of nickel (Ni) on the upper surface of the semiconductor layer 2 and the upper surface of the gate electrode 8, and then reacting Ni with the semiconductor by heat treatment at a temperature of 600°C or higher and 1100°C or lower.

[0093] Subsequently, an Al alloy or the like is deposited on the upper surface of the interlayer insulating film 13, inside the gate contact 34, and inside the source contact 31, and then patterned to form the gate wiring 18 via the gate contact 34 and the source electrode 11 via the source contact 31.

[0094] Then, an Al alloy or the like is deposited on the side of the silicon carbide semiconductor substrate 1 opposite to the side where the semiconductor layer 2 is formed to form a drain electrode 12. The semiconductor device 100 is formed through the above process.

[0095] <Regarding the effects and benefits of semiconductor devices> Next, the effects and advantages of the semiconductor device 100 according to this embodiment will be described.

[0096] In the semiconductor device 100 according to this embodiment shown in Figures 2 to 5, the on and off states of the semiconductor device 100 are controlled by controlling the voltage applied between the gate electrode 8 and the source electrode 11, thereby controlling the channel formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7.

[0097] When a voltage large enough to turn on the semiconductor device 100 is applied between the gate electrode 8 and the source electrode 11, a voltage above a threshold is applied to the gate electrode 8. As a result, a channel is formed in the base region 4 opposite the gate electrode 8 via the gate insulating film 7, and a path is formed between the n-type source region 5 and the n-type drift layer 3 for electron carriers to flow.

[0098] Then, electrons flowing from the source region 5 into the drift layer 3 reach the drain electrode 12 via the drift layer 3 and the silicon carbide semiconductor substrate 1, through the electric field formed by the voltage applied between the drain electrode 12 and the source electrode 11. As a result, by applying a voltage above the threshold voltage to the gate electrode 8, current flows from the drain electrode 12 to the source electrode 11. This state is the ON state of the semiconductor device 100.

[0099] On the other hand, when a voltage below the threshold is applied between the gate electrode 8 and the source electrode 11, no channel is formed in the base region 4 facing the gate electrode 8 via the gate insulating film 7. In this case, since a p-type base region 4 exists between the n-type source region 5 and the n-type drift layer 3, no current flows from the drain electrode 12 to the source electrode 11. This state is the off state of the semiconductor device 100.

[0100] When the semiconductor device 100 is turned off, a high voltage supplied from an external electrical circuit is applied between the drain electrode 12 and the source electrode 11. When the semiconductor device 100 is turned off, a depletion layer spreads within the drift layer 3 from the diffusion protection layer 9 and the termination protection layer 19. This suppresses the concentration of the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 into the gate insulating film 7 at the bottom of the gate trench 6, thereby suppressing its destruction even when a high electric field is applied to the gate insulating film 7 at the bottom of the gate trench 6.

[0101] On the other hand, when the semiconductor device 100 is turned on, a voltage supplied from an external electrical circuit is applied between the gate electrode 8 and the source electrode 11. This voltage application creates an electric field in the gate insulating film 7. Because the upper corner of the semiconductor layer 2 in the gate trench 6 is formed in a rounded shape with a radius of curvature Re, the gate insulating film 7 also has a rounded shape with a radius of curvature Re. Therefore, the electric field caused by the voltage applied between the drain electrode 12 and the source electrode 11 is suppressed from concentrating on the gate insulating film 7 at the upper corner of the gate trench 6, and the destruction of the gate insulating film 7 is suppressed even when an electric field is applied to it.

[0102] Furthermore, when the semiconductor device 100 is turned on, a current flows from the drain electrode 12 to the source electrode 11 due to a voltage supplied from an external electrical circuit. As a result, the voltage between the drain electrode 12 and the source electrode 11 becomes the on-voltage, which is determined by the current flowing from the drain electrode 12 to the source electrode 11 and the on-resistance of the semiconductor device 100. The on-voltage is much lower than the voltage applied between the drain electrode 12 and the source electrode 11 in the off state. Therefore, the depletion layer that has spread from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 in the off state shrinks towards the diffusion protection layer 9 and the termination protection layer 19 when the device is turned on.

[0103] In other words, when the semiconductor device 100 repeatedly switches between an ON state and an OFF state, the depletion layer that spreads from the diffusion protection layer 9 and the termination protection layer 19 into the drift layer 3 expands and contracts in conjunction with the switching.

[0104] The semiconductor device 100 functions by repeatedly switching between an off state and an on state. However, even during this repeated on-off operation, voltage stress is applied to the gate insulating film 7, accelerating its degradation. Since the upper corner of the semiconductor layer 2 in the gate trench 6 is formed in a rounded shape with a radius of curvature Re, the gate insulating film 7 at that location also takes on a rounded shape with a radius of curvature Re. Therefore, it is possible to suppress the concentration of the electric field between the drain electrode 12 and the source electrode 11 on the gate insulating film 7 at the upper corner of the semiconductor layer 2. Thus, it is possible to suppress the acceleration of degradation of the gate insulating film 7 and prevent its destruction.

[0105] In this embodiment, as shown in Figure 4, an electrically non-functional gate trench 26 is formed at the boundary between the termination region 30 and the active region 20. The termination region 30 and the active region 20 differ in their stacked structure and processing dimensions along the silicon carbide semiconductor substrate 1. Therefore, residual stress is generated at the boundary, affecting the electrical characteristics and potentially causing the gate insulating film 7 to break down. Furthermore, the failure rate of the gate insulating film 7 increases as it approaches the outermost periphery. For this reason, by electrically isolating the outermost cell (corresponding to the gate trench 26) as the termination region 30 and making its gate potential floating without electrically connecting its gate electrode 8 to the source electrode 11 and gate wiring 18, device failure can be suppressed.

[0106] Furthermore, increasing the number of gate trenches 26 shown in Figure 4 increases the yield rate. In other words, forming multiple gate trenches 26 improves the quality of the semiconductor device 100.

[0107] <Second Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0108] <About the configuration of semiconductor devices> Figure 19 is a schematic plan view showing an example of the configuration of a semiconductor device 101 according to this embodiment. As shown in the example in Figure 19, the semiconductor device 101 comprises an active region 20 and a termination region 30.

[0109] The active region 20 has multiple gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trenches 6, and gate wiring 18 connected to the gate electrode 8 via gate contacts 34. The gate contacts 34 are formed directly below the gate wiring 18 and directly above the gate electrode 8.

[0110] The gate electrode 8 is connected to a gate bonding pad 58 located on the outer periphery of the chip. The gate bonding pad 58 and the gate electrode 8 are metal layers, such as aluminum, and are formed in the same process.

[0111] A source electrode 11 is formed on the upper surface of the source region 5, which is formed on the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to the source bonding pad 59.

[0112] In the termination region 30, a termination trench 16 and gate wiring 18 in a portion of the termination trench 16 are formed. Metal wiring 120 is formed on the upper surface of the gate wiring 18 via gate contacts 34. The metal wiring 120 is formed in the same process as the gate electrode 8 and source electrode 11. Since the metal wiring 120 and the gate wiring 18 are formed in parallel, the electrical resistance can be reduced. The semiconductor device 101 is configured as described above.

[0113] <Regarding the manufacturing method of semiconductor devices> Next, a method for manufacturing the semiconductor device 101 according to this embodiment will be described.

[0114] Figures 20 to 22 show examples of methods for manufacturing a semiconductor device according to this embodiment.

[0115] The structure shown in Figure 20 corresponds to a plan view of the structure shown in Figure 10. A gate trench 6 is formed in the active region 20, and the outermost gate trench 26 and the terminal trench 16 are formed in the terminal region 30.

[0116] The structure shown in Figure 21 corresponds to a plan view of the structure shown in Figure 16. Gate wiring 18 is formed in the gate trench 6 of the active region 20. Gate wiring 18 is also formed in the gate trench 26 of the termination region 30. Furthermore, gate wiring 18 is formed in a portion of the termination trench 16.

[0117] The gate wiring 18 is formed by depositing polysilicon in the gate trench 6, and then forming a mask with a resist or the like in some areas and etching back the polysilicon.

[0118] In Figure 21, regions 108 and 109, indicated by dashed lines, are areas where polysilicon remains on the upper surface of the semiconductor layer 2 without being etched back due to the placement of the mask described above. In these regions, polysilicon is formed not only within the gate trench 6 but also covering the upper corners of the gate trench 6 and on the mesa region (upper surface of the semiconductor layer 2). The radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. Therefore, the destruction of the gate insulating film 7 is suppressed.

[0119] In Figure 21, the gate electrodes 8 formed in the gate trenches 26 of the termination region 30 and the gate electrodes 8 formed in the gate trenches 6 arranged in a stripe pattern in the central part of the active region 20 are separated in a plan view. As shown in Figures 16 to 18, the gate wiring 18 is formed by etching back the deposited polysilicon.

[0120] In the etch-back process, polysilicon remains as a sidewall in areas with trench steps (areas where the height of the upper surface differs due to the formation of trenches). In a structure where this remaining polysilicon is electrically connected, an electric field is applied to the gate insulating film 7 below the remaining polysilicon as a sidewall, causing the gate insulating film 7 to break down. In contrast, in the structure shown in Figure 21, the potential of the remaining polysilicon as a sidewall is floating and it is not electrically connected to the gate electrode. Therefore, the breakdown of the gate insulating film 7 can be suppressed.

[0121] Figure 22 is a plan view showing an example of the structure after the process shown in Figure 21, in which the interlayer insulating film 13 is formed and the source contact 31 and gate contact 34 are formed.

[0122] In Figure 22, gate contacts 34 are formed on the upper surface of the gate electrode 8 in regions 108 and 109. In the structure shown in Figure 22, the gate contacts 34 and gate wiring 18 can be formed in positions that overlap with the striped gate trenches 6 in a plan view, so there is no need to provide a separate region for forming the gate contacts 34. As a result, the chip area can be reduced and the degree of freedom in design layout is increased.

[0123] Subsequently, as shown in Figure 19, aluminum is deposited and etched with a resist mask to pattern the aluminum. Then, gate wiring 18 is formed in region 108 and connected to gate bonding pad 58. In region 109, aluminum is patterned to form metal wiring 120, and the metal wiring 120 extends to the upper surface of the gate electrode 8 formed in the termination region 30. Then, the metal wiring 120 is electrically connected to the gate electrode 8 via contact holes (gate contacts 34). The gate electrode 8 in the termination region 30 extends to just below the gate bonding pad 58 and is electrically connected to the gate electrode 8 via the gate contacts 34 within the gate bonding pad 58.

[0124] The gate electrode 8 in the gate trench 6 within the cell array is electrically connected from the gate bonding pad 58 via the gate contact 34 in the central part of the active region 20, and is also electrically connected to the gate electrode 8 formed in the termination region 30, the aluminum layer (metal wiring 120), and other gate electrode 8 within the active region 20. As a result, the resistance value of the gate electrode 8 in the gate trench 6 within the active region 20 is reduced, and good electrical characteristics (switching characteristics, on-characteristics) are obtained.

[0125] The radius of curvature Re at the upper corner of the gate trench 6 in region 108 in the central part of the active region 20 where the gate contact 34 is formed is large. Therefore, even when the gate voltage is applied during device operation, the concentration of the electric field at the upper corner of the gate trench 6 can be suppressed, and the destruction of the gate insulating film 7 can be suppressed.

[0126] <Third Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0127] <About the configuration of semiconductor devices> Figure 23 is a schematic plan view showing an example of the configuration of a semiconductor device 102 according to this embodiment. As shown in the example in Figure 23, the semiconductor device 102 comprises an active region 20 and a termination region 30.

[0128] The active region 20 has multiple gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trenches 6, and gate wiring 18 connected to the gate electrode 8 via gate contacts 34. The gate contacts 34 are formed directly below the gate wiring 18 and on top of the gate electrode 8.

[0129] The gate electrode 8 is connected to a gate bonding pad 58 located on the outer edge of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum and are formed in the same process.

[0130] A source electrode 11 is formed on the upper surface of the source region 5, which is formed on the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to the source bonding pad 59.

[0131] In the termination region 30, a termination trench 16 and a gate electrode 8 in a portion of the termination trench 16 are formed. A metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. The metal wiring 122 is formed in the same process as the gate wiring 18 and the source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel, the gate resistance can be reduced. The semiconductor device 102 is configured as described above.

[0132] <Regarding the manufacturing method of semiconductor devices> Next, a method for manufacturing the semiconductor device 102 according to this embodiment will be described.

[0133] Figures 24 and 25 show examples of methods for manufacturing a semiconductor device according to this embodiment.

[0134] The structure shown in Figure 24 corresponds to a plan view of the structure shown in Figure 16. A gate electrode 8 is formed in the gate trench 6 of the active region 20. A gate electrode 8 is also formed in the gate trench 26 of the terminal region 30. Furthermore, a gate electrode 8 is formed in a portion of the terminal trench 16.

[0135] The gate electrode 8 is formed by depositing polysilicon in the gate trench 6, and then etching back the polysilicon by forming a mask with a resist or the like in a certain area.

[0136] In Figure 24, regions 108 and 109, indicated by dashed lines, are areas where polysilicon remains on the upper surface of the semiconductor layer 2 without being etched back due to the placement of the mask described above. In these regions, polysilicon is formed not only within the gate trench 6 but also covering the upper corners of the gate trench 6 and on the mesa region (upper surface of the semiconductor layer 2). The radius of curvature Re of the upper corners of the gate trench 6 is large, which can suppress the concentration of the electric field. Therefore, the destruction of the gate insulating film 7 is suppressed.

[0137] As shown in Figure 24, the outermost edge of the active region 20 (corresponding to region 109) can electrically connect multiple gate electrodes 8 arranged in a stripe pattern via the gate contact 34, thereby lowering the gate resistance of the narrowly extended gate trench 6.

[0138] Figure 25 is a plan view showing an example of the structure after the process shown in Figure 24, in which the interlayer insulating film 13 is formed and the source contact 31 and gate contact 34 are formed.

[0139] In Figure 25, gate contacts 34 are formed on the upper surface of the gate electrode 8 in regions 108 and 109.

[0140] Subsequently, as shown in Figure 23, aluminum is deposited and etched with a resist mask to pattern the aluminum. Then, a gate electrode 8 is formed in region 108 and connected to the gate bonding pad 58 via gate wiring 18. In region 109, aluminum is patterned to form metal wiring 122 (gate wiring 18), and the metal wiring 122 extends to the upper surface of the gate electrode 8 formed in the termination region 30. Then, the metal wiring 122 is electrically connected to the gate electrode 8 via contact holes (gate contacts 34). The gate wiring 18 in the termination region 30 extends to directly below the gate bonding pad 58 and is electrically connected to the gate electrode 8 via the gate contacts 34 within the gate bonding pad 58.

[0141] The gate electrode 8 in the gate trench 6 within the cell array is electrically connected from the gate bonding pad 58 via the gate contact 34 in the central part of the active region 20. Furthermore, the gate electrode 8 in the gate trench 6 within the cell array is also electrically connected to other gate wirings 18 within the active region 20 via the gate contact 34 formed at the edge of the active region 20 and the aluminum layer (electrode portion 121). As a result, the resistance value of the gate wirings 18 in the gate trench 6 within the active region 20 is reduced, and good electrical characteristics (switching characteristics, on-characteristics) are obtained.

[0142] The radius of curvature Re of the upper corner of the gate trench 6 in region 108 in the central part of the active region 20 where the gate contact 34 is formed, and the radius of curvature Re of the upper corner of the gate trench 6 in region 109 at the edge of the active region 20 are formed to be large. Therefore, even when a gate voltage is applied during device operation, the concentration of the electric field at the upper corner of the gate trench 6 can be suppressed, and the destruction of the gate insulating film 7 can be suppressed.

[0143] <Fourth Embodiment> A semiconductor device and a method for manufacturing a semiconductor device according to this embodiment will be described. In the following description, components similar to those described in the embodiments described above will be denoted by the same reference numerals, and their detailed descriptions will be omitted as appropriate.

[0144] <About the configuration of semiconductor devices> Figures 26 to 30 are schematic cross-sectional views showing an example of the configuration of a semiconductor device 103 according to this embodiment. As shown in the example in Figures 26 to 30, the semiconductor device 103 comprises an active region 20 and a termination region 30.

[0145] The active region 20 has multiple gate trenches 6 arranged in a plan view, a gate electrode 8 formed in the gate trenches 6, and gate wiring 18 connected to the gate electrode 8 via gate contacts 34. The gate contacts 34 are formed directly below the gate wiring 18 and on top of the gate electrode 8.

[0146] The gate electrode 8 is connected to a gate bonding pad 58 located on the outer edge of the chip. The gate bonding pad 58 and the gate wiring 18 are metal layers such as aluminum and are formed in the same process.

[0147] A source electrode 11 is formed on the upper surface of the source region 5, which is formed on the surface layer of the semiconductor layer 2. The source electrode 11 is electrically connected to the source region 5 via a contact hole (source contact 31). The source electrode 11 also extends to the source bonding pad 59.

[0148] In the termination region 30, a termination trench 16 and a gate electrode 8 in a portion of the termination trench 16 are formed. A metal wiring 122 is formed on the upper surface of the gate electrode 8 via a gate contact 34. The metal wiring 122 is formed in the same process as the gate electrode 8 and the source electrode 11. Since the metal wiring 122 and the gate electrode 8 are formed in parallel, the gate resistance can be reduced. The semiconductor device 103 is configured as described above.

[0149] <Regarding the manufacturing method of semiconductor devices> Next, a method for manufacturing the semiconductor device 103 according to this embodiment will be described.

[0150] The structure shown in Figure 26 corresponds to the structure at the stage after the processes shown in Figures 7 through 9 have been completed.

[0151] Then, as shown in the example in Figure 26, after the gate trench 6, gate trench 26, and terminal trench 16 are formed, impurities are implanted into the bottom of each trench. Specifically, a p-type diffusion protective layer 39 is formed at the bottom of gate trench 6 and gate trench 26 by Al ion implantation. Similarly, a p-type terminal protective layer 49 is formed at the bottom of terminal trench 16 by Al ion implantation. The concentration of Al impurities to be ion-implanted is, for example, 1 × 10⁻⁶. 16 cm -3 The above, and 1 × 10 18 cm -3 The following conditions apply, and the ion implantation depth is preferably, for example, 0.1 μm or more and 2.0 μm or less.

[0152] Subsequently, as shown in Figure 27, a resist mask 51 is formed in gate trenches 6 and 26 at the boundary between the active region 20 and the termination region 30. Then, additional Al ion implantation is performed on the exposed p-type diffusion protective layer 39 and termination protective layer 49. The Al impurity concentration is, for example, 1 × 10⁻⁶. 16 cm -3 The above, and 1 × 10 1 8 cm -3 The following conditions apply, and the ion implantation depth is preferably, for example, 0.1 μm or more and 2.0 μm or less.

[0153] As a result of the two ion implantations described above, the impurity concentration in the diffusion protective layer 39 in gate trenches 6 and 26 at the boundary between the active region 20 and the terminal region 30 becomes lower than the impurity concentration in the diffusion protective layer 9 in gate trench 6 (a trench formed in a location other than the boundary) where the two ion implantations were performed. Similarly, the impurity concentration in the diffusion protective layer 39 becomes lower than the impurity concentration in the terminal protective layer 19 in terminal trench 16 where the two ion implantations were performed.

[0154] Subsequently, the resist is removed, and then an annealing treatment is performed using a heat treatment device to activate the ion-implanted impurities. The annealing treatment is carried out by heating in an inert gas atmosphere such as argon (Ar) or in a vacuum, for example, at a range of 1300°C or higher and 1900°C or lower, for example, for 30 seconds or more and 1 hour or less.

[0155] Next, a gate insulating film 97 is deposited, as shown in the example in Figure 28. Then, a resist mask 52 is formed in the gate trench 6 and gate trench 26 at the boundary between the active region 20 and the terminal region 30, and the gate insulating film 97 in the areas not covered by the resist mask 52 is removed by wet treatment with hydrofluoric acid or the like. Here, the thickness of the gate insulating film 97 is, for example, 20 nm or more and 150 nm or less.

[0156] Subsequently, as shown in the example in Figure 29, an additional gate insulating film is deposited over the entire surface. The thickness of the gate insulating film formed in the second deposition is, for example, 20 nm or more and 150 nm or less.

[0157] As a result of the two deposition processes described above, the gate insulating film 87 in some areas is formed to be thicker than the gate insulating film 7 in other areas.

[0158] Subsequently, polysilicon that will become the gate electrode 8 is deposited. Then, the deposited polysilicon is etched back using the resist as a mask. From there, the interlayer insulating film 13, source contact 31, gate contact 34, ohmic electrode 32, source electrode 11, gate wiring 18, etc. are formed in the same process as described in the first embodiment to complete the MOSFET (see Figure 30).

[0159] In the region where the gate contact 34 of the active region 20 is formed, polysilicon remains in the mesa region (upper surface of the semiconductor layer 2), but this area has a large radius of curvature (radius of curvature Re). Therefore, as in the case shown in the first embodiment, electric field concentration at the upper corner of the gate trench 6 can be suppressed, and the breakdown of the gate insulating film 7 can be suppressed.

[0160] In the configuration shown in Figure 30, the termination trench 16 of the termination region 30 is machined with a wide dimension, while the gate trench 6 or gate trench 26 of the cell portion is formed with the minimum machining line width. Due to the structural difference between the two, the thermal history during the wafer process results in different thermal expansion coefficients for the materials. This generates residual stress, which in turn causes differences in the electrical properties of the element and affects the reliability of the semiconductor device.

[0161] In each cell located in the active region 20, the stress increases towards the outermost edge of the gate trench. As a result, the failure rate of the gate insulating film 7 increases as you approach the outermost edge of the gate trench.

[0162] Therefore, electrically isolating the outermost cell from the other cells and floating its gate potential is effective, but if this is done, that region will not function as a MOSFET.

[0163] Therefore, in this embodiment, by increasing the thickness of the gate insulating film 87 of the cells in the peripheral area (the boundary between the active region 20 and the terminal region 30), or by designing the impurity concentration of the diffusion protective layer 39 to be lower than that of the diffusion protective layer 9 of other cells in other active regions 20, the concentrated electric field applied to the gate insulating film 87 when a gate voltage is applied and the semiconductor device turns on can be reduced. As a result, the breakdown of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0164] <Regarding the effects resulting from the multiple embodiments described above> Next, examples of the effects produced by the multiple embodiments described above will be shown. In the following description, the effects will be described based on the specific configurations illustrated in the multiple embodiments described above, but they may be replaced with other specific configurations illustrated in this specification to the extent that similar effects are produced. That is, for convenience, in the following, only one of the corresponding specific configurations may be described as representative, but the specific configuration described as representative may be replaced with other corresponding specific configurations.

[0165] Furthermore, such substitutions may be made across multiple embodiments. That is, the respective configurations exemplified in different embodiments may be combined to produce similar effects.

[0166] According to the embodiment described above, the semiconductor device comprises a drift layer 3 of a first conductivity type (n-type), a base region 4 of a second conductivity type (p-type) provided on the surface of the drift layer 3, a plurality of n-type source regions 5 provided on the surface of the base region 4, at least one trench (e.g., gate trench 6, gate trench 26, termination trench 16) extending from the upper surface of the drift layer 3 through the base region 4 into the drift layer 3, a p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, termination protective layer 19) provided in the drift layer 3 below the trench, a gate insulating film 7 provided along the interior of the trench including the upper corner of the trench, and a gate electrode 8 provided at least in the trench, surrounded by the gate insulating film 7. Here, the regions separated in a plan view of the trench are referred to as the first region and the second region. Furthermore, the semiconductor device includes a source electrode 11 electrically connected to a source region 5 adjacent to a trench (gate trench 6) in the first region, and a gate wiring 18 provided on the upper surface of a gate electrode 8 provided in a trench (gate trench 6 or termination trench 16) in the second region. The radius of curvature Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is greater than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0167] With this configuration, even when a gate voltage is applied to the gate insulating film 7, which is formed in a round shape with a large radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field. As a result, the breakdown of the gate insulating film 7 is suppressed.

[0168] Furthermore, the same effect can be achieved even if other configurations exemplified in this specification are appropriately added to the above configuration, that is, if other configurations in this specification that are not mentioned as the above configuration are appropriately added.

[0169] Furthermore, according to the embodiment described above, the gate wiring 18 is provided on the upper surface of the gate electrode 8 that extends to the upper surface of the source region 5. With this configuration, the breakdown of the gate insulating film can be suppressed, and the reliability of the semiconductor device can be improved.

[0170] Furthermore, according to the embodiment described above, the gate wiring 18 is connected to the upper surface of the gate electrode 8, which extends to the upper surface of the source region 5, via a plurality of contact holes (gate contacts 34). With this configuration, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0171] Furthermore, according to the embodiment described above, the thickness of the gate insulating film 7 provided in the trench in the first region is equal to the thickness of the gate insulating film 7 provided in the trench in the second region. With such a configuration, the gate insulating films 7 formed in multiple trenches can be formed in a single step.

[0172] Furthermore, according to the embodiment described above, multiple trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one gate trench 26 is provided in the termination region 30. In addition, the gate electrode 8 provided in the gate trench 26 in the termination region 30 is not electrically connected to the source electrode 11 and the gate wiring 18. With this configuration, the potential of the gate electrode 8 in the gate trench 26 is made floating, thereby suppressing the breakdown of the element.

[0173] Furthermore, according to the embodiment described above, multiple trenches are provided. The multiple gate trenches 6 are arranged in a stripe pattern in a plan view. The gate wiring 18 is provided across the upper surface of each gate electrode 8 provided within the multiple gate trenches 6. With this configuration, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0174] Furthermore, according to the embodiment described above, multiple trenches are provided. At least one gate trench 6 is provided in the active region 20, and at least one terminal trench 16 is provided in the terminal region 30. In addition, the width of the terminal trench 16 provided in the terminal region 30 is wider than the width of the gate trench 6 (or gate trench 26) provided in the active region 20. With this configuration, it is possible to create a structure in which no polysilicon remains on the side walls of the terminal trench 16, and thus the destruction of the gate insulating film can be suppressed compared to a structure in which an electric field is applied to the lower gate insulating film 7 via the polysilicon remaining on the side walls of the terminal trench.

[0175] Furthermore, according to the embodiment described above, multiple trenches are provided. At least one gate trench 6 is provided in the active region 20 surrounded by the termination region 30 in a plan view. Also, the thickness of the gate insulating film 87 provided in the trenches (gate trench 6 and gate trench 26) at the boundary between the active region 20 and the termination region 30 is greater than the thickness of the gate insulating film 7 provided in the trenches (gate trench 6 and termination trench 16) in the active region 20 and the termination region 30 other than the boundary. With this configuration, when a gate voltage is applied and the semiconductor device turns on, the concentrated electric field applied to the gate insulating film 87 can be reduced. As a result, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0176] Furthermore, according to the embodiment described above, multiple trenches are provided. At least one gate trench 6 is provided in the active region 20 surrounded by the termination region 30 in a plan view. In addition, the impurity concentration of the protective layer (diffusion protective layer 39) provided below the gate trench 6 and gate trench 26 at the boundary between the active region 20 and the termination region 30 is lower than the impurity concentration of the protective layer (diffusion protective layer 9, termination protective layer 19) provided below the trenches (gate trench 6, termination trench 16) in the active region 20 and termination region 30 other than the boundary. With this configuration, when a gate voltage is applied and the semiconductor device turns on, the concentrated electric field applied to the gate insulating film 87 can be reduced. As a result, the destruction of the gate insulating film is suppressed, and the reliability of the semiconductor device can be improved.

[0177] According to the embodiment described above, in a method for manufacturing a semiconductor device, a p-type base region 4 is provided on the surface layer of an n-type drift layer 3. Multiple n-type source regions 5 are provided on the surface layer of the base region 4. At least one trench (e.g., gate trench 6, gate trench 26, termination trench 16) is provided extending from the upper surface of the drift layer 3 through the base region 4 into the interior of the drift layer 3. A p-type protective layer (e.g., diffusion protective layer 9, diffusion protective layer 39, termination protective layer 19) is provided in the drift layer 3 below the trench. Here, the regions separated by the trench in a plan view are referred to as the first region and the second region. The upper corners of the trench (gate trench 6) are etched in the first region and the second region. The upper corners of the trench (gate trench 6 or termination trench 16) are etched in the second region. A gate insulating film 7 is provided along the interior of the trench, including the upper corners of the trench. Then, a gate electrode 8 is provided in a trench surrounded by a gate insulating film 7. A source electrode 11 is provided so as to be electrically connected to a source region 5 adjacent to a trench (gate trench 6) in the first region. Then, a gate wiring 18 is provided on the upper surface of the gate electrode 8 provided in a trench (gate trench 6 or termination trench 16) in the second region. Here, the radius of curvature Re of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6 or termination trench 16) in the second region is greater than the radius of curvature Rc of the gate insulating film 7 provided at the upper corner of the trench (gate trench 6) in the first region.

[0178] With this configuration, even when a gate voltage is applied to the gate insulating film 7, which is formed in a round shape with a large radius of curvature (radius of curvature Re), the large radius of curvature effectively suppresses electric field concentration, thereby preventing the application of a high electric field. As a result, the breakdown of the gate insulating film 7 is suppressed.

[0179] Unless otherwise specified, the order in which each process is performed can be changed.

[0180] Furthermore, the same effect can be achieved even if other configurations illustrated in the present specification are added to the above configuration as appropriate, that is, if other configurations in the present specification that were not mentioned as the above configuration are added as appropriate.

[0181] <Modifications of the multiple embodiments described above> In the various embodiments described above, the material, dimensions, shape, relative arrangement, or implementation conditions of each component may also be described, but these are all examples and not limiting.

[0182] Accordingly, countless variations and equivalents not shown are envisioned within the scope of the art disclosed herein. These include, for example, modifications, additions, or omissions of at least one component, as well as the extraction of at least one component from at least one embodiment and its combination with a component from another embodiment.

[0183] Furthermore, in at least one embodiment described above, if a material name or the like is mentioned without further specification, it is assumed that the material includes other additives, such as an alloy, unless otherwise specified, to avoid any inconsistencies. [Explanation of symbols]

[0184] 3 Drift layer, 4 Base region, 5 Source region, 6 Gate trench, 7 Gate insulating film, 8 Gate gate, 11 Source electrode, 16 Termination trench, 18 Gate wiring, 20 Active region, 26 Gate trench, 30 Termination region, 34 Gate contact, 87 Gate insulating film, 97 Gate insulating film, 100 Semiconductor device, 101 Semiconductor device, 102 Semiconductor device, 103 Semiconductor device, 108 Region, 109 Region, 1000 Region.

Claims

1. A first conductive drift layer, A second conductive base region is provided on the surface of the drift layer, Multiple first conductive source regions are provided on the surface of the base region, At least one trench extending from the upper surface of the drift layer through the base region into the drift layer, A second conductive protective layer is provided in the drift layer below the trench, A gate insulating film is provided along the interior of the trench, including the upper corner of the trench, A gate electrode surrounded by the gate insulating film and provided at least within the trench, A source electrode electrically connected to the source region adjacent to the trench, The trench is further provided with gate wiring provided on the upper surface of the gate electrode, Of the regions demarcated in a plan view of the trench, the region where the source electrode is provided is designated as the first region, and the region where the gate wiring is provided is designated as the second region. The radius of curvature of the gate insulating film provided at the upper corner of the trench in the second region is greater than the radius of curvature of the gate insulating film provided at the upper corner of the trench in the first region. Semiconductor equipment.

2. The semiconductor device according to claim 1, The gate wiring is provided on the upper surface of the gate electrode that extends to the upper surface of the source region. Semiconductor equipment.

3. The semiconductor device according to claim 2, The gate wiring is connected to the upper surface of the gate electrode, which extends to the upper surface of the source region, via a plurality of contact holes. Semiconductor equipment.

4. A semiconductor device according to claim 1 or 2, The thickness of the gate insulating film provided in the trench in the first region is equal to the thickness of the gate insulating film provided in the trench in the second region. Semiconductor equipment.

5. A semiconductor device according to claim 1 or 2, Multiple trenches are provided, At least one of the trenches is provided in the active region and in the terminal region that surrounds the active region in a plan view, The gate electrode provided in the trench provided in the terminal region is not electrically connected to the source electrode and the gate wiring. Semiconductor equipment.

6. A semiconductor device according to claim 1 or 2, Multiple trenches are provided, Multiple trenches are arranged in a striped pattern in a plan view, The gate wiring is provided across the upper surface of each of the gate electrodes provided in the plurality of trenches. Semiconductor equipment.

7. A semiconductor device according to claim 1 or 2, Multiple trenches are provided, At least one of the trenches is provided in the active region and the terminal region surrounding the active region in a plan view, spaced apart from each other. The width of the trench formed in the terminal region is wider than the width of the trench formed in the active region. Semiconductor equipment.

8. A semiconductor device according to claim 1 or 2, Multiple trenches are provided, At least one of the trenches is provided in the active region surrounded by the terminal region in a plan view, The thickness of the gate insulating film provided in the trench at the boundary between the active region and the terminal region is greater than the thickness of the gate insulating film provided in the trench in the active region and the terminal region other than the boundary portion. Semiconductor equipment.

9. A semiconductor device according to claim 1 or 2, Multiple trenches are provided, At least one of the trenches is provided in the active region surrounded by the terminal region in a plan view, The impurity concentration of the protective layer provided below the trench at the boundary between the active region and the terminal region is lower than the impurity concentration of the protective layer provided below the trench in the active region and the terminal region other than the boundary region. Semiconductor equipment.

10. A second conductive base region is provided on the surface of the first conductive drift layer. Multiple first conductive source regions are provided on the surface of the base region. A trench is provided that extends from the upper surface of the drift layer through the base region into the drift layer, A second conductive protective layer is provided within the drift layer below the trench. The regions demarcated in a plan view of the trench are defined as the first region and the second region. In the first and second regions, the upper corners of the trenches are etched. In the second region, the upper corner of the trench is etched, A gate insulating film is provided along the interior of the trench, including the upper corner portion of the trench. A gate electrode is provided in the trench surrounded by the gate insulating film, A source electrode is provided so as to be electrically connected to the source region adjacent to the trench in the first region, A gate wire is provided on the upper surface of the gate electrode located within the trench in the second region. The radius of curvature of the gate insulating film provided at the upper corner of the trench in the second region is greater than the radius of curvature of the gate insulating film provided at the upper corner of the trench in the first region. A method for manufacturing a semiconductor device.

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