General-purpose logic memory block using multiple general-purpose logic memory cells

Abstract

To provide a universal logic memory block using a plurality of universal logic memory cells.SOLUTION: A universal logic memory block 500 implements various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells 510 using triple-gate silicon elements driven by a positive feedback loop. A switch box 520 determines the directions of input voltage applied to the universal logic memory cells and output voltage outputted from the universal logic memory cells 510. A line switch 530 controls interconnection between the switch box 520 and the universal logic memory cells 510.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] [Cross-reference with related applications] This application claims priority under Korean Patent Application No. 10-2023-0191706 dated December 26, 2023, and all content disclosed in the said Korean Patent Application is incorporated herein by reference.

[0002] The present invention relates to a general-purpose logic memory block using multiple general-purpose logic memory cells, and more specifically, to a technology for realizing a general-purpose logic memory block that embodies various combinatorial logic operations in a single structure by combining the results of logic operations in multiple general-purpose logic memory cells using triple-gate silicon elements driven by a positive feedback loop. [Background technology]

[0003] In conventional von Neumann-based computer systems, the processor and memory are separated, and data is transmitted via a bus.

[0004] However, with the increase in computing power, bottlenecks are beginning to occur due to the difference in data processing speed between the processor and memory, and the processing of large amounts of data is starting to show its limitations.

[0005] In other words, while the von Neumann-based system, a revolutionary development in the semiconductor industry, improved the integration density and performance of modern computers, it has the drawback of consuming a lot of energy and resulting in long data transmission and latency due to the physical separation between the processor and memory hierarchy.

[0006] In the post-Fourth Industrial Revolution era, considering the increase in data-intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI), a new computing paradigm is essential to meet the demands of large-scale data processing.

[0007] To address the aforementioned problems, research into logic-in-memory (LIM) technology, which integrates computation and memory functions, is being intensified and accelerated.

[0008] Logic memory technology allows the processor's arithmetic functions and the memory's storage functions to be performed in the same space, thereby reducing delay time and power consumption during data transmission and significantly improving the system's integration density.

[0009] Conventional logic memory technology has been actively researched based on volatile memory elements such as SRAM (static random access memory) and DRAM (dynamic RAM), and non-volatile memory elements such as ReRAM (resistive RAM), MRAM (magnetoresistive RAM), and PCRAM (phase-change RAM).

[0010] In the case of volatile memory element-based logic memory technology, a large number of transistors are required for stable operation, resulting in limitations such as a large overall area and high power consumption.

[0011] Furthermore, in the case of logic memory technology based on non-volatile memory elements, complex manufacturing processes are required because non-silicon materials are used, and practical application is difficult due to low element uniformity and stability.

[0012] Furthermore, existing logic memory technologies cannot implement all basic CMOS logic operations in a single cell, and require individual circuits and wiring for each logic operation, resulting in a low level of integration.

[0013] Therefore, there is a need to develop a general-purpose logic memory cell technology that can be manufactured using silicon-based CMOS processes, perform all basic logic operations within a single cell, and store the resulting values.

[0014] Conventional logic memory technology has been studied using various types of memory, including volatile memory elements such as DRAM (dynamic random access memory) and SRAM (static RAM), and non-volatile memory elements such as PRAM (phase-change RAM), ReRAM (resistive RAM), and MRAM (magnetoresistive RAM).

[0015] However, these methods have difficulty being applied to existing CMOS logic operations because they cannot define n-channel and p-channel configurations.

[0016] In particular, non-volatile memory element-based logic memory technology requires novel process steps that are almost entirely different from silicon-based CMOS processes, and its low element uniformity and reliability make it difficult to implement in practice.

[0017] Combinatorial logic operations are performed using a structure in which basic logic operations are arranged sequentially, and each logic operation requires a logic circuit with a specific structure, making it difficult to increase the integration density. [Overview of the Initiative] [Problems that the invention aims to solve]

[0018] The present invention aims to realize a general-purpose logic memory block that embodies various combinatorial logic operations in a single structure by combining the results of logic operations in multiple general-purpose logic memory cells using triple-gate silicon elements driven by a positive feedback loop.

[0019] The present invention aims to realize a general-purpose logic memory block that utilizes a CMOS process to perform combinational logic operations by combining the results of logical operations and stores the results of these combinational logic operations.

[0020] The present invention aims to realize a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element that applies an existing CMOS process, and to realize a general-purpose logic memory block that can perform binary combinatorial logic operations using a general-purpose logic memory cell and store the results of those operations.

[0021] The present invention aims to improve the limitations of processing speed and integration caused by data bottlenecks by integrating logical operations and storage functions.

[0022] The present invention aims to realize a general-purpose logic memory block that significantly improves computational efficiency compared to existing CMOS logic circuits by performing various binary combinational logic operations with a single structure through the channel mode reconstruction characteristics of a triple-gate silicon element.

[0023] The present invention aims to improve standby power efficiency with excellent memory characteristics that maintain logical values ​​without structural changes or external biases, using channel mode reconfiguration characteristics. [Means for solving the problem]

[0024] A general-purpose logic memory block according to one embodiment of the present invention includes a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, a switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, and a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell. In a structure in which a plurality of the general-purpose logic memory cells are arranged according to a predetermined setting, combinational logic operation functions and memory functions can be performed by controlling the interconnection of the general-purpose logic memory cells to the logic operation functions based on the determined input voltage and output voltage directions.

[0025] The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function can be realized with at least one output based on the output voltage.

[0026] The switch box provides a first input voltage V to the general-purpose logic memory cells, among the general-purpose logic memory cells arranged in the plurality of rows and columns, which operate as XOR gates and as AND gates. IN1 and second input voltage V IN2 By applying a certain force, the output from the general-purpose logic memory cell operating as an XOR gate can be controlled to be output as a sum S, and the output from the general-purpose logic memory cell operating as an AND gate can be controlled to be output as a carry number COUT.

[0027] The switch box provides a first input voltage V to the general-purpose logic memory cells, which are arranged in the plurality of rows and columns, and which operate as a first XOR gate and a second XOR gate, and which operate as a first AND gate and a second AND gate, respectively. IN1 , second input voltage V IN2 and 3 input voltage V CIN By applying a voltage, the output from the general-purpose logic memory cell operating as the second XOR gate is output as a sum S, and the outputs from the general-purpose logic memory cells operating as the first AND gate and the second AND gate are transmitted to the input of the general-purpose logic memory cell operating as an OR gate, and the output voltage is controlled to be output as the carry number COUT.

[0028] The switch box applies an input voltage V to general-purpose logic memory cells operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN Applies a selection voltage V to a general-purpose logic memory cell operating as a NOT gate among the logic operation functions. S Outputs the output from the general-purpose logic memory cell operating as the first AND gate as a first output OUT1, and can control to output the output from the general-purpose logic memory cell operating as the second AND gate as a second output OUT2.

[0029] The switch box applies a first input voltage V and a second input voltage V to general-purpose logic memory cells operating as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN1 And a second input voltage V IN2 Applies a selection voltage V to a general-purpose logic memory cell operating as a NOT gate among the logic operation functions. S After transmitting the output from the general-purpose logic memory cell operating as the first AND gate and the output from the general-purpose logic memory cell operating as the second AND gate to the input of a general-purpose logic memory cell operating as an OR gate, it can control to output the output voltage as an output OUT.

[0030] The switch box applies a first input voltage V and a second input voltage V to general-purpose logic memory cells operating as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, and to general-purpose logic memory cells operating as a first NOT gate and a second NOT gate among the logic operation functions. IN1 And a second input voltage V IN2By selectively applying the signal, the output of the general-purpose logic memory cell operating as the first AND gate can be controlled as the first output OUT1, the output of the general-purpose logic memory cell operating as the second AND gate can be controlled as the second output OUT2, the output of the general-purpose logic memory cell operating as the third AND gate can be controlled as the fourth output OUT4, and the output of the general-purpose logic memory cell operating as the fourth AND gate can be controlled as the third output OUT3.

[0031] The switch box supplies a second input voltage V to the general-purpose logic memory cells that operate as a first OR gate and a second OR gate, among the general-purpose logic memory cells arranged in the plurality of rows and columns. IN2 , 3rd input voltage V IN3 and the fourth input voltage V IN4 By applying a voltage, the output of the general-purpose logic memory cell operating as the first OR gate can be controlled as the first output OUT1, and the output of the general-purpose logic memory cell operating as the second OR gate can be controlled as the second output OUT2.

[0032] The switch box provides a first input voltage V to the general-purpose logic memory cells arranged in the plurality of rows and columns, including general-purpose logic memory cells that operate as XNOR gates and XOR gates, general-purpose logic memory cells that operate as first NOT gates and second NOT gates, and general-purpose logic memory cells that operate as first AND gates and second AND gates. IN1 and second input voltage V IN2 By selectively applying the signal, the output of the general-purpose logic memory cell operating as an XNOR gate can be controlled as a first output OUT1, the output of the general-purpose logic memory cell operating as an XOR gate can be controlled as a second output OUT2, the output of the general-purpose logic memory cell operating as a second AND gate can be controlled as a third output OUT3, and the output of the general-purpose logic memory cell operating as a first AND gate can be controlled as a fourth output OUT4.

[0033] The switch box supplies a first input voltage V to the general-purpose logic memory cells that operate as a first XOR gate and a second XOR gate, among the general-purpose logic memory cells arranged in the plurality of rows and columns. IN1 , second input voltage V IN2 and 3 input voltage V IN3 Selectively apply the first input voltage V IN1 The first output OUT1 can be controlled, the output of the general-purpose logic memory cell operating as the first XOR gate can be controlled as the second output OUT2, and the output of the general-purpose logic memory cell operating as the second XOR gate can be controlled as the third output OUT3.

[0034] The general-purpose logic memory cell includes a first network element and a second network element using a plurality of triple-gate silicon elements, each of the plurality of triple-gate silicon elements including a drain region, a channel region and a source region, to which a supply voltage is applied, and to which a gate region is formed on the channel region, on which first and second programming gate electrodes and a control gate electrode is formed, and a program voltage V is applied via the first and second programming gate electrodes. PG Depending on the level, the channel region below the first and second programming gate electrodes in the channel region performs one of the first channel mode and the second channel mode, and the control voltage V applied via the control gate electrode CG Based on the level, it is determined to be in either an on state or an off state, and the first network element and the second network element change the output voltage V depending on the state in either of the channel modes performed. OUT The logical operation function and memory function can be performed according to the level.

[0035] The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected, and the drain voltage V of the common voltage is connected via the first parallel connection section of the first network element. DD The source voltage V of the common voltage is applied and transmitted through the second parallel connection of the second network element. SS A voltage is applied, and at the point where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected, the output voltage V is set as one of the above. OUT This can be measured.

[0036] The triple-gate silicon element has a drain region that is p-doped, a source region that is n-doped, and a channel region that is intrinsic, and in the channel region, the channel region below the first and second programming gate electrodes has the program voltage V PG When the level of is positive, it operates as an n-channel corresponding to the first channel mode, and the program voltage V PG When the level is negative, it can operate as a p-channel corresponding to the second channel mode.

[0037] The general-purpose logic memory cell has a drain voltage V applied to the drain region. DD , source voltage V applied to the source region SS , the aforementioned program voltage V PG and the control voltage V CG When applied at zero level, the output voltage V OUT The memory function can be performed while maintaining the level. [Effects of the Invention]

[0038] This invention enables the realization of a general-purpose logic memory block that can implement various combinational logic operations in a single structure by combining the results of logic operations in multiple general-purpose logic memory cells using triple-gate silicon elements driven by a positive feedback loop.

[0039] This invention utilizes a CMOS process to implement a general-purpose logic memory block that performs combinational logic operations by combining the results of logical operations and stores the results of these combinational logic operations.

[0040] This invention realizes a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element that applies an existing CMOS process. This general-purpose logic memory block can perform binary combinational logic operations using the general-purpose logic memory cell and store the results of those operations.

[0041] This invention can improve the limitations of processing speed and integration caused by data bottlenecks by integrating logical operations and storage functions.

[0042] This invention embodies a general-purpose logic memory block that significantly improves computational efficiency compared to existing CMOS logic circuits by performing various binary combinational logic operations in a single structure through the channel mode reconstruction characteristics of a triple-gate silicon element.

[0043] This invention can improve standby power efficiency with excellent memory characteristics that maintain logical values ​​without structural changes or external biases, by utilizing channel mode reconfiguration characteristics. [Brief explanation of the drawing]

[0044] [Figure 1A] This figure illustrates a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 1B] This figure illustrates a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 2A] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 2B] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 2C] This figure illustrates the operating principle of a triple-gate silicon element according to one embodiment of the present invention. [Figure 3] This figure illustrates a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4A] This figure illustrates binary logic operations of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4B] This figure illustrates binary logic operations of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4C] This figure illustrates binary logic operations of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4D] This figure illustrates binary logic operations of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 4E] This figure illustrates binary logic operations of a general-purpose logic memory cell according to one embodiment of the present invention. [Figure 5] This figure illustrates a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to one embodiment of the present invention. [Figure 6] This figure illustrates the operation of a half adder in a general-purpose logic memory block according to one embodiment of the present invention. [Figure 7] This figure illustrates the operation of a half adder in a general-purpose logic memory block according to one embodiment of the present invention. [Figure 8] This figure illustrates the operation of a full adder in a general-purpose logic memory block according to one embodiment of the present invention. [Figure 9]This figure illustrates the operation of a full adder in a general-purpose logic memory block according to one embodiment of the present invention. [Figure 10] This figure illustrates the operation of a demultiplexer for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 11] This figure illustrates the operation of a demultiplexer for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 12] This figure illustrates the operation of a multiplexer for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 13] This figure illustrates the operation of a multiplexer for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 14] This figure illustrates the operation of a decoder for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 15] This figure illustrates the operation of a decoder for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 16] This figure illustrates the operation of an encoder for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 17] This figure illustrates the operation of an encoder for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 18] This figure illustrates the operation of a bit comparator for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 19] This figure illustrates the operation of a bit comparator for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 20] This figure illustrates the operation of a bit-binary to Gray code converter for a general-purpose logic memory block according to one embodiment of the present invention. [Figure 21] This figure illustrates the operation of a bit-binary to Gray code converter for a general-purpose logic memory block according to one embodiment of the present invention. [Modes for carrying out the invention]

[0045] Various embodiments of this document are described below with reference to the attached drawings.

[0046] The examples and the terminology used herein are not intended to limit the technology described herein to any particular embodiment, but should be understood to include various modifications, equivalents, and / or substitutions of such embodiments.

[0047] In describing various embodiments below, if it is determined that a specific description of a relevant known function or configuration may obscure the gist of the invention, such detailed description will be omitted.

[0048] Furthermore, the terms described later are defined considering the functions in various embodiments, and these may change depending on the intent or conventions of the user or operator. Therefore, their definitions should be based on the content throughout this specification.

[0049] In relation to the description of the drawings, similar reference numerals may be used for similar components.

[0050] A singular expression can contain multiple expressions unless the context clearly indicates a different meaning.

[0051] In this document, expressions such as "A or B" or "at least one of A and / or B" may include all possible combinations of the items listed together.

[0052] Expressions such as "first," "second," "first," or "second" can modify the constituent elements regardless of their order or importance, and are used only to distinguish one constituent element from others, without limiting it to that constituent element.

[0053] When it is said that one component (e.g., component 1) is "connected" or "linked" to another component (e.g., component 2), that component may be directly connected to the other component or connected via another component (e.g., component 3).

[0054] In this specification, “configured to” may be used interchangeably with, depending on the context, “suitable for,” “capable of,” “modified to,” “made to,” “capable of,” or “designed to,” either in hardware or software.

[0055] In some situations, the expression "a device configured to do ~" may mean that the device "can do ~" together with other devices or components.

[0056] For example, the phrase "a processor configured (or set up) to perform A, B, and C" can mean a dedicated processor for performing those operations (e.g., an embedded processor), or a general-purpose processor (e.g., a CPU or application processor) that can perform those operations by executing one or more software programs stored in a memory device.

[0057] Furthermore, the term "or" here refers to inclusive OR rather than exclusive OR.

[0058] In other words, unless otherwise stated or made clear from the context, the expression "x uses a or b" means one of the natural inclusive permutations.

[0059] The terms "...part" and "...device" used below refer to a unit that processes at least one function or operation, which can be embodied in hardware, software, or a combination of hardware and software.

[0060] Figures 1A and 1B illustrate a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention.

[0061] Figure 1A illustrates the structure of a triple-gate silicon element constituting a general-purpose logic memory cell according to one embodiment of the present invention.

[0062] Referring to Figure 1A, a triple-gate silicon element 100 according to one embodiment of the present invention includes a drain region 101, a channel region 102, a source region 103, and a gate region, the gate region including first and second programming gate electrodes 106 and a control gate electrode 105 formed on a gate insulating film 104.

[0063] For example, a drain electrode may be connected to the drain region 101 to apply a drain voltage, and a source electrode may be connected to the source region 103 to apply a source voltage.

[0064] According to one embodiment of the present invention, the triple-gate silicon element 100 includes a drain region 101, a channel region 102, and a source region 103, which are pin nanostructures.

[0065] For example, the drain region 101 may be in a p-doped state, the source region 103 in an n-doped state, and the channel region 102 in an intrinsic state.

[0066] In channel region 102, the channel region below the first and second programming gate electrodes 106 is the program voltage V PG When the level is positive, it operates as an n-channel corresponding to the first channel mode, and the program voltage V PG When the level is negative, it can operate as a p-channel corresponding to the second channel mode.

[0067] Multiple triple-gate silicon elements 100 can be combined to form a general-purpose logic memory cell.

[0068] In other words, the triple-gate silicon element 100 is composed of multiple elements to form a general-purpose logic memory cell, but some of the elements may be composed of a first network element and some may be composed of a second network element.

[0069] The triple-gate silicon element 100 is programmed by a program voltage V applied via the first and second programming gate electrodes 106. PG Depending on the level, the channel region below the first and second programming gate electrodes 106 in the channel region can perform either the first channel mode or the second channel mode.

[0070] Furthermore, the triple-gate silicon element 100 is subjected to a control voltage V applied via the control gate electrode. CG Based on the level, it can be determined to be in either an on state or an off state.

[0071] Therefore, the general-purpose logic memory cell has an output voltage V which changes depending on one state in any of the channel modes already performed. OUT Logical operations and memory functions can be performed based on the level.

[0072] For example, since the first and second programming gate electrodes 106 are electrically connected, the same programming voltage V is applied at the same time.PG It may be applied.

[0073] Figure 1B illustrates the operating state of a general-purpose logic memory cell according to one embodiment of the present invention and the associated circuit symbols.

[0074] Referring to Figure 1B, circuit symbol 111 according to one embodiment of the present invention illustrates a circuit symbol when the channel region of a triple-gate silicon element performs in first channel mode and operates as an n-channel element.

[0075] As an example, circuit symbol 110 illustrates a circuit symbol when the channel region of a triple-gate silicon element performs in second channel mode and operates as a p-channel.

[0076] Circuit symbols 110 and 111 show a nanostructure including a drain region, a channel region, a source region, and a gate region, in which a first and second programming gate electrode and a control gate electrode are formed in the gate region and connected to the programming gate terminal PG and the control gate terminal CG, a drain electrode is formed in the drain region and connected to the drain terminal D, and a source electrode is formed in the source region and connected to the source terminal S.

[0077] Circuit symbol 111 indicates that the triple-gate silicon element is in the first channel mode state through the channel mode state region.

[0078] In other words, circuit symbol 111 can indicate that the triple-gate silicon element is operating as an n-channel by showing the channel mode state region in solid form.

[0079] Circuit symbol 110 indicates that the triple-gate silicon element is in the second channel mode state through the channel mode state region.

[0080] Circuit symbol 110 indicates that the triple-gate silicon element is operating as a p-channel by showing the channel mode state region in an empty form.

[0081] For example, a triple-gate silicon element can be called a triple-gate feedback field-effect element.

[0082] Figures 2A to 2C illustrate the operating principle of a triple-gate silicon element according to one embodiment of the present invention.

[0083] Figure 2A illustrates the operating principle when a triple-gate silicon element according to one embodiment of the present invention operates as a p-channel.

[0084] Referring to Figure 2A, in one embodiment of the present invention, when a positive voltage is applied through the drain terminal and a negative voltage corresponding to a negative level of the program voltage is applied from the programming gate terminal, the channel region below the programming gate electrode PG in the channel region is programmed to be a p-channel and operates as a p-channel.

[0085] When the triple-gate silicon element 200 according to one embodiment of the present invention operates as a p-channel, the operating state is determined to be ON when the level of the control voltage applied via the control gate terminal is lower than the latch-up voltage, which is the voltage when the current increases rapidly, and OFF when the level of the applied control voltage is higher than the latch-up voltage.

[0086] For example, a triple-gate silicon element is determined to be on or off based on the level of a control voltage applied through the control gate terminal.

[0087] The on and off operating states of the triple-gate silicon element can be further described through energy band 201, which corresponds to the off state, and energy band 202, which corresponds to the on state.

[0088] When a triple-gate silicon element according to one embodiment of the present invention operates as a p-channel, the energy band 202 when it is on and the energy band 201 when it is off can be determined based on the level of the control voltage.

[0089] According to energy bands 201 and 202, when the channel region below the first and second programming gate electrodes performs the second channel mode, which corresponds to the p-channel mode, the control voltage V CG When the level decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the first programming gate electrode adjacent to the drain region decreases. This lowered potential barrier creates a second positive feedback loop in which holes are injected from the drain region, resulting in an ON state where current flows.

[0090] In other words, the triple-gate silicon element generates a second positive feedback loop, allowing it to switch from energy band 201 to energy band 202.

[0091] We can confirm that the repeated injection and accumulation of charge creates a positive feedback loop, switching to an ON state where current flows.

[0092] For example, a second positive feedback loop could be a positive feedback loop in which holes become the majority carriers in the channel region.

[0093] Figure 2B illustrates the operating principle when a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel element.

[0094] Referring to Figure 2B, in one embodiment of the present invention, when a negative voltage is applied through the source terminal and a positive voltage corresponding to the level of the program voltage is applied from the programming gate terminal, the channel region below the programming gate electrode PG in the channel region is programmed to be an n-channel and operates as an n-channel.

[0095] For example, a triple-gate silicon element is determined to be on or off based on the level of a control voltage applied through the control gate terminal.

[0096] When the triple-gate silicon element 210 according to one embodiment of the present invention operates as an n-channel, the operating state is determined to be ON when the level of the control voltage applied via the control gate terminal is higher than the latch-up voltage, which is the voltage when the current increases rapidly, and OFF when it is lower than the latch-up voltage.

[0097] When a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel, the energy band 211 when it is in the off state and the energy band 212 when it is in the on state are illustrated based on the level of the control voltage.

[0098] Referring to energy bands 211 and 212, when the channel region below the first and second programming gate electrodes performs the first channel mode corresponding to the n-channel mode, the control voltage V CGWhen the level increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region below the control gate electrode and the channel region below the second programming gate electrode adjacent to the source region decreases. This lowered potential barrier creates a first positive feedback loop in which electrons are injected from the source region, resulting in an ON state where current flows.

[0099] In other words, a triple-gate silicon element generates a first positive feedback loop, causing a switch from energy band 201 to energy band 202.

[0100] We can confirm that the repeated injection and accumulation of charge creates a positive feedback loop, switching to an ON state where current flows.

[0101] For example, the first positive feedback loop could be a positive feedback loop in which electrons become majority carriers in the channel region.

[0102] Figure 2C illustrates the operation of the first and second positive feedback loops and related functions when a triple-gate silicon element according to one embodiment of the present invention operates as an n-channel and a p-channel.

[0103] Referring to Figure 2C, Graph 220 shows the operating characteristics of the n-channel mode of the triple-gate silicon device, and Graph 221 shows the operating characteristics of the p-channel mode of the triple-gate silicon device.

[0104] Graph 220 shows that a triple-gate silicon device operating in n-channel mode has an on-state and an off-state depending on the voltage applied to the control gate electrode. When the control gate voltage is lower than the latch-up voltage, which is the voltage at which the current rapidly increases, the flow of electrons and holes is blocked by the potential barrier, resulting in an off-state. It also shows that as the control gate voltage increases and becomes greater than the latch-up voltage, electrons from the source region are injected into the channel across the potential barrier and accumulate in the drain region and adjacent potential wells, reducing the height of the potential barrier.

[0105] As a result, holes in the drain region are injected into the channel and accumulate in the source region and adjacent potential wells, lowering the height of the potential barrier.

[0106] The repeated injection and accumulation of charge creates a positive feedback loop, resulting in an ON state where current flows.

[0107] Graph 221 shows that in the case of a triple-gate silicon device operating in p-channel mode, when the control gate voltage is greater than the latch-up voltage, the flow of electrons and holes is blocked by the potential barrier and the device enters an off state. When the control gate voltage decreases and becomes less than the latch-up voltage, holes in the drain region are injected into the channel over the potential barrier and accumulate in the source region and adjacent potential wells, resulting in a decrease in the height of the potential barrier.

[0108] According to one embodiment of the present invention, a triple-gate silicon element may be an element in which a first positive feedback loop or a second positive feedback loop is formed depending on the level of a control voltage applied to the gate region, and together with this, the on or off state is variably controlled in the first channel mode and the second channel mode. Here, the first channel mode is an n-channel mode, and the second channel mode is a p-channel mode.

[0109] Furthermore, triple-gate silicon elements are turned on while charge carriers accumulate in the potential well of the channel region, forming a positive feedback loop. This can be utilized as a memory function for storing data in the channel region.

[0110] Therefore, the present invention can realize a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element to which an existing CMOS process is applied.

[0111] Figure 3 is a diagram illustrating a general-purpose logic memory cell according to one embodiment of the present invention.

[0112] Figure 3 illustrates a circuit diagram of a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements according to one embodiment of the present invention.

[0113] Referring to Figure 3, a general-purpose logic memory cell 300 according to one embodiment of the present invention is composed of a first network element 310 and a second network element 311, and the first network element 310 and the second network element 311 consist of a plurality of triple-gate silicon elements 301.

[0114] More specifically, the first network element 310 and the second network element 311 are composed of a first series connection section in which the drain regions and source regions of two of the four triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain regions and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected.

[0115] The first network element 310 can be called a pull-up network element, and the second network element 311 can be called a pull-down network element.

[0116] According to one embodiment of the present invention, the general-purpose logic memory cell 300 performs a memory function that maintains the voltage state already set by controlling the supply voltage, the voltage corresponding to the voltage applied via the program gate electrode, and the input voltage applied via the control gate electrode to "0".

[0117] According to one embodiment of the present invention, each of the first network element 310 and the second network element 311 is composed of four triple-gate silicon elements, which can be divided into two triple-gate silicon elements as upper, lower, left, and right sides, or into one triple-gate silicon element as upper left, upper right, lower left, and lower right sides.

[0118] The triple-gate silicon elements arranged at each position can be selectively driven in either the first channel mode or the second channel mode.

[0119] The configuration described above can be modified by the arrangement of network elements and may be referred to differently depending on the modified connection configuration.

[0120] The first network element 310, via the first parallel connection section of the first network element 310, receives the drain voltage V of the common voltage. DD It is applied.

[0121] The second network element 311, via its second parallel connection section, transmits the source voltage V of the common voltage. SS It is applied.

[0122] In one embodiment of the present invention, the general-purpose logic memory cell 300 has an output voltage V at the point where the second parallel connection portion of the first network element 310 and the first parallel connection portion of the second network element 311 are connected. OUT This can be measured.

[0123] The general-purpose logic memory cell 300 is composed of a first network element 310 and a second network element 311, and the drain voltage V depends on the operating state of the triple-gate silicon element 301. DD and source voltage V SS Output voltage V OUT It implements logical operations based on the content measured by [the system / method].

[0124] A general-purpose logic memory cell 300 according to one embodiment of the present invention uses a plurality of triple-gate silicon elements.

[0125] Each of the multiple triple-gate silicon elements includes a drain region, a channel region, and a source region, to which a supply voltage is applied, and to which a gate region is formed on the channel region, with first and second programming gate electrodes and a control gate electrode.

[0126] Furthermore, each of the multiple triple-gate silicon elements has a program voltage V applied to it via the first and second programming gate electrodes. PG Depending on the level, the channel region below the first and second programming gate electrodes operates in either the first channel mode or the second channel mode, and the control voltage V applied via the control gate electrode operates in either channel mode or the first channel mode. CG Based on the level, it can be determined to be in either an on state or an off state.

[0127] The first network element 310 and the second network element 311 can perform logical operation functions and memory functions based on one state that has already been determined in one of the channel modes that has already been performed.

[0128] The logical operations functions are the NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates and related logical operations.

[0129] Therefore, the present invention can embody a general-purpose logic memory cell that provides logic operation and memory functions using a triple-gate silicon element driven by a positive feedback loop.

[0130] Furthermore, the present invention can realize a general-purpose logic memory cell that performs all basic logic operations in a single structure using a triple-gate silicon element and stores the results of those operations.

[0131] Figure 4A is a diagram illustrating the operation of the NOT gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0132] Figure 4A illustrates a circuit diagram and timing diagram for the operation of a NOT gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0133] Referring to Figure 4A, in one embodiment of the present invention, the general-purpose logic memory cell 400 has a triple-gate silicon element constituting the first network element perform a second channel mode based on a programming voltage applied via the programming gate terminal PG, and the triple-gate silicon element constituting the second network element perform a first channel mode.

[0134] At this time, the general-purpose logic memory cell 400 has a control voltage V which is the input voltage IN applied via the control gate terminal CG. CG When the level is negative, the output voltage V measured via the output terminal OUT The level is positive, and the control voltage V CG When the level is positive, the output voltage V OUT It can perform logical operations that correspond to the operation of a NOT gate with a negative level.

[0135] Timing diagram 401 shows the input voltage V at a negative level corresponding to "0". IN When applied, the output voltage V corresponds to a positive level of "1". OUTThis illustrates how a logical operation is performed and the result is output.

[0136] Furthermore, timing diagram 401 shows the positive level input voltage V corresponding to "1". IN When applied, the output voltage V corresponds to a negative level of "0". OUT This illustrates how a logical operation is performed and the result is output.

[0137] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0138] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0139] Furthermore, in the general-purpose logic memory cell, based on the programming voltage applied via the programming gate terminal PG, the triple-gate silicon elements constituting the first network element perform the first channel mode, the triple-gate silicon elements constituting the second network element perform the second channel mode, and the control voltage V, which is the input voltage IN applied via the control gate terminal CG, is applied. CG When the level is positive, the output voltage V measured via the output terminal is OUT The level is positive, and the control voltage V CG When the level is negative, the output voltage V OUT This allows for the execution of logical operations corresponding to the operation of a YES gate with a negative level.

[0140] Figure 4B is a diagram illustrating the operation of the AND gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0141] Figure 4B illustrates a circuit diagram and timing diagram for the operation of an AND gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0142] Referring to Figure 4B, in one embodiment of the present invention, the general-purpose logic memory cell 410 has a triple-gate silicon element constituting the first network element that performs a first channel mode and a triple-gate silicon element constituting the second network element that performs a second channel mode based on a programming voltage applied via the programming gate terminal PG.

[0143] Furthermore, the general-purpose logic memory cell 410 has a control voltage V CG Of these, the first control voltage IN1 is applied to the upper side of the first network element and the left side of the second network element, and the control voltage V CG Of these, the second control voltage IN2 is applied to the lower side of the first network element and to the right side of the second network element.

[0144] As a result, the general-purpose logic memory cell 410 controls the first control voltage V IN1 and second control voltage V IN2 If any one of the levels is negative, the output voltage V OUT Perform a logical operation to determine that the level is negative.

[0145] Furthermore, the general-purpose logic memory cell 410 has a first control voltage V IN1 and second control voltage V IN2 When both levels are at a positive level, the output voltage V OUT An AND gate operation is performed to determine the level as a positive level.

[0146] Timing diagram 411 shows two input voltages V IN1 ,V IN2When inputs corresponding to "00", "01", "10", and "11" are applied, the output voltage V OUT performs a binary logic operation function by calculating values corresponding to "0", "0", "0", and "1".

[0147] Also, when the supply voltage V SUP , the program voltage V PG , the input voltage V IN1 , V IN2 are removed, it performs a memory function to maintain (hold) the calculated logical value.

[0148] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0149] FIG. 4C is a diagram for explaining the operation of the OR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0150] FIG. 4C illustrates a circuit diagram and a timing diagram in the operation of the OR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0151] Referring to FIG. 4C, in the general-purpose logic memory cell 420 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element performs the first channel mode, and the triple-gate silicon element constituting the second network element performs the second channel mode.

[0152] Also, the general-purpose logic memory cell 420 has a control voltage V CGOf these, the first control voltage IN1 is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Of these, the second control voltage IN2 is applied to the right side of the first network element and below the second network element.

[0153] As a result, the general-purpose logic memory cell 420 controls the first control voltage V IN1 and second control voltage V IN2 If any one of the levels is positive, the output voltage V OUT The level is determined to be the positive level.

[0154] Furthermore, the general-purpose logic memory cell 420 has a first control voltage V IN1 and second control voltage V IN2 When both levels are at a negative level, the output voltage V OUT The level is determined to be a negative level.

[0155] Timing diagram 421 shows two input voltages V IN1 ,V IN2 When inputs corresponding to “00”, “01”, “10”, and “11” are applied to the output voltage V OUT This demonstrates that binary logical operations are performed by calculating values ​​corresponding to "0", "1", "1", and "1".

[0156] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0157] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N, and the program voltage V corresponding to the p channel PG P It is composed of.

[0158] Figure 4D is a diagram illustrating the operation of the XNOR gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0159] Figure 4D illustrates a circuit diagram and timing diagram for the operation of an XNOR gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0160] Referring to Figure 4D, in one embodiment of the present invention, the general-purpose logic memory cell 430 has the following configurations: the left triple-gate silicon element constituting the first network element performs the first channel mode, the right triple-gate silicon element performs the second channel mode, the upper left triple-gate silicon element constituting the second network element performs the second channel mode, the upper right triple-gate silicon element performs the first channel mode, the lower left triple-gate silicon element performs the first channel mode, and the lower right triple-gate silicon element performs the second channel mode.

[0161] A general-purpose logic memory cell 430 according to one embodiment of the present invention has a control voltage V CG Of these, the first control voltage V IN1 However, a control voltage V is applied to the upper side of the first network element and the second network element. CG Of these, the second control voltage V IN2 However, this is applied to the underside of the first network element and the second network element.

[0162] According to one embodiment of the present invention, the general-purpose logic memory cell 430 has a first control voltage V IN1 and second control voltage V IN2 When the levels are at the same level, the output voltage V OUT The level is output as a positive level, and the first control voltage V IN1 and second control voltage V IN2 When the levels are at different levels, the output voltage V OUTThe XNOR logical operation function can be performed to determine the level as a negative level.

[0163] Timing diagram 431 shows two input voltages V IN1 ,V IN2 When inputs corresponding to “00”, “01”, “10”, and “11” are applied to the output voltage V OUT This demonstrates that binary logical operations are performed by calculating values ​​corresponding to "1", "0", "0", and "1".

[0164] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0165] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0166] Figure 4E is a diagram illustrating the operation of the XOR gate of a general-purpose logic memory cell according to one embodiment of the present invention.

[0167] Figure 4E illustrates a circuit diagram and timing diagram for the operation of an XOR gate in a general-purpose logic memory cell according to one embodiment of the present invention.

[0168] Referring to Figure 4E, in one embodiment of the present invention, the general-purpose logic memory cell 440 has the following configurations: the upper left triple-gate silicon element constituting the first network element operates in second channel mode, the upper right triple-gate silicon element operates in first channel mode, the lower left triple-gate silicon element operates in first channel mode, and the lower right triple-gate silicon element constituting the second network element operates in first channel mode and the lower right triple-gate silicon element operates in second channel mode.

[0169] A general-purpose logic memory cell 440 according to one embodiment of the present invention has a control voltage V CG Of these, the first control voltage V IN1 However, a control voltage V is applied to the upper side of the first network element and the second network element. CG Of these, the second control voltage V IN2 However, this is applied to the underside of the first network element and the second network element.

[0170] As an example, the general-purpose logic memory cell 440 has a first control voltage V IN1 and second control voltage V IN2 When both levels are positive or both are negative, the output voltage V OUT The level is determined to be a negative level.

[0171] Furthermore, the general-purpose logic memory cell 440 has a first control voltage V IN1 and second control voltage V IN2 When the levels are at different levels, the output voltage V OUT Output the level as a positive level.

[0172] Timing diagram 441 shows two input voltages V IN1 ,V IN2 When inputs corresponding to “00”, “01”, “10”, and “11” are applied to the output voltage V OUT This demonstrates that binary logical operations are performed by arithmetic operations on values ​​corresponding to "0", "1", "1", and "0".

[0173] Also, the supply voltage V SUP , program voltage V PG , input voltage V IN1 ,V IN2 This indicates that the memory function will maintain (hold) the calculated logical value even when it is removed.

[0174] For example, supply voltage V SUP The drain voltage V DD and source voltage V SS It consists of a program voltage V PG This is the program voltage V corresponding to the n channel. PG N , and the program voltage V corresponding to the p channel PG P It is composed of.

[0175] Therefore, the present invention can improve the limitations of processing speed and integration caused by data bottlenecks through the integration of logical operations and storage functions.

[0176] Furthermore, the present invention can improve standby power efficiency with excellent memory characteristics that maintain logical operation values ​​without structural changes or external biases by using channel type variable characteristics.

[0177] Figure 5 illustrates a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to one embodiment of the present invention.

[0178] Figure 5 illustrates the components of a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to one embodiment of the present invention.

[0179] Referring to Figure 5, according to one embodiment of the present invention, the general-purpose logic memory block 500 includes a general-purpose logic memory cell 510 which includes a first network element and a second network element using a plurality of triple-gate silicon elements, and is realized by using a plurality of such cells.

[0180] For example, the switch box 520 can determine the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell 510.

[0181] A line switch 530 according to one embodiment of the present invention controls the interconnection between a switch box 520 and a general-purpose logic memory cell 510.

[0182] According to one embodiment of the present invention, the general-purpose logic memory block 500 has a structure in which a plurality of general-purpose logic memory cells 510 are arranged according to a predetermined setting, and can perform combinational logic operation functions and memory functions by controlling the interconnection of the general-purpose logic memory cells 510 to the logic operation functions based on the determined input voltage and output voltage directions.

[0183] As an example, in a general-purpose logic memory block 500, the general-purpose logic memory cells 510 are arranged in multiple rows and multiple columns according to a pre-configured setting, and a switch box 520 and a line switch 530 are arranged between the general-purpose logic memory cells 510.

[0184] The general-purpose logic memory block 500 has a number of line switches 530 that correspond to the number of input voltages transmitted via the switch box 520, and embodies a combinational logic operation function with at least one output based on the output voltage.

[0185] The general-purpose logic memory block 500 can embody various combinational logic operations in a single structure by having the general-purpose logic memory cell 510 selectively embody binary logic operation functions.

[0186] Combinatorial logic operations are realized through combinations of NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates and related logic operations based on binary logic operations.

[0187] Combinatorial logic functions may include the operation of a half adder, a full adder, a demultiplexer, a multiplexer, an encoder, a bit comparator, and a bit-binary to Gray code converter.

[0188] The general-purpose logic memory block 500 can not only perform the combinational logic operations described above, but can also implement various combinations of logic operations in a single structure.

[0189] Combinatorial logic operations are performed in a structure in which basic logic operations are arranged sequentially, and the structure is designed to allow interconnection between the input and output ports of each cell. When an input voltage is applied, various combinational logic operations are performed according to the type of logic gate and connection method of each cell, and the results of the operations can be stored.

[0190] Therefore, the present invention can realize a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element to which an existing CMOS process is applied, and a general-purpose logic memory block that can perform binary combinational logic operations using a general-purpose logic memory cell and store the results of the operations.

[0191] Figures 6 and 7 illustrate the operation of a half adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0192] Figure 6 illustrates a structure related to the operation of a half-adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0193] Referring to Figure 6, a general-purpose logic memory block 600 according to one embodiment of the present invention implements the operation of a half-adder based on the control of a switch box 620 and a line switch 630 for a general-purpose logic memory cell 610 that operates as an XOR gate and a general-purpose logic memory cell 611 that operates as an AND gate.

[0194] The switch box 620 has general-purpose logic memory cells arranged in multiple rows and columns, and among them, a general-purpose logic memory cell 610 that operates as an XOR gate and a general-purpose logic memory cell 611 that operates as an AND gate, which receive a first input voltage V IN1 and second input voltage V IN2 Apply the solution.

[0195] Furthermore, the switch box 620 controls the output from the general-purpose logic memory cell 610, which operates as an XOR gate, to output as a sum S, and the output from the general-purpose logic memory cell 611, which operates as an AND gate, to output as a carry number COUT.

[0196] Figure 7 illustrates a timing diagram related to the operation of a half adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0197] Referring to Figure 7, the timing diagram 700 according to one embodiment of the present invention shows the first input voltage V IN1 and second input voltage V IN2 This demonstrates the operation of a half-adder in a general-purpose logic memory block, which derives the calculation result as the sum S and carry COUT.

[0198] The general-purpose logic memory block 600 outputs a logical operation value corresponding to a half-adder by distributing input and output voltages, and performs a memory function that maintains the operation result even when all voltages are removed.

[0199] Figures 8 and 9 illustrate the operation of a full adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0200] Figure 8 illustrates a structure related to the operation of a full adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0201] Referring to Figure 8, a general-purpose logic memory block 800 according to one embodiment of the present invention embodies the operation of a full adder based on the control of a switch box 820 and a line switch 830 over general-purpose logic memory cells operating as a first XOR gate 810 and a second XOR gate 811, general-purpose logic memory cells operating as a first AND gate 812 and a second AND gate 813, and general-purpose logic memory cells operating as an OR gate 814.

[0202] As an example, the switch box 820 has general-purpose logic memory cells arranged in multiple rows and columns, and among these, general-purpose logic memory cells that operate as the first XOR gate 810 and the second XOR gate 811, and general-purpose logic memory cells that operate as the first AND gate 812 and the second AND gate 813, receive a first input voltage V IN1 , second input voltage V IN2 and 3 input voltage V CIN Apply the solution.

[0203] Furthermore, the switch box 820 outputs the output from the general-purpose logic memory cell operating as a second XOR gate 811 as a sum S, and transmits the outputs from the general-purpose logic memory cells operating as a first AND gate 812 and a second AND gate 813 to the input of the general-purpose logic memory cell operating as an OR gate 814, and then controls the output voltage to be output as the carry number COUT.

[0204] Figure 9 illustrates a timing diagram related to the operation of a full adder in a general-purpose logic memory block according to one embodiment of the present invention.

[0205] Referring to Figure 9, the timing diagram 900 according to one embodiment of the present invention shows the first input voltage V IN1 , second input voltage V IN2 and 3 input voltage VCIN The operation of a full adder of a general-purpose logic memory block that derives operation results as a sum S and a carry number COUT with respect to

[0206] The general-purpose logic memory block 800 outputs a logical operation value corresponding to a full adder by distributing input / output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0207] FIGS. 10 and 11 are diagrams for explaining the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0208] FIG. 10 illustrates a structure related to the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0209] Referring to FIG. 10, a general-purpose logic memory block 1000 according to an embodiment of the present invention implements the operation of a demultiplexer based on the control of a switch box 1020 and a line switch 1030 for a general-purpose logic memory cell operating as a first AND gate 1011 and a second AND gate 1012, and a general-purpose logic memory cell operating as a NOT gate 1010.

[0210] As an example, the switch box 1020 applies an input voltage V to a general-purpose logic memory cell operating as a first AND gate 1011 and a second AND gate 1012 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN to apply.

[0211] Also, the switch box 1020 applies a selection voltage V to a general-purpose logic memory cell operating as a NOT gate 1010 among the logic operation functions. S to apply.

[0212] As a result, the switch box 1020 controls the output from the general-purpose logic memory cell operating as the first AND gate 1011 to be output as the first output OUT1, and the output from the general-purpose logic memory cell operating as the second AND gate 1012 to be output as the second output OUT2.

[0213] Figure 11 illustrates a timing diagram related to the operation of a demultiplexer for a general-purpose logic memory block according to one embodiment of the present invention.

[0214] Referring to Figure 11, the timing diagram 1100 according to one embodiment of the present invention shows the input voltage V IN and the selected voltage V S This demonstrates the operation of a demultiplexer in which the output is generated in the order of first output OUT1 and second output OUT2.

[0215] The general-purpose logic memory block 1000 outputs a logic operation value corresponding to a demultiplexer by distributing input and output voltages, and performs a memory function that maintains the operation result even when all voltages are removed.

[0216] Figures 12 and 13 illustrate the operation of a general-purpose logic memory block multiplexer according to one embodiment of the present invention.

[0217] Figure 12 illustrates a structure related to the operation of a 2*1 multiplexer of a general-purpose logic memory block according to one embodiment of the present invention.

[0218] Referring to Figure 12, a general-purpose logic memory block 1200 according to one embodiment of the present invention embodies the operation of a 2*1 multiplexer based on the control of a switch box 1220 and a line switch 1230 over general-purpose logic memory cells that operate as a first AND gate 1211 and a second AND gate 1212, a general-purpose logic memory cell that operates as a NOT gate 1210, and a general-purpose logic memory cell that operates as an OR gate 1213.

[0219] As an example, the switch box 1220 supplies a first input voltage V to the general-purpose logic memory cells that operate as the first AND gate 1211 and the second AND gate 1212, among the general-purpose logic memory cells arranged in multiple rows and columns. IN1 and second input voltage V IN2 Apply the solution.

[0220] In one embodiment of the present invention, the switch box 1220 has a selection voltage V for a general-purpose logic memory cell that operates as a NOT gate 1210 among the logic operation functions. S Apply the solution.

[0221] For example, the switch box 1220 can transmit the output from a general-purpose logic memory cell operating as a first AND gate 1211 and the output from a general-purpose logic memory cell operating as a second AND gate 1212 to the input of a general-purpose logic memory cell operating as an OR gate 1213, and then control the output voltage to be output as output OUT.

[0222] Figure 13 illustrates a timing diagram related to the operation of a 2*1 multiplexer of a general-purpose logic memory block according to one embodiment of the present invention.

[0223] Referring to Figure 13, the timing diagram 1300 according to one embodiment of the present invention shows the first input voltage V IN1 , second input voltage V IN2 and selected voltage V S This shows the operation of the multiplexer based on the order in which the outputs are output as OUT.

[0224] The general-purpose logic memory block 1200 outputs a logical calculation value corresponding to a 2*1 multiplexer by distributing input and output voltages, and performs a memory function that maintains the calculation result even when all voltages are removed.

[0225] Figures 14 and 15 illustrate the operation of a decoder for a general-purpose logic memory block according to one embodiment of the present invention.

[0226] Figure 14 illustrates a structure related to the operation of a decoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0227] Referring to Figure 14, a general-purpose logic memory block 1400 according to an embodiment of the present invention implements the operation of a 2*4 decoder based on the control of a switch box 1420 and a line switch 1430 for general-purpose logic memory cells operating as a first NOT gate 1410 and a second NOT gate 1411, and general-purpose logic memory cells operating as a first AND gate 1412, a second AND gate 1413, a third AND gate 1414, and a fourth AND gate 1415.

[0228] As an example, the switch box 1420 selectively applies a first input voltage V IN1 and a second input voltage V IN2 to general-purpose logic memory cells operating as a first AND gate 1412, a second AND gate 1413, a third AND gate 1414, and a fourth AND gate 1415 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns, and general-purpose logic memory cells operating as a first NOT gate 1410 and a second NOT gate 1411 among the logic operation functions.

[0229] The switch box 1420 controls the output of the general-purpose logic memory cell operating as the first AND gate 1412 as the first output OUT1, controls the output of the general-purpose logic memory cell operating as the second AND gate 1413 as the second output OUT2, controls the output of the general-purpose logic memory cell operating as the third AND gate 1414 as the fourth output OUT4, and controls the output of the general-purpose logic memory cell operating as the fourth AND gate 1415 as the third output OUT3.

[0230] Figure 15 illustrates a timing diagram related to the operation of a decoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0231] Referring to Figure 15, a timing diagram 1500 according to an embodiment of the present invention is a first input voltage VIN1 and the second input voltage V IN2 This demonstrates the operation of the decoder in which the outputs are generated in the following order: first output OUT1, second output OUT2, third output OUT3, and fourth output OUT4.

[0232] The general-purpose logic memory block outputs logical calculation values ​​corresponding to a 2x4 decoder by distributing input and output voltages, and performs memory functions that maintain the calculation results even when all voltages are removed.

[0233] Figures 16 and 17 illustrate the operation of an encoder in a general-purpose logic memory block according to one embodiment of the present invention.

[0234] Figure 16 illustrates a structure related to the operation of an encoder in a general-purpose logic memory block according to one embodiment of the present invention.

[0235] Referring to Figure 16, a general-purpose logic memory block 1600 according to one embodiment of the present invention embodies the operation of an encoder based on the control of a switch box 1620 and a line switch 1630 to general-purpose logic memory cells that operate as a first OR gate 1610 and a second OR gate 1611.

[0236] As an example, the switch box 1620 provides a second input voltage V to the general-purpose logic memory cells that operate as the first OR gate 1610 and the second OR gate 1611, which are arranged in multiple rows and columns of general-purpose logic memory cells. IN2 , 3rd input voltage V IN3 and the fourth input voltage V IN4 The system controls the application of the first input voltage V. IN1 This is not applied to general-purpose logic memory cells.

[0237] The switch box 1620 controls the output of a general-purpose logic memory cell that operates as a first OR gate 1610 as the first output OUT1, and controls the output of a general-purpose logic memory cell that operates as a second OR gate 1611 as the second output OUT2.

[0238] Figure 17 illustrates a timing diagram related to the operation of an encoder in a general-purpose logic memory block according to one embodiment of the present invention.

[0239] Referring to Figure 17, the timing diagram 1700 according to one embodiment of the present invention shows the first input voltage V IN1 , second input voltage V IN2 , 3rd input voltage V IN3 and the fourth input voltage V IN4 This demonstrates the operation of the encoder in the order in which it outputs the first output OUT1 and the second output OUT2.

[0240] The general-purpose logic memory block outputs logical calculation values ​​corresponding to a 4*2 encoder by distributing input and output voltages, and performs memory functions that maintain the calculation results even when all voltages are removed.

[0241] Figures 18 and 19 illustrate the operation of a bit comparator for a general-purpose logic memory block according to one embodiment of the present invention.

[0242] Figure 18 illustrates a structure related to the operation of a bit comparator in a general-purpose logic memory block according to one embodiment of the present invention.

[0243] Referring to Figure 18, a general-purpose logic memory block 1800 according to one embodiment of the present invention embodies the operation of a bit comparator based on the control of a switch box 1820 and a line switch 1830 over general-purpose logic memory cells that operate as XNOR gates 1810 and 1811, general-purpose logic memory cells that operate as first NOT gates 1812 and 2 NOT gates 1813, and general-purpose logic memory cells that operate as first AND gates 1814 and 2 AND gates 1815.

[0244] As an example, the switch box 1820 has general-purpose logic memory cells arranged in multiple rows and columns, including general-purpose logic memory cells that operate as XNOR gates 1810 and 1811, general-purpose logic memory cells that operate as first NOT gates 1812 and 2 NOT gates 1813, and general-purpose logic memory cells that operate as first AND gates 1814 and 2 AND gates 1815, to which the first input voltage V IN1 and second input voltage V IN2 Selectively apply [the specified substance].

[0245] Furthermore, the switch box 1820 controls the output of a general-purpose logic memory cell operating as an XNOR gate 1810 as the first output OUT1, the output of a general-purpose logic memory cell operating as an XOR gate 1811 as the second output OUT2, the output of a general-purpose logic memory cell operating as a second AND gate 1815 as the third output OUT3, and the output of a general-purpose logic memory cell operating as a first AND gate 1814 as the fourth output OUT4.

[0246] Figure 19 illustrates a timing diagram related to the operation of a bit comparator in a general-purpose logic memory block according to one embodiment of the present invention.

[0247] Referring to Figure 19, the timing diagram 1900 according to one embodiment of the present invention is as follows: First input voltage V IN1 and second input voltage V IN2 This demonstrates the operation of a bit comparator based on the order in which it outputs the first output OUT1 to the fourth output OUT4.

[0248] The general-purpose logic memory block outputs a logical operation value corresponding to a bit comparator by distributing input and output voltages, and performs memory functions that maintain the operation result even when all voltages are removed.

[0249] Figures 20 and 21 illustrate the operation of a bit-binary to Gray code converter for a general-purpose logic memory block according to one embodiment of the present invention.

[0250] Figure 20 illustrates a structure related to the operation of a bit-binary-to-Gray code converter of a general-purpose logic memory block according to one embodiment of the present invention.

[0251] Referring to Figure 20, a general-purpose logic memory block 2000 according to one embodiment of the present invention embodies the operation of a bit-binary-to-Gray code converter based on the control of a switch box 2020 and a line switch 2030 to a first XOR gate 2010 and a second XOR gate 2011.

[0252] As an example, the switch box 2020 has general-purpose logic memory cells arranged in multiple rows and columns, and the general-purpose logic memory cells that operate as the first XOR gate 2010 and the second XOR gate 2011 receive a first input voltage V IN1 , second input voltage V IN2 and 3 input voltage V IN3 Selectively apply [the specified substance].

[0253] As a result, the switch box 2020 receives the first input voltage V IN1 This is controlled as the first output OUT1, the output of the general-purpose logic memory cell operating as the first XOR gate 2010 is controlled as the second output OUT2, and the output of the general-purpose logic memory cell operating as the second XOR gate 2011 is controlled as the third output OUT3.

[0254] Figure 21 illustrates a timing diagram related to the operation of a bit-binary-to-Gray code converter of a general-purpose logic memory block according to one embodiment of the present invention.

[0255] Referring to Figure 21, the timing diagram 2100 according to one embodiment of the present invention shows the first input voltage V IN1 ~Third input voltage V IN3This demonstrates the operation of the bit-binary-to-Gray code converter, which outputs the results in the order of first output OUT1 to third output OUT3.

[0256] The general-purpose logic memory block outputs a logical operation value corresponding to a bit-binary-to-Gray code converter by distributing input and output voltages, and performs a memory function that maintains the operation result even when all voltages are removed.

[0257] Therefore, the present invention can realize a general-purpose logic memory block that embodies various combinational logic operations in a single structure by combining the results of logic operations in multiple general-purpose logic memory cells using triple-gate silicon elements driven by a positive feedback loop.

[0258] In the specific embodiments described above, the components included in the invention are expressed singly or plurally by the specific embodiments presented.

[0259] However, the singular or plural representations are chosen to suit the situation presented for the sake of explanation, and the embodiments described above are not limited to singular or plural components. A plural component may consist of a singular component, and a singular component may consist of a plural component.

[0260] On the other hand, while specific embodiments have been described in the description of the invention, it goes without saying that various modifications are possible as long as they do not deviate from the scope of the technical idea encompassed by the various embodiments.

[0261] Therefore, the scope of the present invention should not be limited to the embodiments described, but should be defined not only by the claims described below, but also by claims equivalent to those described below.

Claims

1. A general-purpose logic memory cell including a first network element and a second network element using multiple triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box is a general-purpose logic memory block characterized by applying a first input voltage (V IN1) and a second input voltage (V IN2) to general-purpose logic memory cells that operate as XOR gates and general-purpose logic memory cells that operate as AND gates among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns, and controlling the output from the general-purpose logic memory cell that operates as an XOR gate to be output as a sum (S), and the output from the general-purpose logic memory cell that operates as an AND gate to be output as a carry (COUT).

2. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box provides a first input voltage (V) to the general-purpose logic memory cells, which are arranged in the plurality of rows and columns, and which operate as a first XOR gate and a second XOR gate among the logic operation functions. ＩＮ１ ), second input voltage (V ＩＮ２ ) and third input voltage (V ＣＩＮ A general-purpose logic memory block characterized by applying a voltage () and outputting the output from the general-purpose logic memory cell operating as the second XOR gate as a sum (S), transmitting the outputs from the general-purpose logic memory cells operating as the first AND gate and the second AND gate to the input of the general-purpose logic memory cell operating as an OR gate, and then controlling the output voltage to be output as a carry (COUT).

3. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box inputs an input voltage (V) to the general-purpose logic memory cells that operate as the first AND gate and the second AND gate, among the general-purpose logic memory cells arranged in the plurality of rows and columns. ＩＮ A selection voltage (V) is applied to the general-purpose logic memory cell that operates as a NOT gate among the logic operation functions. Ｓ A general-purpose logic memory block characterized by applying a voltage to control the output from a general-purpose logic memory cell operating as the first AND gate to be output as the first output (OUT1), and the output from a general-purpose logic memory cell operating as the second AND gate to be output as the second output (OUT2).

4. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box supplies a first input voltage (V) to the general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and columns. ＩＮ１ ) and second input voltage (V ＩＮ２ A selection voltage (V) is applied to the general-purpose logic memory cell that operates as a NOT gate among the logic operation functions. Ｓ A general-purpose logic memory block characterized by applying a voltage, transmitting the output from a general-purpose logic memory cell operating as a first AND gate and the output from a general-purpose logic memory cell operating as a second AND gate to the input of a general-purpose logic memory cell operating as an OR gate, and then controlling the output voltage to be output as an output (OUT).

5. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box selectively applies a first input voltage (V ＩＮ１ ) and a second input voltage (V ＩＮ２ ) to general-purpose logic memory cells that operate as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate, and general-purpose logic memory cells that operate as a first NOT gate and a second NOT gate among the logic operation functions, controls the output of the general-purpose logic memory cell operating as the first AND gate as a first output (OUT1), controls the output of the general-purpose logic memory cell operating as the second AND gate as a second output (OUT2), controls the output of the general-purpose logic memory cell operating as the third AND gate as a fourth output (OUT4), and controls the output of the general-purpose logic memory cell operating as the fourth AND gate as a third output (OUT3). A general-purpose logic memory block characterized by that.

6. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box supplies a second input voltage (V) to the general-purpose logic memory cells that operate as a first OR gate and a second OR gate among the general-purpose logic memory cells arranged in the plurality of rows and columns. ＩＮ２ ), third input voltage (V ＩＮ３ ) and fourth input voltage (V ＩＮ４ A general-purpose logic memory block characterized by applying a voltage to control the output of a general-purpose logic memory cell operating as the first OR gate as the first output (OUT1), and controlling the output of a general-purpose logic memory cell operating as the second OR gate as the second output (OUT2).

7. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box provides a first input voltage (V) to the general-purpose logic memory cells arranged in the plurality of rows and columns, including general-purpose logic memory cells that operate as XNOR gates and XOR gates, general-purpose logic memory cells that operate as first NOT gates and second NOT gates, and general-purpose logic memory cells that operate as first AND gates and second AND gates. ＩＮ１ ) and second input voltage (V ＩＮ２ A general-purpose logic memory block characterized by selectively applying a gate to control the output of a general-purpose logic memory cell operating as an XNOR gate as a first output (OUT1), the output of a general-purpose logic memory cell operating as an XOR gate as a second output (OUT2), the output of a general-purpose logic memory cell operating as a second AND gate as a third output (OUT3), and the output of a general-purpose logic memory cell operating as a first AND gate as a fourth output (OUT4).

8. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, A switch box that determines the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell, The switch box includes a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell, In a structure in which multiple general-purpose logic memory cells are arranged according to a predetermined setting, the interconnection of the general-purpose logic memory cells with respect to their logic operation functions is controlled by the direction of the applied input voltage and output voltage, thereby performing combinational logic operation functions and memory functions. The general-purpose logic memory cells are arranged in multiple rows and multiple columns according to the aforementioned pre-configured settings, the switch box and the line switches are arranged between the general-purpose logic memory cells, the number of line switches is determined to correspond to the number of input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The switch box supplies a first input voltage (V) to the general-purpose logic memory cells that operate as a first XOR gate and a second XOR gate, among the general-purpose logic memory cells arranged in the plurality of rows and columns. ＩＮ１ ), second input voltage (V ＩＮ２ ) and third input voltage (V ＩＮ３ ) is selectively applied, and the first input voltage (V ＩＮ１ A general-purpose logic memory block characterized by controlling the first XOR gate as the first output (OUT1), controlling the output of a general-purpose logic memory cell operating as the first XOR gate as the second output (OUT2), and controlling the output of a general-purpose logic memory cell operating as the second XOR gate as the third output (OUT3).

9. The general-purpose logic memory cell includes a first network element and a second network element using a plurality of triple-gate silicon elements, each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, a supply voltage is applied to the drain region and the source region, and the channel region includes a gate region on which first and second programming gate electrodes and a control gate electrode are formed, and a program voltage (V) is applied through the first and second programming gate electrodes. ＰＧ Depending on the level of the control voltage (V), the channel region below the first and second programming gate electrodes in the channel region performs one of the first channel mode and the second channel mode, and the control voltage (V) applied via the control gate electrode is determined. ＣＧ Based on the level of ), it is determined to be in either an on state or an off state, and the first network element and the second network element have an output voltage (V) that changes depending on the state in either of the channel modes performed. ＯＵＴ The general-purpose logic memory block according to claim 1, characterized in that it performs the logical operation function and memory function according to the level of ).

10. The first network element and the second network element are composed of a first series connection section in which the drain and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, a first parallel connection section to which a common drain region is connected between the first series connection section in which the drain and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection section to which a common source region is connected, and the drain voltage (V) of the common voltage is connected via the first parallel connection section of the first network element. ＤＤ ) is applied, and the source voltage (V) of the common voltage is applied via the second parallel connection part of the second network element. ＳＳ A voltage (V) is applied, and at the point where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected, the output voltage (V) is applied to either one of them. ＯＵＴ The general-purpose logic memory block according to claim 9, characterized in that ) is measured.

11. The triple-gate silicon element has a drain region that is p-doped, a source region that is n-doped, and a channel region that is intrinsic, and in the channel region, the channel region below the first and second programming gate electrodes has the program voltage (V ＰＧ When the level of the program voltage (V) is at a positive level, it operates as an n-channel corresponding to the first channel mode, and the program voltage (V) ＰＧ The general-purpose logic memory block according to claim 10, characterized in that it operates as a p-channel corresponding to the second channel mode when the level of ) is at a negative level.

12. The general-purpose logic memory cell has a drain voltage (V) applied to the drain region. ＤＤ ), the source voltage (V) applied to the source region ＳＳ ), the program voltage (V ＰＧ ) and the control voltage (V ＣＧ When the output voltage (V) is applied at zero level, ＯＵＴ The general-purpose logic memory block according to claim 9, characterized in that it performs the memory function while maintaining the level of ).

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