Semiconductor devices, inverter circuits, drive systems, vehicles, and elevators.

Abstract

To provide a semiconductor device capable of improving a surge current tolerance.SOLUTION: A semiconductor device according to an embodiment includes a transistor region and a diode region. The transistor region includes an n-type first silicon carbide region having a first portion contacting a first plane, a p-type second silicon carbide region, an n-type third silicon carbide region, and a gate electrode. The diode region includes the n-type first silicon carbide region having a second portion in contact with the first plane and a p-type fourth silicon carbide region. The semiconductor device includes a first electrode in contact with the first portion and the second portion and a second electrode in contact with a second plane. An occupied area per unit area of the fourth silicon carbide region is larger than an occupied area per unit area of the second silicon carbide region. In addition, a first diode region is provided between a first transistor region and a second transistor region. An inorganic insulating layer is provided between the first electrode and gate wiring adjacent to the first electrode.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] Embodiments of the present invention relate to semiconductor devices, inverter circuits, drive devices, vehicles, and elevators. [Background technology]

[0002] Silicon carbide is expected to be a promising material for next-generation semiconductor devices. Compared to silicon, silicon carbide has superior physical properties, including a band gap three times larger, a breakdown field strength approximately ten times greater, and thermal conductivity approximately three times higher. By utilizing these properties, it is possible to realize, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) that have high voltage resistance, low loss, and can operate at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a built-in pn junction diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, even when the MOSFET is off, it is possible to pass a freewheeling current using the built-in diode.

[0004] However, when a freewheel current is passed through using a body diode, stacking faults grow in the silicon carbide layer due to the carrier recombination energy, which increases the on-resistance of the MOSFET. This increase in on-resistance leads to a decrease in the reliability of the MOSFET. For example, by providing a unipolar Schottky Barrier Diode (SBD) as an internal diode in the MOSFET, it is possible to suppress the growth of stacking faults in the silicon carbide layer. By providing an SBD as an internal diode in the MOSFET, the reliability of the MOSFET is improved.

[0005] In some cases, a large surge current may flow through a MOSFET, momentarily exceeding its steady state. When a large surge current flows, a large surge voltage is applied, causing heat generation and potentially destroying the MOSFET. The maximum allowable peak current value (I) of the surge current that a MOSFET can handle is... FSM) is referred to as the surge current withstand capacity. In a MOSFET provided with an SBD, it is desirable to improve the surge current withstand capacity.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] The problem to be solved by the present invention is to provide a semiconductor device with improved surge current withstand capacity.

Means for Solving the Problems

[0008] The semiconductor device of the embodiment comprises a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, wherein the plurality of transistor regions is a silicon carbide layer having a first surface and a second surface facing the first surface, and includes an n-type first silicon carbide region having a plurality of first portions in contact with the first surface, a p-type second silicon carbide region provided between the first silicon carbide region and the first surface, and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, a first electrode in contact with the plurality of first portions, the second silicon carbide region and the third silicon carbide region, a second electrode in contact with the second surface, a gate electrode facing the second silicon carbide region, and the gate electrode The diode region includes a silicon carbide layer comprising an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, and a first electrode in contact with the plurality of second portions and the fourth silicon carbide region, and a second electrode, wherein the peripheral region comprises the silicon carbide layer, a gate electrode pad provided on the first surface side with respect to the silicon carbide layer, a gate wiring that electrically connects the gate electrode pad and the gate electrode and extends in a first direction parallel to the first surface, and an inorganic insulating layer provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction. 、 A resin layer provided on the inorganic insulating layer, Including, the area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface, and the first diode region, which is one of the at least one diode region, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in the first direction relative to the first transistor region. The first electrode includes a first region of the plurality of transistor regions and a second region of at least one diode region, and the inorganic insulating layer is provided between the second region and the gate wiring in the second direction, and the inorganic insulating layer is provided between the first region and the gate wiring in the second direction. . [Brief explanation of the drawing]

[0009] [Figure 1] A schematic top view of the semiconductor device according to the first embodiment. [Figure 2] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 3] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 4] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 5] A schematic top view of the semiconductor device according to the first embodiment. [Figure 6] A schematic top view of the semiconductor device according to the first embodiment. [Figure 7] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 8] A schematic cross-sectional view of the semiconductor device according to the first embodiment. [Figure 9] A schematic top view of the semiconductor device of the first comparative example. [Figure 10] A schematic cross-sectional view of the semiconductor device of the first comparative example. [Figure 11] Equivalent circuit diagram of the semiconductor device of the first comparative example. [Figure 12] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 13] A schematic cross-sectional view of the semiconductor device of the second comparative example. [Figure 14] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 15] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 16] A diagram illustrating the operation and effects of the semiconductor device according to the first embodiment. [Figure 17] A schematic cross-sectional view of the semiconductor device of the third comparative example. [Figure 18] A schematic cross-sectional view of the semiconductor device of the third comparative example. [Figure 19] Diagram illustrating the problem of the semiconductor device in the third comparative example. [Figure 20] Diagram illustrating the problem of the semiconductor device in the third comparative example. [Figure 21] A schematic cross-sectional view of a first modified example of the first embodiment. [Figure 22] A schematic cross-sectional view of a first modified example of the first embodiment. [Figure 23] A schematic top view of the semiconductor device according to the second embodiment. [Figure 24] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 25] A schematic cross-sectional view of the semiconductor device according to the second embodiment. [Figure 26] A schematic cross-sectional view of a modified example of the second embodiment. [Figure 27] A schematic cross-sectional view of a modified example of the second embodiment. [Figure 28] A schematic top view of the semiconductor device according to the third embodiment. [Figure 29] A schematic top view of the semiconductor device according to the fourth embodiment. [Figure 30] A schematic diagram of the drive unit of the fifth embodiment. [Figure 31] A schematic diagram of the vehicle according to the sixth embodiment. [Figure 32] A schematic diagram of the vehicle according to the seventh embodiment. [Figure 33] A schematic diagram of the elevator according to the eighth embodiment. [Modes for carrying out the invention]

[0010] Embodiments of the present invention will be described below with reference to the drawings. In the following description, the same or similar components will be denoted by the same reference numerals, and components that have already been described may be omitted from the description as appropriate.

[0011] Furthermore, in the following explanation, n + , n, n - and, p + , p, p - When using this notation, the above notation represents the relative high or low levels of impurity concentration in each conductivity type. That is, n + The concentration of n-type impurities is relatively higher in n than in n. - This indicates that the concentration of n-type impurities is relatively lower than that of n. Also, p+ has a relatively higher p-type impurity concentration than p, and p - has a relatively lower p-type impurity concentration than p. Note that n + type and n - type may simply be referred to as n-type and p + type and p - type may also simply be referred to as p-type in some cases.

[0012] The impurity concentration can be measured, for example, by Secondary Ion Mass Spectrometry (SIMS). Also, the relative high or low impurity concentration can be determined, for example, from the high or low carrier concentration obtained by Scanning Capacitance Microscopy (SCM). Also, distances such as the depth and thickness of the impurity region can be obtained, for example, by SIMS. Also, distances such as the depth, thickness, width, and interval of the impurity region can be obtained, for example, from a composite image of the SCM image and the Atomic Force Microscope (AFM) image.

[0013] In this specification, unless otherwise specified, the impurity concentration in the semiconductor region means the maximum impurity concentration in the semiconductor region.

[0014] (First Embodiment) The semiconductor device of the first embodiment includes a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and at least one diode region. The plurality of transistor regions include a silicon carbide layer having a first surface and a second surface facing the first surface, comprising: an n-type first silicon carbide region having a plurality of first portions in contact with the first surface; a p-type second silicon carbide region provided between the first silicon carbide region and the first surface; and an n-type third silicon carbide region provided between the second silicon carbide region and the first surface; a first electrode in contact with the plurality of first portions, the second silicon carbide region, and the third silicon carbide region; a second electrode in contact with the second surface; a gate electrode facing the second silicon carbide region; and a gate insulating layer provided between the gate electrode and the second silicon carbide region. At least one diode region includes a silicon carbide layer comprising an n-type first silicon carbide region having a plurality of second portions in contact with a first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface; a first electrode in contact with the plurality of second portions and the fourth silicon carbide region; and a second electrode. The peripheral region includes a silicon carbide layer, a gate electrode pad provided on the first surface side relative to the silicon carbide layer, gate wiring electrically connecting the gate electrode pad and the gate electrode and extending in a first direction parallel to the first surface, and an inorganic insulating layer provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction. The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. Furthermore, a first diode region, which is at least one diode region, is provided between a first transistor region, which is one of a plurality of transistor regions, and a second transistor region, which is one of a plurality of transistor regions provided in a first direction relative to the first transistor region.

[0015] The semiconductor device of the first embodiment is a planar gate type vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is a Double Implantation MOSFET (DIMOSFET) in which the body region and source region are formed by ion implantation, for example. The semiconductor device of the first embodiment also includes an SBD (Shottky Barrier Diode) as an internal diode. The MOSFET 100 is a vertical n-channel type MOSFET that uses electrons as carriers.

[0016] Figures 1(a) and 1(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 1(a) is a diagram showing the arrangement of each region of the MOSFET 100. Figure 1(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 100.

[0017] Figure 2 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 2 is a cross-sectional view AA' of Figure 1(a).

[0018] Figure 3 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 is a cross-sectional view of BB' in Figure 1(a).

[0019] Figures 4(a) and 4(b) are schematic cross-sectional views of a semiconductor device according to the first embodiment. Figure 4(a) is a cross-sectional view of Figure 1(a) at CC'. Figure 4(b) is a cross-sectional view of Figure 1(a) at DD'.

[0020] As shown in Figure 1(a), the MOSFET 100 comprises a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a diode region 102a (first diode region), a diode region 102b, and a peripheral region 103. Transistor region 101a is an example of the first transistor region. Transistor region 101b is an example of the second transistor region. Diode region 102a is an example of the first diode region.

[0021] Hereinafter, transistor regions 101a, 101b, 101c, and 101d may be referred to individually or collectively simply as transistor region 101. Similarly, diode regions 102a and 102b may be referred to individually or collectively simply as diode region 102.

[0022] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0023] The peripheral region 103 surrounds the transistor region 101 and the diode region 102. The peripheral region 103 is provided with a gate electrode pad 22 and gate wiring 24.

[0024] In the peripheral region 103, for example, a termination structure is provided to improve the breakdown voltage of the MOSFET 100. The termination structure that improves the breakdown voltage of the MOSFET 100 is, for example, a resurf or a guard ring.

[0025] The diode region 102 is provided between the two transistor regions 101. For example, the diode region 102a is provided between the transistor region 101a and the transistor region 101b. The transistor region 101b is provided in a first direction parallel to the first plane P1 with respect to the transistor region 101a.

[0026] For example, the diode region 102b is provided between the transistor region 101c and the transistor region 101d. The transistor region 101d is provided in a first direction relative to the transistor region 101c.

[0027] The width of the diode region 102 in the first direction is, for example, 30 μm or more. For example, the width of the diode region 102a in the first direction is 30 μm or more.

[0028] The MOSFET 100 comprises a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, an interlayer insulating layer 20, a gate electrode pad 22, gate wiring 24, a substrate insulating layer 40, and an inorganic insulating layer 42.

[0029] Within the silicon carbide layer 10, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), p-type p-region 32 (fourth silicon carbide region), n + This includes a source region 34 (third silicon carbide region) of type n, a first bottom region 36 (fifth silicon carbide region) of type n, and a second bottom region 38 (sixth silicon carbide region) of type n.

[0030] The drift region 28 includes a plurality of first parts 28a and a plurality of second parts 28b. The body region 30 includes a low-concentration part 30a and a high-concentration part 30b. The p region 32 includes a low-concentration part 32a and a high-concentration part 32b.

[0031] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is provided between the gate electrode 18 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H-SiC.

[0032] The silicon carbide layer 10 comprises a first surface ("P1" in Figure 2) and a second surface ("P2" in Figure 2). The first surface P1 and the second surface P2 face each other. Hereinafter, the first surface may be referred to as the front surface and the second surface as the back surface. Hereinafter, "depth" refers to the depth relative to the first surface.

[0033] The first surface P1 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (0001) surface. The second surface P2 is, for example, a surface inclined at an angle of 0 to 8 degrees relative to the (000-1) surface. The (0001) surface is referred to as the silicon surface. The (000-1) surface is referred to as the carbon surface.

[0034] n + The drain region 26 is provided on the back side of the silicon carbide layer 10. The drain region 26 contains, for example, nitrogen (N) as an n-type impurity. The concentration of n-type impurities in the drain region 26 is, for example, 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0035] n - A drift region 28 of this type is provided between the drain region 26 and the first surface P1. A drift region 28 is provided between the source electrode 12 and the drain electrode 14. A drift region 28 is provided between the gate electrode 18 and the drain electrode 14.

[0036] The drift region 28 is located on the drain region 26. The drift region 28 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the drift region 28 is lower than the n-type impurity concentration in the drain region 26. The n-type impurity concentration in the drift region 28 is, for example, 4 × 10⁻⁶. 14 cm -3 The above 1 x 10 17 cm -3 The following applies: The thickness of the drift region 28 is, for example, between 5 μm and 150 μm.

[0037] The drift region 28 includes a plurality of first portions 28a and a plurality of second portions 28b. The first portions 28a are tangent to the first surface P1. The first portions 28a are sandwiched between two body regions 30. The first portions 28a function as the n-type semiconductor region of the SBD.

[0038] The second portion 28b is in contact with the first surface P1. The second portion 28b is sandwiched between two p-regions 32. The second portion 28b functions as the n-type semiconductor region of the SBD.

[0039] The p-type body region 30 is provided between the drift region 28 and the first surface P1. A portion of the body region 30 functions as the channel region of the MOSFET 100. The body region 30 functions as the p-type semiconductor region of the pn junction diode.

[0040] The body region 30 includes a low-concentration portion 30a and a high-concentration portion 30b. The high-concentration portion 30b is provided between the low-concentration portion 30a and the first surface P1. The p-type impurity concentration in the high-concentration portion 30b is higher than the p-type impurity concentration in the low-concentration portion 30a.

[0041] The body region 30 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration in the low-concentration portion 30a is, for example, 1 × 10⁻⁶. 16 cm -3 The above 5 x 10 17 cm -3 The following applies: The p-type impurity concentration in the high-concentration portion 30b is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0042] The depth of the body region 30 is, for example, 0.3 μm or more and 1.0 μm or less.

[0043] The body region 30 is fixed at the potential of the source electrode 12.

[0044] The p-type p-region 32 is provided between the drift region 28 and the first surface P1. The p-region 32 functions as the p-type semiconductor region of the pn junction diode.

[0045] The p-region 32 includes a low-concentration portion 32a and a high-concentration portion 32b. The high-concentration portion 32b is located between the low-concentration portion 32a and the first surface P1. The p-type impurity concentration in the high-concentration portion 32b is higher than that in the low-concentration portion 32a.

[0046] The p-region 32 contains, for example, aluminum (Al) as a p-type impurity. The concentration of p-type impurities in the low-concentration portion 32a is, for example, 1 × 10⁻⁶.16 cm -3 The above 5 x 10 17 cm -3 The following applies: The p-type impurity concentration in the high-concentration portion 32b is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following applies:

[0047] The concentration of p-type impurities in the low-concentration portion 32a of the p-region 32 is substantially equal to, for example, the concentration of p-type impurities in the low-concentration portion 30a of the body region 30.

[0048] The concentration of p-type impurities in the high-concentration portion 32b of the p-region 32 is substantially equal to, for example, the concentration of p-type impurities in the high-concentration portion 30b of the body region 30.

[0049] The width of the p region 32 in the first direction is, for example, greater than the width of the body region 30 in the first direction. The depth of the p region 32 is, for example, between 0.3 μm and 1.0 μm.

[0050] The p region 32 is fixed at the potential of the source electrode 12.

[0051] n + The source region 34 of the mold is provided between the body region 30 and the first surface P1. The source region 34 is provided between the low-density portion 30a of the body region 30 and the first surface P1.

[0052] Source region 34 contains, for example, phosphorus (P) as an n-type impurity. The concentration of n-type impurities in source region 34 is higher than the concentration of n-type impurities in drift region 28.

[0053] The n-type impurity concentration in source region 34 is, for example, 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 21 cm -3 The following conditions apply: The depth of the source region 34 is shallower than the depth of the body region 30. For example, the depth of the source region 34 is between 0.1 μm and 0.3 μm.

[0054] The n-type first bottom region 36 is provided between the drift region 28 and the body region 30. The first bottom region 36 is in contact with, for example, the drift region 28 and the body region 30. The width of the first bottom region 36 in the first direction is substantially the same as, for example, the width of the body region 30 in the first direction.

[0055] The first bottom region 36 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the first bottom region 36 is higher than the n-type impurity concentration in the drift region 28.

[0056] The n-type impurity concentration in the first bottom region 36 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 2 x 10 17 cm -3 The following applies: The thickness of the first bottom region 36 is, for example, 0.4 μm or more and 1.5 μm or less.

[0057] The n-type second bottom region 38 is provided between the drift region 28 and the p region 32. The second bottom region 38 is in contact with, for example, the drift region 28 and the p region 32. The width of the second bottom region 38 in the first direction is substantially the same as, for example, the width of the p region 32 in the first direction.

[0058] The second bottom region 38 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration in the second bottom region 38 is higher than that in the drift region 28. The n-type impurity concentration in the second bottom region 38 is substantially the same as, for example, that of the first bottom region 36.

[0059] The n-type impurity concentration in the second bottom region 38 is, for example, 1 × 10⁻⁶ 16 cm -3 The above 2 x 10 17 cm -3 The following applies: The thickness of the second bottom region 38 is, for example, 0.4 μm or more and 1.5 μm or less.

[0060] The gate electrode 18 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate electrode 18 extends in a second direction parallel to the first surface P1 and perpendicular to the first direction. Multiple gate electrode 18s are arranged parallel to each other in the first direction. The gate electrode 18 has a so-called stripe shape.

[0061] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polycrystalline silicon containing p-type or n-type impurities.

[0062] The gate electrode 18 faces, for example, the portion that contacts the first surface P1 of the body region 30. The gate electrode 18 also faces, for example, the portion that contacts the first surface P1 of the drift region 28.

[0063] The gate insulating layer 16 is provided between the gate electrode 18 and the body region 30. The gate insulating layer 16 is provided between the gate electrode 18 and the drift region 28.

[0064] The gate insulating layer 16 is, for example, silicon oxide. For the gate insulating layer 16, for example, a high-k insulating material (high dielectric constant insulating material) can be applied.

[0065] The interlayer insulating layer 20 is provided on the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 has the function of electrically isolating the gate electrode 18 and the source electrode 12. The interlayer insulating layer 20 is, for example, silicon oxide.

[0066] The source electrode 12 is provided on the side of the first surface P1 of the silicon carbide layer 10. The source electrode 12 is in contact with the first surface P1.

[0067] The source electrode 12 is in contact with the first portion 28a of the drift region 28, the second portion 28b of the drift region 28, the body region 30, the p region 32, and the source region 34.

[0068] The source electrode 12 has a first region 12a on the transistor region 101 and a second region 12b on the diode region 102.

[0069] The source electrode 12 contains a metal. The metal forming the source electrode 12 is, for example, a layered structure of titanium (Ti) and aluminum (Al).

[0070] The body region 30, the p region 32, and the portion of the source electrode 12 in contact with the source region 34 are, for example, made of metal silicide. The metal silicide is, for example, titanium silicide or nickel silicide. The portion of the source electrode 12 in contact with the first portion 28a and the second portion 28b of the drift region 28 is not provided with metal silicide.

[0071] The junction between the body region 30, the p region 32, and the source region 34 and the source electrode 12 is, for example, an ohmic junction. The junction between the first portion 28a and the second portion 28b of the drift region 28 and the source electrode 12 is, for example, a Schottky junction.

[0072] The drain electrode 14 is provided on the side of the second surface P2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second surface P2. The drain electrode 14 is in contact with the drain region 26.

[0073] The drain electrode 14 is, for example, a metal or a metal-semiconductor compound. The drain electrode 14 includes, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0074] The junction between the drain region 26 and the drain electrode 14 is, for example, an ohmic junction.

[0075] The gate electrode pad 22 is provided on the first surface P1 side of the silicon carbide layer 10. The gate electrode pad 22 is provided on the interlayer insulating layer 20. The gate electrode pad 22 is provided to achieve an electrical connection between the outside and the gate electrode 18.

[0076] The gate wiring 24 is provided on the side of the first surface P1 of the silicon carbide layer 10. The gate wiring 24 is connected to the gate electrode pad 22. The gate wiring 24 is electrically connected to the gate electrode 18.

[0077] A portion of the gate wiring 24 extends in a first direction parallel to the first plane P1. Another portion of the gate wiring 24 extends in a second direction parallel to the first plane P1 and perpendicular to the first direction.

[0078] The gate electrode pad 22 and gate wiring 24 contain metal. The metal forming the gate electrode pad 22 and gate wiring 24 is, for example, a laminated structure of titanium (Ti) and aluminum (Al). The gate electrode pad 22 and gate wiring 24 are formed from, for example, the same metallic material as the source electrode 12.

[0079] The gate wiring 24 between the two source electrodes 12 extends in a first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in the first direction. The source electrode 12 is sandwiched between the two gate wirings 24 extending in a second direction.

[0080] As shown in Figure 2, the transistor region 101 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. Within the silicon carbide layer 10 of the transistor region 101, n + Drain region 26 of type n - Type drift region 28 (first silicon carbide region), p-type body region 30 (second silicon carbide region), n +The source region 34 (third silicon carbide region) of the n-type transistor includes an n-type first bottom region 36 (fifth silicon carbide region). The drift region 28 of the transistor region 101 also includes multiple first portions 28a.

[0081] In the transistor region 101, the source electrode 12, the first portion 28a of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the body region 30, the first bottom region 36, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0082] The first distance (d1 in Figures 4(a) and 4(b)) between two adjacent first portions 28a with the body region 30 in between is, for example, 3 μm or more and 30 μm or less.

[0083] As shown in Figure 3, the diode region 102 includes a silicon carbide layer 10, a source electrode 12 (first electrode), and a drain electrode 14 (second electrode). Within the silicon carbide layer 10 of the diode region 102, n + Drain region 26 of type n - The diode region 102 includes a drift region 28 of type n (the first silicon carbide region), a p-type p-region 32 (the fourth silicon carbide region), and a second bottom region 38 (the sixth silicon carbide region) of type n. In addition, the drift region 28 of the diode region 102 includes multiple second portions 28b.

[0084] In the diode region 102, the source electrode 12, the second portion 28b of the drift region 28, the drain region 26, and the drain electrode 14 constitute an SBD. In addition, the source electrode 12, the p region 32, the second bottom region 38, the drain region 26, and the drain electrode 14 constitute a pn junction diode.

[0085] The second distance (d2 in Figures 4(a) and 4(b)) between two adjacent second portions 28b with the p region 32 in between is, for example, 3 μm or more and 30 μm or less. The second distance d2 between two adjacent second portions 28b with the p region 32 in between is substantially equal to the first distance d1 between two adjacent first portions 28a with the body region 30 in between. The first distance d1 and the second distance d2 are distances in the first direction.

[0086] Figure 5 is a schematic top view of a semiconductor device according to the first embodiment. Figure 5 shows the pattern of the body region 30 projected onto the first surface P1 and the pattern of the p region 32 projected onto the first surface P1. The patterns of the body region 30 and the p region 32 in Figure 5 are patterns projected onto the first surface P1 in a direction perpendicular to the first surface P1.

[0087] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. In other words, in a region of a predetermined size, the occupancy rate of the p region 32 projected onto the first surface P1 is greater than the occupancy rate of the body region 30 projected onto the first surface P1. The above occupancy rate is the occupancy rate of the transistor region 101 and the diode region 102 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0088] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is, for example, 1.2 times or more and 3 times or less of the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1.

[0089] The above unit area is not particularly limited, as long as it is a size that allows for a comparison of the average occupancy rate of the body region 30 of the transistor region 101 and the average occupancy rate of the p region 32 of the diode region 102. For example, the above unit area could be 30 μm × 30 μm = 900 μm. 2 That is the case.

[0090] Furthermore, the contact area per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0091] Figures 6(a) and 6(b) are schematic top views of a semiconductor device according to the first embodiment. Figure 6(a) is a diagram showing the arrangement of each region of the MOSFET 100. Figure 6(b) is a diagram showing the electrode and inorganic insulating layer patterns on the top surface of the MOSFET 100.

[0092] Figure 7 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 7 is a cross-sectional view of EE' in Figures 6(a) and 6(b).

[0093] Figure 8 is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 8 is a cross-sectional view of FF' in Figures 6(a) and 6(b).

[0094] The substrate insulating layer 40 is provided in the peripheral region 103. The substrate insulating layer 40 is provided on top of the silicon carbide layer 10. The substrate insulating layer 40 has the function of electrically isolating the gate electrode 18 and the silicon carbide layer 10.

[0095] The substrate insulating layer 40 contains, for example, an oxide. The substrate insulating layer 40 is, for example, silicon oxide.

[0096] A gate electrode 18 is provided on the substrate insulating layer 40. The gate electrode 18 on the substrate insulating layer 40 extends, for example, in a first direction.

[0097] The gate wiring 24 is provided on the gate electrode 18. The gate wiring 24 is in contact with the gate electrode 18.

[0098] The inorganic insulating layer 42 is provided on top of the interlayer insulating layer 20, the source electrode 12, the gate electrode pad 22, and the gate wiring 24.

[0099] The inorganic insulating layer 42 is provided between the source electrode 12 and the gate wiring 24 in a direction parallel to the first surface P1. The inorganic insulating layer 42 is also provided between the source electrode 12 and the gate wiring 24 in a second direction, for example.

[0100] The inorganic insulating layer 42 is in contact with, for example, the upper surface of the source electrode 12. The inorganic insulating layer 42 is in contact with, for example, the upper surface of the gate wiring 24.

[0101] The inorganic insulating layer 42 is in contact with, for example, the side surface of the source electrode 12. The inorganic insulating layer 42 is in contact with, for example, the side surface of the gate wiring 24. The inorganic insulating layer 42 is provided, for example, between the side surface of the source electrode 12 and the side surface of the gate wiring 24.

[0102] The inorganic insulating layer 42 is provided, for example, between the second region 12b of the source electrode 12 and the gate wiring 24, as shown in Figure 7. The inorganic insulating layer 42 is provided, for example, between the first region 12a of the source electrode 12 and the gate wiring 24, as shown in Figure 8.

[0103] The inorganic insulating layer 42 includes, for example, at least one of an oxide and a nitride. The inorganic insulating layer 42 includes, for example, at least one of silicon oxide and silicon nitride. The inorganic insulating layer 42 has, for example, a laminated structure of a silicon oxide layer and a silicon nitride layer.

[0104] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0105] Figures 9(a) and 9(b) are schematic top views of the semiconductor device of the first comparative example. Figure 9(a) is a diagram showing the arrangement of each region of the MOSFET 901 of the first comparative example. Figure 9(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 901 of the first comparative example. Figures 9(a) and 9(b) correspond to Figures 1(a) and 1(b) of the first embodiment.

[0106] Figure 10 is a schematic cross-sectional view of the semiconductor device of the first comparative example. Figure 10 is a cross-sectional view of GG' in Figure 9(a). Figure 10 corresponds to Figure 4(a) of the first embodiment.

[0107] The MOSFET 901 of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not have a diode region 102. Furthermore, the MOSFET 901 of the first comparative example differs from the MOSFET 100 of the first embodiment in that it does not have an inorganic insulating layer 42.

[0108] In the transistor region 101 of the MOSFET of the first comparative example, a MOSFET and an SBD are provided, similar to the MOSFET 100 of the first embodiment.

[0109] Figure 11 is an equivalent circuit diagram of the semiconductor device of the first comparative example. Between the source electrode 12 and the drain electrode 14, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes.

[0110] For example, consider the case where MOSFET901 is used as a switching element connected to an inductive load. When MOSFET901 is off, a load current caused by the inductive load may apply a voltage that makes the source electrode 12 positive relative to the drain electrode 14. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0111] The forward voltage (Vf) at which forward current begins to flow through an SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, forward current flows through the SBD first.

[0112] The forward voltage (Vf) of an SBD is, for example, 1.0V. The forward voltage (Vf) of a pn junction diode is, for example, 2.5V.

[0113] The SBD operates unipolar. Therefore, even when a forward current flows, stacking faults do not grow in the silicon carbide layer 10 due to carrier recombination energy.

[0114] Figures 12(a) and 12(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 12(a) and 12(b) are schematic cross-sectional views of the first comparative example. Figures 12(a) and 12(b) correspond to Figure 10.

[0115] Figures 12(a) and 12(b) show the currents flowing through the built-in diode of the MOSFET901 of the first comparative example. Figure 12(a) shows the state where forward current flows only through the SBD, and Figure 12(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0116] Specifically, Figure 12(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 12(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0117] In Figures 12(a) and 12(b), the dotted arrows indicate the current flowing through the SBD. In Figure 12(b), the solid arrows indicate the current flowing through the pn junction diode.

[0118] As shown in Figure 12(a), the current flowing through the SBD wraps around to the bottom of the body region 30. As a result, electrostatic potential wraps around to the drift region 28 opposite the bottom of the body region 30. This electrostatic potential wraps around to the drift region 28, which is the opposite of the bottom of the body region 30, and reduces the voltage applied between the body region 30 and the drift region 28.

[0119] Therefore, the forward voltage (Vf) of the pn junction diode is less likely to be exceeded at the bottom of the body region 30. In other words, the forward voltage (Vf) of the pn junction diode of MOSFET 901 in the first comparative example can be made higher compared to the case where an SBD is not provided. As a result, the bipolar operation of the pn junction diode is suppressed, and the formation of stacking faults in the silicon carbide layer 10 due to carrier recombination energy is suppressed.

[0120] The forward voltage (Vf) of the pn junction diode in the first comparative example MOSFET901 depends on the distance between two adjacent SBDs in the first direction. By reducing the distance between two adjacent SBDs in the first direction, the forward voltage (Vf) of the pn junction diode in the first comparative example MOSFET901 can be increased.

[0121] In some cases, a large surge current exceeding the steady state may be applied to the MOSFET momentarily. The surge current flows from the source electrode 12 towards the drain electrode 14.

[0122] When a large surge current flows, a large surge voltage is applied, causing heat generation and damaging the MOSFET. The maximum allowable peak current value (I) of the surge current that can be tolerated by the MOSFET. FSM This is referred to as surge current withstand capability. In MOSFETs equipped with SBDs, it is desirable to improve the surge current withstand capability.

[0123] When a large surge voltage is applied to MOSFET901 in the first comparative example, the voltage applied across the pn junction of the pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode.

[0124] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 12(b).

[0125] Figure 13 is a schematic cross-sectional view of the semiconductor device of the second comparative example. Figure 13 corresponds to Figure 10 of the first comparative example.

[0126] The MOSFET902 in the second comparative example differs from the MOSFET901 in the first comparative example in that its transistor region does not contain an SBD. The built-in diode in the MOSFET902 in the second comparative example is only a pn junction diode.

[0127] Figure 14 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 14 is a diagram showing the voltage-current characteristics of the built-in diodes of MOSFET901 of the first comparative example and MOSFET902 of the second comparative example.

[0128] As shown in Figure 14, in the second comparative example, MOSFET 902, current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf2 of the pn junction diode is applied. On the other hand, in the first comparative example, MOSFET 901, current flows through the SBD until the forward voltage Vf1 of the pn junction diode is applied. In the first comparative example, MOSFET 901, current flows through the pn junction diode when a voltage equal to or greater than the forward voltage Vf1 of the pn junction diode is applied.

[0129] Since MOSFET 901 of the first comparative example operates unipolar up to the forward voltage Vf1, the slope of the current increase is smaller compared to MOSFET 902 of the second comparative example. Therefore, the maximum allowable peak current value I of MOSFET 902 of the second comparative example is FSM Compared to 2, the maximum allowable peak current value I of the MOSFET901 in the first comparative example FSM 1 becomes smaller. In other words, the surge current withstand capability of MOSFET901 in the first comparative example becomes smaller than the surge current withstand capability of MOSFET902 in the second comparative example.

[0130] The MOSFET 903 of the third comparative example differs from the MOSFET 100 of the first embodiment only in that it does not have an inorganic insulating layer 42.

[0131] The MOSFET 903 of the third comparative example, like the MOSFET 100 of the first embodiment, includes a diode region 102 provided between the transistor regions 101. The inclusion of the diode region 102 in the MOSFET 903 of the third comparative example improves its surge current withstand capability. This will be described in detail below.

[0132] Figures 15(a) and 15(b) are explanatory diagrams illustrating the operation and effects of the semiconductor device of the first embodiment. Figures 15(a) and 15(b) are schematic cross-sectional views of the MOSFET 903 of the third comparative example. Figures 15(a) and 15(b) correspond to Figure 4(a).

[0133] Figures 15(a) and 15(b) show the current flowing through the built-in diode of the MOSFET903 of the third comparative example. Figure 15(a) shows the state where forward current flows only through the SBD, and Figure 15(b) shows the state where forward current flows through both the SBD and the pn junction diode.

[0134] Specifically, Figure 15(a) shows a state where the voltage applied across the pn junctions of a pn junction diode is lower than the forward voltage (Vf) of the pn junction diode. Figure 15(b) shows a state where the voltage applied across the pn junctions of a pn junction diode is higher than the forward voltage (Vf) of the pn junction diode.

[0135] In Figures 15(a) and 15(b), the dotted arrows indicate the current flowing through the SBD. In Figure 15(b), the solid arrows indicate the current flowing through the pn junction diode.

[0136] In the diode region 102, the second distance d2 between two adjacent second portions 28b separated by the p region 32 is substantially equal to the first distance d1 between two adjacent first portions 28a separated by the body region 30 in the transistor region 101. In other words, the diode region 102 has second portions 28b spaced at the same intervals as the first portions 28a in the transistor region 101. To put it another way, the diode region 102 has SBD regions spaced at the same intervals as the transistor region 101.

[0137] Therefore, as shown in Figure 15(a), in the diode region 102, the current flowing through the SBD flows around to the bottom of the p region 32. As a result, it becomes less likely for the forward voltage (Vf) of the pn junction diode to be exceeded at the bottom of the p region 32. The forward voltage (Vf) of the pn junction diode in the diode region 102 is increased by the presence of the SBD region.

[0138] When the voltage applied across the pn junction of a pn junction diode becomes higher than the forward voltage (Vf) of the pn junction diode, current flows through the pn junction diode, as shown in Figure 15(b).

[0139] In the third comparative example, MOSFET903, the occupancy rate per unit area of ​​the p-region 32 projected onto the first surface P1 is greater than the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. That is, the occupancy rate of the pn junction diode in the diode region 102 is greater than the occupancy rate of the pn junction diode in the transistor region 101.

[0140] Furthermore, the contact area per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is larger than the contact area per unit area between the source electrode 12 and the body region 30 in the transistor region 101. In other words, the contact resistance per unit area between the source electrode 12 and the p-region 32 in the diode region 102 is smaller than the contact resistance per unit area between the source electrode 12 and the body region 30 in the transistor region 101.

[0141] Therefore, the current flowing through the pn junction diode in diode region 102 is greater than the current flowing through the pn junction diode in transistor region 101.

[0142] Furthermore, the large current flowing through the pn junction diode in diode region 102 causes carrier propagation and heat propagation to the adjacent transistor region 101. Consequently, conductivity modulation in the transistor region 101 adjacent to diode region 102 is promoted. Therefore, the current flowing through the pn junction diode in the transistor region 101 adjacent to diode region 102 becomes larger.

[0143] Figure 16 is an explanatory diagram of the operation and effects of the semiconductor device of the first embodiment. Figure 16 is a diagram showing the voltage-current characteristics of the built-in diodes of MOSFET901 of the first comparative example, MOSFET902 of the second comparative example, and MOSFET903 of the third comparative example.

[0144] As shown in Figure 16, in the third comparative example MOSFET903, current flows through the SBD until the forward voltage Vf3 of the pn junction diode is applied. In the third comparative example MOSFET903, when a voltage equal to or greater than the forward voltage Vf3 of the pn junction diode is applied, current flows through the pn junction diode.

[0145] In the third comparative example, the diode region 102 of MOSFET 903 is provided with an SBD region at the same interval as the transistor region 101. Therefore, the forward voltage Vf3 of the pn junction diode in MOSFET 903 of the third comparative example is equivalent to the forward voltage Vf1 of the pn junction diode in the MOSFET of the first comparative example.

[0146] On the other hand, in the third comparative example MOSFET903, the current after exceeding the forward voltage Vf3 of the pn junction diode is greater than the current after exceeding the forward voltage Vf1 of the pn junction diode in the first comparative example MOSFET901. This is because the current flowing through the pn junction diode in diode region 102 and the pn junction diode in transistor region 101 adjacent to diode region 102 is greater than in the first comparative example MOSFET901.

[0147] The current increases after the forward voltage Vf3 of the pn junction diode, which affects the maximum allowable peak current value I of the MOSFET903 in the third comparative example. FSM 3 is the maximum allowable peak current value I of the MOSFET903 in the third comparative example. FSM It becomes larger compared to 1. In other words, the surge current withstand capability of MOSFET903 in the third comparative example is greater than the surge current withstand capability of MOSFET903 in the third comparative example.

[0148] As described above, the MOSFET 903 of the third comparative example has improved surge current withstand capability by including a diode region 102 provided between transistor regions 101.

[0149] The occupancy rate per unit area of ​​the p region 32 projected onto the first surface P1 is preferably 1.2 times or more and 3 times or less of the occupancy rate per unit area of ​​the body region 30 projected onto the first surface P1. Exceeding the lower limit further improves the surge current withstand capability. Also, below the upper limit suppresses the decrease in the forward voltage Vf3 and suppresses the decrease in reliability.

[0150] Figure 17 is a schematic cross-sectional view of a semiconductor device of a third comparative example. Figure 17 corresponds to Figure 7 of the first embodiment.

[0151] Figure 18 is a schematic cross-sectional view of a semiconductor device of a third comparative example. Figure 18 corresponds to Figure 8 of the first embodiment.

[0152] The MOSFET 903 of the third comparative example differs from the MOSFET 100 of the first embodiment in that it does not have an inorganic insulating layer 42 between the source electrode 12 and the gate wiring 24.

[0153] In the third comparative example MOSFET903, there is no material between the source electrode 12 and the gate wiring 24. Furthermore, in the third comparative example MOSFET903, there is a resin layer (not shown) between the source electrode 12 and the gate wiring 24. The resin layer is, for example, polyimide.

[0154] Figures 19(a), 19(b), and 20 are explanatory diagrams illustrating the problems of the semiconductor device of the third comparative example. Figures 19(a) and 19(b) correspond to Figures 1(a) and 1(b) of the first embodiment. Figure 20 corresponds to Figure 17.

[0155] As described above, the MOSFET 903 of the third comparative example has improved surge current withstand capability by providing a diode region 102 between transistor regions 101. On the other hand, the MOSFET 903 of the third comparative example has the problem of large variations in surge current withstand capability from chip to chip. In other words, there is a problem that chips with low surge current withstand capability may occur by chance.

[0156] The inventors' failure analysis of chips with low surge current withstand capability revealed that one of the causes of low surge current withstand capability is a short circuit between the source electrode 12 and the gate wiring 24. It was found that the short circuit between the source electrode 12 and the gate wiring 24 occurs when the source electrode 12 adjacent to the gate wiring 24 melts and flows laterally, coming into contact with the gate wiring 24, as shown by the dotted circle in Figures 19(b) and 20.

[0157] It became clear that short circuits between the source electrode 12 and the gate wiring 24 are particularly likely to occur between the second region 12b of the source electrode 12 in the diode region 102 and the gate wiring 24, as shown in Figures 19(b) and 20.

[0158] The reason why a short circuit is likely to occur between the second region 12b and the gate wiring 24 is thought to be that the surge current flowing through the diode region 102 is larger than that flowing through the transistor region 101, resulting in greater heat generation. In other words, it is thought that the increased heat generation makes the source electrode 12 more likely to melt.

[0159] In the first embodiment of the MOSFET 100, as shown in Figures 6(b), 7, and 8, an inorganic insulating layer 42 is provided between the source electrode 12 and the gate wiring 24. The inorganic insulating layer 42 prevents the molten portion from flowing laterally and coming into contact with the gate wiring 24, even if the source electrode 12 melts. Therefore, a short circuit between the source electrode 12 and the gate wiring 24 is suppressed.

[0160] For example, if a resin layer is provided between the source electrode 12 and the gate wiring 24, it is difficult to suppress a short circuit between the source electrode 12 and the gate wiring 24 because the resin layer has low heat resistance. The inorganic insulating layer 42 has higher heat resistance compared to the resin layer, and therefore can suppress a short circuit between the source electrode 12 and the gate wiring 24.

[0161] (First variation) The semiconductor device of the first modification of the first embodiment differs from the semiconductor device of the first embodiment in that the peripheral region further includes a resin layer provided on an inorganic insulating layer.

[0162] Figure 21 is a schematic cross-sectional view of a first modified example of the first embodiment. Figure 21 corresponds to Figure 7 of the first embodiment.

[0163] Figure 22 is a schematic cross-sectional view of a first modified example of the first embodiment. Figure 22 corresponds to Figure 8 of the first embodiment.

[0164] The first modified MOSFET 110 includes a resin layer 44 on top of an inorganic insulating layer 42. The resin layer 44 has a function, for example, to suppress the intrusion of moisture into the interior of the MOSFET 110. The resin layer 44 also has a function, for example, to improve the adhesion between the MOSFET 110 and the sealing resin.

[0165] The resin layer 44 is, for example, polyimide.

[0166] (Second variation) The semiconductor device of the second modification of the first embodiment differs from the semiconductor device of the first embodiment in that the second distance between two adjacent second parts separated by a fourth silicon carbide region is greater than the first distance between two adjacent first parts separated by a second silicon carbide region.

[0167] The MOSFET of the second modified form has a structure similar to the MOSFET 100 of the first embodiment, except that the second distance d2 between two adjacent second portions 28b with a p region 32 in between is greater than the first distance d1 between two adjacent first portions 28a with a body region 30 in between. The second distance d2 is, for example, 1.1 times or more and 2 times or less than or equal to the first distance d1.

[0168] As the distance d2 increases, the forward voltage (Vf) of the pn junction diode in diode region 102 decreases. Therefore, when a large surge voltage is applied to the MOSFET in the second modified example, the current flowing through the pn junction diode in diode region 102 becomes larger compared to the MOSFET 100 in the first embodiment. Thus, the surge current withstand capability of the MOSFET is further improved.

[0169] Furthermore, from the viewpoint of preventing the forward voltage (Vf) of the pn junction diode in the diode region 102 from becoming too low, it is preferable that the second distance d2 be twice or less the first distance d1.

[0170] As described above, according to the first embodiment and its modifications, a MOSFET with improved surge current withstand capability is realized.

[0171] (Second embodiment) The semiconductor device of the second embodiment differs from the semiconductor device of the first embodiment in that the inorganic insulating layer is not provided between the first region of the first electrode and the gate wiring. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0172] Figures 23(a) and 23(b) are schematic top views of a semiconductor device according to the second embodiment. Figure 23(a) is a diagram showing the arrangement of each region of the MOSFET 200. Figure 23(b) is a diagram showing the electrode and inorganic insulating layer patterns on the top surface of the MOSFET 200.

[0173] Figure 24 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 24 is a cross-sectional view of HH' in Figures 23(a) and 23(b).

[0174] Figure 25 is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 25 is a cross-sectional view II' of Figures 23(a) and 23(b).

[0175] In the second embodiment, as shown in Figures 23(b) and 24, the MOSFET 200 is provided between the second region 12b of the source electrode 12 and the gate wiring 24 in the second direction. On the other hand, as shown in Figures 24(b) and 25, the inorganic insulating layer 42 is not provided between the first region 12a of the source electrode 12 and the gate wiring 24 in the second direction. The inorganic insulating layer 42 is provided only in a portion of the space between the source electrode 12 and the gate wiring 24.

[0176] In the second embodiment of the MOSFET 200, an inorganic insulating layer 42 is provided only between the second region 12b of the source electrode 12 in the diode region 102, which is prone to short circuits, and the gate wiring 24. By not providing the inorganic insulating layer 42 in other regions, disconnection of the gate wiring 24 due to stress migration, for example, can be suppressed.

[0177] (modified version) The semiconductor device of the modified second embodiment differs from the semiconductor device of the second embodiment in that the peripheral region further includes a resin layer provided on an inorganic insulating layer, and the resin layer is provided between the first region and the gate wiring in a direction parallel to the first surface.

[0178] Figure 26 is a schematic cross-sectional view of a modified example of the second embodiment. Figure 26 corresponds to Figure 24 of the second embodiment.

[0179] Figure 27 is a schematic cross-sectional view of a modified example of the second embodiment. Figure 27 corresponds to Figure 25 of the first embodiment.

[0180] In the modified MOSFET 210, a resin layer 44 is provided on top of the inorganic insulating layer 42. The resin layer 44 is also provided between the first region 12a of the source electrode 12 and the gate wiring 24 in the second direction.

[0181] The resin layer 44 is in contact with, for example, the side and top surfaces of the first region 12a. The resin layer 44 is also in contact with, for example, the side and top surfaces of the gate wiring 24. The resin layer 44 is provided, for example, between the side surface of the first region 12a and the side surface of the gate wiring 24.

[0182] The resin layer 44 has a function, for example, to suppress the intrusion of moisture into the interior of the MOSFET 210. Furthermore, the resin layer 44 has a function, for example, to improve the adhesion between the MOSFET 210 and the sealing resin.

[0183] The resin layer 44 is, for example, polyimide.

[0184] As described above, according to the second embodiment and its modifications, a MOSFET with improved surge current withstand capability is realized.

[0185] (Third embodiment) The semiconductor device of the third embodiment differs from the semiconductor device of the first embodiment in that a first transistor region is provided between a second diode region, which is at least one of the diode regions, and a first diode region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0186] Figures 28(a) and 28(b) are schematic top views of the semiconductor device of the third embodiment. Figure 28(a) is a diagram showing the arrangement of each region of the MOSFET 300 of the third embodiment. Figure 28(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET of the third embodiment. Figures 28(a) and 28(b) correspond to Figures 1(a) and 1(b) of the first embodiment.

[0187] As shown in Figure 28(a), the MOSFET 300 of the third embodiment includes a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a diode region 102a (first diode region), a diode region 102b, a diode region 102c (second diode region), a diode region 102d, a diode region 102e, a diode region 102f, and a peripheral region 103. Transistor region 101a is an example of the first transistor region. Transistor region 101b is an example of the second transistor region. Diode region 102a is an example of the first diode region. Diode region 102c is an example of the second diode region.

[0188] Hereinafter, transistor regions 101a, 101b, 101c, and 101d may be referred to individually or collectively simply as transistor region 101. Similarly, diode regions 102a and 102b may be referred to individually or collectively simply as diode region 102.

[0189] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0190] The diode region 102 is provided between the two transistor regions 101. For example, the diode region 102a is provided between the transistor region 101a and the transistor region 101b. The transistor region 101b is provided in a first direction parallel to the first plane P1 with respect to the transistor region 101a.

[0191] The transistor region 101 is located between the two diode regions 102. For example, transistor region 101a is located between diode region 102a and diode region 102c. Also, for example, transistor region 101b is located between diode region 102a and diode region 102d.

[0192] In the third embodiment, when a surge current flows through the MOSFET 300, the amount of heat generated in the diode region 102 is greater than the amount of heat generated in the transistor region 101. In the third embodiment, the diode regions 102 are distributed, so that the high-temperature regions within the MOSFET 300 chip are dispersed. Therefore, the failure of the MOSFET 300 due to heat generation is suppressed.

[0193] Furthermore, in the MOSFET 300 of the third embodiment, diode regions 102 are provided on both sides of the transistor region 101. Therefore, carrier propagation and heat propagation from the diode region 102 to the transistor region 101 are promoted. As a result, the current flowing through the pn junction diode of the transistor region 101 adjacent to the diode region 102 increases, further improving the surge current withstand capability.

[0194] As described above, according to the third embodiment, a MOSFET with further improved surge current withstand capability is realized.

[0195] (Fourth embodiment) The semiconductor device of the fourth embodiment differs from the semiconductor device of the first embodiment in that a third diode region, which is at least one of the diode regions, is provided between the first transistor region and the third transistor region, which is one of a plurality of transistor regions arranged in a second direction parallel to the first plane and perpendicular to the first direction with respect to the first transistor region. Hereafter, some descriptions that overlap with the first embodiment may be omitted.

[0196] Figures 29(a) and 29(b) are schematic top views of the semiconductor device according to the fourth embodiment. Figure 29(a) is a diagram showing the arrangement of each region of the MOSFET 400 according to the fourth embodiment. Figure 29(b) is a diagram showing the electrode and wiring patterns on the top surface of the MOSFET 400 according to the fourth embodiment. Figures 29(a) and 29(b) correspond to Figures 1(a) and 1(b) of the first embodiment.

[0197] As shown in Figure 29(a), the MOSFET 400 of the fourth embodiment includes a transistor region 101a (first transistor region), a transistor region 101b (second transistor region), a transistor region 101c, a transistor region 101d, a transistor region 101e (third transistor region), a transistor region 101g, a transistor region 101h, a diode region 102a (first diode region), a diode region 102b, a diode region 102c (third diode region), a diode region 102d, a diode region 102e, a diode region 102f, and a peripheral region 103. Transistor region 101a is an example of the first transistor region. Transistor region 101e is an example of the third transistor region. Diode region 102a is an example of the first diode region. Diode region 102c is an example of the third diode region.

[0198] Hereinafter, transistor regions 101a, 101b, 101c, and 101d may be referred to individually or collectively simply as transistor region 101. Similarly, diode regions 102a and 102b may be referred to individually or collectively simply as diode region 102.

[0199] A MOSFET and an SBD are provided in the transistor region 101. An SBD is provided in the diode region 102. No MOSFET is provided in the diode region 102.

[0200] The diode region 102 is provided between the two transistor regions 101. For example, the diode region 102a is provided between transistor region 101a and transistor region 101b. Transistor region 101b is provided in a first direction parallel to the first plane P1 with respect to transistor region 101a. The diode region 102a extends in a second direction.

[0201] Furthermore, for example, the diode region 102c is provided between the transistor region 101a and the transistor region 101e. The transistor region 101e is provided in a second direction parallel to the first plane P1 and perpendicular to the first direction with respect to the transistor region 101a. The diode region 102c extends in the first direction. The diode region 102c is in contact with the diode region 102a.

[0202] In the fourth embodiment, when a surge current flows through the MOSFET 400, the amount of heat generated in the diode region 102 is greater than the amount of heat generated in the transistor region 101. In the fourth embodiment, the diode regions 102 are distributed, thereby distributing the high-temperature regions of the MOSFET 400. Therefore, the breakdown of the MOSFET 400 due to heat generation is suppressed.

[0203] Furthermore, in the MOSFET 400 of the fourth embodiment, a diode region 102 is provided adjacent to the transistor region 101 in both the first and second directions. Therefore, carrier propagation and heat propagation from the diode region 102 to the transistor region 101 are promoted. As a result, the current flowing through the pn junction diode of the transistor region 101 adjacent to the diode region 102 increases, further improving the surge current withstand capability.

[0204] Furthermore, in the MOSFET 400 of the fourth embodiment, the diode region 102 extending in the first direction and the diode region 102 extending in the second direction are in contact. Therefore, the propagation of carriers and heat from the diode region 102 to the transistor region 101 is further promoted. As a result, the current flowing through the pn junction diode of the transistor region 101 adjacent to the diode region 102 increases, further improving the surge current withstand capability.

[0205] (Fifth embodiment) The inverter circuit and drive device of the fifth embodiment is an inverter circuit and drive device equipped with the semiconductor device of the first embodiment.

[0206] Figure 30 is a schematic diagram of the drive unit of the fifth embodiment. The drive unit 800 comprises a motor 140 and an inverter circuit 150.

[0207] The inverter circuit 150 consists of three semiconductor modules 150a, 150b, and 150c, each using a MOSFET 100 from the first embodiment as a switching element. By connecting the three semiconductor modules 150a, 150b, and 150c in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The motor 140 is driven by the AC voltage output from the inverter circuit 150.

[0208] According to the fifth embodiment, the characteristics of the inverter circuit 150 and the drive unit 800 are improved by providing a MOSFET 100 with improved characteristics.

[0209] (Sixth embodiment) The vehicle of the sixth embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0210] Figure 31 is a schematic diagram of a vehicle according to the sixth embodiment. The vehicle 900 of the sixth embodiment is a railway vehicle. The vehicle 900 includes a motor 140 and an inverter circuit 150.

[0211] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized. The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 900.

[0212] According to the sixth embodiment, the characteristics of the vehicle 900 are improved by providing a MOSFET 100 with improved characteristics.

[0213] (Seventh Embodiment) The vehicle of the seventh embodiment is a vehicle equipped with the semiconductor device of the first embodiment.

[0214] Figure 32 is a schematic diagram of a vehicle according to the seventh embodiment. The vehicle 1000 of the seventh embodiment is an automobile. The vehicle 1000 includes a motor 140 and an inverter circuit 150.

[0215] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0216] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the wheels 90 of the vehicle 1000.

[0217] According to the seventh embodiment, the characteristics of the vehicle 1000 are improved by providing a MOSFET 100 with improved characteristics.

[0218] (Eighth embodiment) The elevator of the eighth embodiment is an elevator equipped with the semiconductor device of the first embodiment.

[0219] Figure 33 is a schematic diagram of an elevator according to the eighth embodiment. The elevator 1100 of the eighth embodiment includes a car 610, a counterweight 612, a wire rope 614, a hoisting machine 616, a motor 140, and an inverter circuit 150.

[0220] The inverter circuit 150 is composed of three semiconductor modules, each using a MOSFET 100 as a switching element according to the first embodiment. By connecting the three semiconductor modules in parallel, a three-phase inverter circuit 150 with three AC voltage output terminals U, V, and W is realized.

[0221] The AC voltage output from the inverter circuit 150 drives the motor 140. The motor 140 rotates the hoisting machine 616, causing the cage 610 to rise and fall.

[0222] According to the eighth embodiment, the characteristics of the elevator 1100 are improved by providing a MOSFET 100 with improved characteristics.

[0223] In the first to fourth embodiments, the case of 4H-SiC as the crystal structure of SiC was described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. Furthermore, it is possible to apply a plane other than the (0001) plane to the surface of the silicon carbide layer 10.

[0224] In the first to fourth embodiments, the case in which the gate electrode 18 has a so-called stripe shape was described as an example, but the shape of the gate electrode 18 is not limited to a stripe shape. For example, the shape of the gate electrode 18 may be a grid shape.

[0225] In the first to fourth embodiments, aluminum (Al) was exemplified as a p-type impurity, but boron (B) can also be used. Furthermore, while nitrogen (N) and phosphorus (P) were exemplified as n-type impurities, arsenic (As), antimony (Sb), etc., can also be applied.

[0226] Furthermore, although the fifth to eighth embodiments were described using a configuration comprising the MOSFET 100 of the first embodiment as an example, it is also possible to use a configuration comprising the MOSFET of the second to fourth embodiments.

[0227] Furthermore, while the fifth to eighth embodiments described the application of the semiconductor device of the present invention to vehicles and elevators as examples, it is also possible to apply the semiconductor device of the present invention to, for example, a power conditioner for a solar power generation system.

[0228] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or modified with components of another embodiment. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. [Explanation of Symbols]

[0229] 10. Silicon carbide layer 12 Source electrode (first electrode) 12a First region 12b Second area 14. Drain electrode (second electrode) 16 Gate insulating layer 18 Guard gate 22 Pollution Pad 24 gate wiring 28. Drift region (first silicon carbide region) 28a Part 1 28b Second part 30 Body region (second silicon carbide region) 32 p region (fourth silicon carbide region) 34. Source region (third silicon carbide region) 42 Inorganic insulating layer 44 resin layer 100 MOSFETs (Semiconductor Devices) 101 Transistor Region 101a Transistor region (first transistor region) 101b Transistor region (second transistor region) 102 Diode region 102a Diode region (first diode region) 103 Peripheral area 800 Drive unit 900 vehicles 1000 vehicles 1100 Elevator P1 First side P2 Second side d1 First distance d2 Second distance

Claims

1. It comprises a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, The plurality of transistor regions are A silicon carbide layer having a first surface and a second surface facing the first surface, An n-type first silicon carbide region having a plurality of first portions in contact with the first surface, A p-type second silicon carbide region is provided between the first silicon carbide region and the first surface, A silicon carbide layer including an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The aforementioned peripheral region is The aforementioned silicon carbide layer, A gate electrode pad provided on the first surface side of the silicon carbide layer, A gate wire electrically connects the gate electrode pad and the gate electrode, and extends in a first direction parallel to the first surface. An inorganic insulating layer is provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction, The inorganic insulating layer includes a resin layer provided on top of the inorganic insulating layer, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode regions, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in the first direction relative to the first transistor region. The first electrode includes a first region of the plurality of transistor regions and a second region of at least one diode region. The inorganic insulating layer is provided between the second region and the gate wiring in the second direction. The inorganic insulating layer is provided between the first region and the gate wiring in the second direction, in a semiconductor device.

2. The semiconductor device according to claim 1, wherein the inorganic insulating layer is in contact with the upper and side surfaces of the first electrode, and the inorganic insulating layer is in contact with the upper and side surfaces of the gate wiring.

3. The semiconductor device according to claim 1, wherein the inorganic insulating layer comprises at least one of an oxide and a nitride.

4. The semiconductor device according to claim 1, wherein the inorganic insulating layer comprises at least one of silicon oxide and silicon nitride.

5. The semiconductor device according to claim 1, wherein the resin layer comprises polyimide.

6. The semiconductor device according to claim 1, wherein the first electrode, the gate electrode pad, and the gate wiring are formed of the same metallic material.

7. comprising a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, The plurality of transistor regions are A silicon carbide layer having a first surface and a second surface facing the first surface, An n-type first silicon carbide region having a plurality of first portions in contact with the first surface, A p-type second silicon carbide region is provided between the first silicon carbide region and the first surface, A silicon carbide layer including an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The aforementioned peripheral region is The aforementioned silicon carbide layer, A gate electrode pad provided on the first surface side of the silicon carbide layer, A gate wire electrically connects the gate electrode pad and the gate electrode, and extends in a first direction parallel to the first surface. The present invention includes an inorganic insulating layer provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode regions, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in the first direction relative to the first transistor region. A semiconductor device wherein the contact area per unit area between the first electrode and the fourth silicon carbide region is greater than the contact area per unit area between the first electrode and the second silicon carbide region.

8. The semiconductor device according to claim 1, wherein the second distance between two adjacent second portions separated by the fourth silicon carbide region is equal to the first distance between two adjacent first portions separated by the second silicon carbide region.

9. comprising a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, The plurality of transistor regions are A silicon carbide layer having a first surface and a second surface facing the first surface, An n-type first silicon carbide region having a plurality of first portions in contact with the first surface, A p-type second silicon carbide region is provided between the first silicon carbide region and the first surface, A silicon carbide layer including an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The aforementioned peripheral region is The aforementioned silicon carbide layer, A gate electrode pad provided on the first surface side of the silicon carbide layer, A gate wire electrically connects the gate electrode pad and the gate electrode, and extends in a first direction parallel to the first surface. The present invention includes an inorganic insulating layer provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode regions, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in the first direction relative to the first transistor region. A semiconductor device wherein the second distance between two adjacent second portions separated by the fourth silicon carbide region is greater than the first distance between two adjacent first portions separated by the second silicon carbide region.

10. The semiconductor device according to claim 9, wherein the second distance is less than or equal to twice the first distance.

11. comprising a plurality of transistor regions, at least one diode region, and a peripheral region surrounding the plurality of transistor regions and the at least one diode region, The plurality of transistor regions are A silicon carbide layer having a first surface and a second surface facing the first surface, An n-type first silicon carbide region having a plurality of first portions in contact with the first surface, A p-type second silicon carbide region is provided between the first silicon carbide region and the first surface, A silicon carbide layer including an n-type third silicon carbide region provided between the second silicon carbide region and the first surface, The plurality of first portions, the second silicon carbide region, and the first electrode in contact with the third silicon carbide region, A second electrode in contact with the second surface, A gate electrode facing the second silicon carbide region, The gate insulating layer is provided between the gate electrode and the second silicon carbide region, The at least one diode region is The silicon carbide layer includes an n-type first silicon carbide region having a plurality of second portions in contact with the first surface, and a p-type fourth silicon carbide region provided between the first silicon carbide region and the first surface, The first electrode in contact with the plurality of second portions and the fourth silicon carbide region, The above second electrode and, The aforementioned peripheral region is The aforementioned silicon carbide layer, A gate electrode pad provided on the first surface side of the silicon carbide layer, A gate wire electrically connects the gate electrode pad and the gate electrode, and extends in a first direction parallel to the first surface. The present invention includes an inorganic insulating layer provided between the first electrode and the gate wiring in a second direction parallel to the first surface and perpendicular to the first direction, The area occupied per unit area of ​​the fourth silicon carbide region projected onto the first surface is greater than the area occupied per unit area of ​​the second silicon carbide region projected onto the first surface. The first diode region, which is one of the at least one diode regions, is provided between the first transistor region, which is one of the plurality of transistor regions, and the second transistor region, which is one of the plurality of transistor regions, provided in the first direction relative to the first transistor region. A semiconductor device in which the width of the first diode region in the first direction is 30 μm or more.

12. An inverter circuit comprising a semiconductor device according to any one of claims 1 to 11.

13. A drive device comprising a semiconductor device according to any one of claims 1 to 11.

14. A vehicle comprising a semiconductor device according to any one of claims 1 to 11.

15. An elevator comprising a semiconductor device according to any one of claims 1 to 11.

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