Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of preventing warpage and a method of manufacturing the semiconductor device.SOLUTION: A semiconductor device according to one embodiment includes a conductive layer, a semiconductor portion, a first source electrode, a second source electrode, a first control electrode, and a second control electrode. The semiconductor portion is provided on the conductive layer. The semiconductor portion has a first element region and a second element region. A first end portion of the conductive layer is located inside a second end portion of the semiconductor portion in a plan view. An outer periphery formed by the first end portion surrounds both at least a part of a third end portion of the first element region and at least a part of a fourth end portion of the second element region.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device.

Background Art

[0002] In semiconductor devices such as vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), in order to reduce the on-resistance, increasing the thickness of the metal layer serving as the current path or reducing the thickness of the semiconductor substrate has been considered.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] On the other hand, in a semiconductor device, warpage may occur in the semiconductor device due to heat. For example, in a mounting process of soldering a semiconductor device on a mounting substrate, if warpage occurs in the semiconductor device, there is a risk of connection failure.

[0005] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device capable of suppressing warpage.

Means for Solving the Problems

[0006] The semiconductor device according to the embodiment includes a conductive layer, a semiconductor portion provided on the conductive layer, a first source electrode provided on the semiconductor portion, a second source electrode provided on the semiconductor portion away from the first source electrode, a first control electrode provided on the semiconductor portion and electrically isolated from the first source electrode and the second source electrode, and a second control electrode provided on the semiconductor portion and electrically isolated from the first source electrode, the second source electrode and the first control electrode. The semiconductor portion includes a first semiconductor region of a first conductivity type provided on the conductive layer, a second semiconductor region of a second conductivity type provided on the first semiconductor region, a third semiconductor region of a second conductivity type provided on the first semiconductor region away from the second semiconductor region, a fourth semiconductor region of a first conductivity type provided on the second semiconductor region, and a fifth semiconductor region of a first conductivity type provided on the third semiconductor region. The first source electrode is electrically connected to the second semiconductor region and the fourth semiconductor region. The second source electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. The first control electrode is positioned opposite the first semiconductor region, the second semiconductor region, and the third semiconductor region via a first insulating film. The second control electrode is positioned opposite the first semiconductor region, the fourth semiconductor region, and the fifth semiconductor region via a second insulating film. In a plan view, the first end of the conductive layer is located inward from the second end of the semiconductor portion, and the outer periphery formed by the first end surrounds at least a portion of the third end of the first element region including the second semiconductor region and at least a portion of the fourth end of the second element region including the fourth semiconductor region. [Brief explanation of the drawing]

[0007] [Figure 1] This is a schematic plan view illustrating a semiconductor device according to the first embodiment. [Figure 2] This is a schematic bottom view illustrating a semiconductor device according to the first embodiment. [Figure 3] This is a schematic cross-sectional view along line AA in Figure 1. [Figure 4] This is a schematic cross-sectional view along the line B1-B1 in Figure 1. [Figure 5] This is a schematic cross-sectional view along the line B2-B2 in Figure 1. [Figure 6] This is a schematic cross-sectional view along the CC line in Figure 1. [Figure 7] This is a schematic cross-sectional view of the DD line in Figure 1. [Figure 8] This is a schematic bottom view illustrating a semiconductor device according to a modified example of the first embodiment. [Figure 9] This is a schematic cross-sectional view along the line B3-B3 in Figure 8. [Figure 10] This is a schematic bottom view illustrating a semiconductor device according to another modification of the first embodiment. [Figure 11] This is a schematic cross-sectional view along the line B4-B4 in Figure 10. [Figure 12] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 13] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 14] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 15] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 16] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 17] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to the second embodiment. [Figure 18] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 19] This is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor device according to a second embodiment. [Figure 20] This is a schematic perspective cross-sectional view illustrating a magnified view of section E in Figure 17. [Figure 21] This is a schematic perspective cross-sectional view illustrating an enlarged version of the modified example corresponding to Figure 8, specifically the region corresponding to section E in Figure 17. [Figure 22] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 23] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 24] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 25] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 26] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 27] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 28] It is a schematic cross-sectional view illustrating a method of manufacturing a semiconductor device according to a third embodiment. [Figure 29] It is a schematic perspective cross-sectional view illustrating an enlarged view of part F in FIG. 26.

Embodiments for Carrying Out the Invention

[0008] Hereinafter, each embodiment of the present invention will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, there are cases where the dimensions and ratios are represented differently in the drawings. In the present specification and each figure, the same reference numerals are given to the same elements as those already described, and the detailed description is appropriately omitted. In the following description and drawings, n + 、n - and p +The notation "p" indicates the relative level of each impurity concentration. That is, a notation with "+" indicates a relatively higher impurity concentration than a notation without either "+" or "-", and a notation with "-" indicates a relatively lower impurity concentration than a notation without either. When both p-type and n-type impurities are present in each region, these notations represent the relative level of the net impurity concentration after the impurities have compensated for each other. Note that the carrier concentration is considered to be the effective impurity concentration. Each embodiment described below may be implemented by reversing the p-type and n-type of each semiconductor region.

[0009] (First Embodiment) Figure 1 is a schematic plan view illustrating a semiconductor device according to the first embodiment. Figure 2 is a schematic bottom view illustrating a semiconductor device according to the first embodiment. Figure 3 is a schematic cross-sectional view along line AA in Figure 1. As shown in Figures 1 to 3, the semiconductor device 100 according to this embodiment includes a semiconductor portion 10, a lower electrode (conductive layer) 11, a first source electrode 61, a second source electrode 62, a first gate electrode (first control electrode) 41, and a second gate electrode (second control electrode) 42. The first source electrode 61 is electrically connected to the first source electrode pad S1. The second source electrode 62 is electrically connected to the second source electrode pad S2. The first gate electrode 41 is electrically connected to the first gate electrode pad G1. The second gate electrode 42 is connected to the second gate electrode pad G2.

[0010] The semiconductor portion 10 is provided on the lower electrode 11. The first source electrode 61, the second source electrode 62, the first gate electrode 41, and the second gate electrode 42 are provided on the semiconductor portion 10.

[0011] In the following explanation, the Z-axis is a coordinate axis having a direction from the lower electrode 11 toward the semiconductor portion 10, and the direction in which the Z-axis points is sometimes called the Z-direction. The X-axis and Y-axis are coordinate axes perpendicular to the Z-axis. The direction in which the X-axis points is called the X-direction, and the direction in which the Y-axis points is sometimes called the Y-direction. For example, the plane containing the X-axis and Y-axis is parallel to the upper or lower surface of the semiconductor substrate 20a, which will be explained in relation to Figures 3 and 4. These directions are based on the relative positional relationship between the lower electrode 11 and the semiconductor portion 10, and do not limit the actual direction. The positive direction of the Z-axis is sometimes called "up" or "upward," and the negative direction of the Z-axis is sometimes called "down" or "downward," but this is unrelated to the direction of gravity. The Z-direction is, for example, the direction perpendicular to the upper surface of the semiconductor substrate. Viewing from the positive direction of the Z-axis toward the negative direction is sometimes called a top view, and viewing from the negative direction of the Z-axis toward the positive direction is sometimes called a bottom view. Also, top views and bottom views are sometimes not distinguished and are simply called plan views.

[0012] The semiconductor device 100 according to this embodiment includes a first element region R1 and a second element region R2. The first element region R1 and the second element region R2 are spaced apart from each other in the X direction. A first transistor Q1 is provided in the first element region R1, and a second transistor Q2 is provided in the second element region R2. The first transistor Q1 and the second transistor Q2 are, for example, MOSFETs.

[0013] A first source electrode pad S1 and a first gate electrode pad G1 are provided on the surface side of the first element region R1. In this example, one first gate electrode pad G1 is positioned between two first source electrode pads S1 aligned in the Y direction. The first source electrode pad S1 is electrically connected to the first source electrode 61 on top of it. The first gate electrode pad G1 is electrically isolated from the first source electrode pad S1 and the first source electrode 61.

[0014] Similarly, a second source electrode pad S2 and a second gate electrode pad G2 are provided on the surface side of the second element region R2. In this example, one second gate electrode pad G2 is positioned between two second source electrode pads S2 aligned in the Y direction. The second source electrode pad S2 is electrically connected to the second source electrode 62 on top of it. The second gate electrode pad G2 is electrically isolated from the second source electrode pad S2 and the second source electrode 62.

[0015] The first source electrode pad S1 and the second source electrode pad S2 are aligned in the X direction. The first gate electrode pad G1 and the second gate electrode pad G2 are aligned in the X direction. The arrangement and shape of each electrode pad shown in Figure 1 are examples, and embodiments are not limited to those shown.

[0016] When the semiconductor device 100 is viewed from below, as shown in Figure 2, the outer periphery of the first element region R1 and the outer periphery of the second element region R2 are located inside the outer periphery of the lower electrode 11. Furthermore, the outer periphery of the lower electrode 11 is located inside the outer periphery of the semiconductor portion 10.

[0017] The semiconductor portion 10 and the lower electrode 11 are rectangular in shape when viewed from above or below. The semiconductor portion 10 has ends 10a to 10d. End 10a is located opposite to end 10c. End 10b is located opposite to end 10d. Ends 10b and 10d are adjacent to ends 10a and 10c. The lower electrode 11 has ends 11a to 11d. End 11a is located opposite to end 11c. End 11b is located opposite to end 11d. Ends 11b and 11d are adjacent to ends 11a and 11c. The semiconductor portion 10 is rectangular with ends 10a to 10d as its outer circumference, and the lower electrode 11 is rectangular with ends 11a to 11d as its outer circumference.

[0018] The first element region R1 is, for example, rectangular in plan view and has four ends R1a to R1d. End R1a is positioned opposite to end R1c. End R1b is positioned opposite to end R1d. Ends R1b and R1d are adjacent to ends R1a and R1c. The second element region R2 is, for example, rectangular in plan view and has four ends R2a to R2d. End R2a is positioned opposite to end R2c. End R2b is positioned opposite to end R2d. Ends R2b and R2d are adjacent to ends R2a and R2c.

[0019] The first element region R1 and the second element region R2 are aligned apart in the X direction, with their ends R1c and R2c facing each other.

[0020] The shapes of the edges of the first element region R1 and the second element region R2 in a plan view are not limited to these and can be appropriately and arbitrarily set. The edge of the first element region R1 is, for example, the outermost interface in a plan view of the interface between the first base region 22 and the drift layer 20b, as described in relation to Figures 3 and 4. The edge of the second element region R2 is, for example, the outermost interface in a plan view of the interface between the second base region 24 and the drift layer 20b.

[0021] In the semiconductor device 100 according to this embodiment, the ends 11a to 11d of the lower electrode 11 only need to be located inside the ends 10a to 10d of the semiconductor portion 10. Preferably, the circumference formed by the ends 11a to 11d of the lower electrode 11 is located outside the ends R1a to R1d of the first element region R1 and outside the ends R2a to R2d of the second element region R2.

[0022] The lower electrode 11 is formed from a material having high conductivity. The lower electrode 11 includes, for example, metals such as aluminum, copper, silver, titanium, and tungsten. The conductivity of the lower electrode 11 is higher than that of the semiconductor part 10. The thickness of the lower electrode 11 is, for example, thinner than the thickness of the semiconductor part 10.

[0023] Figure 4 is a schematic cross-sectional view along the line B1-B1 in Figure 1. Figure 5 is a schematic cross-sectional view along the line B2-B2 in Figure 1. Figure 6 is a schematic cross-sectional view along the CC line in Figure 1. Figure 7 is a schematic cross-sectional view of the DD line in Figure 1. Note that Figures 6 and 7 are simplified to more clearly show the configuration of corresponding parts. Specifically, the number of multiple first gate electrodes 41 and their corresponding gate insulating films 51 is fewer than in the examples in Figures 4 and 5. Similarly, the number of multiple second gate electrodes 42 and their corresponding gate insulating films 52 is fewer than in the examples in Figures 4 and 5. In addition, Figures 6 and 7 show a simplified wiring structure for connecting multiple first gate electrodes 41 to each other and for electrical connection with the first gate electrode pad G1. Similarly, the wiring structure for connecting multiple second gate electrodes 42 to each other and for electrical connection with the second gate electrode pad G2 is also shown in a simplified manner. The detailed configuration of the semiconductor device 100 according to this embodiment will be described using Figures 3 to 7.

[0024] As shown in Figures 3 to 5, the semiconductor section 10 includes a semiconductor substrate 20a, a drift layer (first semiconductor region) 20b, a first base region (second semiconductor region) 22, a second base region (third semiconductor region) 24, a first source region (fourth semiconductor region) 23, and a second source region (fifth semiconductor region) 25. The semiconductor substrate 20a is provided on the lower electrode 11. The drift layer 20b is provided on the semiconductor substrate 20a. The semiconductor substrate 20a and the drift layer 20b are provided throughout the semiconductor section 10. In other words, the edges of the semiconductor substrate 20a and the drift layer 20b coincide with the edges 10a to 10d of the semiconductor section 10 shown in Figures 1 and 2. In other words, in a plan view, the outer periphery shape of the semiconductor substrate 20a and the drift layer 20b coincides with the outer periphery shape of the semiconductor section 10.

[0025] The first base region 22 and the second base region 24 are provided on the drift layer 20b and are spaced apart in the X direction. As shown in Figures 6 and 7, the first source region 23 is selectively provided on the first base region 22, and the second source region 25 is selectively provided on the second base region 24.

[0026] The semiconductor substrate 20a, the drift layer 20b, the first source region 23, and the second source region 25 are of the first conductivity type. The first base region 22 and the second base region 24 are of the second conductivity type. In the semiconductor device 100 described below, the first conductivity type is assumed to be n-type and the second conductivity type is assumed to be p-type. In embodiments, however, the first conductivity type may be p-type and the second conductivity type n-type.

[0027] The first base region 22 is located within the first element region R1. The second base region 24 is located within the second element region R2. For example, in a plan view, the outer perimeter of the first base region 22 coincides with the outer perimeter of the first element region R1, and the outer perimeter of the second base region 24 coincides with the outer perimeter of the second element region R2. In other words, the end of the first base region 22 coincides with the end of the first element region R1, and the end of the second base region 24 coincides with the end of the second element region R2.

[0028] As shown in Figures 6 and 7, the first base region 22 is provided with a plurality of first gate electrodes 41 via a first gate insulating film 51. The plurality of first gate electrodes 41 extend in a trench-like manner in the Z direction into the drift layer 20b. In addition, the second base region 24 is provided with a plurality of second gate electrodes 42 via a second gate insulating film 52. The plurality of second gate electrodes 42 extend in a trench-like manner in the Z direction into the drift layer 20b.

[0029] Within the trench T1, which includes the first gate electrode 41 and the first gate insulating film 51, an insulating portion 55 is provided between the first gate electrode 41 and the first source electrode 61. Furthermore, within the trench T2, which includes the second gate electrode 42 and the second gate insulating film 52, an insulating portion 56 is provided between the second gate electrode 42 and the second source electrode 61.

[0030] Multiple first gate electrodes 41 are arranged at approximately equal intervals in the Y direction within the first base region 22. In other words, multiple first gate electrodes 41 are arranged in the Y direction within the first element region R1. Similarly, multiple second gate electrodes 42 are arranged at approximately equal intervals in the Y direction within the second base region 24. In other words, multiple gate electrodes 42 are arranged at approximately equal intervals in the Y direction within the second element region R2.

[0031] As shown in Figure 3, the multiple first gate electrodes 41 are arranged in a striped pattern extending in the X direction within the first element region R1. The multiple second gate electrodes 42 are arranged in a striped pattern extending in the X direction within the second element region R2.

[0032] Although not shown, the first gate electrode 41 is electrically connected to the gate electrode pad G1 shown in Figure 1 via conductive parts such as gate contacts and gate wiring. Similarly, the second gate electrode 42 is also electrically connected to the gate electrode pad G1 shown in Figure 1 via conductive parts such as gate contacts and gate wiring (not shown).

[0033] The first source electrode 61 is provided on a plurality of first source regions 23 and is electrically connected to the plurality of first source regions 23. That is, the first source electrode pad S1 is electrically connected to the source region 23 via the first source electrode 61. The second source electrode 62 is provided on a plurality of second source regions 25 and is electrically connected to the plurality of second source regions 25. That is, the second source electrode pad S2 is electrically connected to the second source region 25 via the second source electrode 62.

[0034] An insulating layer 70 is provided between the first source electrode 61 and the second source electrode 62. The first gate electrode pad G1 is provided on the insulating layer 70. Although not shown, the second gate electrode pad G2 is also provided on the insulating layer 70. Therefore, each electrode pad is electrically isolated. A passivation layer 71 is provided on the insulating layer 70.

[0035] The semiconductor section 10 is configured as described above. The semiconductor substrate 20a, first base region 22, second base region 24, first source region 23, and second source region 25 of the semiconductor section 10 contain silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as n-type impurities. Boron can be used as a p-type impurity. In addition, the first source electrode 61, second source electrode 62, first source electrode pad S1, second source electrode pad S2, first gate electrode pad G1, and second gate electrode pad G2 contain metals such as aluminum, copper, silver, titanium, and tungsten.

[0036] In the above description, the first transistor Q1 and the second transistor Q2 are assumed to have a striped trench gate structure, but they are not limited to this and may have a mesh-like trench gate structure. Furthermore, they are not limited to a trench gate structure, but can have any other suitable transistor structure. For example, the first transistor Q1 and the second transistor Q2 may have a planar gate structure.

[0037] The operation and effects of the semiconductor device 100 according to this embodiment will be described. First, let's explain the electrical operation of the semiconductor device 100. The first transistor Q1 is a MOSFET having a semiconductor substrate 20a provided via a drift layer 20b as its drain electrode, and a first source electrode 61 and a first gate electrode 41. In the first transistor Q1, the current flowing between the drift layer 20b and the first source electrode 61 can be controlled by controlling the voltage of the first gate electrode 41 to the first source electrode 61. The second transistor Q2 is a MOSFET having a semiconductor substrate 20a provided via a drift layer 20b as its drain electrode, and a second source electrode 62 and a second gate electrode 42. In the second transistor Q2, the current flowing between the drift layer 20b and the second source electrode 62 can be controlled by controlling the voltage of the second gate electrode 42 to the second source electrode 62.

[0038] In the semiconductor device 100, the first transistor Q1 and the second transistor Q2 are electrically connected by a drift layer 20b. In other words, the semiconductor device 100 constitutes an inverse series circuit in which the first transistor Q1 and the second transistor Q2 are connected by their drain electrodes.

[0039] In the semiconductor device 100, the drift layer 20b is provided on the semiconductor substrate 20a, and the semiconductor substrate 20a is provided with a lower electrode 11, which is electrically connected to it. In other words, the lower electrode 11 is electrically connected to the drift layer 20b via the semiconductor substrate 20a. Here, the conductivity of the lower electrode 11 is sufficiently higher than the conductivity of the semiconductor substrate 20a and the drift layer 20b. Therefore, most of the current flowing through the first transistor Q1 and the second transistor Q2 is diverted to the lower electrode 11.

[0040] The dashed arrows in Figure 3 indicate the current paths cp1 and cp2 that are branched to the lower electrode 11. Current path cp1 is the path of the current flowing from the first source electrode pad S1 to the second source electrode pad S2. Current path cp2 is the path of the current flowing from the second source electrode pad S2 to the first source electrode pad S1. In this way, the current flowing between the first transistor Q1 and the second transistor Q2 flows along the thickness direction of the semiconductor part 10 and then flows in a direction that intersects the thickness direction of the lower electrode 11 at the lower electrode 11.

[0041] By reducing the thickness of the semiconductor portion 10, the resistance value in the direction of the current flowing through the semiconductor portion 10 can be reduced. Similarly, by increasing the thickness of the lower electrode 11, the resistance value in the direction of the current flowing through the lower electrode 11 can be reduced. In other words, in the semiconductor device 100, by reducing the thickness of the semiconductor portion 10 and increasing the thickness of the lower electrode 11, the voltage drop during conduction of the semiconductor device 100 can be suppressed, and heat loss can be reduced.

[0042] Next, the mechanical operation of the semiconductor device 100 will be described. Here, mechanical action refers to the application of shear stress based on the difference between the coefficient of thermal expansion of the semiconductor part 10 and the coefficient of thermal expansion of the lower electrode 11 when thermal stress is applied to the semiconductor device 100.

[0043] The semiconductor portion 10 and the lower electrode 11 are formed from the materials described above. The coefficient of linear expansion of the lower electrode 11 is greater than that of the semiconductor portion 10. When thermal stress is applied to such a semiconductor device 100, the lower electrode 11 expands more than the semiconductor portion 10, causing the semiconductor device 100 to warp in a convex direction in the negative Z-axis direction.

[0044] The warping of the semiconductor device 100, based on differences in the coefficient of thermal expansion, increases with increasing volume. Therefore, the thinner the semiconductor portion 10, the less the volume increase of the semiconductor portion 10 when thermal stress is applied. On the other hand, the thicker the lower electrode 11, the greater the volume increase of the lower electrode 11 when thermal stress is applied. To reduce the warping of the semiconductor device 100, it is necessary to increase the thickness of the semiconductor portion 10 and decrease the thickness of the lower electrode 11.

[0045] As described above regarding electrical operation, reducing the thickness of the semiconductor portion 10 and increasing the thickness of the lower electrode 11 is advantageous for the characteristics of the semiconductor device 100. On the other hand, from the viewpoint of reducing warping that occurs in the semiconductor device 100 due to shear stress generated based on the difference in coefficient of linear expansion, it is preferable to make the semiconductor portion 10 thicker and the lower electrode 11 thinner.

[0046] In other words, there is a trade-off relationship between electrical and mechanical properties, and the thickness of the semiconductor part 10 and the thickness of the lower electrode 11 are appropriately set for each semiconductor device, depending on the material of the semiconductor part 10 and the material of the lower electrode 11.

[0047] In the semiconductor device 100 according to this embodiment, in a plan view, the end of the lower electrode 11 is positioned inward from the end of the semiconductor device 100. The lower electrode 11 has sufficient thickness, and while achieving low resistance, its volume can be reduced, thereby suppressing the increase in volume when thermal stress is applied. Therefore, in the semiconductor device 100 according to this embodiment, warping of the semiconductor device 100 due to the application of thermal stress can be reduced.

[0048] Furthermore, the end of the lower electrode 11 is positioned outside the region spanning the first element region R1 and the second element region R2. In the semiconductor portion 10, current flows almost along the thickness direction of the semiconductor portion 10, so the current flowing through the semiconductor portion 10 can be more reliably guided to the lower electrode 11. As a result, the resistance between the first transistor Q1 provided in the first element region R1 and the second transistor Q2 provided in the second element region R2 can be effectively reduced.

[0049] The semiconductor device 100 having the configuration described above is used as a bidirectional switch circuit. The bidirectional switch circuit is mounted in a lithium-ion secondary battery battery pack, for example, to protect against over-discharge and overcharge of the lithium-ion secondary battery. Battery packs for lithium-ion secondary batteries continue to improve in energy capacity, and are becoming smaller and larger in capacity. To miniaturize the battery pack, it is necessary to miniaturize and thin the circuit board on which the bidirectional switch circuit is mounted, and higher mountability is required for the circuit components. Furthermore, the circuit components are required to suppress warping of the components even when flow mounting with high-temperature solder, etc., in order to achieve a high yield. The semiconductor device 100 according to this embodiment has reduced warping of the semiconductor device 100, so it can easily accommodate the miniaturization and thinning of such devices such as battery packs.

[0050] From the perspective of increasing the capacity of battery packs, higher performance of bidirectional switch circuits is required, specifically low on-resistance (low voltage drop). To achieve this, the size of the bidirectional switch circuit is unavoidable, and a bidirectional switch with performance that meets the requirements of the device is needed. The amount of warping of the semiconductor device 100 increases as the length of the semiconductor part 10 in the longitudinal direction increases. For example, using a simple approximation, the amount of warping increases in proportion to the square of the length in the longitudinal direction. When the semiconductor device 100 is enlarged to accommodate the increased capacity of battery packs, the absolute amount of warping of the semiconductor device 100 increases as the length of the semiconductor part 10 in the X or Y direction increases.

[0051] In the semiconductor device 100 according to this embodiment, since it is configured as described above, it is possible to enlarge the shape of the semiconductor portion 10 in plan view while suppressing an increase in the volume of the lower electrode 11.

[0052] As described above, the end of the lower electrode 11 can be appropriately positioned at any location based on the distribution of current density formed at the lower electrode 11 by the current flowing in the thickness direction of the semiconductor portion 10 in the first element region R1 and the second element region R2. That is, in a plan view, the outer circumference formed by the end of the lower electrode 11 does not necessarily have to surround all the ends of the first element region R1 and all the ends of the second element region R2, but rather it is sufficient that it surrounds at least a part of the ends of both the first element region R1 and at least a part of the ends of the second element region R2.

[0053] (Variation 1) Figure 8 is a schematic bottom view illustrating a semiconductor device according to a modified example of the first embodiment. Figure 9 is a schematic cross-sectional view along the line B3-B3 in Figure 8. As shown in Figures 8 and 9, the semiconductor device 100a according to this modified example includes a lower electrode 111. The lower electrode 111 differs from the lower electrode 11 of the semiconductor device 100 shown in Figures 1 to 5. In other respects, the semiconductor device 100a according to this modified example is the same as the semiconductor device 100, and the same reference numerals are used for the same components, and detailed descriptions are omitted.

[0054] The end of the lower electrode 111 coincides with the envelope of the end of the first element region R1 and the end of the second element region R2. The envelope of the end of the first element region R1 and the end of the second element region R2 is the line connecting the ends R1a, R1b, R2d, R2a, R2b, and R1d in Figures 1 and 2. For example, as shown in Figures 3 to 5, the end of the first element region R1 is the end of the first base region 22, and the end of the second element region R2 is the end of the second base region 24.

[0055] In this modified example, the current flowing between the first element region R1 and the lower electrode 111, and the current flowing between the second element region R2 and the lower electrode 111, can be guided to the lower electrode 111 without leakage and diverted. As a result, the semiconductor device 100a can achieve a sufficiently low on-resistance value while suppressing an increase in the volume of the lower electrode 111.

[0056] In this modified example as well, the end of the lower electrode 111 can be appropriately positioned at any desired location based on the distribution of current density formed at the lower electrode 111 by the current flowing in the thickness direction of the semiconductor portion 10 in the first element region R1 and the second element region R2.

[0057] (Modification 2) Figure 10 is a schematic bottom view illustrating a semiconductor device according to another modification of the first embodiment. Figure 11 is a schematic cross-sectional view along the line B4-B4 in Figure 10. As shown in Figures 10 and 11, the semiconductor device 100b according to this modified example includes a lower electrode 211. The lower electrode 211 differs from the lower electrode 11 of the semiconductor device 100 shown in Figures 1 to 4. In other respects, the semiconductor device 100b according to this modified example is the same as the semiconductor device 100, and the same reference numerals are used for the same components, and detailed descriptions are omitted.

[0058] The lower electrode 211 has the shape of a frustum. This frustum is approximately square in plan view, and may have rounded corners. The frustum has an upper surface 212a and a lower surface 212b. The upper surface 212a of the frustum is a region enclosed by ends 211a1 to 211d1 that coincide with ends 10a to 10d of the semiconductor portion 10. For example, the lower surface 212b of the frustum is a region enclosed by ends 211a2 to 211d2 that coincide with the envelopes of the ends of the first element region R1 and the second element region R2. In other words, the lower electrode 211 is a frustum that gradually narrows from the positive Z-axis to the negative Z-axis. The side surface of the frustum is not limited to a straight line as in this example, but may be a convex or concave curved surface.

[0059] In this modified example, the lower electrode 211 has sufficient thickness in the region enclosed by the envelopes at the ends of the first element region R1 and the second element region R2 to reduce the resistance value in the direction intersecting the thickness direction of the semiconductor portion 10. On the other hand, outside the envelopes at the ends of the first element region R1 and the second element region R2, the lower electrode 211 is tilted to form a truncated square pyramid, thereby suppressing the increase in volume of the lower electrode 211 when thermal stress is applied.

[0060] In this modified example, by doing so, the current flowing between the first element region R1 and the lower electrode 211 and the current flowing between the second element region R2 and the lower electrode 211 can be guided to the lower electrode 211 without leakage and diverted. Therefore, a sufficiently low on-resistance value can be achieved while suppressing an increase in the volume of the lower electrode 111.

[0061] In this modified example, the inclined surface of the pyramidal pyramid does not have to be flat; it may be a curved surface that is convex in the negative direction of the Z-axis or convex in the positive direction of the Z-axis, or it may be a staircase-like shape with multiple steps.

[0062] In this modified example as well, the end of the lower electrode 211 can be appropriately positioned and shaped as any desired shape based on the distribution of current density formed at the lower electrode 211 by the current flowing in the thickness direction of the semiconductor portion 10 in the first element region R1 and the second element region R2.

[0063] (Second embodiment) The following describes a method for manufacturing the semiconductor device 100, which was described as the first embodiment. Figures 12 to 19 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. In Figures 12 to 19, the structure above the semiconductor substrate 20a of the semiconductor part 10 described in Figure 1, etc., is shown in a simplified manner to avoid complexity in the illustration. Similarly, Figures 22 to 28 in the third embodiment described later are also shown in a simplified manner. The simplified part is the semiconductor layer 1002, which includes the drift layer 20b, first base region 22, second base region 24, first source region 23, second source region 25, first gate electrode 41, and second gate electrode 42 of the semiconductor device 100 shown in Figures 3 to 5. Furthermore, the first source electrode 61, second source electrode 62, first source electrode pad S1, second source electrode pad S2, first gate electrode pad G1, and second gate electrode pad G2 shown in Figures 3 to 5 are formed on the semiconductor layer 1002, and an insulating layer 70 and a passivation layer 71 are also provided. In addition, in the semiconductor layer 1002, only the portion corresponding to the drift layer 20b is provided on the semiconductor substrate 20a in the area corresponding to the dicing line Ld.

[0064] As shown in Figure 12, an intermediate member 1000 is prepared. The intermediate member 1000 includes a semiconductor substrate 1001 and semiconductor layers 1002. Multiple semiconductor layers 1002 are formed on the semiconductor substrate 1001. The semiconductor substrate 1001 has a first surface 1001a and a second surface 1001b. The second surface 1001b is the surface located opposite the first surface. The multiple semiconductor layers 1002 are formed on the first surface 1001a of the semiconductor substrate 1001.

[0065] Multiple semiconductor layers 1002 are formed on a semiconductor substrate 1001, separated by a dicing width Wd. The semiconductor substrate 1001 is, for example, a silicon wafer, and the multiple semiconductor layers 1002 are formed in a grid pattern on the silicon substrate 1001. The dicing width Wd is provided to divide the semiconductor substrate 1001 into individual semiconductor layers 1002 by inserting a dicing blade, as will be described later. The dicing width Wd is preset according to the width of the dicing blade and the precision of the insertion position of the dicing blade.

[0066] In adjacent semiconductor layers 1002, the edges 1002a and 1002c of the semiconductor layer 1002 are spaced apart by the dicing width Wd.

[0067] As shown in Figure 13, a resist layer 1010 is formed on the second surface 1001b of the semiconductor substrate 1001 of the intermediate member 1000 shown in Figure 12, thereby forming the intermediate member 1000a. The resist layer 1010 is formed over the entire surface of the second surface 1001b.

[0068] As shown in Figure 14, a mask 1012 is formed on the side where the resist layer 1010 is formed. The mask 1012 is provided at a position corresponding to the dicing line Ld. The mask 1012 has a mask width Md that is equal to the dicing width Wd, which is the width of the dicing line.

[0069] The intermediate member 1000b on which the mask 1012 is formed is exposed from the side on which the resist layer 1010 is formed, and the resist layer 1010 is patterned.

[0070] As shown in Figure 15, after exposure, the mask 1012 shown in Figure 14 is removed, and a seed metal layer 1020 is formed on the second surface 1001b and the resist 1010a remaining by the mask 1012 to form the intermediate member 1000c. For example, vacuum deposition or sputtering can be used to form the seed metal layer 1020.

[0071] As shown in Figure 16, the resist 1010a shown in Figure 15 is removed to form the intermediate member 1000d. By removing the resist 1010a, the seed metal 1020a is formed at a position other than the position corresponding to the dicing line Ld. Therefore, the distance Sd between two adjacent seed metals 1020a is approximately equal to the dicing width Wd.

[0072] As shown in Figure 17, an intermediate member 1000e is formed by forming a lower electrode 1030 on the seed metal 1020a. The lower electrode 1030 can be formed, for example, by electroplating. By forming the lower electrode 1030 by electroplating, a sufficient thickness can be achieved.

[0073] Furthermore, by forming the lower electrode 1030 using electroplating, the lower electrode 1030 is formed at the position of the seed metal 1020a, so the distance Ed between two adjacent lower electrodes 1030 is approximately equal to the distance Sd between adjacent seed metals 1020a. In other words, adjacent lower electrodes 1030 are formed with their ends 11a and 11c separated by a distance Sd.

[0074] As shown in Figure 18, an intermediate member 1000f is formed by attaching a dicing sheet 1040 to the intermediate member 1000e shown in Figure 17. The dicing sheet 1040 is attached to the second surface 1001b side of the semiconductor substrate 1001. The dicing sheet 1040 is provided to prevent the separated semiconductor layers 1002 and semiconductor substrate 1001 from scattering after the intermediate member 1000f has been separated into semiconductor layers 1002.

[0075] The dicing blade 1100 is positioned in accordance with the dicing line Ld. On the dicing line Ld, the insertion position of the dicing blade 1100 is, for example, half the dicing width Wd. The dicing width Wd is set based on the width Wb of the dicing blade 1100 when the insertion position of the dicing blade 1100 is half the dicing width Wd. More specifically, 1 / 2Wd > 1 / 2Wb + the positioning accuracy of the dicing blade. By setting it in this way, it is possible to prevent the dicing blade 1100 from cutting the semiconductor layer 1002.

[0076] As shown in Figure 19, the intermediate member 1000f shown in Figure 18 is divided by the dicing blade 1100 to form multiple semiconductor devices 100. In the multiple semiconductor devices 100, the surfaces cut by the dicing blade 1100 form the ends. In the example in Figure 19, the semiconductor device 100 has one end 10a and the other end 10c. In two semiconductor devices 100 each having two adjacent semiconductor layers 1002, the end 10a of one semiconductor device 100 is positioned opposite the end 10c of the other semiconductor device 100 and is the end cut by one dicing blade 1100. Immediately after division, these ends 10a and 10c are separated by approximately the width Wb of the dicing blade.

[0077] Furthermore, the metal seed 1020a and lower electrode 1030 in the semiconductor device 100 after separation constitute the lower electrode 11. As shown in Figures 16 to 18, two adjacent seed metals 1020a are separated by a distance Sd, and two adjacent lower electrodes 1030 are separated by a distance Ed. Distances Sd and Ed are set to be equal to the dicing width Wd. On the other hand, the dicing width Wd is set to be sufficiently wide based on the width Wb of the dicing blade 1100 and the precision of the setting position of the dicing blade. Therefore, distances Sd and Ed are sufficiently longer than the width Wb of the dicing blade. In other words, in the semiconductor device 100, the ends of the lower electrode 11 are positioned inward from the ends of the semiconductor part 10. Immediately after separation, the ends 11a and 11c are separated by a distance Ed = Sd. Since the distance Ed=Sd is longer than the width Wb of the dicing blade, the end of the lower electrode 11 is located inward from the edge of the semiconductor substrate.

[0078] Figure 20 is a schematic perspective cross-sectional view illustrating an enlarged section E of Figure 17. As shown in Figure 20, in the intermediate member 1000e, the semiconductor layer 1002 includes a semiconductor substrate 20a, a drift layer 20b, and a first base region 22, and the edge of the first base region 22 is the edge R1a of the first element region R1. As has been described in detail in relation to Figures 3 to 6, the first source electrode 61 is formed on the first base region 22 via a first source region.

[0079] Outside the end R1a, in this example, a gate wiring Ga connected to the first gate electrode 41 shown in Figure 4 is provided, and the gate wiring Ga is covered by the insulating layer 70 and the passivation layer 71. Therefore, the end 1002a of the semiconductor layer 1002 is positioned outside the end R1a of the first element region R1. In other examples, other wiring layers, etc., may be formed in the region between the end of the semiconductor layer 1002 and the end of the first element region R1, and the dicing line Ld needs to have a sufficient distance between adjacent semiconductor layers 1002.

[0080] Figure 21 is a schematic perspective cross-sectional view illustrating an enlarged version of the area corresponding to section E in Figure 17, in the case of a modified example corresponding to Figure 8. In Figure 21, arrows indicate that the current in the first element region R1 flows in the thickness direction of the drift layer 20b and the semiconductor substrate 20a. As shown in Figure 21, regions that are not paths for the current flowing through the first element region R1 and the second element region R2 may be provided outside the edges of the first element region R1 and the second element region R2. In other words, Figure 21 shows that the current flowing in the thickness direction of the drift layer 20b and the semiconductor substrate 20a hardly flows outward from the edge R1a of the first element region R1. The edge 111a of the lower electrode 111 is determined based on a boundary that results in a sufficiently high current density when the current flowing in the thickness direction of the drift layer 20b and the semiconductor substrate 20a flows through the lower electrode 111. In the example in Figure 21, this boundary is the edge R1a of the first element region R1.

[0081] In the example shown in Figure 21, the position of the end 111a of the lower electrode 111 is as described in relation to Figure 14. This can be set by adjusting the width Md of the mask 1012. Specifically, by making the mask width Md sufficiently wider than the dicing width Wd, it is possible to position the end of the lower electrode 111 sufficiently inward from the end of the semiconductor portion 10. Furthermore, by using the end positions of the first element region R1 and the second element region R2, the mask width Md can be set so that the end of the lower electrode 111 aligns with the end positions of the first element region R1 and the second element region R2.

[0082] The effects of the semiconductor device manufacturing method according to this embodiment will be explained. In the semiconductor device manufacturing method according to this embodiment, by making the mask width Md of the seed metal for forming the lower electrode 11 the same as or wider than the dicing width Wd, the end of the lower electrode 11 can be reliably positioned inward from the end of the semiconductor portion 10. By forming the semiconductor device 100 in this manner, it is possible to form a semiconductor device 100 that exhibits less warping when thermal stress is applied.

[0083] In the semiconductor device manufacturing method according to this embodiment, by ensuring that the end of the lower electrode 11 is positioned inward from the end of the semiconductor portion 10, the dicing blade 1100 can avoid cutting the seed metal 1020a and the lower electrode 1030. By avoiding the cutting of the metal portion including the seed metal 1020a and the lower electrode 1030 by the dicing blade 1100, the generation of burrs on the metal portion due to cutting can be suppressed. Furthermore, by avoiding the cutting of the metal portion, chipping of the dicing blade 1100 can be prevented, thereby preventing chipping caused by such chipping, making the manufacturing of the semiconductor device 100 smoother and improving the quality of the semiconductor device 100.

[0084] (Third embodiment) The following describes the manufacturing method of the semiconductor device 100b, which was explained in relation to Figures 10 and 11. Figures 22 to 28 are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to a second embodiment. As shown in Figure 22, the intermediate member 1000 shown in Figure 12 is prepared, and a seed metal layer 2020 is formed on the second surface 1001b of the semiconductor substrate 1001 of the intermediate member 1000, thereby forming the intermediate member 2000a. The seed metal layer 2020 is formed over the entire surface of the second surface 1001b. For example, vacuum deposition or sputtering can be used to form the seed metal layer 2020.

[0085] As shown in Figure 23, a lower electrode layer 2030 is formed on the seed metal layer 2020 of the intermediate member 2000a shown in Figure 22, and the intermediate member 2000b is formed. For example, electroplating is used to form the lower electrode layer 2030, and the lower electrode layer 2030 is formed over the entire surface of the seed metal layer 2020 by electroplating. By forming the lower electrode layer 2030 by electroplating, a lower electrode layer 2030 of sufficient thickness can be formed.

[0086] As shown in Figure 24, a resist mask 2010 is formed on the lower electrode layer 2030, and an intermediate member 2000c is formed. The resist mask 2010 is provided at a position corresponding to the semiconductor layer 1002, and the distance Md1 between adjacent resist masks 2010 is set according to the dicing width Wd. For example, the distance Md1 between resist masks 2010 is set to be equal to or wider than the dicing width Wd.

[0087] As shown in Figure 25, the intermediate member 2000c shown in Figure 24 is immersed in an etching solvent to separate the seed metal layer 2020 and the lower electrode layer 2030, thereby forming an intermediate member 2000d having a lower electrode 2030a formed on the seed metal 2020a. In the formation of the intermediate member 2000d, the seed metal layer 2020 and the lower electrode layer 2030 are separated by wet etching, so the etching of the seed metal layer 2020 and the lower electrode layer 2030 proceeds in the same direction, and the seed metal 2020a and the lower electrode 2030a are formed into a dendritic shape that tapers in the direction from the first surface 1001a toward the second surface 1001b of the semiconductor substrate 1001.

[0088] As shown in Figure 26, the resist mask 2010 shown in Figure 25 is removed, and the intermediate member 2000e is formed.

[0089] As shown in Figure 27, an intermediate member 2000f is formed by attaching a dicing sheet 2040 to the intermediate member 2000e shown in Figure 26. The dicing sheet 2040 is provided to prevent the separated semiconductor layers 1002 and semiconductor substrate 1001 from scattering after the intermediate member 2000f has been separated into semiconductor layers 1002.

[0090] The dicing blade 1100 is positioned in accordance with the dicing line Ld. On the dicing line Ld, the insertion position of the dicing blade 1100 is, for example, half the dicing width Wd. The dicing width Wd is set based on the width Wb of the dicing blade 1100 when the insertion position of the dicing blade 1100 is half the dicing width Wd. More specifically, 1 / 2Wd > 1 / 2Wb + the positioning accuracy of the dicing blade. By setting it in this way, it is possible to prevent the dicing blade 1100 from cutting the semiconductor layer 1002.

[0091] As shown in Figure 28, the intermediate member 2000f shown in Figure 27 is divided by the dicing blade 1100 to form a plurality of semiconductor devices 100b. In the plurality of semiconductor devices 100b, the surfaces cut by the dicing blade 1100 form the ends. In the example in Figure 28, the semiconductor device 100b has one end 10a and the other end 10c. In the two semiconductor devices 100b, each having two adjacent semiconductor layers 1002, the end 10a of one semiconductor device 100 is located opposite the end 10c of the other semiconductor device 100 and is the end cut by one dicing blade 1100.

[0092] In two semiconductor devices 100b, each having two adjacent semiconductor layers, the distance between the resist masks 2010 is Md1, which is set based on the dicing width Wd. This distance Md1 can be the same as or wider than the dicing width Wd. Therefore, the distance between the end 211c1 of one lower electrode 211 and the end 211a1 of the adjacent lower electrode 211 can be set to Md1. The distance between the end 10c of the semiconductor portion 10 and the adjacent end 10a is approximately the blade width Wb. Therefore, the end of the lower electrode 211 can be aligned with or inward from the end of the semiconductor portion 10. The distance between the end 211c2 of the lower electrode 211 at a position where the semiconductor substrate 1001 narrows in the direction from the first surface 1001a toward the second surface 1001b, and the end 211a2 of the adjacent lower electrode 211, can be further widened than the distance between the end 211c1 and the end 211a1.

[0093] Figure 29 is a schematic perspective cross-sectional view illustrating an enlarged view of section F in Figure 26. As shown in Figure 29, the distance between the edges 1002c and 1002a of adjacent semiconductor layers 1002 can be the width Md1 of the mask shown in Figure 24, which is set based on the dicing width Wd. Therefore, in the example in Figure 29, the position of the edge 211c1 of the lower electrode 211 can be made to coincide with the edge 1002c of the semiconductor layer 1002, or to be located inside the edge 1002c.

[0094] Since wet etching is used to form the lower electrode 211, etching progresses more from the first surface 1001a to the second surface 1001b of the semiconductor substrate 1001, allowing the side surface of the lower electrode 211 to have a tapered shape. The degree of taper can be appropriately set by the wet etching conditions, etc. In the example of Figure 29, by making the end 211c2 of the lower electrode 211 outside the end R1a of the first element region R1, sufficient thickness of the lower electrode 211 can be ensured in the first element region R1.

[0095] In this modified example, the distance between adjacent seed metals 2020a can be set by the mask width Md1. The mask width Md1 can be set based on the dicing width Wd. Sufficient distance can be ensured so that the semiconductor layer 1002 is not cut by the dicing blade 1100. For example, by setting the mask width Md1 to the same as the dicing width Wd, the formation of the resist mask 2010 becomes easier.

[0096] In this way, a semiconductor device capable of suppressing warping and a method for manufacturing a semiconductor device can be realized.

[0097] Although several embodiments of the present invention have been illustrated above, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims of the invention and its equivalents. Furthermore, the embodiments described above can be implemented in combination with each other.

[0098] The embodiments include the following aspects:

[0099] (Note 1) A conductive layer, A semiconductor portion provided on the conductive layer, A first source electrode provided on the semiconductor portion, On the semiconductor portion, a second source electrode is provided, which is located away from the first source electrode. A first control electrode is provided in the semiconductor portion and is electrically isolated from the first source electrode and the second source electrode, A second control electrode is provided in the semiconductor portion and is electrically isolated from the first source electrode, the second source electrode, and the first control electrode, Equipped with, The aforementioned semiconductor section is A first semiconductor region of a first conductivity type provided on the conductive layer, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of the first conductivity type is provided on the third semiconductor region, Includes, The first source electrode is electrically connected to the second semiconductor region and the fourth semiconductor region. The second source electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. The first control electrode is positioned opposite the first semiconductor region, the second semiconductor region, and the third semiconductor region via a first insulating film. The second control electrode is positioned opposite the first semiconductor region, the fourth semiconductor region, and the fifth semiconductor region via a second insulating film. In plan view, The first end of the conductive layer is located inside the second end of the semiconductor portion. A semiconductor device in which the outer periphery, comprising the first end, surrounds at least a portion of the third end of the first element region including the second semiconductor region and at least a portion of the fourth end of the second element region including the fourth semiconductor region.

[0100] (Note 2) The semiconductor device according to Appendix 1, wherein, in a plan view, the first end is located outside the third end and outside the fourth end.

[0101] (Note 3) The semiconductor device according to Appendix 1 or 2, wherein, in a plan view, the third end coincides with the end of the second semiconductor region, and the fourth end coincides with the end of the fourth semiconductor region.

[0102] (Note 4) The conductive layer is a frustum having an upper surface facing the semiconductor portion and a lower surface located on the opposite side of the upper surface. The frustum is a semiconductor device as described in any one of the appendices 1 to 3, wherein the frustum tapers from the top surface to the bottom surface.

[0103] (Note 5) A step of preparing a semiconductor substrate having a first surface and a second surface located opposite the first surface, wherein a plurality of semiconductor layers are formed on the first surface, The process involves forming a mask layer on the second surface between two adjacent semiconductor layers, according to a first distance between the two semiconductor layers, among the plurality of semiconductor layers. A step of forming a conductive layer on the second surface and the mask layer, The process involves removing the mask layer to form two first conductive portions corresponding to the positions of the two semiconductor layers, The process of forming two second conductive parts on the two first conductive parts, A step of dicing the semiconductor substrate between the two semiconductor layers, It has, The first distance is set based on the settings of the dicing blade used to dice the semiconductor substrate. The width of the mask layer is set based on the first distance. The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type provided on the semiconductor substrate, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of the first conductivity type is provided on the third semiconductor region, A method for manufacturing a semiconductor device containing [a specific component].

[0104] (Note 6) The width of the aforementioned mask layer is The edge of the first element region including the second semiconductor region, and A method for manufacturing a semiconductor device according to Appendix 5, set based on the position of the edge of the second element region including the fourth semiconductor region.

[0105] (Note 7) A step of preparing a semiconductor substrate having a first surface and a second surface located opposite the first surface, wherein a plurality of semiconductor layers are formed on the first surface, The process involves forming a third conductive layer on the aforementioned second surface, The process involves forming a second mask layer on the third conductive layer between two adjacent semiconductor layers, according to a first distance between the two semiconductor layers, among the plurality of semiconductor layers. A step of dividing the aforementioned third conductive layer by etching to form two third conductive layers corresponding to the positions of the two semiconductor layers, A step of removing the mask layer and dicing the semiconductor substrate between the two semiconductor layers, It has, The first distance is set based on the settings of the dicing blade used to dice the semiconductor substrate. The width of the second mask layer is set based on the first distance. The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type provided on the semiconductor substrate, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of the first conductivity type is provided on the third semiconductor region, A method for manufacturing a semiconductor device containing [a specific component].

[0106] (Note 8) The method for manufacturing a semiconductor device according to Appendix 7, wherein the step of forming the two third conductive layers includes a wet etching step. [Explanation of symbols]

[0107] 10...Semiconductor portion, 10a~10d, 11a~11d, 111a~111d, 211a1~211d1, 211a2~211d2, R1a~R1d, R2a~R2d...Edges, 11, 111, 211...Lower electrodes, 20a...Semiconductor substrate, 20b...Drift layer, 22...First base region, 23...First source region, 24...Second base region, 25...Second source region, 41...First gate electrode, 42...Second gate electrode, 51, 52…Gate insulating film, 61…First source electrode, 62…Second source electrode, 70…Insulating layer, 71…Passivation layer, 100, 100a, 100b…Semiconductor device, 1001…Semiconductor substrate, 1002…Semiconductor layer, 1010…Resist layer, 1020, 2020…Seed metal layer, 1020a…Seed metal, 1030, 2030a…Bottom electrode, 1100…Dicing blade, 2030…Bottom electrode layer

Claims

1. A conductive layer, A semiconductor portion provided on the conductive layer, A first source electrode provided on the semiconductor portion, On the semiconductor portion, a second source electrode is provided, which is located away from the first source electrode. A first control electrode is provided in the semiconductor portion and is electrically isolated from the first source electrode and the second source electrode, A second control electrode is provided in the semiconductor portion and is electrically separated from the first source electrode, the second source electrode, and the first control electrode, Equipped with, The aforementioned semiconductor section is A first semiconductor region of a first conductivity type provided on the conductive layer, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of a first conductivity type is provided on the third semiconductor region, Includes, The first source electrode is electrically connected to the second semiconductor region and the fourth semiconductor region. The second source electrode is electrically connected to the third semiconductor region and the fifth semiconductor region. The first control electrode is arranged opposite the first semiconductor region, the second semiconductor region, and the third semiconductor region via a first insulating film. The second control electrode is positioned opposite the first semiconductor region, the fourth semiconductor region, and the fifth semiconductor region via a second insulating film. In plan view, The first end of the conductive layer is located inside the second end of the semiconductor portion. The outer periphery, which consists of the first end, surrounds at least a portion of the third end of the first element region including the second semiconductor region and at least a portion of the fourth end of the second element region including the fourth semiconductor region.

2. The semiconductor device according to claim 1, wherein, in a plan view, the first end is located outside the third end and outside the fourth end.

3. The semiconductor device according to claim 1, wherein, in a plan view, the third end coincides with the end of the second semiconductor region, and the fourth end coincides with the end of the fourth semiconductor region.

4. The conductive layer is a frustum having an upper surface facing the semiconductor portion and a lower surface located on the opposite side of the upper surface. The semiconductor device according to claim 1, wherein the frustum tapers from the upper surface to the lower surface.

5. A step of preparing a semiconductor substrate having a first surface and a second surface located opposite the first surface, wherein a plurality of semiconductor layers are formed on the first surface, The process involves forming a mask layer on the second surface between two adjacent semiconductor layers, according to a first distance between the two semiconductor layers, among the plurality of semiconductor layers. A step of forming a conductive layer on the second surface and the mask layer, The process involves removing the mask layer to form two first conductive parts (seed metals) corresponding to the positions of the two semiconductor layers, The process involves forming two second conductive portions on the two first conductive portions, A step of dicing the semiconductor substrate between the two semiconductor layers, It has, The first distance is set based on the settings of the dicing blade used to dice the semiconductor substrate. The width of the mask layer is set based on the first distance. The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type provided on the semiconductor substrate, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of a first conductivity type is provided on the third semiconductor region, A method for manufacturing a semiconductor device containing [a specific component].

6. The width of the aforementioned mask layer is The edge of the first element region including the second semiconductor region, and A method for manufacturing a semiconductor device according to claim 5, set based on the position of the edge of the second element region including the fourth semiconductor region.

7. A step of preparing a semiconductor substrate having a first surface and a second surface located opposite the first surface, wherein a plurality of semiconductor layers are formed on the first surface, The process involves forming a third conductive layer on the second surface, The process involves forming a second mask layer on the third conductive layer between two adjacent semiconductor layers, according to a first distance between the two semiconductor layers, among the plurality of semiconductor layers. A step of dividing the aforementioned third conductive layer by etching to form two third conductive layers corresponding to the positions of the two semiconductor layers, A step of removing the mask layer and dicing the semiconductor substrate between the two semiconductor layers, It has, The first distance is set based on the settings of the dicing blade used to dice the semiconductor substrate. The width of the second mask layer is set based on the first distance. The aforementioned semiconductor layer is A first semiconductor region of a first conductivity type provided on the semiconductor substrate, A second semiconductor region of a second conductivity type provided on the first semiconductor region, A third semiconductor region of a second conductivity type is provided on the first semiconductor region, separated from the second semiconductor region, A fourth semiconductor region of the first conductivity type is provided on the second semiconductor region, A fifth semiconductor region of a first conductivity type is provided on the third semiconductor region, A method for manufacturing a semiconductor device containing [a specific component].

8. The method for manufacturing a semiconductor device according to claim 7, wherein the step of forming the two third conductive layers includes a wet etching step.

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