Multilayer ceramic electronic components and mounting structures for multilayer ceramic electronic components

Abstract

Provided is a multilayer ceramic electronic component capable of suppressing deterioration in insulation resistance due to hydrogen.　In a multilayer ceramic electronic component according to the present invention, a first external electrode 30a has: a first base electrode layer 32a; a first lower plating layer 34a1 disposed on the first base electrode layer 32a; and a first upper plating layer 34a2 that is disposed on the first lower plating layer 34a1 excluding a first plating exposed region 35a, such that the first lower plating layer 34a1 has the first plating exposed region 35a exposed to a surface of the first external electrode 30a. A second external electrode 30b has: a second base electrode layer 32b; a second lower plating layer 34b1 disposed on the second base electrode layer 32b; and a second upper plating layer 34b2 that is disposed on the second lower plating layer 34b1 excluding a second plating exposed region 35b, such that the second lower plating layer 34b1 has the second plating exposed region 35b exposed to a surface of the second external electrode 30b.

Description

Technical Field

[0001] This invention relates to a multilayer ceramic electronic component and a mounting structure of the multilayer ceramic electronic component.

Background Art

[0002] A multilayer ceramic capacitor includes a laminate and external electrodes. The laminate includes an inner layer portion and an outer layer portion. The inner layer portion is formed by alternately laminating a plurality of ceramic layers and a plurality of internal electrode layers in a predetermined lamination direction. The outer layer portion is formed by disposing a ceramic layer on the surface of the inner layer portion so as to sandwich the inner layer portion in the lamination direction. The plurality of internal electrode layers are exposed at both end faces in the length direction orthogonal to the lamination direction. The external electrodes are disposed on the surface of the end faces so as to be electrically connected to the internal electrode layers exposed from the end faces. The external electrodes include a Ni plating layer for preventing solder erosion when mounting the multilayer ceramic capacitor on a substrate using solder, and a Sn plating layer disposed on the Ni plating layer for improving the application performance of the solder. The Ni plating layer and the Sn plating layer are usually formed by an electrolytic plating method.

[0003] Patent Document 1 discloses that hydrogen generated by a chemical reaction in a plating process for forming a plating layer deteriorates the performance of a multilayer ceramic capacitor. Specifically, hydrogen generated in the plating process is absorbed by the internal electrode layer, causing problems such as deterioration of dielectric loss and insulation resistance. To solve this problem, Patent Document 1 describes that, for example, by including a metal such as Ni in an internal electrode layer mainly composed of an Ag-Pd alloy or the like, absorption of hydrogen by the internal electrode layer is suppressed, and deterioration of the ceramic layer is suppressed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] However, although Patent Document 1 states that Ni inactivates the hydrogen absorption effect, research by the inventors of the present invention has shown that even when Ni or the like is included in the materials constituting the internal electrode layer and external electrodes, hydrogen is absorbed by the internal electrode layer and external electrodes, and depending on the temperature conditions, the absorbed hydrogen is released from the metal, and this hydrogen causes deterioration of the insulation resistance. In particular, when high temperature and high humidity load tests such as PCBT (Pressure Cooker Bias Test) are performed, the deterioration of the insulation resistance becomes significant due to the hydrogen released from the hydrogen-absorbing metal, which can lead to deterioration of the multilayer ceramic capacitor.

[0006] Therefore, the main objective of this invention is to provide a multilayer ceramic electronic component and a mounting structure for a multilayer ceramic electronic component that can suppress the deterioration of insulation resistance due to hydrogen. [Means for solving the problem]

[0007] The multilayer ceramic electronic component according to this invention comprises a laminate having a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, a plurality of first internal electrode layers disposed on the plurality of ceramic layers and drawn out to the first end surface, a plurality of second internal electrode layers disposed on the plurality of ceramic layers and drawn out to the second end surface, a first external electrode disposed on the first end surface, extending from the first end surface and disposed on a part of the first main surface, a part of the second main surface, a part of the first side surface, a part of the second side surface, and a part of the second side surface, and connected to the first internal electrode layer, and a second external electrode disposed on the second end surface, extending from the second end surface and disposed on a part of the first main surface, a part of the second main surface, and A multilayer ceramic electronic component comprising: a first external electrode disposed on a part of the side of a first and a part of the side of a second, and connected to a second internal electrode layer, wherein the first external electrode comprises a first underlayment electrode layer disposed on a laminate, a first underlayment plating layer disposed on the first underlayment electrode layer, and a first upper plating layer disposed on the first underlayment plating layer except for the first plating exposure region such that the first underlayment plating layer has a first plating exposure region exposed on the surface of the first external electrode, and the second external electrode comprises a second underlayment electrode layer disposed on a laminate, a second underlayment plating layer disposed on the second underlayment electrode layer, and a second upper plating layer disposed on the second underlayment plating layer except for the second plating exposure region such that the second underlayment plating layer has a second plating exposure region exposed on the surface of the second external electrode.

[0008] In the multilayer ceramic electronic component according to this invention, the first lower plating layer is exposed to the surface of the first external electrode in the first plating exposure region, so that hydrogen within the multilayer ceramic electronic component can be released to the outside of the multilayer ceramic electronic component from the first plating exposure region. Furthermore, since the second lower plating layer is exposed to the surface of the second external electrode in the second plating exposure region, hydrogen within the multilayer ceramic electronic component can be released to the outside of the multilayer ceramic electronic component from the second plating exposure region. In the plating process for forming the first and second lower plating layers and the first and second upper plating layers, hydrogen ions are generated by a chemical reaction. These hydrogen ions may be absorbed as hydrogen by at least one of the first and second lower plating layers, the first and second internal electrode layers, or the first and second base electrode layers. With the above configuration, the hydrogen absorbed by at least one of the layers (absorption layer) of the first and second lower plating layers, the first and second internal electrode layers, or the first and second base electrode layers can be released to the outside of the multilayer ceramic electronic component from the first and second plating exposed regions. Therefore, it is possible to suppress the hydrogen remaining absorbed in the absorption layer and to suppress the deterioration of insulation resistance due to hydrogen. In particular, even if the absorption layer contains a metal such as Ni that does not easily absorb hydrogen, the deterioration of the insulation resistance of the ceramic layer can be suppressed by releasing hydrogen to the outside of the multilayer ceramic electronic component from the first and second plating exposed regions. Furthermore, if the first and second plating exposure regions are formed on the first main surface side, and the second main surface side becomes the mounting surface for the multilayer ceramic capacitor on the mounting substrate, and solder is mainly applied to the first and second end faces, then hydrogen from the absorption layer can be efficiently released from the first main surface, which is not soldered and does not face the mounting substrate, through the first and second plating exposure regions. [Effects of the Invention]

[0009] According to this invention, it is possible to provide a multilayer ceramic electronic component and a mounting structure for a multilayer ceramic electronic component that can suppress the deterioration of insulation resistance due to hydrogen.

[0010] The above-mentioned objectives, other objectives, features, and advantages of this invention will become even clearer from the following description of embodiments for carrying out the invention, with reference to the drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of this invention. [Figure 2] It is a cross-sectional view taken along line II-II of FIG. 1. [Figure 3] It is a cross-sectional view taken along line III-III of FIG. 1. [Figure 4] It is a cross-sectional view taken along line IV-IV of FIG. 2. [Figure 5] It is a cross-sectional view taken along line V-V of FIG. 2. [Figure 6] It is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted on a mounting substrate using solder. [Figure 7] It is an explanatory diagram for explaining a calculation method according to the first example of the exposed area. [Figure 8] It is an explanatory diagram for explaining a calculation method according to the second example of the exposed area. [Figure 9] It is a partial cross-sectional view showing a state where the base electrode layer is exposed. [Figure 10] It is a partial cross-sectional view showing another state where the base electrode layer is exposed. [Figure 11] It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 12] It is a top view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 13] It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to the second embodiment of the present invention. [Figure 14] It is a cross-sectional view taken along line XIV-XIV of FIG. 11. [Figure 15] It is a cross-sectional view taken along line XV-XV of FIG. 11. [Figure 16] It is a cross-sectional view taken along line XVI-XVI of FIG. 14. [Figure 17] It is a cross-sectional view taken along line XVII-XVII of FIG. 14.

Mode for Carrying Out the Invention

[0012] A. First Embodiment 1.2-Terminal Multilayer Ceramic Capacitor As an example of a multilayer ceramic electronic component according to the first embodiment of the present invention, a 2-terminal multilayer ceramic capacitor will be described.

[0013] FIG. 1 is an external perspective view showing an example of a 2-terminal multilayer ceramic capacitor as a multilayer ceramic electronic component according to the first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of FIG. 1. FIG. 4 is a cross-sectional view taken along line IV-IV of FIG. 2. FIG. 5 is a cross-sectional view taken along line V-V of FIG. 2.

[0014] As shown in FIGS. 1 to 3, the 2-terminal multilayer ceramic capacitor 10 includes a rectangular parallelepiped-shaped laminate 12 and external electrodes 30 disposed at both ends of the laminate 12.

[0015] (1) Laminate The laminate 12 has a first main surface 12a and a second main surface 12b that face each other in the height direction x (lamination direction), a first side surface 12c and a second side surface 12d that face each other in the width direction y orthogonal to the height direction x, and a first end surface 12e and a second end surface 12f that face each other in the length direction z orthogonal to the height direction x and the width direction y. In the laminate 12 of the present embodiment, the corners and ridge lines are rounded. Here, the corner means a portion where three adjacent surfaces of the laminate 12 intersect, and the ridge line means a portion where two adjacent surfaces of the laminate 12 intersect. Further, irregularities or the like may be formed on a part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0016] The laminate 12 includes an outer layer 14a composed of multiple ceramic layers 14, and an inner layer 14b composed of one or more ceramic layers 14 and multiple internal electrode layers 16 arranged on them. The outer layer 14a is located on the side of the first main surface 12a and the side of the second main surface 12b of the laminate 12. The outer layer 14a is an aggregate of multiple ceramic layers 14 (first outer layer) located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a, and multiple ceramic layers 14 (second outer layer) located between the second main surface 12b and the internal electrode layer 16 closest to the second main surface 12b. The region sandwiched between the two outer layers 14a is the inner layer 14b. In the inner layer 14b, the ceramic layers 14 and internal electrode layers 16 are stacked alternately in the height direction x.

[0017] The portion of the laminate 12 sandwiched between the first outer layer and the second outer layer, where the first internal electrode layer 16a and the second internal electrode layer 16b (described later) face each other, is called the opposing portion (effective layer portion). The portion between the opposing portion and the first side surface 12c, and the portion between the opposing portion and the second side surface 12d, are also called the W gap or side gap. The portion between the opposing portion and the first end surface 12e, and the portion between the opposing portion and the second end surface 12f, which includes the lead-out electrode portion of either the first internal electrode layer 16a or the second internal electrode layer 16b, is also called the L gap or end gap.

[0018] The dimensions of the laminate 12 are not particularly limited.

[0019] As the dielectric material for forming the ceramic layer 14, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3 can be used. When the above dielectric material is included as the main component, depending on the desired properties of the laminate 12, a material with a lower content of minor components than the main component, such as Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds, may be used.

[0020] Furthermore, when a piezoelectric ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as a piezoelectric component. Specific examples of piezoelectric ceramic materials include, for example, PZT (lead zirconate titanate) based ceramic materials. Furthermore, when a semiconductor ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as a thermistor element. Specific examples of semiconductor ceramic materials include, for instance, spinel-based ceramic materials. Furthermore, when a magnetic ceramic material is used for the ceramic layer 14, the multilayer ceramic electronic component functions as an inductor element. When functioning as an inductor element, the internal electrode layer 16 becomes a coil-shaped conductor. Specific examples of magnetic ceramic materials include, for example, ferrite ceramic materials.

[0021] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of laminated ceramic layers 14 is preferably 10 or more and 2000 or less. This number of ceramic layers 14 is the sum of the number of ceramic layers 14 in the inner layer portion 14b and the number of ceramic layers 14 in the outer layer portion 14a on the first main surface 12a side and the outer layer portion 14a on the second main surface 12b side.

[0022] The laminate 12 has a plurality of internal electrode layers 16, consisting of a plurality of first internal electrode layers 16a drawn out from the first end face 12e and a plurality of second internal electrode layers 16b drawn out from the second end face 12f. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are embedded in the inner layer portion 14b so as to be alternately arranged at equal intervals along the height direction x of the laminate 12, with the ceramic layer 14 in between. The surfaces of the plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are generally parallel to the first main surface 12a and the second main surface 12b, and are, for example, roughly rectangular in plan view.

[0023] As shown in Figure 4, the first internal electrode layer 16a is arranged on a plurality of ceramic layers 14 and is located inside the laminate 12. The first internal electrode layer 16a has a first opposing electrode portion 26a facing the second internal electrode layer 16b, and a first drawn-out electrode portion 28a located on one end side of the first internal electrode layer 16a, extending from the first opposing electrode portion 26a to the first end face 12e of the laminate 12. The end of the first drawn-out electrode portion 28a is drawn out to the surface of the first end face 12e and exposed from the laminate 12. In other words, the first drawn-out electrode portion 28a is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the second end face 12f. The end of the first opposing electrode portion 26a is positioned recessed in the width direction from the surface of the second end face 12f.

[0024] The shape of the first opposing electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0025] The shape of the first lead-out electrode portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0026] The width of the first opposing electrode portion 26a of the first internal electrode layer 16a and the width of the first leading electrode portion 28a of the first internal electrode layer 16a may be the same, or one of them may be narrower.

[0027] As shown in Figure 5, the second internal electrode layer 16b is arranged on a plurality of ceramic layers 14 and is located inside the laminate 12. The second internal electrode layer 16b has a second opposing electrode portion 26b facing the first internal electrode layer 16a, and a second drawn-out electrode portion 28b located on one end side of the second internal electrode layer 16b, extending from the second opposing electrode portion 26b to the second end face 12f of the laminate 12. The end of the second drawn-out electrode portion 28b is drawn out to the surface of the second end face 12f and exposed from the laminate 12. In other words, the second drawn-out electrode portion 28b is not exposed on the first main surface 12a, the second main surface 12b, the first side surface 12c, the second side surface 12d, and the first end face 12e. The end of the second opposing electrode portion 26b is positioned recessed in the width direction from the surface of the first end face 12e.

[0028] The shape of the second opposing electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0029] The shape of the second lead-out electrode portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners may be rounded in plan view, or the corners may be formed at an angle in plan view (tapered). It may also be tapered in plan view with a slope towards one side.

[0030] The width of the second opposing electrode portion 26b of the second internal electrode layer 16b and the width of the second leading electrode portion 28b of the second internal electrode layer 16b may be the same, or one of them may be narrower.

[0031] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys. Furthermore, when the laminate 12 including the internal electrode layers 16 and the integrated object including the external electrodes 30 on the surface of the laminate 12 are fired simultaneously, the metal constituting the internal electrode layer 16 will form a compound with the metal contained in the external electrodes 30.

[0032] The thickness of each of the internal electrode layers 16, namely the first internal electrode layer 16a and the second internal electrode layer 16b, is preferably 0.40 μm or more and 0.50 μm or less. Furthermore, it is preferable that the total number of the first internal electrode layer 16a and the second internal electrode layer 16b is between 10 and 2000.

[0033] (2) External electrode External electrodes 30 are arranged on the first end face 12e and the second end face 12f of the laminate 12, as shown in Figures 1 to 3.

[0034] The external electrode 30 has a first external electrode 30a and a second external electrode 30b.

[0035] The first external electrode 30a is connected to the first internal electrode layer 16a and is positioned on at least the surface of the first end face 12e. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first external electrode 30a extends from the first end face 12e of the laminate 12 and is also positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as on a portion of the first side surface 12c and a portion of the second side surface 12d.

[0036] The second external electrode 30b is connected to the second internal electrode layer 16b and is positioned on at least the surface of the second end face 12f. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second external electrode 30b extends from the second end face 12f and is also positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as on a portion of the first side surface 12c and a portion of the second side surface 12d.

[0037] Within the laminate 12, capacitance is formed when the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other via the ceramic layer 14. As a result, capacitance can be obtained between the first external electrode 30a to which the first internal electrode layer 16a is connected and the second external electrode 30b to which the second internal electrode layer 16b is connected, and the characteristics of a capacitor are exhibited.

[0038] The external electrode 30 is preferably composed of a base electrode layer 32 and a plating layer 34. In this embodiment, the external electrode 30 includes a base electrode layer 32 containing a metal component and a plating layer 34 disposed on the base electrode layer 32. The plating layer 34 includes a first plating layer 34a and a second plating layer 34b. The first external electrode 30a includes a first base electrode layer 32a containing a metal component, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. The first external electrode 30a also has a first plating exposed region 35a exposed on the surface of the first external electrode 30a. The second external electrode 30b includes a second base electrode layer 32b containing a metal component, a second lower plating layer 34b1 disposed on the second base electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1. The second external electrode 30b also has a second plating exposed region 35b exposed on the surface of the second external electrode 30b.

[0039] (2-1) Base electrode layer The first base electrode layer 32a is connected to the first internal electrode layer 16a and is positioned on the surface of the first end face 12e. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 28a of the first internal electrode layer 16a. In this embodiment, the first base electrode layer 32a extends from the first end face 12e and is also positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d.

[0040] The second base electrode layer 32b is connected to the second internal electrode layer 16b and is positioned on the surface of the second end face 12f. In this case, the second base electrode layer 32b is electrically connected to the second lead electrode portion 28b of the second internal electrode layer 16b. In this embodiment, the second base electrode layer 32b extends from the second end face 12f and is also positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d.

[0041] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0042] (When the base electrode layer includes a baking layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer may consist of multiple layers. The baked layer is formed by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it, and may be baked simultaneously with the internal electrode layer 16 and the ceramic layer 14, or it may be baked after the internal electrode layer 16 and the ceramic layer 14 have been baked. When the baked layer is baked simultaneously with the internal electrode layer 16 and the ceramic layer 14, it is preferable to add a ceramic component instead of a glass component to form the baked layer. The ceramic component may be the same type of ceramic material as the ceramic layer 14, or a different type of ceramic material may be used. The ceramic component includes at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc. By including a glass component or a ceramic component in the baking layer, the adhesion between the laminate 12 and the base electrode layer 32, which is the baking layer, can be improved. The baking layer may also contain both a glass component and a ceramic component.

[0043] The thickness of the first and second baked layers in the central part of the height direction of the first and second base electrode layers 32a and 32b located at the first end face 12e and the second end face 12f is preferably, for example, 3 μm or more and 20 μm or less. Furthermore, when a base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, the thickness of the first and second baked layers in the central part of the length direction z, which are the first and second base electrode layers 32a and 32b located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, is preferably, for example, 1 μm or more and 20 μm or less.

[0044] (When the underlying electrode layer includes a conductive resin layer) The conductive resin layer may consist of multiple layers. The conductive resin layer may be positioned on top of the baking layer so as to cover it, or the conductive resin layer may be positioned directly on the laminate 12. To further explain the case where a conductive resin layer is placed on a baked layer, the conductive resin layer is placed so as to cover the base electrode layer 32, which is the baked layer. The conductive resin layer has a first conductive resin layer and a second conductive resin layer. The first conductive resin layer is placed so as to cover the first base electrode layer 32a, and the second conductive resin layer is placed so as to cover the second base electrode layer 32b. Specifically, the first and second conductive resin layers are placed on the first base electrode layer 32a and the second base electrode layer 32b, which are located on the first end face 12e and the second end face 12f. Furthermore, it is preferable that the first and second conductive resin layers are placed so as to extend to the first main surface 12a and the second main surface 12b, as well as the first side surface 12c and the second side surface 12d. However, the first and second conductive resin layers may be arranged only on the first and second base electrode layers 32a and 32b located on the first and second end faces 12e and 12f, respectively. If the external electrode 30 has a plating layer 34, the conductive resin layer can be arranged between the base electrode layer 32 and the plating layer 34.

[0045] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than conductive layers made of, for example, a plated film or a fired conductive paste. Therefore, even if the two-terminal multilayer ceramic capacitor 10 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the two-terminal multilayer ceramic capacitor 10.

[0046] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Furthermore, metal powders with an Ag coating on their surface can also be used. When using metal powders with an Ag coating on their surface, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high weather resistance. The reason for using Ag-coated metal powder is that it is possible to use an inexpensive base metal while maintaining the aforementioned properties of Ag.

[0047] Furthermore, the metals included in the conductive resin layer can also be Cu or Ni that have undergone oxidation prevention treatment. Furthermore, as the metal contained in the conductive resin layer, metal powder coated with Sn, Ni, or Cu can also be used. When using metal powder coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0048] Preferably, the metal contained in the conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, 0.3 μm to 10 μm. The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0049] The shape of the metal contained in the conductive resin layer is not particularly limited, and spherical, flattened, or other shapes can be used. It is preferable to use a mixture of spherical metal powder and flattened metal powder as the metal contained in the conductive resin layer.

[0050] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Preferably, the resin contained in the conductive resin layer is present in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0051] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0052] The thickness of the conductive resin layer located in the central part of the laminate 12 in the height direction, at the first end face 12e and the second end face 12f, is preferably, for example, 3 μm or more and 30 μm or less.

[0053] Furthermore, when conductive resin layers are also provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, it is preferable that the thickness of the conductive resin layer at the center of the longitudinal direction z of the conductive resin layer located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is, for example, 3 μm or more and 30 μm or less.

[0054] (When the underlying electrode layer includes a thin film layer) The thin film layer is a layer less than 1 μm thick in thickness, formed by a thin film formation method such as sputtering or vapor deposition, and in which metal particles are deposited.

[0055] (2-2) Plating layer Next, the first plating layer 34a and the second plating layer 34b, which are plating layers 34 placed on the base electrode layer 32, will be described with reference to Figures 2 to 5. This plating layer 34 has a plating exposure region 35.

[0056] The first plating layer 34a is arranged to cover the first underlay electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be arranged to cover the first underlay electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the first plating layer 34a may be arranged only on the first underlay electrode layer 32a on the first end face 12e side. This first plating layer 34a has a first lower plating layer 34a1 arranged on the first underlay electrode layer 32a and a first upper plating layer 34a2 arranged on the first lower plating layer 34a1. The first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 so as to expose a portion of the first lower plating layer 34a1. In other words, the first upper plating layer 34a2 is positioned on the first lower plating layer 34a1, excluding the first plating exposed region 35a, such that the first lower plating layer 34a1 has a first plating exposed region 35a that is exposed on the surface of the first external electrode 30a.

[0057] In this embodiment, the first plated exposed area 35a is located on the first main surface 12a. In this case, as shown in Figure 6, the second main surface 12b of the two-terminal multilayer ceramic capacitor 10 becomes the mounting surface to the mounting substrate 40. Figure 6 is a side view showing an example of a two-terminal multilayer ceramic capacitor mounted using solder. According to Figure 6, a pair of planar lands 41 for mounting the two-terminal multilayer ceramic capacitor 10 are formed on the mounting substrate 40. The two-terminal multilayer ceramic capacitor 10 is positioned such that the second main surface 12b faces the mounting surface of the mounting substrate 40, and the first main surface 12a is furthest from the mounting surface, with the first external electrode 30a and the second external electrode 30b located on each of the pair of lands 41. In this state, the two-terminal multilayer ceramic capacitor 10 is mounted on the mounting substrate 40 by applying solder 42 to the first end face 12e and the second end face 12f.

[0058] Although not limited thereto, it is preferable that the first upper plating layer 34a2 covers the edge of the first lower plating layer 34a1. Specifically, it is preferable that the tip of the first lower plating layer 34a1 on the second end face 12f side is covered by the tip of the first upper plating layer 34a2 on the second end face 12f side. This makes it possible to suppress peeling of the first lower plating layer 34a1.

[0059] Preferably, the first ratio of the area of ​​the first plated exposed area 35a to the area of ​​the exposed area of ​​the first external electrode 30a on the first main surface 12a when viewed from the height direction x of the laminate 12 is 0.4% or more and 83.4% or less. Because the first ratio is 0.4% or more, for example, hydrogen released from the first and second internal electrode layers 16a, 16b, the first and second underlayment electrode layers 32a, 32b, and the first and second lower plating layers 34a1, 34b1 can be sufficiently released from the first plated exposed area 35a to the outside of the two-terminal multilayer ceramic capacitor 10, thereby suppressing the deterioration of insulation resistance due to hydrogen. Also, because the first ratio is 83.4% or less, the proportion of the first lower plating layer 34a1 that is not covered by the first upper plating layer 34a2 can be suppressed. This makes it possible to suppress the decrease in moisture resistance due to water vapor intrusion into the two-terminal multilayer ceramic capacitor 10 from the first plated exposed area 35a. More preferably, the first percentage is 1.17% or more and 83.4% or less. Even more preferably, the first percentage is 1.40% or more and 83.4% or less. Even more preferably, the first percentage is 1.40% or more and 25.0% or less.

[0060] The first ratio can be determined as follows, as a first example. First, the area of ​​the exposed region of the first external electrode 30a can be determined from the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the exposed region of the first external electrode 30a can be determined from the area of ​​the region where the first external electrode 30a faces the outside of the two-terminal multilayer ceramic capacitor 10 on the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, and the second side surface 12d. Also, the area of ​​the first plating exposed region 35a can be determined from the area of ​​the region where the first lower plating layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10. For example, the area of ​​the first plating exposure region 35a can be determined from the area of ​​the region where the first lower plating layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10 on the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, and the second side surface 12d. Then, the first ratio can be determined from the ratio of the area of ​​the first plating exposure region 35a to the area of ​​the exposure region of the first external electrode 30a.

[0061] In the first example, as shown in Figure 7, the area S30a of the exposed region of the first external electrode 30a can be determined from the region on the first main surface 12a where the first external electrode 30a (first base electrode layer 32a, first lower plating layer 34a1, first upper plating layer 34a2) faces the outside of the two-terminal multilayer ceramic capacitor 10 when viewed from the first main surface 12a side (view in the direction of the first main surface). In addition, in this embodiment, the area S35a of the first plating exposed region 35a can be determined from the region where the first lower plating layer 34a1 faces the outside of the two-terminal multilayer ceramic capacitor 10 on all surfaces of the first main surface 12a, second main surface 12b, first end surface 12e, first side surface 12c, and second side surface 12d. Figure 7 shows an example configuration in which the first plating exposure region 35a is located on the side of the first main surface 12a. The first ratio can be determined from the ratio of the area S35a of the first plating exposure region 35a to the area S30a of the exposure region of the first external electrode 30a. The areas S30a and S35a can be observed, for example, using a microscope (for example, the VHX series manufactured by Keyence Corporation (hereinafter referred to as VHX)) at a magnification of 200x and in bright-field mode.

[0062] Furthermore, the first ratio can be determined as follows, as a second example. The area of ​​the exposed region of the first external electrode 30a is determined in the same way as in the first example. Also, if the first exposed plating region 35a intersects with the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, or the second side surface 12d due to the first lower plating layer 34a1 being scraped in addition to the first upper plating layer 34a2, the area of ​​the first exposed plating region 35a can be determined by multiplying the thickness of the exposed first lower plating layer 34a1 by the perimeter length of the first exposed plating region 35a. Then, the first ratio can be determined from the ratio of the area of ​​the first exposed plating region 35a to the area of ​​the exposed region of the first external electrode 30a.

[0063] In the second example, in this embodiment, similar to Figure 7, the area S30a of the exposed region of the first external electrode 30a can be determined from the region on the first main surface 12a that the first external electrode 30a faces outward on the two-terminal multilayer ceramic capacitor 10 when viewed from the first main surface 12a side (view in the direction of the first main surface). Furthermore, the area SS35a of the first plating exposed region 35a can be determined by multiplying the thickness t35a of the exposed first lower plating layer 34a1 by the length of the perimeter of the first plating exposed region 35a (sum of l35a1, l35a2, l35a3, l35a4), when the first plating exposed region 35a intersects with the first main surface 12a, the second main surface 12b, the first end surface 12e, the first side surface 12c, or the second side surface 12d. Figure 8 shows an example where the first plated exposed area 35a intersects with the first main surface 12a. The first ratio can be determined from the ratio of the area SS35a of the first plated exposed area 35a to the area S30a of the exposed area of ​​the first external electrode 30a. The lengths l35a1 to l35a4 can be observed, for example, using a microscope (VHX) at 200x magnification and in bright field. The thickness t35a can be observed, for example, by cross-polishing the cross section to, for example, half the width y dimension W of the two-terminal multilayer ceramic capacitor 10, and then using a microscope (VHX) at 2000x magnification and in bright field.

[0064] The second plating layer 34b is arranged to cover the second underlayer electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be arranged to cover the second underlayer electrode layer 32b on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be arranged only on the second underlayer electrode layer 32b on the second end face 12f side. This second plating layer 34b has a second lower plating layer 34b1 arranged on the second underlayer electrode layer 32b and a second upper plating layer 34b2 arranged on the second lower plating layer 34b1. The second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 so as to expose a portion of the second lower plating layer 34b1. In other words, the second upper plating layer 34b2 is positioned on the second lower plating layer 34b1, excluding the second plating exposure region 35b, such that the second lower plating layer 34b1 has a second plating exposure region 35b that is exposed on the surface of the second external electrode 30b. In this embodiment, the second plating exposure region 35b is positioned on the first main surface 12a. In this case, the second main surface 12b of the two-terminal multilayer ceramic capacitor 10 becomes the mounting surface for the mounting substrate.

[0065] Although not limited thereto, it is preferable that the second upper plating layer 34b2 covers the edge of the second lower plating layer 34b1. Specifically, it is preferable that the tip of the second lower plating layer 34b1 on the first end face 12e side is covered by the tip of the second upper plating layer 34b2 on the first end face 12e side. This makes it possible to suppress peeling of the second lower plating layer 34b1.

[0066] For the same reasons as the first ratio, the second ratio of the area of ​​the second plating exposed area 35b to the area of ​​the exposed area of ​​the second external electrode 30b on the first main surface 12a when viewed from the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. Because the second ratio is 0.4% or more, for example, hydrogen released from the first and second internal electrode layers 16a, 16b, the first and second underlayment electrode layers 32a, 32b, and the first and second underlayer plating layers 34a1, 34b1 can be sufficiently released from the second plating exposed area 35b to the outside of the two-terminal multilayer ceramic capacitor 10, thereby suppressing the deterioration of insulation resistance due to hydrogen. Also, because the second ratio is 83.4% or less, the decrease in moisture resistance due to water vapor intrusion into the two-terminal multilayer ceramic capacitor 10 from the second plating exposed area 35b can be suppressed. More preferably, the second proportion is 1.17% or more and 83.4% or less. Even more preferably, the second proportion is 1.40% or more and 83.4% or less. Even more preferably, the second proportion is 1.40% or more and 25.0% or less.

[0067] The second ratio can be determined in the same way as the first ratio. In the first example described above, in this embodiment, the area of ​​the exposed region of the second external electrode 30b can be determined from the area of ​​the region on the first main surface 12a where the second external electrode 30b (second base electrode layer 32b, second lower plating layer 34b1, second upper plating layer 34b2) faces the outside of the two-terminal multilayer ceramic capacitor 10, when viewed from the first main surface 12a side. Also in this embodiment, the area of ​​the second plating exposed region 35b can be determined from the area of ​​the region where the second lower plating layer 34b1 faces the outside of the two-terminal multilayer ceramic capacitor 10, when viewed from all surfaces of the first main surface 12a, second main surface 12b, second end surface 12f, first side surface 12c, and second side surface 12d.

[0068] Furthermore, in the case of the second example described above, in this embodiment, the area of ​​the exposed region of the second external electrode 30b can be determined in the same way as in the first example. Also, in this embodiment, the area of ​​the second plating exposed region 35b can be determined from the area obtained by multiplying the thickness of the exposed second lower plating layer 34b1 by the length of the perimeter of the second plating exposed region 35b, when the second plating exposed region 35b intersects with the first main surface 12a, the second main surface 12b, the second end surface 12f, the first side surface 12c, or the second side surface 12d. The second ratio can then be determined from the ratio of the area of ​​the second plated exposed area 35b to the area of ​​the exposed area of ​​the second external electrode 30b.

[0069] In the above, the first and second exposure ratios are determined separately. However, the exposure ratio may also be the ratio of the total area of ​​the first plated exposed area 35a and the second plated exposed area 35b to the total area of ​​the exposed areas of the first external electrode 30a and the second external electrode 30b. Preferably, this total exposure ratio is between 0.4% and 83.4%.

[0070] The first plating layer 34a and the second plating layer 34b include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0071] Preferably, the first lower plating layer 34a1 and the second lower plating layer 34b1 are Ni plating layers, and the first upper plating layer 34a2 and the second upper plating layer 34b2 are Sn plating layers.

[0072] The first and second lower plating layers 34a1 and 34b1, made of Ni plating, are used to prevent the underlying electrode layer 32 from being corroded by solder when mounting the two-terminal multilayer ceramic capacitor 10. The first and second upper plating layers 34a2 and 34b2, made of Sn plating, are used to improve the wettability of the solder when mounting the two-terminal multilayer ceramic capacitor 10, thereby facilitating easier mounting.

[0073] The thickness of the first main surface 12a, second main surface 12b, first end surface 12e, first side surface 12c, and second side surface 12d of the first lower plating layer 34a1 and the first upper plating layer 34a2 is preferably 2 μm or more and 7 μm or less. The thickness of the first main surface 12a, second main surface 12b, second end surface 12f, first side surface 12c, and second side surface 12d of the second lower plating layer 34b1 and the second upper plating layer 34b2 is preferably 2 μm or more and 7 μm or less.

[0074] Furthermore, if a conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is arranged to cover the conductive resin layer. In this case as well, the lower plating layer, the Ni plating layer, of the plating layer 34 prevents the conductive resin layer from being corroded by solder, and the upper plating layer, the Sn plating layer, improves the wettability of the solder.

[0075] (3) Dimensions of a 2-terminal multilayer ceramic capacitor The dimension in the length direction z of the two-terminal multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension L. The dimension in the height direction x of the two-terminal multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension T. The dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10, which includes the laminate 12, the first external electrode 30a, and the second external electrode 30b, is defined as dimension W. The dimensions of the two-terminal multilayer ceramic capacitor 10 are as follows: the length (L) dimension (z) is 0.2 mm to 6.5 mm; the width (W) dimension (y) is 0.1 mm to 5.5 mm; and the height (T) dimension (x) is 0.1 mm to 6.5 mm. Furthermore, the dimensions of the two-terminal multilayer ceramic capacitor 10 can be measured using a microscope.

[0076] 2.2-Terminal Multilayer Ceramic Capacitor Manufacturing Method Next, a method for manufacturing the two-terminal multilayer ceramic capacitor 10 will be described.

[0077] (Step 1) First, a dielectric sheet for the ceramic layer 14 and a conductive paste for the internal electrode layer 16 are prepared. The dielectric sheet and the conductive paste for the internal electrode layer 16 contain a binder and a solvent. The binder and solvent may be known.

[0078] (Step 2) Then, a conductive paste for the internal electrode layer 16 is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer 16a formed on it, and a dielectric sheet with the pattern of the second internal electrode layer 16b formed on it.

[0079] Furthermore, regarding dielectric sheets, dielectric sheets for the outer layer that do not have the pattern of the internal electrode layer printed on them are also prepared.

[0080] (Step 3) A predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked to form the outer layer portion 14a on the second main surface 12b side (outer layer portion formation step). An inner layer 14b is formed by sequentially laminating a dielectric sheet with the pattern of the first internal electrode layer 16a printed on it, and a dielectric sheet with the pattern of the second internal electrode layer 16b printed on it, on the outer layer 14a on the second main surface 12b side, in such a manner that the structure of the present invention is obtained (inner layer formation step). Next, a predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the inner electrode layer printed on them, are stacked on top of the inner layer. This forms the outer layer portion 14a on the first main surface 12a side on top of the inner layer portion 14b (outer layer portion formation step).

[0081] (Step 4) Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0082] (Step 5) The laminated block is then cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0083] (Step 6) Next, the laminated chips are fired to produce the laminated body 12. The firing temperature depends on the materials of the dielectric ceramic layer and the internal electrode layer, but is preferably between 900°C and 1400°C.

[0084] (Step 7) Next, a base electrode layer 32 is formed by applying a conductive paste for external electrodes to both end faces 12e, 12f, etc. of the laminate 12. The manufacturing process for each case where the base electrode layer 32 is a baked layer, a conductive resin layer, and a thin film layer is described below.

[0085] (When the underlying electrode layer is a baked-on layer) If the base electrode layer 32 is a baked layer, a conductive paste containing glass components and metal is applied by methods such as dipping and screen printing, and then a baking process is performed to form the base electrode layer 32. The baking temperature at this time is preferably 700°C to 900°C.

[0086] The baking layer may contain a ceramic component instead of a glass component, or both. The ceramic component is preferably the same type of ceramic material as the laminate. When the baking layer contains a ceramic component, it is preferable to apply a conductive paste to the laminated chip before firing, and then bake (fire) the laminated chip and the conductive paste applied to the laminated chip simultaneously to form a laminate with the baking layer. The baking temperature at this time is preferably 900°C to 1400°C.

[0087] (When the underlying electrode layer is a conductive resin layer) When the base electrode layer 32 is a conductive resin layer, a conductive resin paste containing a thermosetting resin and metal components is applied to the baking layer or the laminate 12, and heat treatment is performed at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, in order to prevent the scattering of resin and to prevent oxidation of various metal components, it is preferable to keep the oxygen concentration below 100 ppm.

[0088] (When the underlying electrode layer is a thin film layer) If the underlying electrode layer 32 is a thin film layer, it can be formed by a thin film formation method such as sputtering or vapor deposition. The underlying electrode layer 32 formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited.

[0089] (Step 8) After the base electrode layer 32 is formed, a plating layer 34 is formed on the surface of the base electrode layer 32. When performing the plating process, either electrolytic plating or electroless plating may be used, but electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating. As for the plating method, it is preferable to use barrel plating. In this embodiment, a first lower plating layer 34a1 and a second lower plating layer 34b1 (Ni plating layer), and a first upper plating layer 34a2 and a second upper plating layer 34b2 (Sn plating layer) are sequentially formed on the base electrode layer 32 as the plating layer 34.

[0090] When forming a conductive resin layer on the base electrode layer 32, a conductive resin paste containing resin and metal components is prepared, and the conductive resin paste is applied to the base electrode layer 32 using a dipping method. Subsequently, a plating layer 34 is formed on the conductive resin layer.

[0091] (Step 9) Next, the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) are treated so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. As for the treatment method, for example, a scraping method, a melting method, a laser processing method, a resist method, etc. can be employed. In the scraping method, a metal terminal with a diameter of approximately φ30 to 100 μm is brought into contact with the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) to scrape away the soft Sn plating layer so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. In the melting method, the molded body after the plating layer 34 is formed is immersed in an Enstrip agent (release agent). For example, the heights of multiple molded bodies after the plating layer 34 is formed are aligned using an alignment jig, and one side of the molded body is immersed in the Enstrip agent to dissolve the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. At this time, it is preferable to immerse the first main surface 12a (and / or the second main surface 12b) side. This prevents immersion of the internal electrode layer 16 on the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d. In the laser processing method, multiple molded bodies after the plating layer 34 has been formed are aligned, and a predetermined area of ​​the first upper plating layer 34a2 and the second upper plating layer 34b2 (Sn plating layer) of each molded body is removed by laser so that the first lower plating layer 34a1 and the second lower plating layer 34b1 (Ni plating layer) have a predetermined exposure ratio. By using a resist, first and second lower plating layers 34a1 and 34b1 (Ni plating layers) having a predetermined exposure ratio can also be formed.

[0092] As described above, the two-terminal multilayer ceramic capacitor 10 according to this embodiment is manufactured.

[0093] Since the first lower plating layer 34a1 is exposed on the surface of the first external electrode 30a in the first plating exposure region 35a, hydrogen inside the two-terminal multilayer ceramic capacitor 10 can be released to the outside of the two-terminal multilayer ceramic capacitor 10 from the first plating exposure region 35a. Similarly, since the second lower plating layer 34b1 is exposed on the surface of the second external electrode 30b in the second plating exposure region 35b, hydrogen inside the two-terminal multilayer ceramic capacitor 10 can be released to the outside of the two-terminal multilayer ceramic capacitor 10 from the second plating exposure region 35b. Further explanation is as follows.

[0094] In the plating process for forming the first and second lower plating layers 34a1 and 34b1 and the first and second upper plating layers 34a2 and 34b2, hydrogen ions are generated by a chemical reaction. These hydrogen ions may be absorbed as hydrogen by at least one of the first and second lower plating layers 34a1 and 34b1, the first and second internal electrode layers 16a and 16b, and the first and second base electrode layers 32a and 32b. With the above configuration, the hydrogen absorbed by at least one of the layers (absorption layers) of the first and second lower plating layers 34a1 and 34b1, the first and second internal electrode layers 16a and 16b, and the first and second base electrode layers 32a and 32b can be released to the outside of the two-terminal multilayer ceramic capacitor 10 from the first and second plating exposed regions 35a and 35b. Therefore, it is possible to suppress hydrogen remaining absorbed in the absorption layer and to suppress deterioration of insulation resistance due to hydrogen. In particular, even when the absorption layer contains metals such as Ni that do not easily absorb hydrogen, the deterioration of the insulation resistance of the ceramic layer 14 can be suppressed by releasing hydrogen to the outside of the two-terminal multilayer ceramic capacitor 10 from the first and second plating exposure regions 35a and 35b. Furthermore, since the first and second plating exposure regions 35a and 35b are formed on the first main surface 12a side, and the second main surface 12b side becomes the mounting surface for the two-terminal multilayer ceramic capacitor 10 on the mounting substrate, and when solder is mainly applied to the first and second end faces 12e and 12f, hydrogen from the absorption layer can be efficiently released from the first main surface 12a, which is not soldered and does not face the mounting substrate 40, through the first and second plating exposure regions 35a and 35b.

[0095] 3.2-Terminal Multilayer Ceramic Capacitor Next, a modified example of the two-terminal multilayer ceramic capacitor 10 will be described.

[0096] (1) The external electrode 30 in the first embodiment described above includes a base electrode layer 32 and a plating layer 34. In contrast, the external electrode 30 may include the plating layer 34 but not the base electrode layer 32. Although not shown in the diagrams below, the structure in which the plating layer 34 is provided without the underlying electrode layer 32 for the first and second external electrodes 30a and 30b will be described.

[0097] The first and second external electrodes 30a and 30b may each have no underlying electrode layer 32, and the plating layer 34 may be formed directly on the surface of the laminate 12. That is, the two-terminal multilayer ceramic capacitor 10 may have a structure in which the first end face 12e and the second end face 12f are plated to form a plating layer 34 that is electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, a catalyst may be placed on the surface of the laminate 12 as a pretreatment before the plating layer 34 is formed by the plating treatment. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating. As for the plating method, it is preferable to use barrel plating.

[0098] Furthermore, if the plating layer 34 is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be used to lower the profile, i.e., to make it thinner, or to increase the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design flexibility of the thickness of the laminate 12.

[0099] The plating layer 34 includes first and second lower plating layers 34a1 and 34b1 (lower plating layers) formed on the surface of the laminate 12, and first and second upper plating layers 34a2 and 34b2 (upper plating layers) formed on the surface of the first and second lower plating layers 34a1 and 34b1. The lower plating layers have plating exposed areas that are not covered by the upper plating layers, similar to the embodiments described above. Preferably, the lower plating layer and the upper plating layer each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. Furthermore, the lower plating layer is preferably formed using Ni, which has solder barrier properties, and the upper plating layer is preferably formed using Sn or Au, which has good solder wettability.

[0100] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The plating layer 34 may have the upper plating layer as the outermost layer, or other plating electrodes may be formed on the surface of the upper plating layer.

[0101] In this case, when the external electrode 30 is formed using only the plating layer 34 without providing the underlay electrode layer 32, it is preferable that the thickness of each layer of the plating layer 34, which is arranged without the underlay electrode layer 32, be 1.0 μm or more and 20.0 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. It is preferable that the metal content per unit volume of the plating layer 34 is 99% by volume or more.

[0102] (2) In the first embodiment described above, the first lower plating layer 34a1 has a first plating exposed region 35a that is not covered by the first upper plating layer 34a2, and the second lower plating layer 34b1 has a second plating exposed region 35b that is not covered by the second upper plating layer 34b2. However, the form of the exposed region is not limited thereto, and the external electrode 30 may have an exposed base region 36 in which the base electrode layer 32 is not covered by the plating layer 34.

[0103] Specifically, the first underlay electrode layer 32a has a first underlay exposed region 36a that is not covered by the first plating layer 34a. Such a first underlay exposed region 36a can be formed, for example, in the manner shown in Figures 9 and 10. In Figure 9, the first plating exposed region 35a is formed such that the first main surface 12a side of the first lower plating layer 34a1 is exposed, and the first underlay exposed region 36a is formed within this first plating exposed region 35a. Within the first underlay exposed region 36a, the first main surface 12a side of the first underlay electrode layer 32a is exposed and not covered by the first lower plating layer 34a1 and the first upper plating layer 34a2. In Figure 10, the first plating exposed region 35a and the first underlay exposed region 36a are located at different positions on the first main surface 12a.

[0104] As shown in Figures 9 and 10, it is preferable that the first exposed substrate region 36a is located on the first main surface 12a. Furthermore, it is preferable that the second main surface 12b is the mounting surface. This allows for efficient release of hydrogen from the absorption layer through the first exposed substrate region 36a from the first main surface 12a, which is not soldered and does not face the mounting substrate 40, when solder is mainly applied to the first and second end faces 12e and 12f, as shown in Figure 6.

[0105] The first exposed substrate area 36a may be located on any of the following surfaces other than the first main surface 12a: the second main surface 12b, the first end surface 12e, the first side surface 12c, or the second side surface 12d, provided that no solder is applied to it.

[0106] Furthermore, the first plating exposure region 35a and the first substrate exposure region 36a may be formed on different surfaces. For example, the first plating exposure region 35a may be located on the first end face 12e, and the first substrate exposure region 36a may be located on the first main surface 12a.

[0107] Furthermore, it is preferable that the first exposed substrate region 36a is formed on the side of the first end face 12e of the first lower plating layer 34a1, beyond the tip on the second end face 12f side. In other words, it is preferable that the tip on the second end face 12f side of the first substrate electrode layer 32a is covered by the tip on the second end face 12f side of the first substrate plating layer 34a1. This makes it possible to suppress peeling of the first substrate electrode layer 32a.

[0108] The first exposed substrate region 36a can be formed by removing the first lower plating layer 34a1 and the first upper plating layer 34a2 using methods such as scraping, melting, laser processing, or resist, similar to the first exposed plating region 35a.

[0109] Although not shown in the diagram, the second substrate electrode layer 32b may also have a second substrate exposed region that is not covered by the second plating layer 34b.

[0110] (3) In the first embodiment described above, the first exposed plating region 35a, in which the first lower plating layer 34a1 is not covered by the first upper plating layer 34a2, is provided on the first main surface 12a. Similarly, the second exposed plating region 35b, in which the second lower plating layer 34b1 is not covered by the second upper plating layer 34b2, is provided on the first main surface 12a. However, the exposed plating region 35 may be provided on at least one of the first main surface 12a, the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, or the second side surface 12d.

[0111] (4) In the first embodiment described above, a first plating exposed region 35a of the first external electrode 30a and a second plating exposed region 35b of the second external electrode 30b are provided. However, it is sufficient if at least one of the first plating exposed region 35a and the second plating exposed region 35b is provided.

[0112] (5) In the first embodiment described above, the first lower plating layer 34a1 is arranged to cover the entirety of the first base electrode layer 32a, and the second lower plating layer 34b1 is arranged to cover the entirety of the second base electrode layer 32b. However, it is not limited to this, and the first lower plating layer 34a1 may be arranged to cover a part of the first base electrode layer 32a, and the second lower plating layer 34b1 may be arranged to cover a part of the second base electrode layer 32b.

[0113] B. Second Embodiment 1. 3-terminal multilayer ceramic capacitor As an example of a multilayer ceramic electronic component according to a second embodiment of this invention, a three-terminal multilayer ceramic capacitor will be described.

[0114] Figure 11 is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 12 is a top view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 13 is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 14 is a cross-sectional view taken along line XIV-XIV in Figure 11. Figure 15 is a cross-sectional view taken along line XV-XV in Figure 11. Figure 16 is a cross-sectional view taken along line XVI-XVI in Figure 14. Figure 17 is a cross-sectional view taken along line XVII-XVII in Figure 14.

[0115] As shown in Figure 11, the three-terminal multilayer ceramic capacitor 100 includes, for example, a substantially rectangular parallelepiped-shaped laminate 12 and an external electrode 30.

[0116] (1) Laminate The laminate 12 has a plurality of stacked ceramic layers 14 and a plurality of internal electrode layers 16 stacked on the ceramic layers 14. The ceramic layers 14 and the internal electrode layers 16 are stacked in the height direction x.

[0117] The laminate 12 has a first main surface 12a and a second main surface 12b that are opposite each other in the height direction x, a first side surface 12c and a second side surface 12d that are opposite each other in the width direction y which is perpendicular to the height direction x, and a first end surface 12e and a second end surface 12f that are opposite each other in the length direction z which is perpendicular to both the height direction x and the width direction y. The corners and edges of this laminate 12 are rounded. A corner is the part where three adjacent surfaces of the laminate intersect, and an edge is the part where two adjacent surfaces of the laminate intersect. In addition, some or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may have irregularities or other features formed on them. Note that the dimension L in the length direction z of the laminate 12 is not necessarily longer than the dimension W in the width direction y.

[0118] The laminate 12 includes an inner layer 18 and a first main surface-side outer layer 20a and a second main surface-side outer layer 20b, which are arranged to sandwich the inner layer 18 in the stacking direction.

[0119] The inner layer 18 includes a plurality of ceramic layers 14 and a plurality of internal electrode layers 16. In the stacking direction, the inner layer 18 includes an internal electrode layer 16 located closest to the first main surface 12a to an internal electrode layer 16 located closest to the second main surface 12b. The internal electrode layer 16 has a first internal electrode layer 16a drawn out to the first end face 12e and the second end face 12f, and a second internal electrode layer 16b drawn out to the first side surface 12c and the second side surface 12d. In the inner layer 18, a plurality of first internal electrode layers 16a and second internal electrode layers 16b face each other via the ceramic layer 14. The inner layer 18 is the portion that generates capacitance and functions substantially as a capacitor.

[0120] The laminate 12 has a first main surface side outer layer 20a located on the side of the first main surface 12a, and is formed from a plurality of ceramic layers 14 located between the first main surface 12a and the outermost surface of the inner layer 18 on the first main surface 12a side and a straight line along that outermost surface. The first main surface side outer layer 20a is an aggregate of a plurality of ceramic layers 14 located between the first main surface 12a and the inner electrode layer 16 closest to the first main surface 12a. The ceramic layers 14 used in the first main surface side outer layer 20a may be the same as the ceramic layers 14 used in the inner layer 18. Similarly, the laminate 12 has a second main surface side outer layer 20b located on the second main surface 12b side, which is formed from a plurality of ceramic layers 14 located between the second main surface 12b and the outermost surface of the inner layer 18 on the second main surface 12b side and a straight line along that outermost surface. The second main surface side outer layer 20b is an aggregate of a plurality of ceramic layers 14 located between the second main surface 12b and the inner electrode layer 16 closest to the second main surface 12b. The ceramic layers 14 used in the second main surface side outer layer 20b may be the same as the ceramic layers 14 used in the inner layer 18.

[0121] Furthermore, the laminate 12 has a first side outer layer portion 22a located on the first side surface 12c side and formed from a plurality of ceramic layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side. Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed from a plurality of ceramic layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side. The first side outer layer 22a and the second side outer layer 22b are also referred to as the W gap or side gap.

[0122] Furthermore, the laminate 12 has a first end face side outer layer portion 24a located on the first end face 12e side and formed from a plurality of ceramic layers 14 located between the first end face 12e and the outermost surface of the inner layer portion 18 on the first end face 12e side. Similarly, the laminate 12 has a second end face side outer layer portion 24b located on the second end face 12f side and formed from a plurality of ceramic layers 14 located between the second end face 12f and the outermost surface of the inner layer portion 18 on the second end face 12f side. Furthermore, the first end face outer layer portion 24a and the second end face outer layer portion 24b are also called L gaps or end gaps.

[0123] The dimensions of the laminate 12 are not particularly limited.

[0124] The ceramic layer 14 can be formed from a dielectric material, for example, as the ceramic material. Such a dielectric material can be a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When the above dielectric material is the main component, depending on the desired properties of the laminate 12, a mixture containing less of a minor component than the main component, such as a Mn compound, Fe compound, Cr compound, Co compound, or Ni compound, may be used.

[0125] The thickness of the ceramic layer 14 after firing is preferably 0.35 μm or more and 0.60 μm or less. The number of laminated ceramic layers 14 is preferably 10 or more and 2000 or less. This number of ceramic layers 14 is the sum of the number of ceramic layers 14 in the inner layer portion 18 and the number of ceramic layers 14 in the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0126] The laminate 12 has a plurality of internal electrode layers 16, consisting of a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b. Multiple first internal electrode layers 16a and multiple second internal electrode layers 16b may be alternately stacked via a ceramic layer 14, or multiple ceramic layers 14 on which the first internal electrode layers 16a are arranged may be stacked, followed by the stacking of ceramic layers 14 on which the second internal electrode layers 16b are arranged. In this way, the stacking pattern can be changed according to the desired capacitance value.

[0127] As shown in Figure 16, the first internal electrode layer 16a comprises a first opposing electrode portion 26a facing the second internal electrode layer 16b, a first extraction electrode portion 28a1 drawn out from the first opposing electrode portion 26a to the surface of the first end face 12e of the laminate 12, and a second extraction electrode portion 28a2 drawn out from the first opposing electrode portion 26a to the surface of the second end face 12f of the laminate 12. Specifically, the first extraction electrode portion 28a1 is exposed to the surface of the first end face 12e of the laminate 12, and the second extraction electrode portion 28a2 is exposed to the surface of the second end face 12f of the laminate 12. Therefore, the first internal electrode layer 16a is not exposed to the surfaces of the first side surface 12c and the second side surface 12d of the laminate 12.

[0128] The shape of the first opposing electrode portion 26a and the shapes of the first leading electrode portion 28a1 and the second leading electrode portion 28a2 are not particularly limited, but are preferably rectangular. However, the corners may be rounded.

[0129] Furthermore, the length in the width direction y of the first extraction electrode portion 28a1 and the second extraction electrode portion 28a2 may be the same as the length in the width direction y of the first opposing electrode portion 26a, or they may be formed to be shorter. Furthermore, the shapes of the first extraction electrode portion 28a1 and the second extraction electrode portion 28a2 may be tapered.

[0130] As shown in Figure 17, the second internal electrode layer 16b is substantially cross-shaped and includes a second opposing electrode portion 26b facing the first internal electrode layer 16a, a third leading electrode portion 28b1 drawn out from the second opposing electrode portion 26b to the surface of the first side surface 12c of the laminate 12, and a fourth leading electrode portion 28b2 drawn out from the second opposing electrode portion 26b to the surface of the second side surface 12d of the laminate 12. Specifically, the third leading electrode portion 28b1 is exposed to the surface of the first side surface 12c of the laminate 12, and the fourth leading electrode portion 28b2 is exposed to the surface of the second side surface 12d of the laminate 12. Therefore, the second internal electrode layer 16b is not exposed to the surface of the first end face 12e or the second end face 12f of the laminate 12.

[0131] The shape of the second opposing electrode portion 26b, and the shapes of the third and fourth leading electrode portions 28b1 and 28b2 are preferably rectangular. However, the corners may be rounded.

[0132] It is preferable that the relationship between dimension A in the longitudinal direction z connecting the side of the second opposing electrode portion 26b on the first end face 12e side and the side of the second end face 12f side, and dimension B in the longitudinal direction z connecting the side of the third lead-out electrode portion 28b1 and the side of the fourth lead-out electrode portion 28b2 on the first end face 12e side and the side of the second end face 12f side, is A ≥ B.

[0133] The shape of the third lead-out electrode portion 28b1 may be a tapered shape that narrows in width toward the first side surface 12c, and the shape of the fourth lead-out electrode portion 28b2 may be a tapered shape that narrows in width toward the second side surface 12d.

[0134] The laminate 12 has a counter electrode portion 27. The counter electrode portion 27 is the portion where the first counter electrode portion 26a of the first internal electrode layer 16a and the second counter electrode portion 26b of the second internal electrode layer 16b face each other. The counter electrode portion 27 is configured as part of the inner layer portion 18. The counter electrode portion 27 is also called the capacitor effective portion.

[0135] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of a suitable conductive material such as metals like Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as Ag-Pd alloys.

[0136] The number of the first internal electrode layer 16a and the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 10 to 2000 layers in total.

[0137] The thickness of the first internal electrode layer 16a is not particularly limited, but is preferably, for example, 0.40 μm or more and 0.50 μm or less. The thickness of the second internal electrode layer 16b is not particularly limited, but is preferably, for example, 0.40 μm or more and 0.50 μm or less.

[0138] (2) External electrode External electrodes 30 are arranged on the first end face 12e and the second end face 12f, the first side surface 12c and the second side surface 12d, and the first main surface 12a and the second main surface 12b of the laminate 12.

[0139] The external electrode 30 includes a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0140] The first external electrode 30a is connected to the first internal electrode layer 16a and positioned on the surface of the first end face 12e. The first external electrode 30a also extends from the first end face 12e of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead-out electrode portion 28a1 of the first internal electrode layer 16a.

[0141] The second external electrode 30b is connected to the first internal electrode layer 16a and positioned on the surface of the second end face 12f. The second external electrode 30b also extends from the second end face 12f of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead-out electrode portion 28a2 of the first internal electrode layer 16a.

[0142] The third external electrode 30c is connected to the second internal electrode layer 16b and is positioned on the surface of the first side surface 12c. The third external electrode 30c also extends from the first side surface 12c of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third external electrode 30c is electrically connected to the third lead-out electrode portion 28b1 of the second internal electrode layer 16b. Alternatively, the third external electrode 30c may be positioned only on the surface of the first side surface 12c.

[0143] The fourth external electrode 30d is connected to the second internal electrode layer 16b and positioned on the surface of the second side surface 12d. The fourth external electrode 30d also extends from the second side surface 12d of the laminate 12 and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth external electrode 30d is electrically connected to the fourth lead-out electrode portion 28b2 of the second internal electrode layer 16b. Alternatively, the fourth external electrode 30d may be positioned only on the surface of the second side surface 12d.

[0144] Within the laminate 12, capacitance is formed when the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b face each other via the ceramic layer 14. As a result, capacitance can be obtained between the first external electrode 30a and the second external electrode 30b to which the first internal electrode layer 16a is connected, and the third external electrode 30c and the fourth external electrode 30d to which the second internal electrode layer 16b is connected, thus exhibiting capacitor characteristics.

[0145] The external electrode 30 includes a base electrode layer 32 containing metal and glass components, and a plating layer 34 disposed on the surface of the base electrode layer 32. The plating layer 34 includes a lower plating layer and an upper plating layer. The first external electrode 30a includes a first base electrode layer 32a containing a metal component, a first lower plating layer 34a1 disposed on the first base electrode layer 32a, and a first upper plating layer 34a2 disposed on the first lower plating layer 34a1. The first external electrode 30a also has a first plating exposed region 35a exposed on the surface of the first external electrode 30a. The second external electrode 30b includes a second underlay electrode layer 32b containing a metal component, a second lower plating layer 34b1 disposed on the second underlay electrode layer 32b, and a second upper plating layer 34b2 disposed on the second lower plating layer 34b1. The second external electrode 30b also has a second plating exposed region 35b exposed on the surface of the second external electrode 30b. The third external electrode 30c comprises a third base electrode layer 32c containing a metal component, a third lower plating layer 34c1 disposed on the third base electrode layer 32c, and a third upper plating layer 34c2 disposed on the third lower plating layer 34c1. The fourth external electrode 30d includes a fourth base electrode layer 32d containing a metal component, a fourth lower plating layer 34d1 disposed on the fourth base electrode layer 32d, and a fourth upper plating layer 34d2 disposed on the fourth lower plating layer 34d1.

[0146] (2-1) Base electrode layer The base electrode layer 32 comprises a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d.

[0147] The first base electrode layer 32a is connected to the first internal electrode layer 16a and is positioned on the surface of the first end face 12e. The first base electrode layer 32a also extends from the first end face 12e and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first base electrode layer 32a is electrically connected to the first lead-out electrode portion 28a1 of the first internal electrode layer 16a. The second base electrode layer 32b is connected to the first internal electrode layer 16a and is positioned on the surface of the second end face 12f. The second base electrode layer 32b also extends from the second end face 12f and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b, as well as a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second base electrode layer 32b is electrically connected to the second lead-out electrode portion 28a2 of the first internal electrode layer 16a.

[0148] The third base electrode layer 32c is connected to the second internal electrode layer 16b and is positioned on the surface of the first side surface 12c. The third base electrode layer 32c also extends from the first side surface 12c and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the third base electrode layer 32c is electrically connected to the third lead-out electrode portion 28b1 of the second internal electrode layer 16b. The fourth base electrode layer 32d is connected to the second internal electrode layer 16b and is positioned on the surface of the second side surface 12d. The fourth base electrode layer 32d also extends from the second side surface 12d and is positioned on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth base electrode layer 32d is electrically connected to the fourth lead-out electrode portion 28b2 of the second internal electrode layer 16b.

[0149] The base electrode layer 32 includes at least one selected from a baked layer, a conductive resin layer, a thin film layer, etc. The following describes the configurations when the base electrode layer 32 is the baked layer, conductive resin layer, or thin film layer described above.

[0150] (When the underlying electrode layer is a baked-on layer) The baked layer contains a glass component and a metal component. The glass component of the baked layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. The metal component of the baked layer contains at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The baked layer is formed by applying a conductive paste containing the glass component and the metal component to the laminate 12 and baking it. The baked layer may be formed by simultaneously firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminate chip, or by firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 to obtain the laminate 12, and then baking the conductive paste onto the laminate 12. When the baked layer is formed by simultaneously firing the laminate chip having the internal electrode layer 16 and the ceramic layer 14 and the conductive paste applied to the laminate chip, it is preferable to form the baked layer by baking a material with a dielectric material added instead of the glass component. The baking layer may consist of multiple layers.

[0151] Furthermore, if the base electrode layer 32 contains a dielectric material instead of a glass component, the adhesion between the laminate 12 and the base electrode layer 32 can be improved. The base electrode layer 32 may also contain both a glass component and a dielectric component.

[0152] The dielectric material included in the base electrode layer 32 may be the same type of dielectric material as that used in the ceramic layer 14, or a different type of dielectric material may be used. The dielectric component includes at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0153] When the first base electrode layer 32a is formed by baking, the thickness of the first base electrode layer 32a located at the first end face 12e in the height direction x central part in the length direction z is preferably, for example, 3 μm or more and 20 μm or less. Furthermore, when the second base electrode layer 32b is formed as a baked layer, the thickness of the second base electrode layer 32b located at the second end face 12f in the height direction x central part in the length direction z is preferably, for example, 3 μm or more and 20 μm or less.

[0154] Furthermore, when a base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b by a baking layer, the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the center of the e-inch dimension), and the thickness in the height direction x connecting the first main surface 12a and the second main surface 12b at the center of the length direction z of the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the center of the e-inch dimension).

[0155] Furthermore, when a base electrode layer 32 is provided on the first side surface 12c and the second side surface 12d by a baking layer, the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z of the first base electrode layer 32a located on the first side surface 12c and the second side surface 12d is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the central part of the end face), and the thickness in the width direction y connecting the first side surface 12c and the second side surface 12d at the center of the length direction z of the second base electrode layer 32b located on the first side surface 12c and the second side surface 12d is preferably, for example, 3 μm or more and 20 μm or less (thickness of the base electrode layer in the central part of the side surface).

[0156] (When the underlying electrode layer is a conductive resin layer) When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be arranged on top of the baking layer so as to cover the baking layer, or it may be arranged directly on the laminate 12. The conductive resin layer contains metal and thermosetting resin. The conductive resin layer may completely cover the underlying electrode layer, or it may cover only a portion of the underlying electrode layer.

[0157] Because the conductive resin layer contains a thermosetting resin, it is more flexible than conductive layers made of, for example, a plated film or a fired conductive paste. Therefore, even if the three-terminal multilayer ceramic capacitor 100 is subjected to physical shock or shock caused by thermal cycling, the conductive resin layer functions as a buffer layer, preventing cracks in the three-terminal multilayer ceramic capacitor 100.

[0158] The metals that can be included in the conductive resin layer include Ag, Cu, Ni, Sn, Bi, or alloys containing these metals. Furthermore, metal powders coated with Ag on their surface can also be used. When using metal powders coated with Ag on their surface, it is preferable to use Cu, Ni, Sn, Bi, or alloys thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity among metals, making it suitable for electrode materials, and because Ag is a noble metal, it does not oxidize and has high weather resistance. The reason for using Ag-coated metal powder is that it is possible to use an inexpensive base metal while maintaining the above-mentioned properties of Ag.

[0159] Furthermore, the metals included in the conductive resin layer can also be Cu or Ni that have undergone oxidation prevention treatment. Furthermore, as the metal contained in the conductive resin layer, metal powder coated with Sn, Ni, or Cu can also be used. When using metal powder coated with Sn, Ni, or Cu, it is preferable to use Ag, Cu, Ni, Sn, Bi, or alloys thereof as the metal powder.

[0160] Preferably, the metal contained in the conductive resin layer is present in an amount of 35 vol% to 75 vol% relative to the total volume of the conductive resin. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the conductive filler may be, for example, 0.3 μm to 10 μm. The metals contained in the conductive resin layer are primarily responsible for the conductivity of the conductive resin layer. Specifically, conductive fillers come into contact with each other, forming an electrical pathway within the conductive resin layer.

[0161] The metal contained in the conductive resin layer can be spherical, flattened, or otherwise, but it is preferable to use a mixture of spherical and flattened metal powders.

[0162] As the resin for the conductive resin layer, various known thermosetting resins such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin can be used. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Preferably, the resin contained in the conductive resin layer is present in an amount of 25 vol% to 65 vol% of the total volume of the conductive resin.

[0163] Furthermore, it is preferable that the conductive resin layer contains a curing agent along with the thermosetting resin. When epoxy resin is used as the base resin, various known compounds such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds can be used as curing agents for the epoxy resin.

[0164] The conductive resin layer may consist of multiple layers.

[0165] The thickness of the conductive resin layer located in the central part of the laminate 12 in the height direction, at the first end face 12e and the second end face 12f, is preferably, for example, 3 μm or more and 30 μm or less.

[0166] Furthermore, when conductive resin layers are also provided on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, it is preferable that the thickness of the conductive resin layer at the center of the longitudinal direction z of the conductive resin layer located on the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d is, for example, 3 μm or more and 30 μm or less.

[0167] (When the underlying electrode layer is a thin film layer) When a thin film layer is provided as the base electrode layer 32, the thin film layer is formed by a thin film formation method such as sputtering or vapor deposition, and is a layer of 1 μm or less in thickness on which metal particles are deposited.

[0168] (2-2) Plating layer The first plating layer 34a, the second plating layer 34b, the third plating layer 34c, and the fourth plating layer 34d, which are plating layers 34 that can be placed on the underlay electrode layer 32, will be described with reference to Figures 14 to 17. This plating layer 34 has a plating exposure region 35.

[0169] The first plating layer 34a is arranged to cover the first underlay electrode layer 32a on the first end face 12e side. Furthermore, the first plating layer 34a may be arranged to cover the first underlay electrode layer 32a on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the first plating layer 34a may be arranged only on the first underlay electrode layer 32a on the first end face 12e side. This first plating layer 34a has a first lower plating layer 34a1 arranged on the first underlay electrode layer 32a and a first upper plating layer 34a2 arranged on the first lower plating layer 34a1. The first upper plating layer 34a2 is arranged on the first lower plating layer 34a1 so as to expose a portion of the first lower plating layer 34a1. In other words, the first upper plating layer 34a2 is positioned on the first lower plating layer 34a1, excluding the first plating exposure region 35a, such that the first lower plating layer 34a1 has a first plating exposure region 35a that is exposed on the surface of the first external electrode 30a. In this embodiment, the first plating exposure region 35a is positioned on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 becomes the mounting surface for the mounting substrate.

[0170] Preferably, the first upper plating layer 34a2 covers the edge of the first lower plating layer 34a1. This helps to suppress peeling of the first lower plating layer 34a1.

[0171] Preferably, the first ratio of the area of ​​the first plating exposed area 35a to the area of ​​the exposed area of ​​the first external electrode 30a on the first main surface 12a when viewed from the height direction x of the laminate 12 is 0.4% or more and 83.4% or less. Because the first ratio is 0.4% or more, for example, hydrogen released from the first and second internal electrode layers 16a, 16b, the first and second underlayment electrode layers 32a, 32b, and the first and second lower plating layers 34a1, 34b1 can be sufficiently released from the first plating exposed area 35a to the outside of the three-terminal multilayer ceramic capacitor 100, thereby suppressing the deterioration of insulation resistance due to hydrogen. Also, because the first ratio is 83.4% or less, the proportion of the first lower plating layer 34a1 that is not covered by the first upper plating layer 34a2 can be suppressed. This makes it possible to suppress the decrease in moisture resistance due to water vapor intrusion into the three-terminal multilayer ceramic capacitor 100 from the first plating exposed area 35a. More preferably, the first percentage is 1.17% or more and 83.4% or less. Even more preferably, the first percentage is 1.40% or more and 83.4% or less. Even more preferably, the first percentage is 1.40% or more and 25.0% or less. The method for calculating the first percentage is the same as in the first embodiment.

[0172] The second plating layer 34b is arranged to cover the second underlayer electrode layer 32b on the second end face 12f side. Furthermore, the second plating layer 34b may be arranged to cover the second underlayer electrode layer 32b on the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d side. However, the second plating layer 34b may be arranged only on the second underlayer electrode layer 32b on the second end face 12f side. This second plating layer 34b has a second lower plating layer 34b1 arranged on the second underlayer electrode layer 32b and a second upper plating layer 34b2 arranged on the second lower plating layer 34b1. The second upper plating layer 34b2 is arranged on the second lower plating layer 34b1 so as to expose a portion of the second lower plating layer 34b1. In other words, the second upper plating layer 34b2 is positioned on the second lower plating layer 34b1, excluding the second plating exposure region 35b, such that the second lower plating layer 34b1 has a second plating exposure region 35b that is exposed on the surface of the second external electrode 30b. In this embodiment, the second plating exposure region 35b is positioned on the first main surface 12a. In this case, the second main surface 12b of the three-terminal multilayer ceramic capacitor 100 becomes the mounting surface for the mounting substrate.

[0173] Preferably, the second upper plating layer 34b2 covers the edge of the second lower plating layer 34b1. This helps to suppress peeling of the second lower plating layer 34b1.

[0174] For the same reasons as the first ratio, the second ratio of the second plated exposed area 35b to the exposed area of ​​the second external electrode 30b on the first main surface 12a when viewed from the height direction x of the laminate 12 is preferably 0.4% or more and 83.4% or less. More preferably, the second ratio is 1.17% or more and 83.4% or less. Even more preferably, the second ratio is 1.40% or more and 83.4% or less. Even more preferably, the second ratio is 1.40% or more and 25.0% or less. The method for calculating the second ratio is the same as in the first embodiment.

[0175] In the above, the first and second exposure ratios are determined separately. However, the exposure ratio may also be the ratio of the total area of ​​the first plated exposed area 35a and the second plated exposed area 35b to the total area of ​​the exposed areas of the first external electrode 30a and the second external electrode 30b. Preferably, this total exposure ratio is between 0.4% and 83.4%.

[0176] The third plating layer 34c is positioned to cover the third underlayer electrode layer 32c on the first side surface 12c side. Furthermore, the third plating layer 34c may be positioned to cover the third underlayer electrode layer 32c on the first main surface 12a and the second main surface 12b side. However, the third plating layer 34c may be positioned only on the third underlayer electrode layer 32c on the first side surface 12c side. This third plating layer 34c has a third lower plating layer 34c1 positioned on the third underlayer electrode layer 32c and a third upper plating layer 34c2 positioned on the third lower plating layer 34c1. The third upper plating layer 34c2 covers the third lower plating layer 34c1, and the third lower plating layer 34c1 has no exposed areas.

[0177] The fourth plating layer 34d is positioned to cover the fourth underlayer electrode layer 32d on the second side surface 12d. Furthermore, the fourth plating layer 34d may be positioned to cover the fourth underlayer electrode layer 32d on the first main surface 12a and the second main surface 12b. However, the fourth plating layer 34d may be positioned only on the fourth underlayer electrode layer 32d on the second side surface 12d. This fourth plating layer 34d has a fourth lower plating layer 34d1 positioned on the fourth underlayer electrode layer 32d and a fourth upper plating layer 34d2 positioned on the fourth lower plating layer 34d1. The fourth upper plating layer 34d2 covers the fourth lower plating layer 34d1, and the fourth lower plating layer 34d1 has no exposed areas.

[0178] In the three-terminal multilayer ceramic capacitor 100 of this embodiment, a positive potential is applied to the first external electrode 30a having a first plating exposed region 35a and the second external electrode 30b having a second plating exposed region 35b, while a negative potential is applied to the third external electrode 30c and the fourth external electrode 30d.

[0179] The first to fourth plating layers 34a to 34d include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc.

[0180] Preferably, the first to fourth lower plating layers 34a1 to 34d1 are Ni plating layers, and the first to fourth upper plating layers 34a2 to 34d2 are Sn plating layers.

[0181] The first to fourth lower plating layers 34a1 to 34d1, made of Ni plating, are used to prevent the underlying electrode layer 32 from being corroded by the solder when mounting the three-terminal multilayer ceramic capacitor 100. The first to fourth upper plating layers 34a2 to 34d2, made of Sn plating, are used to improve the wettability of the solder when mounting the three-terminal multilayer ceramic capacitor 100, thereby facilitating easier mounting.

[0182] The thickness of the first main surface 12a, second main surface 12b, first end surface 12e, first side surface 12c, and second side surface 12d of the first lower plating layer 34a1 and the first upper plating layer 34a2 is preferably 2 μm or more and 7 μm or less. The thickness of the first main surface 12a, second main surface 12b, second end surface 12f, first side surface 12c, and second side surface 12d of the second lower plating layer 34b1 and the second upper plating layer 34b2 is preferably 2 μm or more and 7 μm or less. Furthermore, the thickness of the first main surface 12a, second main surface 12b, and first side surface 12c of the third lower plating layer 34c1 and the third upper plating layer 34c2 is preferably 2 μm or more and 7 μm or less. The thickness of the first main surface 12a, the second main surface 12b, and the second side surface 12d of the fourth lower plating layer 34d1 and the fourth upper plating layer 34d2 is preferably 2 μm or more and 7 μm or less.

[0183] Furthermore, if a conductive resin layer is formed on the base electrode layer 32, the plating layer 34 is arranged to cover the conductive resin layer. In this case as well, the lower plating layer, the Ni plating layer, of the plating layer 34 prevents the conductive resin layer from being corroded by solder, and the upper plating layer, the Sn plating layer, improves the wettability of the solder.

[0184] (3) Dimensions of a 3-terminal multilayer ceramic capacitor The dimension in the length direction z of the three-terminal multilayer ceramic capacitor 100, including the laminated body 12 and the first external electrodes 30a to the fourth external electrodes 30d, is defined as dimension L, the dimension in the height direction x of the three-terminal multilayer ceramic capacitor 100, including the laminated body 12 and the first external electrodes 30a to the fourth external electrodes 30d, is defined as dimension T, and the dimension in the width direction y of the three-terminal multilayer ceramic capacitor 100, including the laminated body 12 and the first external electrodes 30a to the fourth external electrodes 30d, is defined as dimension W. The dimensions of the 3-terminal multilayer ceramic capacitor 100 are not particularly limited, but the length (L) dimension (z) is 0.2 mm to 6.5 mm, the width (W) dimension (y) is 0.1 mm to 5.5 mm, and the height (T) dimension (x) is 0.1 mm to 6.5 mm. The dimensions of the 3-terminal multilayer ceramic capacitor 100 can be measured using a microscope.

[0185] 2.3 Terminal Type Multilayer Ceramic Capacitor Manufacturing Method Next, we will explain the manufacturing method for a three-terminal multilayer ceramic capacitor.

[0186] (Step 1) First, a dielectric sheet for the ceramic layer and a conductive paste for the internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and solvent may be known.

[0187] (Step 2) Then, a conductive paste for the internal electrode layer is printed on the dielectric sheet in a predetermined pattern, for example, by screen printing or gravure printing. This prepares a dielectric sheet with the pattern of the first internal electrode layer formed on it, and a dielectric sheet with the pattern of the second internal electrode layer formed on it. More specifically, a screen plate for printing the first internal electrode layer and a screen plate for printing the second internal electrode layer can be prepared separately, and the patterns of each internal electrode layer can be printed using a printing machine that can print the two types of screen plates separately.

[0188] (Step 3) Next, a predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on them, are stacked to form the second outer layer portion on the second main surface side. Then, a dielectric sheet with the pattern of the first internal electrode layer printed on it, and a dielectric sheet with the pattern of the second internal electrode layer printed on it, are sequentially stacked on top of the second outer layer portion to form the structure of the present invention, thereby forming the inner layer portion. A predetermined number of dielectric sheets for the outer layer, which do not have the pattern of the internal electrode layer printed on it, are stacked on top of this inner layer portion to form the first outer layer portion on the first main surface side. This completes the production of the laminated sheet.

[0189] (Step 4) Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or other means to produce a laminated block.

[0190] (Step 5) The laminated block is then cut to a predetermined size, thereby cutting out the laminated chips. At this time, the corners and edges of the laminated chips may be rounded by barrel polishing or the like.

[0191] (Step 6) Next, the cut laminated chips are fired to produce a laminate. The firing temperature depends on the materials of the ceramic layer and the internal electrode layer, but is preferably between 900°C and 1400°C.

[0192] (Step 7) Next, a third base electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminate 12 obtained by firing, and a fourth base electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminate 12. (When the underlying electrode layer is a baked-on layer) When forming the baked layers as the third and fourth base electrode layers 32c and 32d, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the base electrode layers. The temperature of this baking process is preferably between 700°C and 900°C.

[0193] Here, various methods can be used to form the baked layer. For example, a method can be used in which a conductive paste is extruded from a slit and applied. In this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b. It can also be formed using a roller transfer method. In the case of the roller transfer method, when forming the base electrode layer 32 not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, it is possible to form the base electrode layer 32 on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during roller transfer.

[0194] Next, a first base electrode layer 32a for the first external electrode 30a is formed on the first end face 12e of the laminate obtained by firing, and a second base electrode layer 32b for the second external electrode 30b is formed on the second end face 12f. Similar to the third and fourth base electrode layers 32c and 32d, when forming the baked layers as the first and second base electrode layers 32a and 32b, a conductive paste containing glass and metal components is applied, and then a baking process is performed to form the base electrode layers. The temperature of this baking process is preferably between 700°C and 900°C. Methods for applying conductive paste to both end faces of a laminate include, for example, the dipping method and the screen printing method.

[0195] In addition, during the baking process, the third base electrode layer 32c, the fourth base electrode layer 32d, the first base electrode layer 32a, and the second base electrode layer 32b may be baked simultaneously, or the sides 12c and 12d and the end faces 12e and 12f may be baked separately.

[0196] Furthermore, when the base electrode layer is formed by a baked layer, the baked layer may contain a dielectric component. In this case, the dielectric component may be included instead of the glass component, or both may be included.

[0197] The dielectric component is preferably, for example, the same type of dielectric material as the laminate. When the dielectric component is included in the baking layer, it is preferable to apply a conductive paste to the laminated chip before firing, and then bake (fire) the laminated chip and the conductive paste applied to the laminated chip simultaneously to form a laminate with the baking layer. The baking temperature at this time is preferably 900°C to 1400°C.

[0198] (When the underlying electrode layer is a conductive resin layer) Furthermore, when the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of the baking layer, or the conductive resin layer may be formed directly on the laminate 12 by itself without forming a baking layer.

[0199] The method for forming the conductive resin layer involves applying a conductive resin paste containing a thermosetting resin and metal components onto the baking layer or the laminate 12, and then performing heat treatment at a temperature of 250°C to 550°C to heat-cur the resin and form a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent resin scattering and oxidation of various metal components, the oxygen concentration is preferably kept below 100 ppm.

[0200] Furthermore, the conductive resin paste can be applied using a method similar to the method of forming the base electrode layer 32 with a baked layer, such as a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method.

[0201] (When the underlying electrode layer is a thin film layer) Furthermore, when forming the base electrode layer 32 as a thin film layer, masking can be performed, and the base electrode layer can be formed in the area where the external electrode 30 is to be formed by a thin film formation method such as sputtering or vapor deposition. The base electrode layer formed as a thin film layer shall be a layer of 1 μm or less in thickness in which metal particles are deposited.

[0202] (Step 8) Next, a plating layer 34 is formed. The plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer is formed on the base electrode layer 32 as a lower plating layer, and a Sn plating layer is formed as an upper plating layer. In this embodiment, the plating layer 34 is formed sequentially on the base electrode layer 32 as a Ni plating layer: a first lower plating layer 34a1, a second lower plating layer 34b1, a third lower plating layer 34c1, and a fourth lower plating layer 34d1, and a Sn plating layer: a first upper plating layer 34a2, a second upper plating layer 34b2, a third upper plating layer 34c2, and a fourth upper plating layer 34d2. The Ni plating layer and the Sn plating layer are formed sequentially, for example, by a barrel plating method. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, electroplating is generally preferred.

[0203] (Step 9) Next, the first and second upper plating layers 34a2 and 34b2 (Sn plating layers) are processed so that the first and second lower plating layers 34a1 and 34b1 (Ni plating layers) have a predetermined exposure ratio. As for the processing method, for example, a scraping method, a melting method, a laser processing method, a resist method, etc. can be employed. In the scraping method, a metal terminal with a diameter of approximately φ30 to 100 μm is brought into contact with the first and second upper plating layers 34a2 and 34b2, thereby scraping away the soft Sn plating layer so that the first and second lower plating layers 34a1 and 34b1 (Ni plating layers) have a predetermined exposure ratio. In the melting method, the molded body after the plating layer 34 is formed is immersed in an Enstrip agent (release agent). For example, the heights of multiple molded bodies after the plating layer 34 is formed are aligned using an alignment jig, and one side of the molded body is immersed in the Enstrip agent to dissolve the Sn plating layer so that the first and second lower plating layers 34a1 and 34b1 (Ni plating layers) have a predetermined exposure ratio. At this time, it is preferable to immerse the first main surface 12a (and / or the second main surface 12b) side. This prevents immersion of the internal electrode layer 16 on the first end surface 12e, the second end surface 12f, the first side surface 12c, and the second side surface 12d. In the laser processing method, multiple molded bodies after the plating layer 34 has been formed are aligned, and a predetermined area of ​​the Sn plating layer of each molded body is removed by laser so that the first and second lower plating layers 34a1 and 34b1 (Ni plating layers) have a predetermined exposure ratio. Furthermore, by using a resist, first and second lower plating layers 34a1 and 34b1 (Ni plating layers) having a predetermined exposure ratio can also be formed.

[0204] As described above, the three-terminal multilayer ceramic capacitor 100 according to this embodiment is manufactured.

[0205] The three-terminal multilayer ceramic capacitor 100 according to this embodiment has the same effects and advantages as the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0206] 3.3-Terminal Multilayer Ceramic Capacitor Next, a modified example of the 3-terminal multilayer ceramic capacitor 100 will be described.

[0207] (1) The external electrode 30 in the second embodiment described above includes a base electrode layer 32 and a plating layer 34. In contrast, the external electrode 30 may include the plating layer 34 but not the base electrode layer 32. Although not shown in the diagrams below, the structure in which the plating layer 34 is provided without the underlying electrode layer 32 for the first to fourth external electrodes 30a to 30d will be described.

[0208] Each of the first to fourth external electrodes 30a to 30d may not have a base electrode layer 32, and the plating layer 34 may be formed directly on the surface of the laminate 12. That is, the three-terminal multilayer ceramic capacitor 100 may have a structure in which the first end face 12e, the second end face 12f, the first side surface 12c, and the second side surface 12d are plated to form a plating layer 34 that is electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, a catalyst may be placed on the surface of the laminate 12 as a pretreatment before the plating layer 34 is formed by the plating treatment. When performing the plating treatment, either electrolytic plating or electroless plating may be used. However, electroless plating has the disadvantage of requiring pretreatment with a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is generally preferable to use electrolytic plating. As for the plating method, it is preferable to use barrel plating.

[0209] Furthermore, if the plating layer 34 is formed directly on the laminate 12 without providing the underlay electrode layer 32, the reduction in the thickness of the underlay electrode layer 32 can be used to lower the profile, i.e., to make it thinner, or to increase the thickness of the laminate, i.e., the thickness of the effective layer portion, thereby improving the design flexibility of the thickness of the laminate 12.

[0210] The plating layer 34 includes first to fourth lower plating layers 34a1 to 34d1 (lower plating layers) formed on the surface of the laminate 12, and first to fourth upper plating layers 34a2 to 34d2 (upper plating layers) formed on the surface of the first to fourth lower plating layers 34a1 to 34d1. The first and second lower plating layers 34a1 and 34b1 have plating exposed areas that are not covered by the upper plating layers, similar to the embodiments described above. Preferably, the lower plating layers and upper plating layers each contain at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing such metal. Furthermore, the lower plating layer is preferably formed using Ni, which has solder barrier properties, and the upper plating layer is preferably formed using Sn or Au, which has good solder wettability.

[0211] Furthermore, for example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the lower plating layer be formed using Cu, which has good bonding properties with Ni. The upper plating layer may be the outermost layer, or other plating electrodes may be formed on the surface of the upper plating layer.

[0212] In this case, when the external electrode 30 is formed using only the plating layer 34 without providing the underlay electrode layer 32, it is preferable that the thickness of each layer of the plating layer 34, which is arranged without the underlay electrode layer 32, be 1.0 μm or more and 20.0 μm or less. Furthermore, it is preferable that the plating layer 34 does not contain glass. It is preferable that the metal content per unit volume of the plating layer 34 is 99% by volume or more.

[0213] (2) In the second embodiment described above, the first lower plating layer 34a1 has a first plating exposed region 35a that is not covered by the first upper plating layer 34a2, and the second lower plating layer 34b1 has a second plating exposed region 35b that is not covered by the second upper plating layer 34b2. However, the form of the exposed region is not limited to this, and as described in the modified example of the first embodiment (see Figures 9 and 10), the external electrode 30 may have an exposed substrate region 36 in which the substrate electrode layer 32 is not covered by the plating layer 34. For example, the first substrate electrode layer 32a may have a first exposed substrate region that is not covered by the first plating layer 34a. Also, the second substrate electrode layer 32b may have a second exposed substrate region that is not covered by the second plating layer 34b. At this time, the first external electrode 30a has a first exposed substrate region 36a along with a first plated exposed region 35a, and the second external electrode 30b has a second exposed substrate region along with a second plated exposed region 35b, and a positive potential is applied to the first external electrode 30a and the second external electrode 30b.

[0214] The exposed substrate region 36 is preferably located on the first main surface 12a. Furthermore, the second main surface 12b is preferably the mounting surface. As a result, when solder is mainly applied to the first and second end faces 12e and 12f, as shown in Figure 6, hydrogen from the absorption layer can be efficiently released from the first main surface 12a, which is not soldered and does not face the mounting substrate 40, through the exposed substrate region 36.

[0215] The exposed substrate area 36 may be located on any of the following surfaces other than the first main surface 12a: the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, or the second side surface 12d, provided that no solder is applied to it.

[0216] Furthermore, the first plating exposure region 35a and the first substrate exposure region 36a may be formed on different surfaces.

[0217] Furthermore, it is preferable that the first exposed substrate region 36a is formed on the first end face 12e side of the first lower plating layer 34a1, from the tip portion on the second end face 12f side.

[0218] The first exposed substrate region 36a can be formed in the same manner as the first plated exposed region 35a.

[0219] Although not shown in the figures, the third base electrode layer 32c may have a third base exposed region that is not covered by the third plating layer 34c, and the fourth base electrode layer 32d may have a fourth base exposed region that is not covered by the fourth plating layer 34d.

[0220] (3) In the second embodiment described above, the first exposed plating region 35a, in which the first lower plating layer 34a1 is not covered by the first upper plating layer 34a2, is provided on the first main surface 12a. Similarly, the second exposed plating region 35b, in which the second lower plating layer 34b1 is not covered by the second upper plating layer 34b2, is provided on the first main surface 12a. However, the exposed plating region 35 may be provided on at least one of the first main surface 12a, the second main surface 12b, the first end surface 12e, the second end surface 12f, the first side surface 12c, or the second side surface 12d.

[0221] (4) In the second embodiment described above, a first plating exposed region 35a of the first external electrode 30a and a second plating exposed region 35b of the second external electrode 30b are provided. However, in addition to the first plating exposed region 35a of the first external electrode 30a and the second plating exposed region 35b of the second external electrode 30b, a third plating exposed region may be provided on the third external electrode 30c in which the third lower plating layer 34c1 is not covered by the third upper plating layer 34c2, and a fourth plating exposed region may be provided on the fourth external electrode 30d in which the fourth lower plating layer 34d1 is not covered by the fourth upper plating layer 34d2. In this case, a positive potential is applied to one of the first and second external electrodes 30a, 30b or the third and fourth external electrodes 30c, 30d, and a negative potential is applied to the other.

[0222] It is preferable that the third ratio of the area of ​​the third plated exposed area to the area of ​​the third external electrode 30c on the first main surface 12a in a view in the first main surface direction is 0.4% or more and 83.4% or less. Similarly, it is preferable that the fourth ratio of the area of ​​the fourth plated exposed area to the area of ​​the fourth external electrode 30d on the first main surface 12a in a view in the first main surface direction is 0.4% or more and 83.4% or less. Furthermore, it is preferable that the ratio of the total exposed area of ​​the first to fourth plated exposed areas 35a to 35d to the total exposed area of ​​the first to fourth external electrodes 30a to 30d is 0.4% or more and 83.4% or less.

[0223] Furthermore, the first external electrode 30a may not have a first plating exposure region 35a, the second external electrode 30b may not have a second plating exposure region 35b, the third external electrode 30c may have a third plating exposure region in which the third lower plating layer 34c1 is not covered by the third upper plating layer 34c2, and the fourth external electrode 30d may have a fourth plating exposure region in which the fourth lower plating layer 34d1 is not covered by the fourth upper plating layer 34d2. In this case, a positive potential is applied to the third and fourth external electrodes 30c and 30d.

[0224] (5) In the second embodiment described above, the first to fourth underlayer plating layers 34a1 to 34d1 are arranged to cover all of the first to fourth underlayer electrode layers 32a to 32d. However, the embodiment is not limited to this, and the first underlayer plating layer 34a1 may be arranged to cover a part of the first underlayer electrode layer 32a, the second underlayer plating layer 34b1 may be arranged to cover a part of the second underlayer electrode layer 32b, the third underlayer plating layer 34c1 may be arranged to cover a part of the third underlayer electrode layer 32c, and the fourth underlayer plating layer 34d1 may be arranged to cover a part of the fourth underlayer electrode layer 32d.

[0225] C. Experimental Examples (1) Samples of experimental examples First, a two-terminal multilayer ceramic capacitor with the following specifications was fabricated according to the manufacturing method of the multilayer ceramic capacitor described above.

[0226] ◎Structure of multilayer ceramic capacitor: 2 terminals (see Figure 1) ◎Dimensions of the multilayer ceramic capacitor L×W×T (including design value): 1.13mm×0.63mm×0.63mm ◎Material of the ceramic layer: BaTiO3 ◎Capacitance: 22μF ◎Rated voltage: 4V

[0227] ◎ Structure of external electrodes • Underlay electrode layer: Electrode containing conductive metal (Cu) and glass components • Film thickness of the base electrode layer at the end faces: Film thickness of the base electrode layer at the center of the height direction of the base electrode layer located at the first and second end faces = 12 μm • Film thickness of the base electrode layer on the main surface and side surfaces: Film thickness of the base electrode layer at the longitudinal center of the base electrode layer located on the first and second main surfaces, the first and second side surfaces = 12 μm • Plating layer: Two-layer structure consisting of a Ni plating layer and a Sn plating layer. • Thickness of the Ni plating layer on the end faces: Thickness of the Ni plating layer at the center of the height direction of the Ni plating layer located on the first and second end faces = 2 μm • Thickness of the Ni plating layer on the main surface and side surfaces: Thickness of the Ni plating layer in the longitudinal center of the Ni plating layer located on the first and second main surfaces, the first and second side surfaces = 2 μm • Thickness of the Sn plating layer on the end faces: Thickness of the Sn plating layer at the center of the height direction of the Sn plating layer located on the first and second end faces = 3 μm • Thickness of the Sn plating layer on the main surface and side surfaces: Thickness of the Sn plating layer in the longitudinal center of the Sn plating layer located on the first and second main surfaces, the first and second side surfaces = 3 μm

[0228] ◎ Exposure ratio of the first lower plating layer and the second lower plating layer (Ni plating layer) on the first main surface • Exposure ratio = (Exposed area of ​​the first and second lower plating layers) / Area of ​​the first main surface of the first and second external electrodes × 100 The area of ​​the first main surface of the first external electrode and the second external electrode was set to L (200 μm) × W (600 μm), respectively. The exposure ratios for Examples 1-8 and Comparative Example 1 are as follows. (Example 1) 0.2% (Example 2) 0.4% (Example 3) 1.17% (Example 4) 1.4% (Example 5) 1.67% (Example 6) 25% (Example 7) 83.4% (Example 8) 89.2% (Comparative Example 1) 0%

[0229] (2) Experimental results For each of the 100 samples in Examples 1-8 and Comparative Example 1, the degradation of insulation resistance (IR) was confirmed by PCBT testing (125°C, 95%RH, 2V, 72hr) during solder mounting, and the number of degraded samples was counted. Table 1 shows the experimental results.

[0230] [Table 1]

[0231] From the results in Table 1, in Comparative Example 1, 11 out of 100 samples were judged to have deteriorated insulation resistance. On the other hand, in Examples 1 to 8, the number of samples judged to have deteriorated insulation resistance was 8 or less out of 100. Furthermore, in Examples 2 to 7, the number of samples judged to have deteriorated insulation resistance was 4 or less out of 100, and in Examples 3 to 7, the number of samples judged to have deteriorated insulation resistance was also 4 or less out of 100. Moreover, in Examples 4 to 6, the number of samples judged to have deteriorated insulation resistance was 0 out of 100. Therefore, it was found that when the exposure ratio is greater than 0%, the deterioration of the insulation resistance is suppressed. Also, it was found that when the exposure ratio is 0.4% or more and 83.4% or less, the deterioration of the insulation resistance is further suppressed. Further, it was found that the deterioration of the insulation resistance is suppressed even when the exposure ratio is in the range of 1.17% or more and 83.4% or less, and also in the range of 1.40% or more and 83.4% or less. Furthermore, it was found that when the exposure ratio is 1.40% or more and 25.0% or less, the deterioration of the insulation resistance is further suppressed.

[0232] Note that, as described above, the embodiments of the present invention are disclosed in the above description, but the present invention is not limited thereto. That is, without departing from the scope of the technical idea and object of the present invention, various changes can be made to the embodiments described above with respect to the mechanism, shape, material, quantity, position, or arrangement, etc., and they are included in the present invention.

[0233] <1> A laminate having a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction orthogonal to the height direction, and a first side surface and a second side surface facing each other in the width direction orthogonal to the height direction and the length direction; A plurality of first internal electrode layers disposed on the plurality of ceramic layers and drawn out to the first end surface; A plurality of second internal electrode layers disposed on the plurality of ceramic layers and drawn out to the second end surface; A first external electrode disposed on the first end surface, extending from the first end surface and disposed on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer; A second external electrode disposed on the second end surface, extending from the second end surface and disposed on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the second internal electrode layer. The first external electrode includes a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer excluding a first plating exposed region where the first lower plating layer is exposed on the surface of the first external electrode. The second external electrode includes a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer excluding a second plating exposed region where the second lower plating layer is exposed on the surface of the second external electrode. A multilayer ceramic electronic component.

[0234] <2> A laminate having a plurality of stacked ceramic layers, a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction orthogonal to the height direction, and a first side surface and a second side surface facing each other in the width direction orthogonal to the height direction and the length direction. A plurality of first internal electrode layers disposed on the plurality of ceramic layers and drawn out to the first end surface and the second end surface. A plurality of second internal electrode layers disposed on the plurality of ceramic layers and drawn out to the first side surface and the second side surface. A first external electrode disposed on the first end surface, extending from the first end surface and disposed on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer. A second external electrode disposed on the second end surface, extending from the second end surface and disposed on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and connected to the first internal electrode layer. A third external electrode disposed on the first side surface, extending from the first side surface and disposed on a part of the first main surface and a part of the second main surface, and connected to the second internal electrode layer. A fourth external electrode is provided, which is located on the second side surface, extends from the second side surface and is located on a portion of the first main surface and a portion of the second main surface, and is connected to the second internal electrode layer. The first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer except for the first plating exposure region, such that the first lower plating layer has a first plating exposure region exposed on the surface of the first external electrode. The second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer except for the second plating exposed region, such that the second lower plating layer has a second plating exposed region exposed on the surface of the second external electrode. The third external electrode comprises a third base electrode layer disposed on the laminate, a third lower plating layer disposed on the third base electrode layer, and a third upper plating layer disposed on the third lower plating layer. The multilayer ceramic electronic component comprises a fourth external electrode, a fourth base electrode layer disposed on the laminate, a fourth lower plating layer disposed on the fourth base electrode layer, and a fourth upper plating layer disposed on the fourth lower plating layer.

[0235] <3> The third upper plating layer is positioned on the third lower plating layer, excluding the third plating exposed region, such that the third lower plating layer has a third plating exposed region exposed on the surface of the third external electrode. The fourth upper plating layer is positioned on the fourth lower plating layer, excluding the fourth plating exposed region, such that the fourth lower plating layer has a fourth plating exposed region exposed on the surface of the fourth external electrode. <2> Multilayer ceramic electronic components as described above.

[0236] <4> A laminate having multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, A plurality of first internal electrode layers are arranged on the plurality of ceramic layers and drawn out to the first end face and the second end face, A plurality of second internal electrode layers are arranged on the plurality of ceramic layers and are drawn out on the first side and the second side, A first external electrode is positioned on the first end face, extending from the first end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer, A second external electrode is positioned on the second end face, extending from the second end face and positioned on a portion of the first main surface, a portion of the second main surface, a portion of the first side surface, and a portion of the second side surface, and is connected to the first internal electrode layer, A third external electrode is positioned on the first side surface, extending from the first side surface and positioned on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, A fourth external electrode is provided, which is located on the second side surface, extends from the second side surface and is located on a portion of the first main surface and a portion of the second main surface, and is connected to the second internal electrode layer. The first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer. The second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer. The third external electrode comprises a third base electrode layer disposed on the laminate, a third lower plating layer disposed on the third base electrode layer, and a third upper plating layer disposed on the third lower plating layer except for the third plating exposed region, such that the third lower plating layer has a third plating exposed region exposed on the surface of the third external electrode. A multilayer ceramic electronic component comprising: a fourth external electrode comprising: a fourth base electrode layer disposed on the laminate; a fourth lower plating layer disposed on the fourth base electrode layer; and a fourth upper plating layer disposed on the fourth lower plating layer except for the fourth plating exposure region, such that the fourth lower plating layer has a fourth plating exposure region exposed on the surface of the fourth external electrode.

[0237] <5> In the view from the first main surface, the first ratio of the area of ​​the first plating exposed region to the area of ​​the first external electrode exposed region on the first main surface is 0.4% or more and 83.4% or less, and the second ratio of the area of ​​the second plating exposed region to the area of ​​the second external electrode exposed region on the first main surface in the view from the first main surface is 0.4% or more and 83.4% or less. <1> ~ <3> A multilayer ceramic electronic component as described in any of the following.

[0238] <6> The aforementioned first and second percentages are between 1.17% and 83.4%. <5> Multilayer ceramic electronic components as described above.

[0239] <7> The first and second percentages are between 1.40% and 83.4%. <6> Multilayer ceramic electronic components as described above.

[0240] <8> The first and second percentages are between 1.40% and 25.0%. <7> Multilayer ceramic electronic components as described above.

[0241] <9> The first plating exposed area is disposed on the first major surface, the multilayer ceramic electronic component according to any one of <1> to <8>.

[0242] <10> The thickness of the first lower plating layer is 2 μm or more and 7 μm or less, the multilayer ceramic electronic component according to any one of claims <1> to <9>.

[0243] <11> A part of the first base electrode layer is exposed on the first major surface, the multilayer ceramic electronic component according to any one of <1> to <10>.

[0244] <12> The third ratio of the area of the third plating exposed area to the area of the exposed area of the third external electrode on the first major surface in the view in the first major surface direction and / or the fourth ratio of the area of the fourth plating exposed area to the area of the exposed area of the fourth external electrode on the first major surface in the view in the first major surface direction is 0.4% or more and 83.4% or less, the multilayer ceramic electronic component according to <3> or <4>.

[0245] <13> The multilayer ceramic electronic component according to any one of <1> to <12>, A mounting structure of a multilayer ceramic electronic component including a mounting substrate on which the multilayer ceramic electronic component is mounted, The first plating exposed area is disposed on the first major surface, and the multilayer ceramic electronic component is mounted such that the second major surface faces the mounting substrate, a mounting structure of a multilayer ceramic electronic component.

[0246] <14> The multilayer ceramic electronic component according to any one of <2>, <3>, <12>, A mounting structure of a multilayer ceramic electronic component including a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the first external electrode and the second external electrode are electrodes to which a positive potential is applied.

[0247] <15> <4> The multilayer ceramic electronic components described above, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the third and fourth external electrodes are electrodes to which a positive potential is applied. [Explanation of Symbols]

[0248] 10: 2-terminal multilayer ceramic capacitor 12: Laminate 12a: First main surface 12b: Second main surface 12c: First side 12d: Second aspect 12e: First end face 12f: Second end face 14: Ceramic layer 14a: Outer layer 14b: Inner layer 16: Internal electrode layer 16a, 16b: First and second internal electrode layers 18: Inner layer 20a: First main surface side outer layer 20b: Second main surface side outer layer 22a: First side outer layer 22b: Second side outer layer 24a: First end face side outer layer 24b: Second end face side outer layer 26a: First counter electrode portion 26b: Second counter electrode section 27: Counter electrode part 28a: First extraction electrode section 28b: Second extraction electrode section 28a1: First extraction electrode section 28a2: Second extraction electrode section 28b1: Third extraction electrode section 28b2: Fourth extraction electrode section 30: External electrode 30a~30d: 1st to 4th external electrodes 32: Base electrode layer 32a~32d: 1st to 4th base electrode layers 34: Plating layer 34a~34d: 1st to 4th plating layers 34a1~34d1: 1st to 4th lower plating layers 34a2~34d2: 1st to 4th upper plating layers 35: Plating exposure area 35a~35d: 1st to 4th plating exposure regions 36: Base exposed area 36a: First exposed substrate area 40: Implemented circuit board 41: Land 42: Handa 100 : 3-terminal multilayer ceramic capacitor

Claims

1. A laminate having multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, A plurality of first internal electrode layers are arranged on the plurality of ceramic layers and drawn out to the first end face, A plurality of second internal electrode layers are arranged on the plurality of ceramic layers and drawn out to the second end face, A first external electrode is positioned on the first end face, extending from the first end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer. The second external electrode is positioned on the second end face, extends from the second end face and is positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the second internal electrode layer, The first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer except for the first plating exposure region, such that the first lower plating layer has a first plating exposure region exposed on the surface of the first external electrode. The second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer except for the second plating exposed region, such that the second lower plating layer has a second plating exposed region exposed on the surface of the second external electrode. A multilayer ceramic electronic component in which the first plated exposed region is located on the first main surface.

2. A laminate having multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, A plurality of first internal electrode layers are arranged on the plurality of ceramic layers and drawn out to the first end face and the second end face, A plurality of second internal electrode layers are arranged on the plurality of ceramic layers and are drawn out on the first side and the second side, A first external electrode is positioned on the first end face, extending from the first end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer. A second external electrode is positioned on the second end face, extending from the second end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer, A third external electrode is positioned on the first side surface, extending from the first side surface and positioned on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, A fourth external electrode is disposed on the second side surface, extends from the second side surface and is positioned on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, The first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer except for the first plating exposure region, such that the first lower plating layer has a first plating exposure region exposed on the surface of the first external electrode. The second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer except for the second plating exposed region, such that the second lower plating layer has a second plating exposed region exposed on the surface of the second external electrode. The third external electrode comprises a third base electrode layer disposed on the laminate, a third lower plating layer disposed on the third base electrode layer, and a third upper plating layer disposed on the third lower plating layer. The fourth external electrode comprises a fourth base electrode layer disposed on the laminate, a fourth lower plating layer disposed on the fourth base electrode layer, and a fourth upper plating layer disposed on the fourth lower plating layer. A multilayer ceramic electronic component in which the first plated exposed region is located on the first main surface.

3. The third upper plating layer is positioned on the third lower plating layer, excluding the third plating exposed region, such that the third lower plating layer has a third plating exposed region exposed on the surface of the third external electrode. The multilayer ceramic electronic component according to claim 2, wherein the fourth upper plating layer is disposed on the fourth lower plating layer, excluding the fourth plating exposed region, such that the fourth lower plating layer has a fourth plating exposed region exposed on the surface of the fourth external electrode.

4. A laminate having multiple stacked ceramic layers, having a first main surface and a second main surface facing each other in the height direction, a first end surface and a second end surface facing each other in the length direction perpendicular to the height direction, and a first side surface and a second side surface facing each other in the width direction perpendicular to the height direction and the length direction, A plurality of first internal electrode layers are arranged on the plurality of ceramic layers and drawn out to the first end face and the second end face, A plurality of second internal electrode layers are arranged on the plurality of ceramic layers and are drawn out on the first side and the second side, A first external electrode is positioned on the first end face, extending from the first end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer. A second external electrode is positioned on the second end face, extending from the second end face and positioned on a part of the first main surface, a part of the second main surface, a part of the first side surface, and a part of the second side surface, and is connected to the first internal electrode layer, A third external electrode is positioned on the first side surface, extending from the first side surface and positioned on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, A fourth external electrode is disposed on the second side surface, extends from the second side surface and is positioned on a part of the first main surface and a part of the second main surface, and is connected to the second internal electrode layer, The first external electrode comprises a first base electrode layer disposed on the laminate, a first lower plating layer disposed on the first base electrode layer, and a first upper plating layer disposed on the first lower plating layer. The second external electrode comprises a second base electrode layer disposed on the laminate, a second lower plating layer disposed on the second base electrode layer, and a second upper plating layer disposed on the second lower plating layer. The third external electrode comprises a third base electrode layer disposed on the laminate, a third lower plating layer disposed on the third base electrode layer, and a third upper plating layer disposed on the third lower plating layer except for the third plating exposed region, such that the third lower plating layer has a third plating exposed region exposed on the surface of the third external electrode. The fourth external electrode comprises a fourth base electrode layer disposed on the laminate, a fourth lower plating layer disposed on the fourth base electrode layer, and a fourth upper plating layer disposed on the fourth lower plating layer except for the fourth plating exposed region, such that the fourth lower plating layer has a fourth plating exposed region exposed on the surface of the fourth external electrode. The third plated exposed region is located on the first main surface of the multilayer ceramic electronic component.

5. In the view in the direction of the first main surface, the first ratio of the area of ​​the first plating exposed region to the area of ​​the exposed region of the first external electrode on the first main surface is 0.4% or more and 83.4% or less. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the second ratio of the area of ​​the second plating exposed region to the area of ​​the exposed region of the second external electrode on the first main surface in the view in the direction of the first main surface is 0.4% or more and 83.4% or less.

6. The multilayer ceramic electronic component according to claim 5, wherein the first and second proportions are 1.17% or more and 83.4% or less.

7. The multilayer ceramic electronic component according to claim 6, wherein the first and second proportions are 1.40% or more and 83.4% or less.

8. The multilayer ceramic electronic component according to claim 7, wherein the first and second proportions are 1.40% or more and 25.0% or less.

9. The multilayer ceramic electronic component according to any one of claims 1 to 3, wherein the thickness of the first lower plating layer is 2 μm or more and 7 μm or less.

10. A multilayer ceramic electronic component according to any one of claims 1 to 3, wherein a portion of the first underlay electrode layer is exposed on the first main surface.

11. The multilayer ceramic electronic component according to claim 3 or 4, wherein the third ratio of the area of ​​the third plating exposed region to the area of ​​the exposed region of the third external electrode on the first main surface in the view in the direction of the first main surface, and / or the fourth ratio of the area of ​​the fourth plating exposed region to the area of ​​the exposed region of the fourth external electrode on the first main surface in the view in the direction of the first main surface, is 0.4% or more and 83.4% or less.

12. A multilayer ceramic electronic component according to any one of claims 1 to 3, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the first plated exposed region is located on the first main surface, and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate.

13. A multilayer ceramic electronic component according to claim 2 or 3, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the first external electrode and the second external electrode are electrodes to which a positive potential is applied.

14. A multilayer ceramic electronic component according to claim 4, A mounting structure for a multilayer ceramic electronic component comprising a mounting substrate on which the multilayer ceramic electronic component is mounted, A mounting structure for a multilayer ceramic electronic component, wherein the third external electrode and the fourth external electrode are electrodes to which a positive potential is applied.

15. The multilayer ceramic electronic component according to any one of claims 2 to 4, wherein the thickness of the third lower plating layer is 2 μm or more and 7 μm or less.

16. The multilayer ceramic electronic component according to claim 3 or 4, wherein a portion of the third underlay electrode layer is exposed on the first main surface.

17. A multilayer ceramic electronic component according to either claim 3 or 4, A mounting substrate on which the aforementioned multilayer ceramic electronic component is mounted, A mounting structure for multilayer ceramic electronic components comprising, A mounting structure for a multilayer ceramic electronic component, wherein the third plating exposure region is located on the first main surface, and the multilayer ceramic electronic component is mounted such that the second main surface faces the mounting substrate.

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