Silicon Brain

Abstract

To provide a semiconductor device equipped with a three-dimensional neural network using a three-dimensional silicon circuit network and independent of bits, and a method for manufacturing the same.SOLUTION: One module containing three units in the Z-axis direction reproduces an information processing mechanism of a human brain by switching the electrical connection of non-volatile memory cells distributed in a three-dimensional array, at the top, there is a Y-direction bit line BLY(i, k+1), at the bottom, there is an X-direction bit line BLX(j, k-2), and cell gates CG(i, j, k+1), CG(i,j,k), and CG(i, j, k-1) are sandwiched between them. Furthermore, an X-direction bit line BLX(j, k) is provided between CG(i, j, k+1) and CG(i, j, k), and a Y-direction bit line BLY(i, k-1) is provided between CG(i, j, k) and CG(i, j, k-1).SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a technology for providing a three-dimensional neural network using silicon chips.

Background Art

[0002] In a conventional calculation processing method using semiconductors, a storage device (memory) and an arithmetic processing device (such as a CPU) operate in cooperation. The storage device (semiconductor memory) consists of a set (array, cell array, memory cell array, or storage element array) of storage elements called memory cells (memory elements, bit cells, or simply cells). Each element consists of at least a source, a drain, and a gate (or a control gate). The source and the drain can be connected to bit lines respectively. The gates are connected to word lines respectively. , source line, and This connection is generally made through contacts (terminals). For example, a word line contact (terminal) or a bit line contact (terminal). When such a set of elements is distributed on a two-dimensional plane, access to each storage element is performed by word lines (WL) and bit lines (BL) arranged in the X direction and the Y direction perpendicular to each other on the two-dimensional plane. For example, the address of the memory element arranged at the intersection of the A-th word line and the B-th bit line is (A, B). This is called the address of the memory element. Here, A is particularly called the address on the X axis (X address). B is particularly called the address on the Y axis (Y address). According to Moore's law (see Non-Patent Document 1), it has long been the mainstream of semiconductor memory technology development to integrate more memory elements on the surface of a silicon wafer using semiconductor manufacturing processes. However, in recent years (after 2015), it has become difficult to increase the integration degree of memory elements in a two-dimensional plane, and a method of arranging memory elements in a three-dimensional space has become mainstream even at the mass production level. At this time, the address can be represented by (A, B, C). Here, C is the address on the Z axis (Z address) perpendicular to the XY plane.

[0003] ​

[0004] However, whether two-dimensional or three-dimensional, current semiconductor memory devices record information using memory elements as units. If each memory element (cell) has two values, 0 and 1, then each cell has a memory capacity (amount of information that can be stored) of 1 bit. If there are two such memory elements, the memory capacity is 2 bits. In this case, there are four possible combinations of 0 and 1: (00), (01), (10), and (11). The number in this case can be calculated by 2 to the power of 2. If a cell array consists of N memory elements, the memory capacity of that cell array is N bits. The number in this case can be calculated by 2 to the power of N.

[0005] Therefore, the amount of information (number of bits) in conventional semiconductor devices is expressed as a number of possibilities using a logarithmic scale with a base of 2.

[0006] In contrast, the human brain is not composed of memory elements. If there were anything that could be considered equivalent to memory elements, it would be the cell bodies that make up part of nerve cells, but these cell bodies do not store information such as 0s or 1s.

[0007] As briefly shown in Figure 1, a nerve cell (neuron) generally consists of three parts: a cell body, multiple (e.g., dozens) dendrites, and a single axon. The cell body can receive external input from these multiple dendrites. The axon is generally longer than the dendrites, and its tip further branches into dozens to hundreds of branches. The tips of these branched axons are called axon terminals (or axon endpoints).

[0008] As briefly shown in Figure 2, the axonal terminal approaches one of the dendrites of another cell body and forms a junction. This junction is called synapsis.

[0009] We have two cell bodies, A and B. Cell body A receives multiple inputs x(n) from the outside through multiple dendrites (n), where n is an integer from 1 to N. Cell body A assigns a weight W(n) to each input x(n). The signal obtained by summing these weights is called SUM. SUM is transmitted through the axon to one of the axon terminals. When SUM exceeds a certain threshold of exitation, the nerve cell generates an action potential, which drives synapsis and transmits neurotransmitters from cell body A to cell body B.

[0010] This threshold changes as the signal is repeatedly transmitted. In other words, repeated learning from experience can strengthen or weaken synaptic connections, or cause synaptic reassignment. Strengthening of synaptic connections can be explained by a decrease in the threshold. Synaptic breaks can be explained by an increase in the threshold. Synaptic reassignment can be explained by a decrease in the threshold of other synapses.

[0011] Figure 3 shows a model of this. When neurotransmitters are transmitted, the output y is set to 1 (y=1), and otherwise y=0. This model is called a perceptron. It is widely used in deep learning and machine learning.

[0012] There are mainly two ways to implement a perceptron on a computer.

[0013] The traditional method represents the input x(n), weights w(n), sum, threshold, and output y all as bit information; in other words, it's a computer program.

[0014] This method places a heavy load on computers, which is a significant problem. There is a greater need than ever for improved processing speed and reduced power consumption. Deep learning and machine learning require the instantaneous processing of massive amounts of data, and if computations that place a heavy load on the system flood the world, the power consumption of data centers will increase exponentially, making it practically impossible to operate them. Furthermore, there are growing concerns that this could accelerate global warming. (See Non-Patent Document 2)

[0015] The main cause of the computation speed limit is excessive data communication between the arithmetic unit and main memory. While the arithmetic unit can still be made faster, the communication speed of the data bus between the arithmetic unit and main memory has plateaued. This is called the von Neumann bottleneck (or memory bus problem).

[0016] The main reason for the increase in power consumption is that the currently dominant main memory is a volatile memory called dynamic random access memory (DRAM). As a result, the power consumption due to refreshing the recorded data has become significant and cannot be ignored.

[0017] A recent trend is to directly replicate the perceptron within a semiconductor chip to avoid the von Neumann bottleneck and simultaneously reduce power consumption. However, the neural network of the human brain is generally designed to generate synapses between two unspecified nerve cells. In other words, while current semiconductor technology makes it possible to place perceptrons at precisely defined addresses on a two-dimensional plane or three-dimensional space, it is not easy to replicate synapses between arbitrary nerve cells or to freely rearrange them according to learning.

[0018] Furthermore, as mentioned above, while existing memory architectures record information bit by bit, the human brain uses the connections between nerve cells (neural networks), that is, synapses. informationThis means that reproducing deep learning or machine learning on a program written with bit information is equivalent to writing an entire program just to model one unit of a neural network (a perceptron). This results in a significant loss of information processing.

[0019] For example, let's say a perceptron program can be written in about 1000 lines of code. If each line contains 80 bytes of information (1 byte = 8 bits), then reproducing a perceptron in a computer program would require 80 kilobytes of information. Even if the program is compiled and compressed to one-tenth of its original size, it would still be 8 kilobytes. If this could be reproduced using 100 bits on a semiconductor chip, then the computer program would be wasting 640 times the amount of information per perceptron.

[0020] The total number of nerve cells in the human brain (cerebrum and cerebellum) is estimated to be around 86 billion. Assuming that the number of nerve cells and the number of perceptrons are roughly equal, achieving artificial intelligence with human-level capabilities would require having the computer process an enormous amount of unnecessary information.

[0021] Deep learning and machine learning are not yet artificial intelligence that can rival the human brain. As artificial intelligence develops, the amount of information that computers are unnecessarily forced to process is expected to increase even further.

[0022] Next, we will compare the amount of information contained in a network with the amount of information contained in bits.

[0023] The study of networks is called graph theory in mathematics. Networks are generally represented by points connected by lines. In contrast, bit-level information processing involves processing information using only points, without any lines.

[0024] The points mentioned above are called vertices or nodes. The lines mentioned above are called edges or links. Nodes and links are rather terms preferred in physics, but each refers to the same thing as vertices and edges respectively.

[0025] Originally, a network is complex, and quite a few limiting conditions must be imposed to accurately estimate the information volume of a network. Figure 4 shows an example of this.

[0026] When connecting any two points (1 and 2), if the link from 1 to 2 and the link from 2 to 1 are regarded as different, it is called a directed network. Otherwise, it is called an undirected network. In a directed network, as shown in Figure 4, the link is represented by an arrow. The starting point and the ending point are represented by circles. Refer to the case of r = 2 in Figure 4. There are two combinations with two circles and one arrow. Here, r is the number of nodes to be linked.

[0027] When r = 3, two arrows are short-circuited and the starting point and the ending point are connected. The number of such cases is 6. When r = 4, three arrows are short-circuited and the starting point and the ending point are connected. The number of such cases is 8. Let the total number of nodes be N, and the number of cases where the number of linked nodes is r is represented by the product of the permutation P(N, r) of N and r. The sum of this product from r = 3 to N plus P(N, 2) is the number of cases of the network under this constraint. It is obvious that this is larger than the factorial of N (N!).

[0028] This does not cover all the possibilities of the network, but it is possible to show that the information volume of the network under such constraints is larger than the information volume in bits.

[0029] Consider the case where N nodes are distributed on a memory cell array. The information volume in bits is simply N bits. In contrast, the information volume of the network illustrated in Figure 4 is larger than log(2, N!). Here, log(2, x) is the logarithm of x with base 2.

[0030] Using Stirling's formula, when N is sufficiently large (effectively at least greater than 20), log (2, N!) is (Nlog(e,N) - N) / log(e, 2), where log (e, x) is the logarithm of x with base e. Dividing this value by N gives (log(e,N) - 1) / log(e, 2). This value is greater than 1 when N is sufficiently large.

[0031] When converted to 128 Gbit DRAM, the number of nodes (N) is approximately 10 to the power of 11. Since log(2, e) is approximately 1.9, it is obvious from Figure 5 that the amount of information in the network in Figure 4 is far greater than the amount of information in bits.

[0032] Next, networks can record information where the start and end points are the same, but the paths are different.

[0033] Figure 6 shows several examples of paths from a starting point (1) to an ending point (2). From left to right, the examples show paths with 2 links, 3 links, 4 links, 5 links, etc.

[0034] If there are two links, there will be one intermediate node in addition to the start point (1) and the end point (2). Depending on the address of this intermediate node, the signal flowing into the end point (2) may differ.

[0035] If there are three links, there are two intermediate nodes between the start point (1) and the end point (2). Depending on the permutation of the addresses of these two intermediate nodes, the signals flowing into the end point (2) may differ.

[0036] If there are four links, there are three intermediate nodes between the start point (1) and the end point (2). Depending on the permutation of the addresses of these three intermediate nodes, the signals flowing into the end point (2) may differ.

[0037] If there are 5 links, there are 4 intermediate nodes between the start point (1) and the end point (2). Depending on the permutation of the addresses of these 4 intermediate nodes, the signals flowing into the end point (2) may differ.

[0038] Thus, it can be seen that the amount of information a network can store is far greater than the amount of information that can be stored using the same number of bits as the number of nodes.

[0039] We will compare the amount of information contained in a 2D network and a 3D network.

[0040] The extent of a two-dimensional network on the XY plane is determined by the number of elements at address X and address Y. For simplicity, let both be L, then the number of nodes N is L squared. Therefore, using Stirling's formula, the information content of a two-dimensional network is 2log(e,L) - 1 multiplied by L squared.

[0041] The extent of a 3D network in XYZ space is determined by the number of elements at addresses X, Y, and Z. For simplicity, let's denote all of these as L, then the number of nodes N is L cubed. Therefore, using Stirling's formula, the information content of the 3D network is 3log(e,L)-1 multiplied by L cubed.

[0042] Figure 7 plots the ratio of information content in a 3D network to that of a 2D network. As shown, it can be seen that as L increases, the information content of the 3D network overwhelmingly surpasses that of the 2D network.

[0043] As mentioned above, conventional memory systems can only store 2 to the power of N, or N bits, of information for a given number of bit cells (nodes) N. Compared to the amount of information a network can hold, it is inherently inferior for the same number of nodes. If the memory mechanism of the human brain is a three-dimensional network of nerve cells, then an explosion in power consumption will occur before artificial intelligence based on conventional computers can achieve capabilities equivalent to the human brain. Moreover, the von Neumann bottleneck will likely hinder the development of artificial intelligence.

[0044] A considerable amount regarding memory architecture technology Without innovation, it is realistically difficult for artificial intelligence to achieve capabilities equivalent to those of the human brain. [Disclosure of the Invention] [Problems that the invention aims to solve]

[0045] This invention was made in view of the above circumstances, and aims to provide a method for generating a three-dimensional network within a silicon chip and recording information. [Means for solving the problem]

[0046] To solve the above problems, the present invention employs the following means.

[0047] The solution proposed by this invention is, A first unit and a second unit are connected in series in the first axial direction. The second, third, fourth, and fifth word lines extend in the second axial direction, The first and sixth word lines extend in the third axial direction, The first and third bit lines extend in the second axial direction, The second bit line extends in the third axis direction, It is a module consisting of, The second bit line is connected to both the first and second units, The first unit consists of a first, second, and third element, The first, second, and third elements are connected in series in the axial direction of the first element. The first, second, and third elements each have a control gate, The first element has a source, The third element has a drain, The control gate of the first element is connected to the first word line, The control gate of the second element is connected to the second word line, The control gate of the third element is connected to the third word line, The source of the first element is connected to the first bit line, The drain of the third element is connected to the second bit line, The second unit consists of a fourth, fifth, and sixth element, The fourth, fifth, and sixth elements are connected in series in the first axial direction. The fourth, fifth, and sixth elements each have a control gate, The fourth element has a source, The sixth element has a drain, The control gate of the fourth element is connected to the fourth word line, The control gate of the fifth element is connected to the fifth word line, The control gate of the sixth element is connected to the sixth word line, The source of the fourth element is connected to the second bit line, The drain of the sixth element is connected to the third bit line. It is characterized by the following:

[0048] Furthermore, The 7th, 8th, and 9th elements, The aforementioned The seventh and eighth word lines extend in the second axial direction, The aforementioned The ninth word line extends in the third axis direction, The aforementioned It consists of a fourth bit line extending in the third axis direction, The seventh, eighth, and ninth elements are connected in series in the first axial direction. The seventh, eighth, and ninth elements each have a control gate, The seventh element has a source, The eighth element has a drain, The control gate of the seventh element is connected to the seventh word line, The control gate of the eighth element is connected to the eighth word line, The control gate of the ninth element is connected to the ninth word line, The source of the seventh element is connected to the fourth bit line, The drain of the ninth element is connected to the first bit line. It is characterized by the following:

[0049] Furthermore, The 10th, 11th, and 12th elements, The aforementioned The 11th and 12th word lines extend in the second axial direction, The aforementioned The tenth word line extends in the third axis direction, The aforementioned It consists of a fifth bit line extending in the third axis direction, The 10th, 11th, and 12th elements are connected in series in the first axial direction. The 10th, 11th, and 12th elements each have a control gate, The aforementioned 10th element has a source, The 12th element has a drain, The control gate of the 10th element is connected to the 10th word line, The control gate of the 11th element is connected to the 11th word line, The control gate of the 12th element is connected to the 12th word line, The source of the 10th element is connected to the 3rd bit line, The drain of the 12th element is connected to the 5th bit line. It is characterized by the following:

[0050] The solution proposed by the present invention further has the following features. Having a first and a second wiring metal layer, The first bit line is connected to the first wiring metal layer, The second word line is connected to the second wiring metal layer, The third word line is connected to the first wiring metal layer, The fourth word line is connected to the second wiring metal layer, The fifth word line is connected to the first wiring metal layer, The third bit line is connected to the second wiring metal layer, Furthermore, The first and sixth word lines are connected to one of the first and second wiring metal layers, The second bit line connects to the other of the first and second wiring metal layers. It is characterized by the following:

[0051] The solution proposed by the present invention further has the following features. A first voltage is applied to the first, third, seventh, and ninth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, second, third, seventh, eighth, and ninth elements, respectively, in order to allow current to flow between the source and drain of the first, second, third, seventh, eighth, and ninth elements. The voltages of the first and ninth word lines are varied from the first voltage to the transmitted voltage. The transmitted voltage is higher than the threshold of any of the first, second, third, seventh, eighth, and ninth elements. The second and eighth word lines are read voltages applied, The read voltage is higher than the first voltage and lower than the transmitted voltage. Furthermore, A first voltage is applied to the first, third, fourth, and sixth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first to sixth elements, respectively, which is necessary to allow current to flow between the source and drain of the first to sixth elements. The voltages of the third and fourth word lines are varied from the first voltage to the transmitted voltage. The transmitted voltage is higher than the threshold voltage of any of the first to sixth elements. A read voltage is applied to the second and fifth word lines. The read voltage is higher than the first voltage and lower than the transmitted voltage. Furthermore, A first voltage is applied to the first, third, and 21st word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, third, and 21 elements, which is necessary to allow current to flow between the source and drain of the first, third, and 21 elements. The voltage applied to the first and 21st word lines is changed from the first voltage to the transmission voltage. The transmitted voltage is higher than the threshold of any of the first, third, and 21 elements. A read voltage is applied to the second word line. The read voltage is higher than the first voltage and lower than the transmitted voltage. Furthermore, A first voltage is applied to the first, third, and thirtieth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, third, and 33 elements, which is necessary to allow current to flow between the source and drain of the first, third, and 33 elements. The voltage applied to the third and thirtieth word lines is changed from the first voltage to the transmission voltage. The transmitted voltage is higher than the threshold of any of the first, third, and 33 elements. A read voltage is applied to the second and third word lines. The read voltage is higher than the first voltage and lower than the transmitted voltage. It is characterized by the following: [Effects of the Invention]

[0052] According to the present invention, it is possible to reproduce the information processing method of the human brain within a silicon chip without converting it to bit data.

[0053] The best mode for carrying out the invention will be described in detail below. [Best Mode for Carrying Out the Invention]

[0054] As described above, this invention proposes a method for reproducing the information processing method of the human brain using a semiconductor chip (silicon chip) without converting it to bit information (without relying on a computer program). This will be explained in detail below using the drawings. (First embodiment)

[0055] Figure 8 shows the coordinates used to define addresses in three-dimensional space. The address in the X-axis direction (X address) is represented by an integer i from 1 to Lx. The address in the Y-axis direction (Y address) is represented by an integer j from 1 to Ly. The address in the Z-axis direction (Z address) is represented by an integer k from 1 to Lz.

[0056] Figure 9 is a circuit diagram showing a part of an embodiment of the present invention extending in the Z-axis direction (Z direction). The XY address is (i, j). Cell gates CG(i, j, k+1), CG(i, j, k), and CG(i, j, k-1) are arranged from top to bottom. Each cell gate is in series, sandwiched between an upper selection gate SGU and a lower selection gate SGD. In other words, a 1-cell 2-selection gate (SG) structure forms one unit {SGU(i, j, k), CG(i, j, k), SGD(i, j, k)}.

[0057] In other words, three units are connected in series from above in the Z direction. This is considered one module and is represented as {SGU(i, j, k+1), CG(i, j, k+1), SGD(i, j, k+1) / SGU(i, j, k), CG(i, j, k), SGD(i, j, k) / SGU(i, j, k-1), CG(i, j, k-1), SGD(i, j, k-1)}. In this case, by changing k from 2 to L-1, the entire structure in the Z direction can be explained. However, if k+1 is changed to k-1 in the upper unit, it becomes identical to the lower unit. This means that there is a second-order periodicity with respect to the Z address (k). In other words, in this embodiment, there is a second-order periodicity in the Z direction based on two units.

[0058] In this embodiment, the word lines WCX(j, k+1), WCX(j, k), and WCX(j, k-1) of the cell gate CG all extend (are wired) in the X-axis direction (X direction).

[0059] The word lines of the upper selection gate SGU include those extending in the X direction and those extending in the Y direction (Y direction). For example, the word line WUX(j, k+1) of SGU(i, j, k+1) extends in the X direction. The word line WUY(i, k) of SGU(i, j, k) extends in the Y direction. The word line WUX(j, k-1) of SGU(i, j, k-1) extends in the X direction. Thus, in this embodiment, the word lines of SGU alternate between the X direction and the Y direction (in the Z direction) for each layer.

[0060] The word lines of the lower selection gate SGD include those extending in the X direction and those extending in the Y direction. For example, the word line WDY(i, k+1) of SGD(i, j, k+1) extends in the Y direction. The word line WDX(j, k) of SGD(i, j, k) extends in the X direction. The word line WDY(i, k-1) of SGD(i, j, k-1) extends in the Y direction. Thus, in this embodiment, the word lines of SGD alternate between the Y direction and the X direction (in the Z direction) for each layer. (This is the opposite of the word lines of SGU.)

[0061] In other words, the pattern {WUX(j, k+1), WDY(i, k+1)}, {WUY(i, k), WDX(j, k)}, {WUX(j, k-1), WDY(i, k-1)} is repeated for each layer. When decomposed, in this embodiment, the word lines of the selection gate (SG) alternate between the X and Y directions. This is symmetrical to the word lines of the cell gate, which extend only in the X direction.

[0062] Each of these word lines is equipped with a word line selection gate. Each word line selection gate is under the control of a decoder. The decoder consists of an X decoder that controls the selection gates of word lines wired in the X direction, and a Y decoder that controls the selection gates of word lines wired in the Y direction.

[0063] For example, WUX(j, k+1) has an X-direction word line selection gate WSGUX(j, k+1). WCX (j, k+1) has an X-direction word line selection gate WSGCX(j, k+1). WCX (j, k) has an X-direction word line selection gate WSGCX(j, k). WDX (j, k) has an X-direction word line selection gate WSGDX(j, k). WUX(j, k-1) has an X-direction word line selection gate WSGUX(j, k-1). WCX (j, k-1) has an X-direction word line selection gate WSGCX(j, k-1).

[0064] For example, a Y-direction word line selection gate WSGY(i, k+1) is installed at WDY(i, k). A Y-direction word line selection gate WSGY(i, k) is installed at WUY(i, k). A Y-direction word line selection gate WSGY(i, k-1) is installed at WDY(i, k-1).

[0065] Thus, in this embodiment, the selection gates of word lines connected to selection gates are alternately distributed in the X and Y directions for each layer (for every k). However, the selection gates of word lines connected to cell gates are distributed in the X direction.

[0066] The X decoder controls the word and bit lines extending in the X direction. The Y decoder controls the word and bit lines extending in the Y direction.

[0067] In other words, in this embodiment, the upper and lower selection gates are connected. Word lines are for each layer (for every k) This is done alternately by the X decoder and the Y decoder. However, cell gate The word lines connected are controlled by the X decoder. It will be controlled.

[0068] In this embodiment, between each unit, there is a bit line BLX extending in the X direction, Y Bit lines BLY extending in the direction are routed.

[0069] Therefore, a bit line BLX(j, k) is wired in the X direction between SGD(i, j, k+1) and SGU(i, j, k). Below SGD(i, j, k-1), a bit line BLX(j, k-2) extends (is wired) in the X direction.

[0070] Similarly, a bit line BLY(i, k+1) is routed in the Y direction above SGU(i, j, k+1). A bit line BLY(i, k-1) is routed in the Y direction between SGD(i, j, k) and SGU(i, j, k-1).

[0071] Thus, in this embodiment, bit lines are wired (extended) alternately in the X and Y directions for each layer (for every k layers).

[0072] Each of these bit lines has a bit line selection gate installed. Each bit line selection gate is under the control of a decoder. The decoder consists of an X decoder that controls the selection gates of the bit lines wired in the X direction, and a Y decoder that controls the selection gates of the bit lines wired in the Y direction.

[0073] For example, BLY(i, k+1) has a Y-direction bit line selection gate BSGY(i, k+1). BLX(j, k) has an X-direction bit line selection gate BSGX(j, k). BLY(i, k-1) has a Y-direction bit line selection gate BSGY(i, k-1). BLX(j, k-2) has an X-direction bit line selection gate BSGX(j, k-2).

[0074] In other words, in this embodiment, the bit line selection gate is controlled alternately by the X decoder and the Y decoder for each layer (for every k layers).

[0075] Figure 10 shows this circuit extended in the X-axis direction. As an example, three of the above modules are connected in the X direction.

[0076] In other words, three modules, {SGU(i-1, j, k+1), CG(i-1, j, k+1), SGD(i-1, j, k+1) / SGU(i-1, j, k), CG(i-1, j, k), SGD(i-1, j, k) / SGU(i-1, j, k-1), CG(i-1, j, k-1), SGD(i-1, j, k-1)} and {SGU(i, j, k+1), CG(i, j, k+1), SGD(i, j, k+1) / SGU(i, j, k), CG(i, j, k), SGD(i, j, k) / SGU(i, j, k-1), CG(i, j, k-1), SGD(i, j, k-1)}, {SGU(i+1, j, k+1), CG(i+1, j, k+1), SGD(i+1, j, k+1) / SGU(i+1, j, k), CG(i+1, j, k), SGD(i+1, j, k) / SGU(i+1, j, k-1), CG(i+1, j, k-1), SGD(i+1, j, k-1)} and They are arranged in the X direction.

[0077] Figure 11 shows this circuit diagram expanded along the Y-axis. As an example, the above module Y There are three of them lined up in that direction.

[0078] In other words, three modules, {SGU(i, j-1, k+1), CG(i, j-1, k+1), SGD(i, j-1, k+1) / SGU(i, j-1, k), CG(i, j-1, k), SGD(i, j-1, k) / SGU(i, j-1, k-1), CG(i, j-1, k-1), SGD(i, j-1, k-1)} and {SGU(i, j, k+1), CG(i, j, k+1), SGD(i, j, k+1) / SGU(i, j, k), CG(i, j, k), SGD(i, j, k) / SGU(i, j, k-1), CG(i, j, k-1), SGD(i, j, k-1)}, {SGU(i, j+1, k+1), CG(i, j+1, k+1), SGD(i, j+1, k+1) / SGU(i, j+1, k), CG(i, j+1, k), SGD(i, j+1, k) / SGU(i, j+1, k-1), CG(i, j+1, k-1), SGD(i, j+1, k-1)} and They are arranged in the Y direction.

[0079] A selection gate and a cell gate are arbitrary three-terminal elements. A three-terminal element is an electronic device having at least three terminals, including a gate terminal. The gate terminal is connected to a word line, and a control voltage can be input from the word line. The two terminals other than the gate terminal are connected to any bit line, so that an output current can flow to any bit line. However, the selection gate and cell gate may include terminals other than these three terminals.

[0080] For example, the selectable gates and cell gates usable in this application are any one of the following: transistors, non-volatile memory cells, volatile memory cells, phase-change memory cells, magnetoresistive memory cells, resistive random-access memory cells, ferroelectric memory cells, etc. In any case, this does not deviate from the concept and technical essence of this application.

[0081] Alternatively, the select gates and cell gates applicable to this application include at least one of the following as a component: a transistor, a non-volatile memory cell, a volatile memory cell, a phase-change memory cell, a magnetoresistive memory cell, a resistive random-access memory cell, a ferroelectric memory cell, etc. In either case, the application does not deviate from the concept and technical essence of this application.

[0082] In the circuit diagram of Figure 9-11, as an example, non-volatile memory cells with charge storage regions are used for the selection gates and cell gates (SGU, CG, SGD) that make up the unit. Transistors are used as an example for the word line and bit line selection gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY). However, transistors can also be used for the selection gates (SGU, SGD) that make up the unit, similar to the word line and bit line selection gates.

[0083] There are mainly two types of charge storage regions on the market. One is a floating gate, which is widely used in NOR flash and 2D NAND flash. The other is a charge-trapping layer, which is widely used in 3D NAND flash and the like. In either case, the concepts and technical essence of this invention do not deviate.

[0084] Figure 12 shows an example of the concept of the transistor characteristics (electrical characteristics) of a cell gate (CG) related to the present invention.

[0085] The horizontal axis represents the control voltage applied from the word line terminal. The vertical axis represents the output current flowing between the two terminals other than the word line terminal. The control voltage controls this output current according to the state of the charge storage region. Generally, this output current can be flowed through any of the bit lines. By connecting a sense amplifier to the bit line, it becomes possible to read the state of this charge storage region. Generally, such a sense amplifier is included in the decoder.

[0086] When the control voltage is sufficiently high, that is, when the transmission voltage (Vpass) is applied to the word line terminal, the cell gate (CG) outputs a constant output current regardless of the state of the charge storage region (layer). At this time, the cell gate transistor is said to be in the switched-on state. However, the state of the charge storage layer refers to the amount of charge held in the charge storage layer. Regardless of the state of the charge storage layer means regardless of the amount of charge held in the charge storage layer, as long as it is within a certain range. Furthermore, the amount of charge held in the charge storage layer can be intentionally changed by writing to and erasing the element. It is desirable that the transmission voltage be higher than the threshold voltage of any element in which the amount of charge held in the charge storage layer is within a certain range.

[0087] When the control voltage is sufficiently low, that is, when a constant voltage (Voff) is applied to the word line terminal, the cell gate (CG) outputs almost no current, regardless of the state of the charge storage region. At this time, the cell gate transistor is said to be in the switched-off state. In other words, Voff is a voltage lower than the threshold voltage (Vt). If a sufficiently high voltage is applied to the gate of the cell gate transistor, current can flow between the source and drain of the cell gate transistor. The threshold voltage of the cell gate transistor is the voltage threshold required to allow this current to flow.

[0088] Generally, this threshold voltage does not correspond to the threshold of excitation (SUM) that drives synapses to move neurotransmitters from cell body A to cell body B.

[0089] In Figure 12, In addition to Vpass Three dotted lines are drawn vertically. For example, Vread can be adjusted between the two dotted lines at either end. Currents (1), (2), and (3) correspond to the output when Vread is positioned at the central dotted line, as an example.

[0090] When the control voltage is the read voltage (Vread), the output current is variable depending on the state of the charge storage region, for example, as shown in Figure 12 (1), (2), and (3). This can be rephrased as the voltage at which the output current begins to flow (threshold voltage, Vt) being variable. However, Vread is the voltage between Voff and Vpass, and Vread can also be adjusted as needed.

[0091] The output current when Vrea is applied can be reduced by injecting electrons into the charge storage region (writing). For example, this is shown in (3) of Figure 12. This corresponds to an increase in Vt and is called writing. Conversely, the output current when Vread is applied can be increased by removing electrons from the charge storage region (layer) (erasing). For example, this is shown in (1) of Figure 12. This corresponds to a decrease in Vt and is called erasing.

[0092] Since both writing and erasing are performed within a predetermined range, Vt has a convenient upper and lower limit. That is, Vpass is a voltage at least higher than this convenient upper limit of Vt. Therefore, Vpass is higher than the read voltage (Vread). Voff is a voltage lower than this convenient lower limit of Vt.

[0093] When a control voltage Vt is applied, the output current has just begun to flow, and as the control voltage is further increased from Vt, the output current increases. When the control voltage is further increased and becomes sufficiently high, the output current saturates. This current is called the saturation current. Vpass is a voltage high enough that the output current saturates even when Vt is written up to its convenient upper limit. In other words, Vpass is high enough that even when Vt is written up to its convenient upper limit, the output current that flows is about the same as when it is written up to its convenient lower limit.

[0094] The difference between Vpass and the convenient upper limit of Vt can be kept low as the S factor (the voltage required to increase the current by an order of magnitude near Vt) decreases. In terms of transistor characteristics as shown in Figure 12, a lower S factor indicates better transistor characteristics.

[0095] Figure 13 shows an example of the conceptual transistor characteristics (electrical characteristics) of word line and bit line selection gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY) related to this application. These word line and bit line selection gates do not require a charge storage region. Therefore, unlike in Figure 12, the threshold voltage (Vt) is not necessarily variable.

[0096] Generally, this threshold voltage does not correspond to the threshold of exitation (SUM) that drives synapses to move neurotransmitters from cell body A to cell body B.

[0097] The word line and bit line selection gates receive a control voltage from the decoder. The horizontal axis in Figure 13 represents this control voltage, and the vertical axis represents , flowing through the bit line according to the control voltage This is the output current. When the control voltage is higher than Vt, for example, when a high voltage (Von) corresponding to the position of the dotted line in the diagram is applied as the control voltage, an output current flows and the transistor switches on. In other words, Von is a voltage higher than Vt.

[0098] When the control voltage is lower than Vt, for example, when Voff is applied as the control voltage, almost no output current flows and the transistor is switched off. In other words, Voff is a voltage lower than Vt. When Vt in Figure 13 is higher than the convenient lower limit of Vt in Figure 12, Voff in Figure 13 and Voff in Figure 12 can usually be made the same.

[0099] The transistor characteristics (electrical characteristics) of SGD and SGU can be either those shown in Figure 12 or Figure 13. In other words, SGD and SGU may or may not have charge storage regions. However, semiconductor manufacturing costs can be lowered if SGD and SGU have the same device structure as cell gate CG. Therefore, in this embodiment, as an example, SGD and SGU are made into non-volatile memory cells that also have charge storage regions. In this case, the device structure is the same as that of cell gate CG, and it can be manufactured using the same manufacturing method as for CG. Therefore, in this case, the transistor characteristics (electrical characteristics) of SGD and SGU will also be as shown in Figure 12. However, it is not necessary to adjust the state of the charge storage regions of SGD and SGU in coordination with cell gate CG within the same unit.

[0100] However, even if SGD and SGU are transistors having the characteristics shown in Figure 13, this does not exceed the scope of this application. Furthermore, even if any of the word line and bit line selection gates (BSGX, BSGY, WSGC, WSGUX, WSGDX, WSGUY, WSGDY) are transistors having the characteristics shown in Figure 12, this does not exceed the scope of this application. (Second embodiment)

[0101] To generate a free-flowing 3D network similar to the human brain within a semiconductor chip, at least a method is needed to link any two cell gates (CGs) placed on a 3D cell array.

[0102] Figure 14 shows an example of a link between two cells enclosed by dashed lines, CG(i, j, k+1) and CG(i, j, k). Figure 15 shows an example of a voltage set for connecting (linking) these two cells enclosed by dashed lines.

[0103] A bit line BLX(j, k) exists between the two cells enclosed by the dashed line, CG(i, j, k+1) and CG(i, j, k). First, to isolate this from the cells other than the two enclosed by the dashed line, Voff is applied to BSGX(j, k), Voff is applied to WDY(i', k+1), and Voff is applied to WUY(i', k). Here, i' is an integer from 1 to Lx that is different from i.

[0104] Furthermore, Voff is applied to WUX(j, k+1), Vread to WCX(j, k+1), Voff to WDY(i, k+1), Voff to WUY(i, k), Vread to WCX(j, k), and Voff to WDX(j, k). In this way, BLX(j, k) becomes floating.

[0105] Apply Von to WSGUX(j, k+1), WSGCX(j, k+1), WSGDY(i, k+1), WSGUY(i, k), WSGCX(j, k), and WSGDX(j, k). Next, increase the voltages of WDY(i, k+1) and WUY(i, k) from Voff to Vpass, and the two cells enclosed by the dashed lines, CG(i, j, k+1) and CG(i, j, k), will be connected (linked).

[0106] Furthermore, to connect (link) cell gate CG(i, j, k) to CG(i, j, k-1), it is necessary to increase the voltage of WDX(j, k) from Voff to Vpass. Furthermore, to connect (link) cell gate CG(i, j, k+1) to CG(i, j, k+2), it is necessary to increase the voltage of WUX(j, k+1) from Voff to Vpass.

[0107] Since there is a second periodicity in the Z direction, CG(i, j, k) and CG(i, j, k-1) must be linked in a different way than in Figure 14. One example of this is explained in Figures 16 and 17. In Figure 16, CG(i, j, k) and CG(i, j, k-1) are enclosed by dashed lines.

[0108] A bit line BLY(i, k-1) exists between the two cells enclosed by the dashed line, CG(i, j, k) and CG(i, j, k-1). First, to isolate this from cells other than CG(i, j, k) and CG(i, j, k-1), Voff is applied to BSGY(i, k-1), Voff is applied to WDX(j', k-1), and Voff is applied to WUX(j', k-1). Here, j' is an integer from 1 to Ly that is different from j.

[0109] Furthermore, Voff is applied to WUY(i, k), Vread to WCX(j, k), Voff to WDX(j, k), Voff to WUX(j, k-1), Vread to WCX(j, k-1), and Voff to WDY(j, k-1). In this way, BLY(i, k-1) becomes floating.

[0110] Von is applied to WSGUY(i, k), WSGCX(j, k), WSGDX(j, k), WSGUX(j, k-1), WSGCX(j, k-1), and WSGDY(i, k-1).

[0111] Next, when the voltages of WDX(j, k) and WUX(j, k-1) are increased from Voff to Vpass, the two cells enclosed by the dashed lines, CG(i, j, k) and CG(i, j, k-1), are connected (linked).

[0112] To connect cell gate CG(i, j, k) to CG(i, j, k+1), the voltage of WUY(i, k) must be increased from Voff to Vpass. To connect cell gate CG(i, j, k-1) to CG(i, j, k-2), the voltage of WDY(i, k-1) must be increased from Voff to Vpass.

[0113] Next, an example of how to create a link (connection) in the X direction will be explained using Figures 18 and 19.

[0114] In Figure 18, a link in the X direction is realized using the bit line BLX(j, k). First, to isolate it from the cells other than the two cells enclosed by the dashed line, CG(i, j, k) and CG(i+1, j, k), Voff is applied to BSGX(j, k), Voff is applied to WUY(i', k), and Voff is applied to WDY(*, k+1). Here, i' is an integer from 1 to Lx that is different from i, and * is any integer from 1 to Lx. Furthermore, by applying Voff to WUY(i, k) and WUY(i+1, k), BLX(j, k) can be made floating. By applying Voff to WDX(j, k), it is disconnected from the bit line BLY(*, k-1) in the Y direction. Here, * is from 1 to Let Lx be any integer up to Lx. When the voltage applied to WUY(i, k) and WUY(i+1, k) is increased from Voff to Vread, the two cells enclosed by the dashed line This enables linking (connection) between CG(i, j, k) and CG(i+1, j, k).

[0115] To connect the two cells enclosed by the dashed lines, CG(i, j, k) and CG(i+1, j, k), to another cell in the Y direction, it is necessary to increase the voltage applied to WDX(j, k) from Voff to Vpass.

[0116] Next, using Figures 20 and 21, we will look at the Y direction. to This section explains one example of how to link (connect) to something.

[0117] In Figure 20, a link in the Y direction is realized using the bit line BLY(i, k-1). First, to isolate this from the cells other than the two cells enclosed by the dashed line, CG(i, j, k) and CG(i, j+1, k), Voff is applied to BSGY(i, k-1), Voff is applied to WDX(j', k), and Voff is applied to WUX(*, k-1). Here, j' is an integer from 1 to Ly that is different from j, and * is any integer from 1 to Ly. Furthermore, by applying Voff to WDX(j, k) and WDX(j+1, k), BLY(i, k-1) can be made to a floating state. By applying Voff to WUY(i, k), it is disconnected from the bit line BLX(*, k) in the X direction. Here, * is an arbitrary integer from 1 to Ly. Let it be any integer. When the voltage applied to WDX(j, k) and WDX(j+1, k) is increased from Voff to Vread, the two cells enclosed by the dashed line This enables linking (connection) between CG(i, j, k) and CG(i, j+1, k).

[0118] To connect the two cells enclosed by the dashed lines, CG(i, j, k) and CG(i, j+1, k), to another cell in the X direction, it is necessary to increase the voltage applied to WUY(i, k) from Voff to Vpass. (Third embodiment)

[0119] In the second embodiment, a method for connecting any two cell gates distributed in three-dimensional space was described. In Figures 22 to 28 illustrating this embodiment, the two cell gates (or simply called cells, corresponding to memory cells) connected in the second embodiment are simplified and enclosed by solid lines.

[0120] However, to reproduce the perceptron in Figure 3, an additional mechanism for summing multiple inputs is needed. Figure 22 illustrates a method for summing the output currents of cells CG(i, *, k) arranged in the Y direction using the bit line BLY(i, k-1). Here, * can be any integer from 1 to Ly. First, to make BLY(i, k-1) floating, Voff is applied to BSGY(i, k-1), Voff is applied to WDX(*, k), and WUX(* Apply Voff to k-1).

[0121] Of course, it's not always necessary to sum the outputs from all cells arranged in the Y direction. to A function to sum the outputs from various selected cells is sufficient. Therefore, a selection gate W D Vread is applied to X(j1, k). Here, j1 is the Y address (first selected Y address) of the cell selected for summing the outputs in BLY(i, k-1). The number of first selected addresses (j1) can be singular or multiple.

[0122] A cell assigned to the first selected address Y can output current according to the state (Vt) of its charge storage region. As an example, Figure 12 uses three states, (1), (2), and (3), for explanation, but the number of states is not necessarily limited to three. The number of states can be two, four, or even more. That is, M states are possible, and M is generally an integer greater than 1. This is called M Level Per Cell (MLC), but in the field of flash memory technology, MLC is conventionally defined as having 4 states. Eight states above that are called TLC, and 16 states are called QLC. Thus, it is known that the number of states per cell can already reach 16 at the product level. (See Non-Patent Literature 3) Technological innovation may lead to even more states in the future, and it is not necessary to limit it to a multiple of 2. Therefore, it is possible that M (number of states per cell) can be any integer greater than 1.

[0123] To separate BLY(i, k-1) from the layer below, Voff is applied to WUX(*, k-1), where * is any integer from 1 to Ly. The voltage applied to WDX(j1, k) at the first selected Y address (j1) is increased from Voff to Vpass. Alternatively, if Voff is applied to the unselected WCX(unselected j, k), Vpass may be applied to the WDX(*, k) at all Y addresses (*), where * is any integer from 1 to Ly. The Y-direction bit line selection gate BSGY(i, k-1) is in a standby state when the voltage applied to it is Voff. When this Voff is increased to Von, the output currents of the selected cell CG(j1, k) are added together in BLY(i, k-1) and sensed by the sense amplifier (S / A).

[0124] The sense amplifier is usually included in the decoder, but it may be installed separately from the decoder. In any case, it is installed outside the cell array. The sense amplifier determines whether the summed current level in BLY(i, k-1) is higher or lower than a predetermined threshold, and after the determination, applies Voff again to BSGY(i, k-1). If the summed current level is higher than the predetermined threshold, it is considered a synaptic activation state. Otherwise, it is considered a synaptic deactivation state.

[0125] In the synaptic activation state, as shown in Figure 23, the voltage applied to WUX(j2, k-1) is increased from Voff to Vpass, and the summed current of BLY(i, k-1) is transferred as a new input to the second selected cell CG(j2, k-1). Here, j2 is the second selected Y address. When Von, Von, and Vpass are applied to BSGX(j2, k-2), WSGDY(i, k-1), and WDY(i, k-1) respectively, the output from the second selected cell CG(j2, k-1) can be read out by a sense amplifier. This sense amplifier may be the same as the sense amplifier in Figure 22, or it may be a separately installed sense amplifier. In this case, the voltage applied to WCX(j, k-1) is either Vread or Vpass.

[0126] In this way, the cell body (A) in Figures 1 and 2 is simulated using BLY(i, k-1), BSGY(i, k-1), and a sense amplifier. Cells CG (i, j1, k) that have one or more of the aforementioned first selected Y addresses (j1) as arguments correspond to the dendrites of the cell body (A) in Figure 2. That is, the current input to CG(i, j1, k) corresponds to the signal input to the dendrites of the cell body (A) in Figure 2. This signal corresponds to x(j1) in Figure 3. The Vt of these cells is variable and each is in a pre-programmed state. When Vread is applied to each word line, the output from these cells CG (i, j1, k) that have j1 as an argument is variable depending on the programmed state of Vt. This corresponds to multiplying the input x(j1) by the weight W(j1) in the perceptron in Figure 3. However, j1 is an integer from 1 to N in Figure 3. In other words, the input to CG (i, j1, k) is x(j1) in Figure 3, and the output from CG (i, j1, k) is the product x(j1)W(j1) with the weights. BLY(i, k-1) sums up this product x(j1)W(j1) from 1 to N. can be This is the SUM of the perceptron in Figure 3. In this case, BLY(i, k-1) can be considered the main body of the cell (A) in Figure 2. The sense amplifier and selection gate BSGY(i, k-1) are used to explain the function of the cell (A).

[0127] The aforementioned SUM is sensed by a sense amplifier and compared with the threshold of excitation. If the SUM is higher than the threshold, it is considered a synaptic activation state, and Vpass is applied to WUX(j2, k-1) to determine the second selected Y address ( j2) is connected to CG(i, j2, k-1) which has as an argument. This creates a synapse. That is, CG(i, j2, k-1) plays the role of a dendrite on the cell body (B) side, which constitutes the synapse between cell body (B) and cell body (A) in Figure 2. In this case, BLX(j2, k-2) is considered to be the main body of cell body (B) in Figure 2. The selection gate BSGX(j2, k-2) and sense amplifier are used to explain the function of cell body (B).

[0128] Figure 24 is a diagram illustrating an example of how to sum the outputs from CG(*, j, k+1) using BLX(j, k), where * is any integer from 1 to Lx. Vread is applied to the word line WCX(j, k+1) connected to each cell. Next, Voff is applied to BSGX(j, k) to make BLX(j, k) floating, and Voff is also applied to WUY(*, k) and WDY(*, k+1). vinegar The voltage of WDY(i1, k+1) connected to the selected X address (first selected X address i1) is increased from Voff to Vpass. Here, the first selected address i1 can be singular or plural. Next, Vpass is applied to WUY(i2, k) connected to the selected X address (second selected X address i2), and the current added by BLX(j, k) can be transferred to cell CG(i2, j, k).

[0129] In this way, the cell body (A) in Figures 1 and 2 is simulated using BLX(j, k), BSGX(j, k), and a sense amplifier. Multiple or single cells CG (i1, j, k+1) that have the first selected X address (i1) as an argument correspond to the dendrites of the cell body (A) in Figure 2. The current input to CG (i1, j, k+1) corresponds to the signal input to the dendrites of the cell body (A) in Figure 2. This input signal corresponds to x(i1) in Figure 3. The Vt of these cells is variable and each is in a pre-programmed state. When Vread is applied to each word line, the output from these cells CG (i1, j, k+1) that have i1 as an argument is variable depending on the programmed state of Vt. This corresponds to multiplying the input x(i1) by the weight W(i1) in the perceptron in Figure 3. However, i1 is an integer from 1 to N in Figure 3. That is, the input to CG (i1, j, k) is x( in Figure 3). i 1) The output from CG (i1, j, k) is the product x(i1) W(i1) with the weights. In BLX(j, k), this product x(i1) W(i1) is summed up from 1 to N. Obtained This is the SUM of the perceptron in Figure 3. In this case, BLX(j, k) can be considered the main body of the cell (A) in Figure 2. The sense amplifier and selection gate BSGX(j, k) are used to explain the function of the cell (A).

[0130] The aforementioned SUM is sensed by a sense amplifier and compared with the threshold of excitation. If SUM is higher than the threshold, it is considered a synaptic activation state, and Vpass is applied to WUY(i2, k) to connect to CG(i2, j, k) which has the second-selection address X (i2) as an argument. This creates a synapse. In other words, CG(i2, j, k) plays the role of a dendrite on the cell body (B) side, which constitutes the synapse between cell bodies (B) and cell bodies (A) in Figure 2. In this case, BLY(i2, k-1) is considered to be the main body of cell body (B) in Figure 2. The selection gate BSGY(i2, k-1) and the sense amplifier are used to explain the function of cell body (B).

[0131] Thus, in this invention, the bit line plays the role of a cell body, and the cell (memory cell) plays the role of a dendrite. This is one of the most distinctive features of this invention. (Fourth embodiment)

[0132] Repeating the method described in the second embodiment, it is possible to extend various connections in the X, Y, and Z directions. This means that it is possible to connect any two cells distributed within the cell array. Figure 25 shows an example. The starting cell is CG(i', j', k') and the ending cell is CG(i, j, k). For simplicity, the cells that data passes through to transfer data from the starting point to the ending point are represented by hollow square symbols (□). For simplicity, the upper and lower selection gates that form a unit with each cell (□) through which data passes are omitted, but Vpass is applied to each upper and lower selection gate that forms a unit with each passing cell (□). The number of passing cells (□) connecting the starting point and the ending point can be zero, singular, or multiple. The third embodiment shows the passing between the starting point and the ending point. cell This corresponds to the case where the number of (□) is zero.

[0133] The aforementioned passing cells (□) are used to recreate the axons in Figures 1 and 2. The starting cell CG(i', j', k') and the ending cell CG(i, j, k) play the role of dendrites that constitute the synapse between cell bodies (A) and cell bodies (B) in Figure 2. In this case, the starting cell CG(i', j', k') is on the cell body (A) side. axon terminal This corresponds to the terminal cell CG(i, j, k), and the dendrite on the cell body (B) side corresponds to the dendrite.

[0134] In the example shown in Figure 22, it is possible to further connect in the X, Y, and Z directions from the cell CG(i, j, k) where the output signals are added together at BLY(i, k-1), as shown in Figure 25.

[0135] As an example, Figure 26 illustrates the case where inputs from three starting points, CG(ii1, jj1, kk1), CG(ii2, jj2, kk2), and CG(ii3, jj3, kk3), are weighted and then added together by BLY(i, k-1). Of course, the number of starting points is not limited to three. It can be one or two, or even a larger integer. The upper limit of the number of starting points is the product of Lx, Ly, and Lz. These starting points each play the role of dendrites in Figures 1 and 2.

[0136] In Figures 22 and 23, CG(i, j1, k) with the first selected Y address (j1) as an argument becomes the last cell passed through in the sequence leading to BLY(i, k-1). Here, j1 is an integer from 1 to N. N is the number of external inputs received by the perceptron in Figure 3. In this example, it can be considered the same as the number of starting points. That is, the input to the starting cell is the input x(j1) to the perceptron in Figure 3. Vread is applied to the word line of the starting cell. Here, when the input currents are added together in BLY(i, k-1), a weight W(j1) is multiplied according to the state of Vt of each starting cell. The roles of BLY(i, k-1), BSGY(i, k-1), and the sense amplifier are the same as those explained in Figures 22 and 23, so details are omitted.

[0137] For each traversed cell's word line, you should apply either Vpass or Vread. Incidentally, the integer kk3 can be less than or equal to k-1, or greater than or equal to k-1. The integer ii2 can be greater than or equal to i, or less than or equal to i. The integer jj2 can be greater than or equal to j, or less than or equal to j.

[0138] As an example, Figure 27 illustrates the case where inputs from three starting points, CG(ii1, jj1, kk1), CG(ii2, jj2, kk2), and CG(ii3, jj3, kk3), are weighted and then added together by BLX(j, k). Of course, the number of starting points is not limited to three. It can be one or two, or even a larger integer. The upper limit of the number of starting points is the product of Lx, Ly, and Lz. These starting points each play the role of dendrites in Figures 1 and 2.

[0139] In Figure 24, CG(i1, j, k) with the first selected cell X (i1) as an argument becomes the last cell passed through in the sequence leading to BLX(j, k-1). Here, i1 is an integer from 1 to N. N is the number of external inputs the perceptron receives in Figure 3. In this example, it can be considered the same as the number of starting points. That is, the input to the starting cell is the input x(i1) to the perceptron in Figure 3. Vread is applied to the word line of the starting cell. Here, when the inputs are added together in BLX(j, k), a weight W(i1) is multiplied according to the state of Vt of each starting cell. The roles of BLX(j, k), BSGX(j, k), and the sense amplifier are the same as explained in Figure 24, so the details are omitted.

[0140] Let's return to Figure 25. Either Vpass or Vread should be applied to the word lines of each cell passed through between the starting point CG(i', j', k') and the ending point CG(i, j, k). If Vread is applied to the word lines of all cells passed through, the input current flowing into the starting point and the current transferred to the ending point can be considered to be at approximately the same level, excluding the effects of wiring resistance, parasitic resistance, etc. In this case, the path taken from the starting point to the ending point is irrelevant.

[0141] Conversely, when Vread is applied to one or more cells along the path from the starting point to the ending point, the current transferred from the starting point to the ending point may vary depending on the path. This is because the Vt of the cells passed along the way may be different. If Vt is different, the output current from those cells will be different, as shown in Figure 12. In other words, as shown in Figure 28, even if the starting point CG(i', j', k') and the ending point CG(i, j, k) are the same, the currents flowing into BLY(i, k+1) through two different paths (path-A and path-B) may be different from each other. Similarly, as shown in Figure 29, even if the starting point CG(i', j', k') and the ending point CG(i, j, k) are the same, the currents flowing into BLY(i, k+1) through two different paths (path- C and path- D The currents flowing into BLX(j, k) after passing through ) may be different from each other.

[0142] In other words, by applying Vread to the word lines of the cells being passed through, it becomes possible to record information along the path (network) from the starting point to the ending point. Thus, the ability to record information along a path (network) in the same way as a neural network, despite being a silicon chip, is one of the features of this invention.

[0143] Now, let's return to Figure 12. In the voltage domain of Vread, the current differs according to the pre-programmed Vt. In other words, a cell to which Vread is applied can be considered a variable resistor. That is, when Vread is applied to each cell, changing the path from the start to the end point is the same as changing the resistance of the path from the start to the end point. In this way, it becomes possible to record information in a network, just like the neural circuits of the human brain. (Fifth embodiment)

[0144] Figure 9 is an equivalent circuit diagram illustrating an example of the first embodiment, where address X is i and address Y is j. At the top is the Y-direction bit line BLY(i, k+1), and at the bottom is the X-direction bit line BLX(j, k-2). Between them are the cell gates CG(i, j, k+1), CG(i, j, k), and CG(i, j, k-1). Between CG(i, j, k+1) and CG(i, j, k) is the X-direction bit line BLX(j, k). Between CG(i, j, k) and CG(i, j, k-1) is the Y-direction bit line BLY(i, k-1). This reflects the characteristic second-order periodicity of the present invention. Each cell gate is sandwiched between the upper selection gate SGU and the lower selection gate SGD to form one unit. That is, Figure 9 is an equivalent circuit of one module containing three units in the Z-axis direction.

[0145] Figure 30 is a cross-sectional view on the ZY plane showing an example of a cell design that realizes the equivalent circuit of Figure 9. Here, address X is i and address Y is j.

[0146] At the upper end of one module in the Z-axis direction is a bit line BLY(i, k+1) extending in the Y-direction. At the lower end of one module in the Z-axis direction is a bit line BLX(j, k-2) extending in the X-direction. Three units, each consisting of a cell gate CG, an upper selection gate SGU, and a lower selection gate SGD, are arranged from top to bottom along the Z-axis direction. Let them be Unit(k+1), Unit(k), and Unit(k-1) from top to bottom. Between Unit(k+1) and Unit(k) is BLX(j, k) extending in the X-direction, and between Unit(k) and Unit(k-1) is BLY(i, k-1) extending in the Y-direction.

[0147] In this cross-sectional view, when z-address (k) is transformed to k-2, Unit(k+1) is transformed to Unit(k-1). These two units have exactly the same word line layout. Considering one module in the Z-axis direction in this way, it can be seen that this embodiment has a second-order periodicity in the Z-axis direction. In other words, to explain the features of the cross-sectional view of this embodiment, it is sufficient to explain one pair of Unit(k+1) and Unit(k). The same applies to Figure 9.

[0148] Unit(k+1) consists of a cell gate CG(i, j, k+1) and two upper and lower selection gates, SGU(i, j, k+1) and SGD(i, j, k+1), which sandwich it from above and below. SGU(i, j, k+1) is subjected to Vpass or Voff from a word line WUX(j, k+1) extending in the X direction. SGD(i, j, k+1) is subjected to Vpass or Voff from a word line WDY(i, k+1) extending in the Y direction. CG(i, j, k+1) is subjected to Vread, Vpass, or Voff from a word line WCX(j, k+1) extending in the X direction. Thus, it has the same characteristics as the first embodiment.

[0149] Unit(k) consists of a cell gate CG(i, j, k) and two upper and lower selection gates, SGU(i, j, k) and SGD(i, j, k), which sandwich it from above and below. SGU(i, j, k) is subjected to Vpass or Voff from a word line WUY(i, k) extending in the Y direction. SGD(i, j, k) is subjected to Vpass or Voff from a word line WDX(j, k) extending in the X direction. CG(i, j, k) is subjected to Vread, Vpass, or Voff from a word line WCX(j, k) extending in the X direction. Thus, it has the same characteristics as the first embodiment.

[0150] The Z-direction module in Figure 30, used as an example for explanation, is located at the XY address (i, j) on the XY plane. At this XY address (i, j), a hole is drilled in the Z-axis direction and filled with a semiconductor material to form a channel via. As the semiconductor material, polysilicon, amorphous silicon, epitaxial silicon, and other semiconductor materials can be used.

[0151] Channel vias (CVs) are formed between each bit line BLY(i, k+1), BLX(j, k), BLY(i, k-1), and BLX(j, k-2). Since bit lines are usually formed from thin metal films, a diffusion layer needs to be formed between the bit line and the junction (bit line contact, BL contact) to prevent Schottky junction defects. In Figure 30, a dense N-type diffusion layer (N+ layer) is formed. Techniques for forming such junctions are common in semiconductor manufacturing. As an example, holes are first made in an etched thin metal film. As the semiconductor material approaches the thin metal film layer while filling the holes, a dopant can be mixed into the chamber. Then, annealing is performed as needed. For this reason, the spacing between the bit lines and each unit must be sufficiently wide.

[0152] Figure 31 is a top view of the bit lines BLY(i, k+1) and BLY(i, k-1) extending in the Y direction. That is, it is a drawing cut horizontally from the XY plane by layers of BLY(i, k+1) and BLY(i, k-1). The bit line width is even considering manufacturing variations. Channel Department The bit line width must always be larger than the hole (CV) used to create it. Therefore, a sufficient margin is required in the difference between the bit line width and the size of the CV. In Figure 31, multiple bit line contacts (BL contacts) are arranged in the Y direction. In this embodiment, as an example, an N+ diffusion layer is formed inside the CV.

[0153] Figure 32 shows the bit line extending in the X direction. BLX(j, k) and BLX(j, k-2)This is a top view. That is, it is a drawing cut horizontally from the XY plane by layers of BLX(j, k+1) and BLX(j, k-1). The bit line width must always be larger than the vertical hole (CV) made to create the channel, even taking into account manufacturing variations. Therefore, a sufficient margin is required in the difference between the bit line width and the size of the CV. In Figure 32, multiple bit line contacts (BL contacts) are lined up in the X direction. In this embodiment, as an example, an N+ diffusion layer is formed inside the CV.

[0154] Figure 33 is a top view of a word line WCX(j, k+1) extending in the X direction, connected to a cell gate CG(i, j, k+1). That is, it is a drawing cut horizontally from the XY plane by the layer of CG(i, j, k+1). The word line width must always be larger than the vertical hole (CV) created to form the channel, even taking manufacturing variations into account. Therefore, a sufficient margin is required in the difference between the word line width and the size of the CV.

[0155] Inside a channel via (CV), from the center outwards, there is a core, a tunnel oxide film (or simply tunnel oxide), and a charge storage layer. layer It consists of a core, a block film, a control gate, etc. The core is the channel through which current flows when the switch is turned on, and can be formed from polysilicon, for example. The tunnel oxide is a thin film through which electrons or holes can pass by quantum tunneling, and can be formed from a thin insulating film such as silicon oxide, for example. However, quantum tunneling is referred to as representatively Fowler-Nordheim tunneling (FN tunneling), direct tunneling, etc. The charge storage layer can store electrons or holes that have passed from the core through the tunnel oxide, and can be formed from a thin insulating film such as silicon nitride. Incidentally, storing electrons or holes from the core into the charge storage layer by quantum tunneling is called writing (programming). Conversely, by quantum tunneling charge storage layerThe process of extracting electrons or holes from the charge storage layer into the core is called elimination. The block film is used to confine electrons and holes stored in the charge storage layer to the control gate and can be formed from a relatively thick insulating film such as a high dielectric oxide film. A high dielectric constant is required to make the block film as thick as possible to increase the confinement effect. The control gate is connected to a word line and controls the electric field that the word line applies to the core and can be formed from a thin film of a conductive material such as metal. As shown in the cross-sectional view in Figure 33, it is a cylindrical conductive thin film (cylindrical conductive film).

[0156] Figure 34 is a top view of the word line WUX(j, k+1) extending in the X direction, connected to the upper selection gate SGU(i, j, k+1). That is, it is a drawing cut horizontally from the XY plane by the layer of SGU(i, j, k+1). The word line width is even considering manufacturing variations. Channel section to make vertical The word line width must always be larger than the hole (CV). Therefore, a sufficient margin is required in the difference between the word line width and the size of the CV. The contents of the CV are the same as in Figure 33, so the explanation is omitted. However, even though the coaxial structure is the same, since it is used as a selection gate, the writing state to the charge storage layer only needs to be adjusted so that a constant output current (saturation current) flows when Vpass is applied to the word line. As an example, it is desirable that Vt always remain within the range of Vread in Figure 12.

[0157] Figure 35 is a top view of the word line WDY(i, k+1) extending in the Y direction, connected to the lower selection gate SGD(i, j, k+1). That is, it is a drawing cut horizontally from the XY plane by the layer of SGD(i, j, k+1). The word line width must always be larger than the hole (CV) for creating the word line, even taking manufacturing variations into account. Therefore, a sufficient margin is required in the difference between the word line width and the size of the CV. The contents of the CV are the same as in Figure 33, so the explanation is omitted. However, even though the coaxial structure is the same, since it is used as a selection gate, the writing state to the charge storage layer only needs to be adjusted so that a constant output current (saturation current) flows when Vpass is applied to the word line. As an example, it is desirable that Vt always remain within the range of Vread in Figure 12.

[0158] Figure 36 is a top view of the word line WCX(j, k) extending in the X direction, connected to the cell gate CG(i, j, k). That is, it is a drawing cut horizontally from the XY plane by the layer of CG(i, j, k). The word line width is even considering manufacturing variations. Channel section to make vertical It must always be larger than the CV (concentric circle). Therefore, a sufficient margin is required between the word line width and the size of the CV. The contents of the CV are the same as in Figure 33, so the explanation is omitted.

[0159] Figure 37 is a top view of the word line WUY(i, k) extending in the Y direction, connected to the upper selection gate SGU(i, j, k). That is, it is a drawing cut horizontally from the XY plane by the layer of SGU(i, j, k). The word line width must always be larger than the hole (CV) for creating the word line, even taking manufacturing variations into account. Therefore, a sufficient margin is required in the difference between the word line width and the size of the CV. The contents of the CV are the same as in Figure 33, so the explanation is omitted. However, even though the coaxial structure is the same, since it is used as a selection gate, the writing state to the charge storage layer only needs to be adjusted so that a constant output current (saturation current) flows when Vpass is applied to the word line, as indicated by Vt. As an example, it is desirable that Vt always remain within the range of Vread in Figure 12. The explanation for Figure 38 is almost the same as the explanation for Figure 35, so it will be omitted.

[0160] As described above, the cross-sectional view of one module in the Z-direction within the ZX-plane can be explained. Figure 39 is an example of a case where three modules in the Z-direction are arranged in the X-direction. Figure 10 is a diagram showing an example of an equivalent circuit corresponding to Figure 39.

[0161] Figure 40 shows the module in the Z direction at address YZ (i,j) as viewed from a cross-sectional view in the ZY plane. Figure 30 shows the same module as viewed from a cross-sectional view in the ZX plane. The explanation for Figures 30 through 38 is the same and will be omitted here.

[0162] Figure 41 shows three of the modules from Figure 40 arranged in the Y-axis direction. Figure 11 is a diagram showing an example of an equivalent circuit corresponding to Figure 41.

[0163] Figure 42 is a diagram showing an example of the internal structure of the core described in Figures 33 to 38. As mentioned above, the core is surrounded by a tunnel oxide film, a charge storage layer, a block film, and a control gate. However, it is also possible to replace the tunnel oxide film with another tunnel film.

[0164] The aforementioned core can, for example, be further divided from the center into a dielectric core and channel silicon. The dielectric core is made of a dielectric or insulating material, and the channel silicon is made of a material such as silicon, amorphous silicon, or polysilicon, and is the channel portion of the element through which current flows when the switch is turned on. When the channel silicon is polysilicon, this structure is used to reduce the average grain size of the channel silicon and suppress variations in the current flowing through the channel silicon. Furthermore, the core is shared by at least three elements connected in series in the Z-axis direction, and the channel silicon becomes a channel portion shared by the three elements connected in series in the Z-axis direction. Therefore, when current flows in the channel portion, it is when current flows across the three elements connected in series. (Sixth embodiment)

[0165] It is generally known that channel vias in three-dimensional (3D) NAND flash can be manufactured using the gate-last method (see Non-Patent Literature 4). However, as described above, the device structure of the present invention has a second-order periodicity in the Z direction. In order to manufacture the second-order periodicity in the Z direction that is characteristic of the present invention, a manufacturing method different from the general gate-last method is required.

[0166] First, before explaining the features of this application, let's begin with a general explanation of the gate-last method.

[0167] Figures 43 and 44 are diagrams that briefly explain a general gate last method.

[0168] First, as illustrated in (a) of the diagram, oxide and nitride films are stacked alternately along the Z-axis (vertical direction in the drawing). The horizontal axis of the drawing is the X-axis. Next, as illustrated in (b), vertical holes are made (etch holes) that penetrate the stacked oxide and nitride films, the side walls are covered with polysilicon (poly on wall), and then the oxide film is filled (fill oxide). Subsequently, slits are drilled in a different location from the vertical holes (etch slits). The slits extend along the Y-axis. The angle at which the X-axis and Y-axis intersect can be any angle other than 180 degrees (or zero degrees), but a 90-degree angle has the potential to maximize the density of vertical holes in the XY plane.

[0169] Next, a gas is injected through the slit to remove the nitride film, and after removing the nitride film, a tunnel oxide film is deposited. Subsequently, a charge trapping layer is formed, and then a high-dielectric film is applied, resulting in a cross-sectional view as shown in (e). However, to clarify the charge trapping layer, which is difficult to draw due to space limitations, the dashed line portion is shown in (f). In this way, a charge storage layer is formed sandwiched between the tunnel oxide film and the high-dielectric film.

[0170] Furthermore, as shown in (g), a metal gate is formed (metal gate fill). Then, as shown in (h), the metal gate and a portion of the high-dielectric film are etched off (Etch metal & high-K). In this way, the low-dielectric film is filled (fill low-K) as shown in (i).

[0171] The gate-last method is commonly used in the manufacturing of 3D NAND flash memory. In cross-sectional view (i), the poly-on-wall extending in the vertical direction (Z-axis direction) is the channel that serves as the charge pathway for the 3D NAND flash memory. This channel is like a cylindrical shell with the oxide film volumeted in (b) as its core, and is surrounded in order by a tunnel oxide film, a charge trap layer, a high-dielectric film, and a metal gate. Therefore, the metal gate is shell-shaped (donut-shaped), and one metal gate corresponds to one cell (or memory cell). In this cross-sectional view, four metal gates are integrated so as to share a vertically extended channel. That is, multiple gates integrated vertically are connected in series, which is a characteristic of 3D NAND. In this application, in particular, three cells are connected in series vertically to form a single unit. Of these, the top one is designated as the upper selection gate (SGU), the middle one as the cell gate (CG), and the bottom one as the lower selection gate (SGD). A further feature of this invention is that the upper side of each unit is connected to one of the BLX and BLY units, and the lower side is connected to the other unit.

[0172] However, as shown in Figure 9, in this invention, bit lines BLX extending in the X direction and bit lines BLY extending in the Y direction are alternately arranged. This feature is not found in conventional 3D NAND flash memory.

[0173] For example, in Figure 9, six gates are connected in series between two BLX gates (BLX(j, k-2) and BLX(j, k)). The gates, from bottom to top, are SGD(i, j, k-1), CG(i, j, k-1), SGU(i, j, k-1), SGD(i, j, k), CG(i, j, k), and SGU(i, j, k). SGU(i, j, k-1) and SGD(i, j, k) are connected to BLY(i, k-1).

[0174] The word line WDY(i, k-1) connected to the gate electrode (or metal gate) of SGD(i, j, k-1) extends in the Y-axis direction. The word line WCX(j, k-1) connected to the gate electrode (or metal gate) of CG(i, j, k-1) extends in the X-axis direction. The word line WUX(j, k-1) connected to the gate electrode (or metal gate) of SGU(i, j, k-1) extends in the X-axis direction.

[0175] The word line WDX(j, k) connected to the gate electrode (or metal gate) of SGD(i, j, k) extends in the X-axis direction. The word line WDX(j, k) connected to the gate electrode (or metal gate) of CG(i, j, k) extends in the X-axis direction. The word line WUY(i, k) connected to the gate electrode (or metal gate) of SGU(i, j, k) extends in the Y-axis direction.

[0176] In other words, in this application, the direction of the word lines periodically repeats as follows: one in the Y direction (WDY(i, k-1)), two in the X direction (WCX(j, k-1), WUX(j, k-1)), two in the X direction (WDX(j, k), WCX(j, k)) with BLY(i, k-1) in between, and one in the Y direction (WUY(j, k)).

[0177] In Figure 43(c), the slit is cut only in the Y-axis direction, so with the conventional gate last method, it is not possible to periodically create word lines in the X and Y directions as in the present invention.

[0178] The manufacturing method of this invention will be described in detail below with reference to the drawings.

[0179] Figure 45 shows the process of patterning metal bit lines on a substrate. The top row is a cross-sectional view in the ZY plane, and the bottom row is a cross-sectional view in the ZX plane.

[0180] First, a metal film (or simply metal) is deposited (depo metal), and then the metal film is patterned (patterning). In this diagram, as an example, the patterning of a bit line BLX extending in the X direction is used. By swapping the X and Y axes, the patterning of a bit line BLY extending in the Y direction will be explained.

[0181] After patterning, an oxide film is deposited (depo oxide). (ay) is a cross-section in the ZY plane, and (ax) is a cross-section in the ZX plane. A bit line BLX extending in the X direction has already been formed by patterning. Typically, the surface of the deposited oxide film is then flattened by a chemical physical process (CMP). However, the deposited oxide film is also thinned by abrasion. It is necessary to control the thickness of the deposited oxide film, taking into account the reduction in film thickness due to CMP, etc. (by) is a cross-section in the ZY plane, and (bx) is a cross-section in the ZX plane.

[0182] Figure 46 is a view from above (in the XY plane). (a) shows the case where the bit line extends in the X direction, which corresponds to the case explained in Figure 45. (b) shows the case where the bit line extends in the Y direction. Both patterns can be freely selected.

[0183] Figure 45 illustrates an example where a pattern is applied to a substrate (Sub) such as a silicon substrate, but the substrate surface does not necessarily have to be flat. If necessary, a metal film deposited on a substrate surface that has been appropriately patterned may be patterned. Alternatively, a metal film deposited on a polysilicon that has been appropriately patterned may be patterned. In any case, as explained in Figure 46, it is necessary to intentionally pattern the metal film in the X or Y direction. Furthermore, if necessary, as explained in Figures 45(by) and (bx), it is desirable to deposit an oxide film after metal patterning and planarize it by CMP or similar. Also, considering compatibility with silicon or polysilicon, it is desirable that the metal film be a silicide.

[0184] Figures 47 to 60 illustrate the manufacturing process for forming an example of the features of the present invention on a metal film patterned to stretch in the X direction.

[0185] Figure 47(a) is a cross-sectional view of a metal film covered with a deposited oxide film planarized by CMP, etc., on which nitride, oxide, nitride, and oxide films are layered. However, the metal film is patterned to be stretched in the X direction, as an example, and becomes a bit line BLX extending in the X direction. This corresponds to Figure 46(a). The metal film may also be silicide. The part where the nitride film later becomes the gate is common to the gate last method. That is, in this example, two cells are connected in series in the Z-axis direction (vertical direction). If the number of nitride film layers is one, only one cell is formed in the Z-axis direction. If the number of nitride film layers is three, three cells are connected in series in the Z-axis direction. In other words, the number of cells connected in series in the Z-axis direction can be determined by the number of nitride film layers to be laminated. Here, as an example, two cells are connected in series in the Z-axis direction.

[0186] (b) Next, a vertical hole is drilled (etch hole), N+ type polysilicon (N+poly) is deposited, and planarized using CMP or similar methods. (c) The N+ polysilicon is selectively etched and further planarized using CMP or similar methods. The thin film of N+ polysilicon remaining at the bottom of the vertical hole becomes the contact point with BLX.

[0187] Figure 48(d) The side walls of the vertical shaft are covered with polysilicon (poly on wall), and an oxide film is deposited to seal the vertical shaft. (e) Slits are cut in the Y-axis direction (Y-etch slits), and (f) etching gas is injected through the slits to selectively remove only the nitride film. Then a tunnel oxide film is deposited.

[0188] Figure 49(g) shows a charge trapping layer formed on the sidewall and then covered with a high-dielectric film (High-K). (g1) is a magnified view of the dotted line area. The charge trapping layer is sandwiched between the tunnel oxide film and the high-dielectric film.

[0189] Figure 50(h) The slit is covered with metal (metal gate fill) so that it will later become a metal gate. (i) The metal and a portion of the high-dielectric film are stripped off (Etch metal & high-K), a low-dielectric film is deposited on the slit (fill low-K), and then the surface is planarized by CMP or the like.

[0190] In Figure 51, an oxide film, a nitride film, and another oxide film are further layered on top of it (laminate). Since the nitride film that will later serve as the gate is only one layer, here, as an example, one cell is added in the vertical direction. (kx) is a cross-sectional view in the ZX plane, and (ky) is Z— Y This is a cross-sectional view in plan view.

[0191] Figure 52 begins with (ky) in Figure 51. In other words, we will continue the explanation by moving from this drawing to the ZY cross-section. (l) Etch holes in the oxide film initially laid in Figure 51. At this time, the position of the vertical holes in the XY plane should be aligned as closely as possible to the position of the vertical holes made in Figure 47. Then, deposit polysilicon. Furthermore, it is desirable to flatten the surface using CMP or similar methods.

[0192] (m) Partially remove the polysilicon, leaving only the side walls (remove poly), and (n) deposit an oxide film to fill the vertical holes. Furthermore, (o) cut slits in the X-axis direction (X-etch slits). Thus, one of the features of the manufacturing method of this invention is that the slits are cut while switching between the X-axis and Y-axis directions.

[0193] Figure 53(p) shows that gas is injected through a slit to selectively remove the nitride film. Subsequently, a tunnel oxide film is deposited to form a charge trapping layer, and then a high-dielectric film is applied (high-K fill). (p1) When the dotted line area is magnified, it can be seen that the charge trapping layer is sandwiched between the tunnel oxide film and the high-dielectric film.

[0194] Figure 54 starts from (p). (q) The slit is filled with metal (film) which will later become the metal gate (metal gate fill). (r) Some of the metal and high-dielectric film in the slit is stripped away, leaving only the part that will become the metal gate (etch metal & high-K). (sy) A low-dielectric film is deposited on the slit and the surface is planarized by CMP or similar.

[0195] In Figure 55, N+ polysilicon is patterned, which will later become the contact for the Y-direction bit line BLY. Specifically, the resist is patterned and N+ polysilicon is deposited to align with the vertical holes (align, resist patterning, N+ poly depo). After planarizing the surface with CMP, the resist is stripped off, an oxide film is deposited, the surface is planarized with CMP, and then the metal film that will later become the BLY is deposited. Further planarization of the surface with CMP is desirable. (tx) is a cross-sectional view in the ZX plane, and (ty) is a cross-sectional view in the ZY plane.

[0196] In Figure 56, a resist is then patterned on the deposited metal film, the metal is etched, a low-dielectric film is filled in the gaps (metal patterning, or subtractive method), and then an oxide film is deposited and the surface is planarized by CMP or the like. (ux) is a cross-sectional view in the ZX plane, and (uy) is a cross-sectional view in the ZY plane. However, the metal patterning can be replaced with a damascene process or the like.

[0197] In any case, the Y-direction bit line BLY is formed in this way. In this example, three gates are connected in series from the bottom between BLX and BLY, forming a single unit consisting of one cell sandwiched between two selection gates. Both ends of the vertically extending channel are in contact with N+ polysilicon. BLX is below the lower N+ polysilicon, and BLY is above the upper N+ polysilicon. The three layers of gate metal each become a word line. The two lower word lines extend in the Y direction, and the upper word line extends in the X direction.

[0198] In Figure 57, further layers of nitride film, oxide film, nitride film, and oxide film are laminated on top of it. Here, since there are 2 nitride film layers, the number of cells that can be stacked on top of it is 2. (vx) is a cross-sectional view in the ZX plane, and (vy) is a cross-sectional view in the ZY plane.

[0199] In Figure 58, vertical holes are drilled (etch holes) in the oxide-nitride film layers, which are stacked in layers aligned with the BLY substrate contact (N+ polysilicon). Subsequently, N+ polysilicon is deposited (N+ poly depo), and the surface is planarized using CMP or similar methods. (wx) is a cross-sectional view in the ZX plane, and (wy) is a cross-sectional view in the ZY plane.

[0200] In Figure 59, the N+ polysilicon in the vertical hole is appropriately etched (etch N+poly), and the N+ polysilicon remaining at the bottom of the vertical hole is used as the upper contact to the BLY. The side walls are covered with polysilicon (poly on wall), the interior is filled with an oxide film (fill oxide), and the surface is further planarized using CMP or similar methods. (w2x) is a cross-sectional view in the ZX plane, and (w2y) is a cross-sectional view in the ZY plane.

[0201] Figure 60 is a cross-sectional view of the case where (b) is selected in Figure 46. Since the bit line BLY is formed in the Y direction at the bottom, the upper bit line is BLX in the X direction. In other words, BLX and BLY have been swapped (replace BLX&BLY). The rest of the manufacturing process is exactly the same as in Figure 59. That is, the only difference is that the direction in the bit line patterning has been changed. 46 This is a cross-sectional view of a device structure produced through the exact same manufacturing process as shown in Figure 59. Therefore, a detailed explanation would be redundant and will be omitted. (zx) is a cross-sectional view in the ZX plane, and (zy) is a cross-sectional view in the ZY plane.

[0202] Figure 61 is the same as Figure 59 but with X and Y swapped. Swapping the X and Y directions is a coordinate transformation between a right-handed and left-handed system, and does not change the structure of the manufactured device. (w3x) is a cross-sectional view in the ZX plane, and (w3y) is a cross-sectional view in the ZY plane. After this, a slit is made in the X-axis direction to form a word line in the X direction. The process from there onward is the same as in Figure 48(e) and later, so the explanation is omitted. Rather, the purpose of Figure 61 is to clarify that the structure sandwiched between BLX and BLY corresponds to one unit in Figure 9.

[0203] Figure 62 compares (w3x) in Figure 61 with a portion of the module (one unit) in Figure 9. It can be seen that BLX in Figure 61 corresponds to BLX(j, k+1) in Figure 9, and BLY in Figure 61 corresponds to BLY(i, k) in Figure 9.

[0204] Figure 63 shows a modified combination of nitride film layers in Figure 59. Specifically, by changing the number of nitride film layers stacked in Figure 47 from 2 to 1, and changing the number of nitride film layers stacked in Figure 51 from 1 to 2, the device structure obtained by following the same manufacturing process as in Figures 47 to 59 is shown in the cross-sectional view. (w4x) is a cross-sectional view in the ZX plane, and (w4y) is a cross-sectional view in the ZY plane.

[0205] Figure 64 compares (w4x) in Figure 63 with a portion of the module (one unit) in Figure 9. The BLX in Figure 64 is exactly the same as the one in Figure 9. BLX(j, k-2) It can be seen that the BLY in Figure 64 corresponds to the BLY(i, k) in Figure 9.

[0206] Thus, according to this embodiment, it is possible to manufacture a device structure having a second-order periodicity in the Z-axis direction, which is characteristic of the present invention. However, second-order periodicity means that the same structure can be obtained by shifting the value of Z address (k) by 2 in both the cross-sectional view in the ZX plane and the cross-sectional view in the ZY plane. (Seventh Embodiment)

[0207] In 3D integrated circuits, the number of word lines and bit lines generally tends to increase with the number of layers in the Z-axis direction (vertical direction), and the number of contacts to peripheral circuits also tends to be larger than in 2D integrated circuits. Therefore, ingenuity is required in how contacts are arranged to save chip area. Naturally, the characteristics of the core device structure influence how contacts are arranged.

[0208] This invention features a second-order periodicity in address Z(k). The diagrams illustrate in detail how this affects the way contacts are made with the surrounding circuitry.

[0209] Figure 65 is a diagram illustrating how the word line group (WUX and WCX group) and the bit line group (BLX group) extending in the X-axis direction make contact. However, it only illustrates modules located at the end of the X-axis direction (i=Lx) with Z addresses from k+1 to k-2.

[0210] Generally, the size of the contact portion (MC0 and MC1) is larger than the diameter of the metal via portion drilled in the Z-axis direction. Therefore, it is desirable that adjacent contact portions be arranged alternately, with wiring metal layer 0 (M0 layer) (or simply metal layer 0) and wiring metal layer 1 (M1 layer) (or simply metal layer 1). However, the contacts in the M0 layer are MC0, and the contacts in the M1 layer are MC1.

[0211] However, in this application, due to the second-order periodicity of address Z(k), not all word lines and bit lines extend in the X direction. In the example in Figure 65, WDY(Lx, k+1), WUY(Lx, k), and WDY(Lx, k-1) are These are word lines extending in the Y direction. BLY(Lx, k+1) and BLY(Lx, k-1) are bit lines extending in the Y direction.

[0212] In Figure 65, the contact for WUX(j, k+1) is MC0, the contact for WCX(j, k+1) is MC1, the contact for BLX(j, k) is MC0, the contact for WCX(j, k) is MC1, the contact for WDX(j, k) is MC0, the contact for WUX(j, k-1) is MC1, the contact for WCX(j, k-1) is MC0, and the contact for BLX(j, k-2) is MC1.

[0213] Figure 66 is a module that follows below Figure 65, with Z addresses ranging from k-1 to k-4. The contacts for WUX(j, k-1) are MC1, WCX(j, k-1) are MC0, BLX(j, k-2) are MC1, WCX(j, k-2) are MC0, WDX(j, k-2) are MC1, WUX(j, k-3) are MC0, WCX(j, k-3) are MC1, and BLX(j, k-4) are MC0.

[0214] Figure 67 is a module that follows Figure 66, with Z addresses ranging from k-3 to k-6. The contact for WUX(j, k-3) is MC0, the contact for WCX(j, k-3) is MC1, the contact for BLX(j, k-4) is MC0, the contact for WCX(j, k-4) is MC1, the contact for WDX(j, k-4) is MC0, the contact for WUX(j, k-5) is MC1, the contact for WCX(j, k-5) is MC0, and the contact for BLX(j, k-6) is MC1.

[0215] Figure 68 is a module that follows below Figure 67, with Z addresses ranging from k-5 to k-8. The contacts for WUX(j, k-5) are MC1, WCX(j, k-5) are MC0, BLX(j, k-6) are MC1, WCX(j, k-6) are MC0, WDX(j, k-6) are MC1, WUX(j, k-7) are MC0, WCX(j, k-7) are MC1, and BLX(j, k-8) are MC0.

[0216] Figure 69 summarizes which word line or bit line each contact is connected to, divided into M1 and M0 layers.

[0217] According to FIG. 69, for address Y(j), in order to save the area occupied by the contacts to the peripheral circuits, a fourth-order periodicity in the Z-axis direction (period of M1) appears in the set of WUX(j,k+3), BLX(j, k+2), WDX(j, k+2), WCX(j, k+1), WCX(j,k) arranged in the X-axis direction on the M1 layer. That is, when the Z address (k) is shifted by 4, the same pattern appears. As is clear from FIGS. 65 to 68, as the X address advances, the word lines and bit lines to which the contacts are connected also become deeper, and the number of Z addresses increases. That is, this contact pattern in the X-axis direction is related to the structure in the Z-axis direction.

[0218] Similarly, on the M0 layer, arranged in the X-axis direction WUX (j, k+1), BLX (j, k), WDX (j, k), WCX (j, k-1), WCX (j, k-2) a fourth-order periodicity in the Z-axis direction (period of M0) appears in the set. That is, when the Z address (k) is shifted by 4, the same pattern appears. This contact pattern in the X-axis direction is related to the structure in the Z-axis direction. In particular, the appearance of the fourth-order periodicity is because, as will be described later, the contacts are laid out by being divided in the X-axis direction and the Y-axis direction.

[0219] Let's consider shifting the Y address one by one from j to j+1. Also in this case, it is necessary to alternately allocate the contacts adjacent in the Y-axis direction to the M0 layer and the M1 layer. Therefore, for address Y(j+1), on the M0 layer, arranged in the X-axis direction WUX(j+1, k+3), BLX (j+1, k+2), WDX (j+1, k+2), WCX (j+1, k+1), WCX (j+1, k) [[ID=十九]] a fourth-order periodicity in the Z-axis normal direction (period of M0) occurs in the set. Also, on the M1 layer, arranged in the X-axis direction WUX(j + 1, k + 1), BLX(j + 1, k), WDX(j + 1, k), WCX(j + 1, k - 1), WCX(j + 1, k - 2) A fourth-order periodicity (period of M1) in the Z-axis direction appears in the set of

[0220] Figure 70 is a drawing showing an example in which MC0 and MC1 are laid out on the X-Y plane so as to satisfy the above-described fourth-order periodicity in the Z-axis direction.

[0221] Figure 71 is a drawing for explaining how contacts are made between a group of word lines (groups of WDY and WUY) extending in the Y-axis direction and a group of bit lines (group of BLY). However, it shows modules located at the end in the Y-axis direction (i = Ly) and having Z addresses from k + 1 to k - 2.

[0222] As described above, in the present application, there is a second-order periodicity in the Z address, but not all word lines and bit lines extend in the Y direction. In the example of Figure 71, WUX(Ly, k + 1) and WCX(Ly, k + 1), WCX(Ly, k), WDX(Ly, k), WUX(Ly, k - 1), WCX(Ly, k - 1) are word lines extending in the X direction. BLX(Ly, k) and BLX(Ly, k - 2) are bit lines extending in the X direction. However, this cell is located at the Y-direction end (Ly). WDY(i, k+1), WUY(i,k), and WDY(i, k-1) are word lines extending in the Y-direction. BLY(i, k+1) and BLY(i, k-1) are bit lines extending in the Y-direction.

[0223] In Figure 71, the contact of BLY(i, k + 1) is MC0, the contact of WDY(i, k + 1) is MC1, the contact of WUY(i, k) is MC0, the contact of BLY(i, k - 1) is MC1, and the contact of WDY(i, k - 1) is MC0.

[0224] Figure 72 is a module that follows Figure 71, with Z addresses ranging from k-1 to k-4. The contact for BLY(i, k-1) is MC1, the contact for WDY(i, k-1) is MC0, the contact for WUY(i, k-2) is MC1, the contact for BLY(i, k-3) is MC0, and the contact for WDY(i, k-3) is MC1.

[0225] Figure 73 is a module that follows Figure 72, with Z addresses ranging from k-3 to k-6. The contact for BLY(i, k-3) is MC0, the contact for WDY(i, k-3) is MC1, the contact for WUY(i, k-4) is MC0, the contact for BLY(i, k-5) is MC1, and the contact for WDY(i, k-5) is MC0.

[0226] Figure 74 is a module that follows Figure 73, with Z addresses ranging from k-5 to k-8. The contact for BLY(i, k-5) is MC1, the contact for WDY(i, k-5) is MC0, the contact for WUY(i, k-6) is MC1, the contact for BLY(i, k-6) is MC0, and the contact for WDY(i, k-7) is MC1.

[0227] Figure 75 summarizes which word line or bit line each contact is connected to, divided into M1 and M0 layers.

[0228] According to Figure 75, in order to save the area occupied by contacts to the surrounding circuit for address X(i), the M1 layer is arranged in the Y-axis direction. BLY(i, k-1), WUY (i, k-2), WDY (i, k-3) The set in the Z-axis direction 3 Periodicity of M1 appears. That is, address Z (k) 3Shifting the coordinates reveals the same pattern. As is clear from Figures 71 to 74, as we move in the Y-direction, the word lines and bit lines to which the contacts connect also become deeper, and the number of Z-addresses increases. In other words, this contact pattern in the Y-axis direction is related to the structure in the Z-axis direction.

[0229] Similarly, the M0 layer is aligned along the X-axis. BLY (i, k+1), WUY (i, k), WDY (i, k-1) The set in the Z-axis direction 3 Periodicity of M0 appears. That is, address Z (k) 3 Shifting it reveals the same pattern. This contact pattern in the Y-axis direction is related to the structure in the Z-axis direction. In particular, 3 The reason this periodicity appears, as will be explained later, is because the contacts are laid out by dividing them along the X-axis and Y-axis directions.

[0230] Let's consider shifting address X one position at a time from i to i+1. In this case, adjacent contacts along the X-axis must be alternately distributed between layers M0 and M1. Therefore, for address X (i+1), the contacts aligned along the Y-axis on layer M0 must be... BLY(i+1, k-1), WUY (i+1, k-2), WDY (i+1, k-3) A 4th-order periodicity (period of M0) occurs in the Z-axis direction in the set. Also, in the set aligned in the Y-axis direction on the M1 layer, the Z-axis direction 3 Periodicity of M1 appears.

[0231] Figure 76 is the same as described above. 3 This diagram shows an example of MC0 and MC1 being laid out on the XY plane to satisfy the hierarchical periodicity property.

[0232] Figures 77 to 80 are diagrams showing an example of a layout of bit lines, bit line contacts, word lines, and word line contacts on the XY plane.

[0233] As shown in FIGS. 65 and 71, BLX(*, k) is sandwiched vertically between WDY(*, k+1) and WUY(*, k). FIG. 77 is a drawing showing an example of laying out BLX(*, k), WDY(*, k+1), contact MC0, and contact MC1 in the X-Y plane. On the Z-axis, WDY(*, k+1) is above BLX(*, k). Also, for example, the contact of BLX(j, k) is on the M0 layer, the contact of BLX(j+1, k) is on the M1 layer, the contact of WDY(i-1, k+1) is on the M0 layer, and the contact of WDY(i, k+1) is on the M1 layer.

[0234] FIG. 78 is a drawing showing an example of laying out BLX(*, k), WUY(*, k), contact MC0, and contact MC1 in the X-Y plane. On the Z-axis, WUY(*, k) is below BLX(*, k). Also, for example, the contact of WUY(i-1, k) is on the M1 layer, and the contact of WUY(i, k) is on the M0 layer.

[0235] As shown in FIGS. 65 and 71, BLY(*, k-1) is sandwiched vertically between WDX(*, k) and WUX(*, k-1) FIG. 79 is a drawing showing an example of laying out BLY(*, k-1), WDX(*, k), contact MC0, and contact MC1 in the X-Y plane. On the Z-axis, WDX(*, k) is above BLY(*, k-1). Also, for example, the contact of BLY(i, k-1) is on the M1 layer, the contact of BLY(i+1, k-1) is on the M0 layer, the contact of WDX(j, k) is on the M0 layer, and the contact of WDX(j+1, k) is on the M1 layer.

[0236] Figure 80 is a diagram showing an example of laying out BLY(*, k-1), WUX(*, k-1), contact MC0, and contact MC1 on the XY plane. WUX(*, k-1) is below BLY(*, k-1) on the Z axis. Also, for example, the contact of WUX(j, k-1) is on the M1 layer, and the contact of WUX(j+1, k-1) is on the M0 layer.

[0237] [Non-Patent Document 1] Goodon E. Moore, “Cramming more components onto integrated circuits”, Electronics, volume 38, Number 8, April 19, 1965. [Non-Patent Document 2] Masanet, E.; Shhehabi, A.; Lei, N.; Smith, S.; Koomey, J. Recalibrating global data center energy-use estimates. Science 2020, vol. 3667, 984―986. [Non-Patent Document 3] CC Lu et al., "Analysis and Realization of TLC or even QLC Operation with a High-Performance Multi-Times Verify Scheme in 3D NAND Flash memory," 2018 IEEE International Electron Devices Meeting (IEDM), 2018, pp. 2.2.1―2.2.4, doi: 10.1109 / IEDM.2018.8614548. [Non-Patent Document 4] J.-H. Jang et al., “Vertical Cell Array using TCAT (Terabit Cell Array Transistor) Technology for Ultra High-Density NAND Flash Memory”, the 2009 Symmposium on VLSI Technology, Digest of Technical Papers, pp. 192–193, 2009. (Eighth Embodiment)

[0238] The width of the bit and word lines may be wide enough to accommodate multiple channel vias. This is related to the manufacturing reliability of channel vias. As the depth (length) of a channel via increases, it is more likely to collapse during manufacturing. To prevent this, methods of reinforcing with bit and word lines are sometimes used. This will be explained in detail using Figures 81 to 96.

[0239] Figure 81 is a diagram corresponding to Figure 31 and is an example of the width of the Y-direction bit line. The difference from Figure 31 is that two rows of channel vias are arranged within the width of the Y-direction bit line, and the two channel vias are bundled together into a single bit line contact. In contrast, in Figure 31, only one row of channel vias is arranged within the width of the Y-direction bit line. This prevents the channel vias from easily tilting in the X direction. Looking at the cross section cut at A-A' (right figure), it can be seen that the channel vias are located towards the left end of the Y-direction bit line.

[0240] Figure 82 is a diagram corresponding to Figure 31 and is another example regarding the width of the bit line in the Y direction. It is characterized by the fact that three channel vias are bundled together into a single bit line contact.

[0241] Figure 83 is a diagram corresponding to Figure 31 and is another example regarding the width of the bit line in the Y direction. It is characterized by the fact that four channel vias are bundled together into a single bit line contact.

[0242] Figure 84 is a diagram corresponding to Figure 31 and is another example regarding the width of the Y-direction bit line. It is characterized by having three rows of channel vias within the width of the Y-direction bit line and by bundling five channel vias together into a single bit line contact.

[0243] Figure 85 is a diagram corresponding to Figure 32 and is an example of the width of the X-direction bit line. The difference from Figure 32 is that there are two rows of channel vias within the width of the X-direction bit line, and the two channel vias are bundled together into a single bit line contact. In contrast, in Figure 32, there is only one row of channel vias within the width of the X-direction bit line. This prevents the channel vias from easily tilting in the Y direction. Looking at the cross section cut along B-B' (right figure), it can be seen that the channel vias are positioned towards the left end of the Y-direction bit line.

[0244] Figure 86 is a diagram corresponding to Figure 32 and is another example regarding the width of the bit line in the X direction. It is characterized by the bundling of three channel vias into a single bit line contact.

[0245] Figure 87 is a diagram corresponding to Figure 32 and is another example regarding the width of the bit line in the X direction. It is characterized by the fact that four channel vias are bundled together into a single bit line contact.

[0246] Figure 88 is a diagram corresponding to Figure 32 and is another example regarding the width of the X-direction bit line. It is characterized by having three rows of channel vias within the width of the X-direction bit line and by bundling five channel vias together into a single bit line contact.

[0247] Figure 89 is a diagram corresponding to Figures 33, 34, 36, and 38, and is an example of the width of the X-direction word line. The difference from Figures 33, 34, 36, and 38 is that the X-direction word line is arranged in two rows of channel vias, and the two channel vias are bundled together into a single cell gate or selection gate (CG, SGU, SGD). In contrast to Figures 33, 34, 36, and 38, Within the width of the word line in the X direction Only a single row of channel vias is present. This prevents the channel vias from easily tilting in the Y direction.

[0248] Figure 90 is a diagram corresponding to Figures 33, 34, 36, and 38, and is another example regarding the width of the X-direction word line. It is characterized by the fact that the channel vias are arranged in two rows within the width of the X-direction word line, and that the three channel vias are bundled together into a single cell gate or selection gate (CG, SGU, SGD).

[0249] Figure 91 is a diagram corresponding to Figures 33, 34, 36, and 38, and is another example regarding the width of the X-direction word line. It is characterized by the fact that the channel vias are arranged in two rows within the width of the X-direction word line, and that the four channel vias are bundled together into a single cell gate or selection gate (CG, SGU, SGD).

[0250] Figure 92 is a diagram corresponding to Figures 33, 34, 36, and 38, and is another example regarding the width of the X-direction word line. It is characterized by the fact that three rows of channel vias are arranged within the width of the X-direction word line, and that five channel vias are bundled together into a single cell gate or selection gate (CG, SGU, SGD).

[0251] Figure 93 is a diagram corresponding to Figures 35 and 37, and is an example of the width of the Y-direction word line. The difference from Figures 35 and 37 is that there are two rows of channel vias within the width of the Y-direction word line, and the two channel vias are bundled together into a single selection gate (SGD, SGU). In contrast, in Figures 35 and 37, there is only one row of channel vias within the width of the Y-direction bit line. This prevents the channel vias from easily tilting in the X direction.

[0252] Figure 94 is a diagram corresponding to Figures 35 and 37, and is another example relating to the width of the word line in the Y direction. It is characterized by the bundling of three channel vias into a single selection gate (SGD, SGU).

[0253] Figure 95 is a diagram corresponding to Figures 35 and 37, and is another example relating to the width of the word line in the Y direction. 4 channel vias A distinctive feature is that these are bundled together and combined into a single selection gate (SGD, SGU).

[0254] Figure 96 is a diagram corresponding to Figures 35 and 37, and is another example regarding the width of the Y-direction word line. It is characterized by the fact that three rows of channel vias are arranged within the width of the Y-direction word line, and that five channel vias are bundled together into a single selection gate (SGD, SGU).

[0255] Therefore, it is desirable to combine multiple channel vias into a single bit line contact, cell gate, or selection gate. In this case, the number of channel vias that can be combined is not limited to 2-5. The arrangement of channel vias that can be combined is not limited to those shown in Figures 81-96.

[0256] When the number of channel vias that can be combined into one is two or more, the number of columns of channel vias arranged in the direction of the word line or bit line will be at least two. Therefore, it is desirable that the width of the word line or bit line be at least twice the diameter of the channel via. The reason can be easily explained using Figure 97. The ends of the word line or bit line are represented by straight lines (0) and (1). In other words, the width of the word line or bit line is the distance between straight lines (0) and (1). We believe that the width in the dashed line (A)-(D) direction is saved the most when half of the two columns of channel vias (CV) overlap in the lateral direction. In this case, the width in the (A)-(D) direction is about three times the radius of the channel via. If a margin of about the radius of the channel via is taken outside (A) and outside (B), the distance between straight lines (0) and (1) will be about twice the diameter of the channel via.

[0257] The features of this application have been explained above.

[0258] Finally, the technical scope of the present invention is not limited to the embodiments described above, and various modifications can be made without departing from the spirit of the invention. [Industrial applicability]

[0259] Silicon technology makes it possible to provide a method for realizing the information processing mechanisms of the human brain using semiconductor chips. [Brief explanation of the drawing]

[0260] [Figure 1] A diagram illustrating an example of a nerve cell. [Figure 2] A diagram illustrating an example of synapsis. [Figure 3] An example diagram illustrating the concept of a perceptron. [Figure 4] A diagram illustrating one example of a method for counting the number of possible links between two points. [Figure 5]This graph plots the ratio of network information volume to bit-based information volume (number of bits) against the number of nodes (N). [Figure 6] This diagram illustrates that even if the starting and ending points are the same, different paths (routes) can result in different inputs to the ending point. [Figure 7] This figure plots the ratio of the amount of information in a 3D network to the amount of information in a 2D network against the size of one side of a cell array. [Figure 8] A diagram explaining the definitions of addresses X, Y, and Z. [Figure 9] A diagram illustrating an example of one module in the Z direction. [Figure 10] A diagram illustrating an example where one module in the Z direction expands in the X direction. [Figure 11] A diagram illustrating an example where one module in the Z direction expands in the Y direction. [Figure 12] A schematic diagram illustrating the transistor characteristics (electrical characteristics) of a cell gate. [Figure 13] A schematic diagram illustrating the transistor characteristics (electrical characteristics) of the word line and bit line selection gate. [Figure 14] A diagram illustrating an example of how to link two adjacent cell gates in the Z direction. [Figure 15] A diagram illustrating an example of how to apply voltage to link two adjacent cell gates in the Z direction. [Figure 16] A diagram illustrating an example of how to link two adjacent cell gates in the Z direction. [Figure 17] A diagram illustrating an example of how to apply voltage to link two adjacent cell gates in the Z direction. [Figure 18] A diagram illustrating an example of how to link two adjacent cell gates in the X direction. [Figure 19] A diagram illustrating an example of how to apply voltage to link two adjacent cell gates in the X direction. [Figure 20] A diagram illustrating an example of how to link two adjacent cell gates in the Y direction. [Figure 21]A diagram illustrating an example of how to apply voltage to link two adjacent cell gates in the Y direction. [Figure 22] A diagram illustrating an example of an embodiment in which the Y-direction bit line BLY(i, k-1) is used as the cell body. [Figure 23] A diagram illustrating an example of an embodiment in which the Y-direction bit line BLY(i, k-1) is used as the cell body. [Figure 24] A diagram illustrating an example of an embodiment in which the X-direction bit line BLX(j, k) is the cell body. [Figure 25] A drawing illustrating an example of an embodiment that forms a link. [Figure 26] A diagram illustrating an example of an embodiment in which the Y-direction bit line BLY(i, k-1) is used as the cell body. [Figure 27] A diagram illustrating an example of an embodiment in which the X-direction bit line BLX(j, k) is the cell body. [Figure 28] A diagram illustrating an example of an embodiment for recording information based on the route. [Figure 29] A diagram illustrating an example of an embodiment for recording information based on the route. [Figure 30] A diagram illustrating that one module in the Z direction is composed of three units. [Figure 31] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLY(i, k+1) or BLY(i, k-1). [Figure 32] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLX(j, k) or BLX(j, k-2). [Figure 33] This diagram illustrates an example of a top-down view (XY plan view) of a cross-section in a layer where CG(i, j, k+1) exists. [Figure 34] This diagram illustrates an example of a cross-section (XY plan view) of a layer containing SGU(i, j, k+1) as seen from above. [Figure 35] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing SGD(i, j, k+1). [Figure 36] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer where CG(i, j, k) exists. [Figure 37] This diagram illustrates an example of a cross-section (XY plan view) of a layer containing SGU(i, j, k) as seen from above. [Figure 38] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer where SGD(i, j, k) exists. [Figure 39] A diagram illustrating an example of a cross-section with three modules arranged in the X direction. [Figure 40] A diagram illustrating an example of a cross-section obtained by unfolding one module in the Y direction. [Figure 41] A diagram illustrating an example of a cross-section with three modules arranged in the Y direction. [Figure 42] A diagram illustrating an example of the internal structure of a core. [Figure 43] A diagram illustrating a general gate last method. [Figure 44] A diagram illustrating a general gate last method. [Figure 45] A diagram illustrating an example of metal patterning that forms a bit line. [Figure 46] This diagram illustrates the top view (XY plane) of the metal after patterning to form the bit lines. (a) shows the case where the patterning extends in the X direction. (b) shows the case where the patterning extends in the Y direction. [Figure 47] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 48] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 49] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 50]A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 51] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 52] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 53] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 54] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 55] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 56] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 57] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 58] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 59] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 60] A drawing illustrating an example of a manufacturing process for forming a unit having the features of the present invention on a metal film patterned to stretch in the X direction. [Figure 61]This diagram illustrates the case where X and Y are swapped in Figure 59. [Figure 62] A diagram for comparing (w3x) in Figure 61 with a portion of the module (one unit) in Figure 9. [Figure 63] Figure 59 is a diagram illustrating an example of a unit manufactured by changing the combination of the number of nitride film layers. [Figure 64] A diagram for comparing (w4x) in Figure 63 with a portion of the module (one unit) in Figure 9. [Figure 65] This diagram illustrates an example of how to establish contact between a group of word lines (WUX and WCX) and a group of bit lines (BLX) extending in the X-axis direction. [Figure 66] This diagram illustrates an example of how to establish contact between a group of word lines (WUX and WCX) and a group of bit lines (BLX) extending in the X-axis direction. [Figure 67] This diagram illustrates an example of how to establish contact between a group of word lines (WUX and WCX) and a group of bit lines (BLX) extending in the X-axis direction. [Figure 68] This diagram illustrates an example of how to establish contact between a group of word lines (WUX and WCX) and a group of bit lines (BLX) extending in the X-axis direction. [Figure 69] A diagram illustrating which word line or bit line each contact is connected to, divided into M1 and M0 layers. [Figure 70] This diagram illustrates an example of a method for arranging MC0 and MC1 on the XY plane to satisfy the characteristic periodicity in the Z-axis direction of the present invention. [Figure 71] This diagram illustrates an example of how to establish contact between a group of word lines (WDY and WUY) and a group of bit lines (BLY) extending in the Y-axis direction. [Figure 72] This diagram illustrates an example of how to establish contact between a group of word lines (WDY and WUY) and a group of bit lines (BLY) extending in the Y-axis direction. [Figure 73] This diagram illustrates an example of how to establish contact between a group of word lines (WDY and WUY) and a group of bit lines (BLY) extending in the Y-axis direction. [Figure 74] This diagram illustrates an example of how to establish contact between a group of word lines (WDY and WUY) and a group of bit lines (BLY) extending in the Y-axis direction. [Figure 75] A diagram illustrating which word line or bit line each contact is connected to, divided into M1 and M0 layers. [Figure 76] This diagram illustrates an example of a method for arranging MC0 and MC1 on the XY plane to satisfy the characteristic periodicity in the Z-axis direction of the present invention. [Figure 77] A diagram illustrating an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on the XY plane. [Figure 78] A diagram illustrating an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on the XY plane. [Figure 79] A diagram illustrating an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on the XY plane. [Figure 80] A diagram illustrating an example of a layout method for bit lines, bit line contacts, word lines, and word line contacts on the XY plane. [Figure 81] This diagram illustrates an example of a cross-section (XY plan view) of a layer where BLY(i, k±1) exists, viewed from above. [Figure 82] This diagram illustrates an example of a cross-section (XY plan view) of a layer where BLY(i, k±1) exists, viewed from above. [Figure 83] This diagram illustrates an example of a cross-section (XY plan view) of a layer where BLY(i, k±1) exists, viewed from above. [Figure 84] This diagram illustrates an example of a cross-section (XY plan view) of a layer where BLY(i, k±1) exists, viewed from above. [Figure 85] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLX(j, k) or BLX(j, k-2). [Figure 86]This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLX(j, k) or BLX(j, k-2). [Figure 87] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLX(j, k) or BLX(j, k-2). [Figure 88] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing BLX(j, k) or BLX(j, k-2). [Figure 89] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k). [Figure 90] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k). [Figure 91] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k). [Figure 92] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing CG(i, j, k+1), SGU(i, j, k+1), or SGD(i, j, k). [Figure 93] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing SGD(i, j, k+1), SGU(i, j, k+1), or SGU(i, j, k). [Figure 94] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing SGD(i, j, k+1), SGU(i, j, k+1), or SGU(i, j, k). [Figure 95] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing SGD(i, j, k+1), SGU(i, j, k+1), or SGU(i, j, k). [Figure 96] This diagram illustrates an example of a top-view cross-section (XY plan view) of a layer containing SGD(i, j, k+1), SGU(i, j, k+1), or SGU(i, j, k). [Figure 97] A diagram showing an example of the relationship between the diameter of a channel via and the width of a word line or bit line. [Explanation of symbols]

[0261] BLX X-direction bit line BLY Y-direction bit line BSGX X-direction bitline bitline selection gate BSGY Y-direction bitline bitline selection gate SGU Upper Selection Gate CG Cellgate SGD Lower Selection Gate WUX upper selection gate X direction word line WCX cell gate X-direction word line WDX lower selection gate X direction word line WUY upper selection gate Y direction word line WCY cell gate Y-direction word line WDY lower selection gate Y direction word line WSGUX upper selection gate X direction word line WSGCX cell gate X-direction word line WSGDX Lower Select Gate X Direction Word Line WSGUY upper selection gate Y direction word line WSGDY Lower Selected Gate Y Direction Word Line BL bit line WL Word Line CV channel via, or vertical hole drilled to create a channel section. Core channel via center Tunnel oxide film Charge storage / charge storage layer Control gate / Control gate Block film / Block membrane Dielectric core Channel silicon Sub / Circuit Board Polysilicon Metal Silicide Oxide / Oxide film Nitride film N+poly / N+ type polysilicon High-K / High dielectric MC0 / M0 layer metal contact MC1 / M1 layer metal contact

Claims

1. A first unit and a second unit are connected in series in the first axial direction. The second, third, fourth, and fifth word lines extend in the second axial direction, The first and sixth word lines extend in the third axial direction, The first and third bit lines extend in the second axial direction, A second bit line extending in the third axis direction, It is a module consisting of, The second bit line is connected to both the first and second units, The first unit consists of a first, second, and third element, The first, second, and third elements are connected in series in the axial direction of the first element. The first, second, and third elements each have a control gate, The first element has a source, The third element has a drain, The control gate of the first element is connected to the first word line, The control gate of the second element is connected to the second word line, The control gate of the third element is connected to the third word line, The source of the first element is connected to the first bit line, The drain of the third element is connected to the second bit line, The second unit consists of a fourth, fifth, and sixth element, The fourth, fifth, and sixth elements are connected in series in the first axial direction. The fourth, fifth, and sixth elements each have a control gate, The fourth element has a source, The sixth element has a drain, The control gate of the fourth element is connected to the fourth word line, The control gate of the fifth element is connected to the fifth word line, The control gate of the sixth element is connected to the sixth word line, The source of the fourth element is connected to the second bit line, The drain of the sixth element is connected to the third bit line. A semiconductor device characterized by the following features.

2. Each of the first to sixth elements consists of a cylindrical channel via comprising a tunnel oxide film, a charge storage layer, a block film, and a conductive thin film. The first to third elements each have a first core, The fourth to sixth elements each have a second core, The first core consists of a cylindrical member extending in the first axial direction and constitutes the channel portion of the first to third elements. The second core consists of a cylindrical member extending in the axial direction of the first core, and constitutes the channel portion of the fourth to sixth elements. The tunnel oxide film encloses the first core for each of the first to third elements, and encloses the second core for each of the fourth to sixth elements. The charge storage layer encloses the tunnel oxide film for each of the first to sixth elements, The block film encloses the charge storage layer for each of the first to sixth elements, The conductive thin film encloses the block film for each of the first to sixth elements, The control gate of the first to sixth elements is the conductive thin film. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

3. The width of the first to sixth word lines is greater than the diameter of the cylindrical channel via. The width of the first to third bit lines is greater than the diameter of the cylindrical channel via. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

4. The seventh, eighth, and ninth elements, The seventh and eighth word lines extending in the second axial direction, The ninth word line extending in the third axial direction, It consists of a fourth bit line extending in the third axial direction, The seventh, eighth, and ninth elements are connected in series in the first axial direction. The seventh, eighth, and ninth elements each have a control gate, The seventh element has a source, The eighth element has a drain, The control gate of the seventh element is connected to the seventh word line, The control gate of the eighth element is connected to the eighth word line, The control gate of the ninth element is connected to the ninth word line, The source of the seventh element is connected to the fourth bit line, The drain of the ninth element is connected to the first bit line. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

5. The 10th, 11th, and 12th elements, The 11th and 12th word lines extending in the second axial direction, The third axial direction is extended by a tenth word line, It consists of a fifth bit line extending in the third axial direction, The tenth, eleventh, and twelfth elements are connected in series in the first axial direction. The tenth, eleventh, and twelfth elements each have a control gate, The tenth element has a source, The 12th element has a drain, The control gate of the 10th element is connected to the 10th word line, The control gate of the 11th element is connected to the 11th word line, The control gate of the 12th element is connected to the 12th word line, The source of the 10th element is connected to the 3rd bit line, The drain of the 12th element is connected to the 5th bit line. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

6. The 21st, 22nd, and 23rd elements, It consists of a 21st word line and a 22nd bit line extending in the third direction. The 21st, 22nd, and 23rd elements are connected in series in the first axial direction. The 21st, 22nd, and 23rd elements each have a control gate, The 21st element has a source, The 23rd element has a drain, The control gate of the 21st element is connected to the 21st word line, The control gate of the 22nd element is connected to the second word line, The control gate of the 23rd element is connected to the third word line, The source of the 21st element is connected to the first bit line, The drain of the 23rd element is connected to the 22nd bit line. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

7. The 24th, 25th, and 26th elements, It consists of a 26th word line extending in the third axial direction, The 24th, 25th, and 26th elements are connected in series in the first axial direction. The 24th, 25th, and 26th elements each have a control gate, The 24th element has a source, The 26th element has a drain, The control gate of the 24th element is connected to the fourth word line, The control gate of the 25th element is connected to the 5th word line, The control gate of the 26th element is connected to the 26th word line, The source of the 24th element is connected to the 22nd bit line. The semiconductor device according to claim 6, characterized in that it is as described above.

8. The 31st, 32nd, and 33rd elements, It consists of a 32nd and 33rd word line and a 31st bit line extending in the second direction, The 31st, 32nd, and 33rd elements are connected in series in the first axial direction. The 31st, 32nd, and 33rd elements each have a control gate, The 31st element has a source, The 33rd element has a drain, The control gate of the 31 element is connected to the first word line, The control gate of the 32 element is connected to the word line of the 32 element, The control gate of the 33 element is connected to the word line of the 33 element. The source of the 31 element is connected to the bit line of the 31 element, The drain of the 33 element is connected to the second bit line. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

9. The 34th, 35th, and 36th elements, It consists of the 34th and 35th word lines and the 36th bit line, extending in the second axial direction. The 34th, 35th, and 36th elements are connected in series in the first axial direction. The 34th, 35th, and 36th elements each have a control gate, The 34th element has a source, The 36th element has a drain, The control gate of the 34th element is connected to the word line of the 34th element. The control gate of the 35th element is connected to the word line of the 35th element. The control gate of the 36th element is connected to the 6th word line, The source of the 34th element is connected to the second bit line, The drain of the 36th element is connected to the bit line of the 36th element. The semiconductor device according to claim 8, characterized in that it is a semiconductor device.

10. A first voltage is applied to the first, third, seventh, and ninth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, second, third, seventh, eighth, and ninth elements, respectively, which is necessary to allow current to flow between the source and drain of the first, second, third, seventh, eighth, and ninth elements. The voltages of the first and ninth word lines are varied from the first voltage to the transmitted voltage. The transmitted voltage is higher than the threshold of any of the first, second, third, seventh, eighth, and ninth elements. The second and eighth word lines are used to apply the read voltage. The read voltage is higher than the first voltage and lower than the transmitted voltage. The method for operating the semiconductor device according to feature 4.

11. A first voltage is applied to the first, third, fourth, and sixth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first to sixth elements, respectively, which is necessary to allow current to flow between the source and drain of the first to sixth elements. The voltages of the third and fourth word lines are varied from the first voltage to the transmitted voltage. The transmitted voltage is higher than the threshold value of any of the first to sixth elements. A read voltage is applied to the second and fifth word lines. The read voltage is higher than the first voltage and lower than the transmitted voltage. The method for operating the semiconductor device described in claim 1, characterized by its features.

12. A first voltage is applied to the first, third, and 21st word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, third, and 21 elements, which is necessary to allow current to flow between the source and drain of the first, third, and 21 elements. The voltage applied to the first and 21st word lines is changed from the first voltage to the transmission voltage. The transmitted voltage is higher than the threshold voltage of any of the first, third, and 21 elements. A read voltage is applied to the second word line. The read voltage is higher than the first voltage and lower than the transmitted voltage. The method for operating the semiconductor device according to claim 6, characterized in that it is as described above.

13. A first voltage is applied to the first, third, and thirtieth word lines. The first voltage is lower than the threshold voltage. The threshold voltage is the threshold voltage applied to the gates of the first, third, and 33 elements, which is necessary to allow current to flow between the source and drain of the first, third, and 33 elements. The voltage applied to the third and thirtieth word lines is changed from the first voltage to the transmission voltage. The transmitted voltage is higher than the threshold of any of the first, third, and thirtieth elements. A read voltage is applied to the second and third word lines. The read voltage is higher than the first voltage and lower than the transmitted voltage. The method for operating the semiconductor device according to claim 8, characterized in that it is as described above.

14. The axial direction of either the second or third described above is designated as the first selected axis, and the other as the second selected axis. On top of the first conductive layer which is patterned to extend along the first selection axis, The first to fifth films are stacked, The first, third, and fifth films are insulating films of type 1. The second and fourth films are type 2 insulating films, The first to fifth films are etched along the second selection axis to create a first slit. The first slit extends in the direction of the second selection axis, The second and fourth membranes are removed, After performing the prescribed procedure, a third type insulating film is embedded in the first slit. After performing the prescribed treatment, the sixth, seventh, and eighth films are laminated on the fifth film. The sixth and eighth films are the first type insulating film, The seventh film is the second type of insulating film, The sixth to eighth films are etched in the direction of the first selection axis, and a second slit is opened. The second slit extends in the direction of the first selection axis, The seventh membrane is peeled off, After performing the prescribed procedure, the third type of insulating film is embedded in the second slit. The first conductive layer is a bit line extending in the direction of the first selected axis. A method for manufacturing a semiconductor device according to claim 1, characterized in that it is as described above.

15. After performing a predetermined treatment on the eighth film, The second conductive layer is patterned so as to extend along the second selection axis, The second conductive layer is a bit line extending in the direction of the second selected axis, The ninth to thirteenth films are laminated on the second conductive layer, The ninth, eleventh, and thirteenth films are the first type insulating film, The tenth and twelfth films are the second type of insulating film, The first and second conductive layers intersect each other in the plane formed by the first and second selection axes. A method for manufacturing a semiconductor device according to claim 14, characterized in that it is a semiconductor device.

16. The first type of insulating film consists of an oxide film, The second type of insulating film consists of a nitride film. The third type of insulating film consists of a low dielectric film. The first and second conductive layers are made of a metal or a silicide. A method for manufacturing a semiconductor device according to claim 15, characterized in that it is a semiconductor device.

17. The axial direction of either the second or third is designated as the 21st selection axis, and the other as the 22nd selection axis. On the 21 conductive layer which is patterned to extend along the 21 selection axis, Layers 21 to 23 are stacked, The 21st and 23rd films are type 21 insulating films, The 22nd film is a 22nd type insulating film, The 21st to 23rd films are etched along the 22nd selection axis to open the 21st slit, The 21st slit extends in the direction of the 22nd selection axis, The 22nd film is peeled off, After performing the prescribed procedure, the 23rd insulating film is embedded in the 21st slit. After performing the prescribed treatment, the 24th to 28th films are laminated on the 23rd film. The 24th, 26th, and 28th films are the 21st type insulating film, The 25th and 27th films are the 22nd type insulating film, The films 24 to 28 are etched in the direction of the selection axis 21, and the 22nd slit is opened. The 22nd slit extends in the direction of the 21st selection axis, The 25th and 27th membranes are peeled off, After performing the prescribed procedure, the 23 type insulating film is embedded in the 22 slit. The 21st conductive layer is a bit line extending in the direction of the 21st selected axis. A method for manufacturing a semiconductor device according to claim 1, characterized in that it is as described above.

18. After performing a predetermined treatment on the aforementioned 28 film, The 22nd conductive layer is patterned so as to extend along the 22nd selection axis, The 22nd conductive layer is a bit line extending in the direction of the 22nd selected axis, On the aforementioned 22 conductive layer, The 29th to 31st films are stacked, The 29th and 31st films are type 21 insulating films, The 30th film is the 22nd type insulating film, The 22nd conductive layer is a bit line extending in the direction of the 22nd selected axis, The 21st and 22nd conductive layers intersect each other in the plane formed by the 21st and 22nd selection axes. A method for manufacturing a semiconductor device according to claim 17, characterized in that it is a semiconductor device.

19. The 21st type insulating film consists of an oxide film. The 22nd insulating film is made of a nitride film. The 23rd insulating film is made of a low dielectric film. The 21st and 22nd conductive layers are made of metal or silicide. A method for manufacturing a semiconductor device according to claim 18, characterized in that it is a semiconductor device.

20. Having a first and a second wiring metal layer, The first bit line is connected to the first wiring metal layer, The second word line is connected to the second wiring metal layer, The third word line is connected to the first wiring metal layer, The fourth word line is connected to the second wiring metal layer, The fifth word line is connected to the first wiring metal layer, The third bit line connects to the second wiring metal layer. The semiconductor device according to claim 1, characterized in that it is a semiconductor device.

21. The first and sixth word lines are connected to one of the first and second wiring metal layers, The second bit line connects to the other of the first and second wiring metal layers. The semiconductor device according to claim 20, characterized in that it is as described above.

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