Method for manufacturing a surface-emitting laser element

Abstract

To provide a manufacturing method of a photonic crystal plane emission laser of which an oscillation wavelength and an outgoing beam characteristic are controlled with high accuracy.SOLUTION: A manufacturing method of a photonic crystal plane emission includes the steps of: (a) forming a first semiconductor layer containing a photonic crystal layer on a transparence substrate; (b) forming an active layer and a second semiconductor layer in this order by performing a crystal growth on the first semiconductor layer; (c) performing a spectrometry that radiates light from a front surface of the second semiconductor layer and measures a layer thickness until a reflection position of the radiation light by the photonic crystal layer from the surface; (d) forming a transparence electrode having a layer thickness calculated on the basis of an optical path corresponded to the layer thickness obtained by the spectrometry measurement, on the second semiconductor layer; and (e) forming an optical reflection layer on the transparence electrode. The layer thickness of the transparence electrode is defined so that a light strength of interference light of direct diffraction light emitted from the photonic crystal layer and ejected from a back surface of the substrate and reflection diffraction light emitted from the photonic crystal layer and reflected by the light reflection layer is larger than the light strength of the direct diffraction light.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a surface-emitting laser element, and more particularly to a method for manufacturing a surface-emitting laser element having a photonic crystal. [Background technology]

[0002] In recent years, the development of photonic crystal surface-emitting lasers (PCSELs), which utilize photonic crystals (PCs), has been progressing.

[0003] For example, Patent Document 1 discloses a photonic crystal surface-emitting laser equipped with a p-side electrode that functions as a reflective surface, and capable of emitting a main beam and a sub-beam.

[0004] Non-Patent Document 1 discloses a photonic crystal surface emission laser using a semiconductor DBR as the p-side reflection structure. Non-Patent Document 2 discloses a high-power photonic crystal surface emission laser equipped with a p-side electrode that functions as a reflection surface.

[0005] Furthermore, Non-Patent Document 3 discloses the formulation of diffracted light from a photonic crystal surface-emitting laser, and the diffracted radiation wave profile emitted perpendicular to the photonic crystal layer after diffraction in the photonic crystal layer. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2015-149403 [Non-patent literature]

[0007] [Non-Patent Document 1] Yoshida, M. et al., Double-lattice photonic-crystal resonators enabling high-brightness semiconductor lasers with symmetric narrow-divergence beams. Nat. Mater. 18, 121 (2019). [Non-Patent Document 2] Hirose, K. et al. Watt-class high-power, high-beam-quality photonic-crystal lasers. Nat. Photon. 8, 406-411 (2014). [Non-Patent Document 3] Y. Liang et al.: Phys.Rev. B vol.84, 195119 (2011) [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] In a photonic crystal surface-emitting laser (PCSEL), light emitted by two-dimensional in-plane resonance in the photonic crystal layer is diffracted perpendicular to the plane, and the emitted light is extracted from the substrate side.

[0009] During this process, light diffracted from the photonic crystal layer toward the substrate (directly diffracted light) interferes with light diffracted in the opposite direction and reflected by the reflective surface (reflected diffracted light). This interference significantly alters characteristics such as the slope efficiency of the emitted light.

[0010] The interference between directly diffracted light and reflected diffracted light is determined by the optical path length of the photonic crystal layer and the semiconductor layer between the reflective surfaces. However, it is extremely difficult to grow the semiconductor layer with high precision control of its thickness so that this optical path length can be determined. Therefore, it has been difficult to manufacture photonic crystal surface-emitting lasers with highly precise control over the characteristics of the emitted light.

[0011] This invention has been made in view of the above points, and aims to provide a method for manufacturing a photonic crystal surface-emitting laser in which the oscillation wavelength and output light characteristics are controlled with high precision. Furthermore, it aims to provide a photonic crystal surface-emitting laser having high performance output light characteristics such as high slope efficiency, and a manufacturing method for producing said photonic crystal surface-emitting laser with high yield. [Means for solving the problem]

[0012] A method for manufacturing a surface-emitting laser element according to one embodiment of the present invention is: (a) A first semiconductor layer of a first conductivity type including a photonic crystal layer is formed on a translucent substrate. (b) Crystal growth is performed on the first semiconductor layer to form an active layer and a second semiconductor layer of the second conductivity type in this order. (c) Light is irradiated from the surface of the second semiconductor layer, and a spectroscopic measurement is performed to measure the layer thickness from the surface to the reflection position of the irradiated light by the photonic crystal layer. (d) A translucent electrode having a layer thickness calculated based on the optical path length corresponding to the layer thickness obtained by the spectroscopic measurement is formed on the second semiconductor layer, (e) A light-reflecting layer is formed on the light-transmitting electrode, The thickness of the translucent electrode is determined such that the light intensity of the interference light between the direct diffracted light emitted from the photonic crystal layer and emitted from the back surface of the substrate and the reflected diffracted light emitted from the photonic crystal layer and reflected by the light reflection layer is greater than the light intensity of the direct diffracted light. [Brief explanation of the drawing]

[0013] [Figure 1A] This is a schematic cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser element 10 according to an embodiment of the present invention. [Figure 1B] Figure 1A is a schematic partially enlarged cross-sectional view showing the vacancy layer 14P (photonic crystal layer) and the air holes 14K arranged within the vacancy layer 14P. [Figure 2A]It is a plan view schematically showing the upper surface of the PCSEL element 10 (in a state where the pad electrode 33 is removed). [Figure 2B] It is a cross-sectional view schematically showing a cross section in a plane parallel to the n-side guide layer 14 of the hole layer 14P. [Figure 2C] It is a plan view schematically showing the lower surface of the PCSEL element 10. [Figure 3] It is a view schematically showing an example of a hole array in a plane parallel to the photonic crystal layer 14P. [Figure 4] It is a manufacturing process flow chart showing the manufacturing method of the PCSEL element 10. [Figure 5] It is a view schematically showing the upper surface of the wafer WF after crystal growth is completed. [Figure 6] It is a graph showing the spectroscopic reflection curve of the wafer WF after growth is completed. [Figure 7] It is a view schematically showing the surface reflected light ES and the reflected light ER by the photonic crystal 14P when the irradiation light EM of the spectroscopic reflection measurement device is irradiated on the wafer WF. [Figure 8] It is a view schematically showing the interference between the reflected diffracted light Lr reflected by the light reflection layer 32 and emitted from the light emission surface and the diffracted light Ld directly emitted from the light emission surface. [Figure 9A] It is a graph plotting the slope efficiency with respect to the oscillation wavelength of the PCSEL element 10 of the example (EX). [Figure 9B] It is a graph plotting the slope efficiency with respect to the oscillation wavelength of the PCSEL element of the comparative example CMP.

Embodiments for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present invention will be described, but these may be appropriately modified and combined. Also, in the following description and the accompanying drawings, substantially the same or equivalent parts will be described with the same reference numerals.

[0015] [First Embodiment] 1. Structure of Photonic Crystal Surface Emitting Laser (a) Element structure A photonic crystal surface-emitting laser (hereinafter also referred to as a PCSEL) is a device that has a resonator layer parallel to the semiconductor light-emitting structural layer (n-side guide layer, light-emitting layer, p-side guide layer) that constitutes the light-emitting element, and emits coherent light in a direction perpendicular to the resonator layer.

[0016] In other words, in a photonic crystal surface-emitting laser (PCSEL), light waves propagating in a plane parallel to the photonic crystal layer are diffracted by the diffraction effect of the photonic crystal, forming a two-dimensional resonance mode, and are also diffracted in a direction perpendicular to that parallel plane. That is, in a photonic crystal surface-emitting laser, the direction of light extraction is perpendicular to the resonance direction (in the plane parallel to the photonic crystal layer).

[0017] Figure 1A is a schematic cross-sectional view showing an example of the structure of a photonic crystal surface-emitting laser element (hereinafter referred to as a PCSEL element) 10 according to an embodiment of the present invention. Figure 1B is a schematic enlarged cross-sectional view showing the photonic crystal layer 14P and the pairs of air holes 14K arranged in the photonic crystal layer 14P in Figure 1A.

[0018] As shown in Figure 1A, the semiconductor structural layer 11 is formed on a translucent substrate 12. The semiconductor layers are stacked perpendicular to the central axis CX of the semiconductor structural layer 11.

[0019] Furthermore, the semiconductor structural layer 11 is made of a hexagonal nitride semiconductor. In this embodiment, the semiconductor structural layer 11 is made of, for example, a GaN-based semiconductor.

[0020] More specifically, a semiconductor structure layer 11 consisting of multiple semiconductor layers is formed on the substrate 12 in the following order: an n-clad layer (first clad layer of the first conductivity type) 13, an n-side guide layer (first guide layer) 14 provided on the n side, an active layer (ACT) 15, a p-side guide layer (second guide layer) 16 provided on the p side, an electron barrier layer (EBL) 17, a p-clad layer (second clad layer of the second conductivity type) 18, and a p-contact layer 19.

[0021] The explanation will focus on the case where the first conductivity type is n-type and the second conductivity type, which is the opposite conductivity type of the first conductivity type, is p-type. However, the first and second conductivity types may also be p-type and n-type, respectively.

[0022] The substrate 12 is a hexagonal GaN single crystal substrate with high transmittance of light emitted from the active layer 15. More specifically, the substrate 12 is a hexagonal GaN single crystal substrate whose main surface (crystal growth surface) is the {0001} plane, or +c plane, where Ga atoms are arranged on the outermost surface. The back surface (light emission surface) is the (000-1) plane, or -c plane, where N atoms are arranged on the outermost surface. The -c plane is suitable as a light emission surface because it is resistant to oxidation and the like.

[0023] The substrate 12 is not limited to this, but a so-called just substrate, or a substrate in which the main surface is offset by about 1° in the m-axis direction, is preferred. For example, a substrate offset by about 1° in the m-axis direction can achieve mirror-finish growth under a wide range of growth conditions.

[0024] The substrate surface (back surface, light-emitting surface) on which the light-emitting region 20L opposite the main surface is the "-c" surface, which is the (000-1) surface where N atoms are arranged on the outermost surface. The -c surface is suitable as a light extraction surface because it is resistant to oxidation and the like.

[0025] The following describes the composition, thickness, and other configurations of each semiconductor layer. However, these are merely examples and can be modified and applied as appropriate.

[0026] The n-cladding layer 13 is, for example, n-Al with an Al composition of 4%. 0.04 Ga 0.96 It is an N-layer with a thickness of 2 μm. The aluminum (Al) composition ratio is such that the refractive index is lower than that of the layer adjacent to the active layer 15 (i.e., the n-side guide layer 14).

[0027] The n-side guide layer 14 consists of a lower guide layer 14A, a photonic crystal layer (PC layer) air-hole layer 14P, and a filling layer 14B. As shown in Figure 1B, the air-hole layer 14P has a layer thickness (depth) d PC The embedded layer 14B has a layer thickness d EMB It has.

[0028] The lower guide layer 14A is, for example, n-GaN with a layer thickness of 20 to 500 nm. The void layer (air-hole layer) 14P is n-GaN with a layer thickness (or void depth 14K) of 60 to 150 nm.

[0029] The embedded layer 14B consists of n-GaN, n-InGaN, or undoped GaN, or undoped InGaN. Alternatively, it may be a layer in which these semiconductor layers are stacked. The embedded layer 14B has a layer thickness of, for example, 50 to 150 nm.

[0030] The active layer 15, which is the light-emitting layer, is, for example, a multiple quantum well (MQW) layer having two quantum well layers. The barrier layer and quantum well layers of the MQW are made of GaN (layer thickness 6.0 nm) and InGaN (layer thickness 3.0 nm), respectively. The gain wavelength of the active layer 15 is 432 nm.

[0031] Furthermore, it is preferable that the active layer 15 is located within 180 nm of the vacancy layer 14P. In this case, a high resonance effect can be obtained due to the vacancy layer 14P.

[0032] The p-side guide layer 16 is made of, for example, undoped GaN or undoped InGaN and has a layer thickness of 100 to 350 nm. Although the p-side guide layer 16 is an undoped layer considering light absorption by the dopant, magnesium (Mg) or the like may be doped to obtain good electrical conductivity.

[0033] Alternatively, the p-side guide layer 16 may have a structure in which an undoped layer and a doped layer are laminated. Furthermore, an InGaN layer and a GaN layer can be laminated as the p-side guide layer 16, and the In composition and thickness of the InGaN layer can be appropriately selected.

[0034] The electron barrier layer (EBL) 17 is made of magnesium (Mg) doped p-type Al. 0.2 Ga 0.8 It has N layers, for example 、 It has a layer thickness of 15 nm.

[0035] The p-cladding layer 18 is Mg-doped p-Al 0.06 Ga 0.94 It is an N layer, and for example, has a layer thickness of 50 to 600 nm. Preferably, the Al composition of the p-clad layer 18 is selected such that its refractive index is lower than that of the p-side guide layer 16.

[0036] Furthermore, the p-contact layer 19 is a Mg-doped p-GaN layer, for example, having a thickness of 25 nm. The carrier density of the p-contact layer 19 is set to a concentration that allows for ohmic bonding with the translucent electrode 31 provided on its surface. Instead of p-type GaN, p-type InGaN may be used. Alternatively, a layer consisting of a GaN layer and an InGaN layer may be used.

[0037] In this specification, "n-side" and "p-side" do not necessarily mean that they have an n-type or p-type structure. For example, the n-side guide layer refers to a guide layer located on the n-side of the active layer, and may be an undoped layer (or i-layer).

[0038] Furthermore, the n-clad layer 13 may consist of multiple layers rather than a single layer, in which case not all layers need to be n-doped layers, and may include undoped layers (i-layers). The same applies to the guide layer 16 and the p-clad layer 18.

[0039] Furthermore, it is not necessary to provide all of the above-mentioned semiconductor layers; a configuration having a first semiconductor layer of the first conductivity type including a photonic crystal layer, a second semiconductor layer of the second conductivity type, and an active layer (light-emitting layer) sandwiched between these layers is sufficient.

[0040] The sides and top surface of the semiconductor structural layer 11 are covered with an insulating film 21 such as SiO2. The insulating film 21 also has an opening OP with a diameter RA (center axis CX) that exposes the top surface of the semiconductor structural layer 11 (i.e., the top surface of the p-contact layer 19).

[0041] The insulating film 21 also functions as a protective film, protecting the aluminum (Al) crystal layer constituting the PCSEL element 10 from corrosive gases, etc. Furthermore, it prevents short circuits caused by deposits and solder creep during mounting, contributing to improved reliability and yield. The material of the insulating film 21 is not limited to SiO2; ZrO2, HfO2, TiO2, Al2O3, SiNx, Si, etc., can be selected.

[0042] A translucent electrode 31 (anode) is provided on the p-contact layer 19 exposed through the opening OP, making ohmic contact with the p-contact layer 19. More specifically, the translucent electrode 31 fills the opening OP, and its peripheral edge is formed to overlap the insulating film 21. For ease of understanding, the region of the translucent electrode 31 within the opening OP will be described as the anode region RA, using the same reference numeral as the diameter of the opening OP.

[0043] The translucent electrode 31 is formed from a translucent conductor, for example, indium tin oxide (ITO). However, the translucent electrode 31 is not limited to ITO, and translucent conductors such as zinc tin oxide (ZTO), GZO (ZnO:Ga), and AZO (ZnO:Al) can be used.

[0044] A silver alloy (Ag alloy) layer is provided on the translucent electrode 31 as a light-reflecting layer 32. The light-reflecting layer 32 is provided so as to cover at least the entire aperture OP when viewed from above. The light-reflecting layer 32 also has a flat surface (top surface) that is parallel to the void layer 14P.

[0045] Furthermore, Ag, Al, Al alloy, dielectric DBR (Distributed Bragg Reflector), etc., can also be used as the light-reflecting layer 32.

[0046] A pad electrode 33 made of nickel / palladium / gold (Ni / Pd / Au) is provided on the light-reflecting layer 32 so as to cover the entire light-reflecting layer 32. The pad electrode 33 can also be made of Ni / Au, platinum / gold (Pt / Au), Pt / Pd / Au, titanium / gold (Ti / Au), Ti / Pt / Au, tungsten / palladium / gold (W / Pd / Au), W / Au, W / Pt / Au, etc.

[0047] An annular cathode electrode 20A is formed on the back surface of the substrate 12. Furthermore, an anti-reflective (AR) coating layer 27 is formed on the inside of the cathode electrode 20A.

[0048] The cathode electrode 20A is made of Ti / Pt / Au and is in ohmic contact with the substrate 12. The electrode material is Ti / Pt In addition to / Au, other options include Ti / Al, Ti / Rh, Ti / Al / Pt / Au, Ti / Au, vanadium / aluminum (V / Al), V / Rh, V / Al / Pt / Au, V / Pt / Au, etc.

[0049] Synchrotron radiation from the active layer 15 is diffracted by the vacancy layer (PC layer) 14P. The light diffracted by the vacancy layer 14P and directly emitted from the vacancy layer 14P (direct diffracted light Ld: first diffracted light) and the light emitted by the diffraction of the vacancy layer 14P and reflected by the light reflection layer 32 (reflected diffracted light Lr: second diffracted light) are emitted to the outside from the light emission region 20L (Figure 2C) on the back surface (emission surface) 12R of the substrate 12.

[0050] Figure 2A is a schematic plan view showing the top surface of the PCSEL element 10. For clarity and ease of understanding, the top surface is schematically shown with the pad electrodes 33 removed.

[0051] Furthermore, Figure 2B is a schematic cross-sectional view showing the cross-section of the void layer 14P in a plane parallel to the n-side guide layer 14, and Figure 2C is a schematic plan view showing the lower surface of the PCSEL element 10.

[0052] As shown in Figure 2B, in the pore layer 14P, the pores 14K are arranged periodically within, for example, a rectangular pore-forming region 14R. As shown in Figure 2C, the anode region RA is formed to be contained within the pore-forming region 14R.

[0053] Furthermore, the cathode electrode 20A is provided as an annular electrode outside the pore formation region 14R so as not to overlap with the pore formation region 14R when viewed from a direction perpendicular to the pore layer 14P.

[0054] The area inside the cathode electrode 20A is the light emission area 20L. A bonding pad 20C is also provided, which is electrically connected to the cathode electrode 20 and to which a wire for external power supply is connected.

[0055] (b) Photonic crystal layer As shown in Figures 1A and 1B, the photonic crystal layer 14P has regularly arranged air holes that cause the light emitted from the active layer 15 to resonate in the horizontal plane.

[0056] Figure 3 is a schematic diagram showing an example of a vacancy arrangement in a plane parallel to the photonic crystal layer 14P. Specifically, it is a schematic plan view of a vacancy pair 14K (hereinafter sometimes simply referred to as vacancy 14K) consisting of a main vacancy 14K1 and a secondary vacancy 14K2, arranged in a square lattice position within the plane of the photonic crystal layer 14P, as viewed from above.

[0057] In other words, the photonic crystal layer 14P has a double lattice structure. For clarity in the drawing, the main vacancies 14K1 and secondary vacancies 14K2 are shown with hatching.

[0058] More specifically, the main voids 14K1 are arranged in a square lattice with periodicity PK in two mutually orthogonal directions (x and y directions) with their centroids CD1. Similarly, the secondary voids 14K2 are arranged in a square lattice with periodicity PK in the x and y directions with their centroids CD2.

[0059] The main void 14K1, when viewed from above (i.e., from a direction perpendicular to the photonic crystal layer 14P), has a long hexagonal shape surrounded by the m-plane, which is a {10-10} plane. The secondary void 14K2 also has a shape surrounded by the m-plane.

[0060] The x and y directions are inclined at 45° with respect to the long axis direction (<11-20> direction) and short axis direction (<1-100> direction) of the main void 14K1, respectively. In this specification, the xy coordinates are also referred to as void coordinates.

[0061] Furthermore, the centroid CD2 of the secondary cavity 14K2 is separated from the centroid CD1 of the main cavity 14K1 by Δx in the x direction and Δy in the y direction. Here, Δx = Δy = 0.46PK. That is, the centroid CD2 of the secondary cavity 14K2 is separated from the centroid CD1 of the main cavity 14K1 in the <1-100> direction.

[0062] Here, the distance between the centers of gravity Δx in the x-direction and the distance between the centers of gravity Δy in the y-direction can be appropriately adjusted according to the laser characteristics, such as the current value required for the device to which the laser element is applied, and the slope efficiency of the laser emission intensity.

[0063] Here, we will explain using the case where the photonic crystal layer 14P has a double lattice structure as an example, but it is not limited to this. The photonic crystal layer 14P may have a single lattice structure or a multi-lattice structure.

[0064] 2. Manufacturing method of PCSEL elements Next, the manufacturing method of the PCSEL element 10 will be described along the manufacturing process flow shown in FIG. 4. In the following examples (EX), the improvement of the slope efficiency of the PCSEL element 10 with an oscillation wavelength of 432 nm was examined.

[0065] (S1: Crystal growth step) Using a MOVPE (Metalorganic Vapor Phase Epitaxy) apparatus, an n-Al 0.04 Ga 0.96 GaN layer as the n-clad layer 13 was formed on the +c-plane GaN substrate 12 with a thickness of 2 μm. Subsequently, an n-GaN layer was formed on the n-clad layer 13 with a thickness of 500 nm.

[0066] (S2: Patterning step) An SiNx film was formed on the n-GaN layer to a thickness of about 100 nm using the plasma CVD method. Next, an electron beam lithography resist was spin-coated on the SiNx film and placed in an electron beam lithography apparatus (EB apparatus) to form a two-dimensional periodic pattern corresponding to the aforementioned two-dimensional photonic crystal structure.

[0067] At this time, in order to investigate the influence of the phase, the resist was patterned so that different hole periods PKj were obtained in a plurality of hole formation regions Wj so that elements with oscillation wavelengths from 429 nm to 440 nm could be obtained within the same substrate.

[0068] After developing the patterned resist, the SiNx was selectively dry-etched using an inductively coupled plasma reactive ion etching (ICP-RIE) apparatus. As a result, holes arranged in a square lattice were formed so as to penetrate the SiNx film.

[0069] Subsequently, the resist was removed, and the n-GaN layer was dry-etched using an ICP-RIE apparatus with Cl2, BCl3, and Ar gas, with SiNx as the hard mask. The etching depth at this time was approximately 190 nm. After that, the SiNx hard mask was removed with buffered hydrofluoric acid (BHF).

[0070] (S3: Recrystallization growth step) The substrate on which the photonic crystal was formed was placed back into the MOVPE apparatus and embedded and grown while leaving voids. Specifically, undoped GaN was grown to a thickness of 70 nm and undoped InGaN to a thickness of 50 nm to form the embedded layer 14B. This formed the n-side guide layer 14, which includes the photonic crystal layer 14P.

[0071] Next, two pairs of InGaN / GaN active layers 15 (MQW layers) were grown on the embedded layer 14B (i.e., on the n-side guide layer 14). Subsequently, undoped InGaN was grown on the active layer 15 to a thickness of 70 nm and undoped GaN to a thickness of 180 nm to form the p-side guide layer 16.

[0072] Next, a p-AlGaN electron barrier layer 17 was grown to a thickness of 15 nm, and a p-AlGaN layer (p-clad layer 18) was grown on the electron barrier layer 17 to a thickness of 300 nm. Then, a p-contact layer 19 consisting of a p-GaN / p-InGaN layer was grown to a thickness of 25 nm.

[0073] Furthermore, the entire group of semiconductor layers formed on these n-side guide layers 14 is referred to as the guide layer semiconductor layer 11K.

[0074] Figure 5 schematically shows the upper surface of the wafer WF after crystal growth has been completed as described above. Specifically, it shows that within the photonic crystal layer 14P formed in the n-side guide layer 14, there are regions Wj (W1 to W9) in which vacancies are arranged with different vacancy periods PKj (j=1 to 9).

[0075] More specifically, the hole periods PKj for each region W1 to W9 are set to integer multiples of the resonant wavelength (λ). To set the oscillation wavelength to 429 nm to 440 nm, the hole periods PKj were set at 1.2 nm intervals from PK1=172 nm, PK2=173.2 nm, ..., PK9=182.8 nm.

[0076] Furthermore, the vacancies 14K1 and 14K2 have a hexagonal shape surrounded by the m-plane, which is a {10-10} plane, when viewed from above. In addition, the depth of the main vacancy 14K1 in the photonic crystal layer 14P was set to 90 nm, and the depth of the secondary vacancy 14K2 was set to 70 nm.

[0077] In this example, wafers WF with different vacancy periods PKj were formed for each region Wj for evaluation by spectral reflectance measurement described later. However, in the wafer WF used to actually manufacture the PCSEL element 10, it is sufficient to form a photonic crystal layer 14P with a single vacancy period PK.

[0078] (S4: Spectroscopic reflectance measurement step) Light was shone from the outermost growth surface (i.e., the surface of the p-contact layer 19) of the grown wafer WF (hereinafter also simply referred to as wafer WF) as described above, and spectral reflectance measurements were performed. Based on the spectral reflectance measurement results, the thickness of the translucent electrode 31 (translucent conductive film) to be deposited thereafter was determined. Details of the spectral reflectance measurement method and its results will be described later.

[0079] (S5: Insulating film formation step) An insulating film 21 was formed on the grown wafer WF by sputtering a 100 nm thick layer of SiO2. Subsequently, the resist was patterned by photolithography, and then the SiO2 was removed with BFH to form a 300 μm diameter opening OP that exposed the top surface of the p-contact layer 19.

[0080] (S6: Transparent electrode formation step) Next, a translucent electrode 31, which is an ITO film that covers the upper surface of the insulating film 21 and fills the opening OP, was formed by sputtering.

[0081] Next, after patterning the resist using photolithography, wet etching was performed to remove the ITO film in unwanted areas, forming a translucent electrode 31 with a flat surface and parallel to the photonic crystal layer 14P.

[0082] Furthermore, based on the results of spectral reflectance measurements, the layer thickness of the translucent electrode 31 was set to 135 nm in the wafer WF of Example (EX). Similarly, the wafer of Comparative Example (CMP) was also set to 135 nm for the same purpose as Example (EX) in order to evaluate the device characteristics.

[0083] In other words, the thickness of the translucent electrode 31 was set such that in Example (EX), the phases of the directly diffracted light Ld and the reflected diffracted light Lr coincided and the conditions for the most constructive interference were met, while in Comparative Example (CMP), the thickness was set to a level that deviated from the conditions for the most constructive interference (however, the light intensity was greater than that of the directly diffracted light Ld).

[0084] Here, the condition for constructive interference between the light intensity of the interference light of the directly diffracted light Ld and the reflected diffracted light Lr (interference condition) is that the light intensity of the interference light is greater than the light intensity of the directly diffracted light Ld. Preferably, the conditions for the most constructive interference are when the phases of the directly diffracted light Ld and the reflected diffracted light Lr emitted from the PCSEL element 10 coincide.

[0085] Furthermore, the thickness of the translucent electrode 31 may be such that the light intensity of the interference light of the direct diffracted light Ld and the reflected diffracted light Lr destructively cancels each other out.

[0086] (S7: Light-reflecting layer formation step) A silver (Ag) alloy film with a thickness of 150 nm was deposited on the translucent electrode 31 to form a light-reflecting layer 32. The formation of the light-reflecting layer 32 created a light-reflecting surface SR at the interface between the translucent electrode 31 and the light-reflecting layer 32.

[0087] (S8: Electrode and anti-reflective layer formation step) A pad electrode 33 was formed by sequentially depositing Ni / Pd / Au films with thicknesses of 10 nm / 200 nm / 800 nm on the light-reflecting layer 32.

[0088] Next, after polishing the back surface of the substrate, a 170nm thick wafer WF was obtained by performing a mirror finish using chemical mechanical polishing (CMP). Subsequently, a Ti / Pt / Au film (layer thickness: 50nm / 50nm / 500nm) was deposited on the polished surface to form a cathode electrode 20A.

[0089] Furthermore, SiN is placed on the back surface of the substrate in the inner region of the cathode electrode 20A (i.e., the light emission region 20L). x A film of SiO2 (layer thickness: 32nm / 53nm) was deposited to form an anti-reflective coating layer 27, which is an anti-reflective layer.

[0090] (S9: Piecemaking step) Finally, the wafer WF was scribed using a laser scribe or diamond scribe, and then cleaved into individual pieces using a cleavage apparatus to obtain 80 PCSEL elements 10 with different vacancy periods PK (oscillation wavelength λ). 3. Spectroscopic reflectance measurement and evaluation results The method and results of the spectral reflectance measurement in the spectral reflectance measurement step (S4) described above will be explained.

[0091] Figure 6 is a graph showing the spectral reflectance curve of the wafer WF after growth is complete. Figure 7 is a schematic diagram showing the surface reflected light ES and the reflected light ER from the photonic crystal 14P when the illumination light EM of the spectroreflective measurement device is irradiated onto the wafer WF. For clarity of the figure, the main vacancies 14K1 and sub-vacancies 14K2 of the photonic crystal layer 14P are shown as vacancy pairs 14K.

[0092] The photonic crystal layer 14P is a layer containing vacancies and has a lower refractive index compared to other semiconductor layers. Therefore, the observed spectral reflectance curve shown in Figure 6 is the result of interference between the surface reflected light ES and the reflected light ER from the photonic crystal 14P, as schematically shown in Figure 7.

[0093] Since the back surface of the GaN substrate 11 is rough, light is scattered, and back surface reflection can be almost ignored. Also, the refractive index difference between other semiconductor layers (for example, between GaN / AlGaN layers) is 10-1 ~10 -2 Because the effect is so minimal, reflections at these interfaces have almost no impact.

[0094] Each semiconductor layer in the semiconductor layer 11K above the guide layer was assumed to be GaN, and the layer thickness was determined from the spectral reflectance curve shown in Figure 6. In detail, the semiconductor layer 11K above the guide layer contains a mixed crystal composition layer (InAlGaN layer), but the optical path length from the photonic crystal layer 14P to the surface of the p-contact layer 19 is important. Therefore, the semiconductor layer 11K above the guide layer was calculated and fitted as a single layer of GaN to determine its layer thickness.

[0095] Furthermore, the thickness of each semiconductor layer 11K on the guide layer may be determined in detail using a spectroscopic ellipsometer. The layer thickness can be determined using existing techniques based on basic Fresnel reflection.

[0096] As described above, the layer thickness DP (or optical path length) from the surface of the p-contact layer 19 (i.e., the surface of the wafer WF) to the reflection position RP of the irradiated light EM in the photonic crystal layer 14P was determined. As a result, the layer thickness DP of Example EX was 735 nm.

[0097] Furthermore, a wafer grown under the same conditions as the wafer WF of Example EX described above was formed as the wafer WC of Comparative Example CMP. That is, the wafer WC of Comparative Example CMP has the same n-guide layer 14 and photonic crystal 14P structure as the wafer WF of Example EX.

[0098] In other words, due to the reproducibility of layer thickness in crystal growth, it is expected that even under the same conditions for crystal growth, the grown layer thickness (thickness of the semiconductor layer 11K above the guide layer) will differ between the wafer WF of Example EX and the wafer WC of Comparative Example CMP.

[0099] In fact, as shown in Figure 6, it was found that the spectral reflectance curve was slightly shifted to the longer wavelength side compared to wafer WF of Example EX. From the measured spectral reflectance curve, the layer thickness DP of wafer WC of Comparative Example CMP was determined to be DP = 755 nm. Therefore, it was found that the layer thickness of semiconductor layer 11K on the guide layer differed by about 3% compared to wafer WF of Example EX.

[0100] 4. Characterization of PCSEL elements Figure 8 schematically shows the interference between reflected diffracted light Lr emitted from the photonic crystal layer 14P, reflected by the light reflection layer 32 (light reflection surface SR), and emitted from the back side (light emission side) of the substrate 12, and directly diffracted light Ld emitted from the photonic crystal layer 14P toward the back side of the substrate 12.

[0101] The directly diffracted light Ld and the reflected diffracted light Lr interfere with each other due to the difference in optical path length corresponding to the layer thickness DP. As is clear from Figure 8, the difference in optical path length between the directly diffracted light Ld and the reflected diffracted light Lr is equal to twice the distance which is the sum of the layer thickness DP and the layer thickness of the translucent electrode 31 (the layer thickness from the surface of the p-contact layer 19 to the light-reflecting layer 32). Therefore, by determining the layer thickness DP, the layer thickness of the translucent electrode 31 that satisfies the interference condition can be calculated. In Example (EX), the layer thickness of the translucent electrode 31 is determined so that the phases of the directly diffracted light Ld and the reflected diffracted light Lr coincide. In Comparative Example (CMP), the translucent electrode 31 has a layer thickness that deviates from the condition for the phases of the directly diffracted light Ld and the reflected diffracted light Lr to coincide.

[0102] Because spectroscopic reflectance measurement is used, the reflection position RP within the photonic crystal 14P can be directly measured. Furthermore, since it is a non-destructive measurement, the optical path length can be calculated with high accuracy even in layers where multiple layers with different refractive indices are stacked. In other words, the difference in optical path length between the directly diffracted light Ld and the reflected diffracted light Lr can be measured directly and with high accuracy.

[0103] Specifically, the accuracy of the optical path length difference is within 1%, which translates to a semiconductor layer thickness of within 2-3 nm.

[0104] Furthermore, the diffraction position (wave source position) WS of the diffracted light in the photonic crystal layer 14P may differ slightly from the reflection position RP in the spectroscopic measurement due to differences between the oscillation wavelength and the wavelength of the irradiation light in the spectroscopic measurement (Figure 8).

[0105] Furthermore, for example, from Non-Patent Document 3, it is possible to calculate the wave source (diffraction plane) of the diffracted wave from the vacancy layer 14P and the radiated wave that is diffracted and emitted perpendicular to the vacancy layer 14P using coupled wave theory.

[0106] However, considering the controllability and reproducibility of the semiconductor layer thickness during crystal growth, the diffraction position (wave source position) WS can be sufficiently approximated by the reflection position RP obtained by spectroscopic reflectance measurement.

[0107] Figure 9A is a graph plotting the slope efficiency of the PCSEL element 10 of Example (EX) obtained from a wafer WF (transparent electrode 31 layer thickness 135 nm) against the oscillation wavelength.

[0108] Figure 9B is a graph plotting the slope efficiency of the PCSEL element of the comparative example CMP obtained from wafer WC (transparent electrode 31 layer thickness 135 nm) against the oscillation wavelength.

[0109] Specifically, the following shows the results of measuring the slope efficiency by injecting pulsed current into the PCSEL element 10 of Example (EX) and the PCSEL element of Comparative Example CMP, and measuring the optical output.

[0110] As shown in Figure 9A, the PCSEL element 10 of Example (EX) showed a maximum slope efficiency around the target oscillation wavelength of 432 nm (dotted line in the figure). This is due to interference, and the slope efficiency changes as the optical path length changes with the oscillation wavelength.

[0111] On the other hand, as shown in Figure 9B, in the comparative example CMP PCSEL element, a maximum slope efficiency was observed around 438 nm, which is an oscillation wavelength that deviates from the target oscillation wavelength. Furthermore, the width of the slope efficiency distribution was wider than that of the PCSEL element 10 in Example (EX), resulting in a lower yield of elements with the desired oscillation wavelength and slope efficiency.

[0112] In other words, in the comparative example CMP wafer WC, in order to obtain the maximum slope efficiency at an oscillation wavelength of 432 nm, similar to the example (EX) wafer WF, the thickness of the translucent electrode 31 should be 110 nm.

[0113] Furthermore, even when the photonic crystal layer 14P has a multi-lattice structure, the layer thickness DP (or optical path length) to the reflection position RP can be measured with high accuracy. This is because, in a multi-lattice structure, the reflection position RP can change significantly depending on the relative size of the main vacancies and sub-vacancies, their relative arrangement in the depth direction, and their shape.

[0114] Furthermore, while we have described the case of crystal growth using the MOVPE method, it is not limited to this. For example, it can also be applied to vapor phase growth methods such as MBE (molecular beam epitaxy), hydride vapor phase growth (HVPE), and sputtering, as well as liquid phase growth methods.

[0115] As explained above, spectral reflectance measurements are performed on the wafer after crystal growth to analyze the thickness of the semiconductor layer, and the thickness of the translucent electrode 31 is determined according to that layer thickness. This makes it possible to obtain a photonic crystal surface-emitting laser with highly controlled oscillation wavelength and emission light characteristics, and to provide a manufacturing method that produces the photonic crystal surface-emitting laser with a high yield. [Explanation of Symbols]

[0116] 10: PCSEL element, 11: Semiconductor structure layer, 11K: Semiconductor layer on top of n guide layer, 12: Substrate, 13: First cladding layer, 14: First guide layer, 14A: Lower guide layer, 14P: Photonic crystal layer, 14B: Embedding layer, 14K: Vacancy, 15: Active layer, 16: Second guide layer, 17: Electron barrier layer, 18: Second cladding layer, 19: Contact layer, 20A: Cathode electrode, 21: Insulating film, 31: Translucent electrode, 32: Light reflection layer, 33: Pad electrode, DP: Layer thickness between surface and reflection position, OP: Aperture, RP: Reflection position, SR: Reflection surface

Claims

1. (a) A first semiconductor layer of a first conductivity type including a photonic crystal layer is formed on a translucent substrate. (b) Crystal growth is performed on the first semiconductor layer to form an active layer and a second semiconductor layer of the second conductivity type in this order. (c) The second semiconductor layer is irradiated with light from a spectroscopic reflectance measuring device from the surface side, and the optical path length from the surface to the reflective surface of the photonic crystal layer is spectrally measured using the first reflected light from the surface and the second reflected light from the photonic crystal layer. (d) A translucent electrode having a layer thickness calculated based on the optical path length is formed on the second semiconductor layer, (e) A light-reflecting layer is formed on the light-transmitting electrode, A method for manufacturing a surface-emitting laser element, wherein the thickness of the translucent electrode is determined such that the light intensity of the interference light between the direct diffracted light emitted from the photonic crystal layer and emitted from the back surface of the substrate and the reflected diffracted light emitted from the photonic crystal layer and reflected by the light-reflecting layer is greater than the light intensity of the direct diffracted light.

2. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the spectroscopic measurement is performed using a spectroscopic ellipsometer.

3. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the photonic crystal layer has a multi-lattice structure.

4. The method for manufacturing a surface-emitting laser element according to claim 1, wherein the active layer and the second semiconductor layer are crystallized by the MOVPE method.

5. A method for manufacturing a surface-emitting laser element according to any one of claims 1 to 4, wherein the thickness of the translucent electrode layer is determined so that the phases of the direct diffracted light and the reflected diffracted light coincide.

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