Semiconductor material detection method and growth equipment calibration method
By alternatingly growing multiple semiconductor layers on a substrate and utilizing solvent selectivity and spectral testing, the accuracy and efficiency issues of semiconductor layer composition and thickness measurement were solved, achieving efficient and accurate composition and thickness measurement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- DOGAIN LASER TECH (SUZHOU) CO LTD
- Filing Date
- 2026-04-16
- Publication Date
- 2026-05-15
AI Technical Summary
In existing technologies, the process of measuring the composition ratio and thickness of semiconductor layers is cumbersome and inaccurate, and it is impossible to measure the composition and thickness accurately at the same time. In particular, the test results have large errors under layer structures with different thicknesses.
By alternately growing multiple first and second semiconductor layers on one side of the substrate, and utilizing the bidirectional orthogonal selectivity of the etching solvents for the first and second semiconductor layers, combined with XRD and PL tests, the composition ratio and thickness of the second semiconductor layer are measured respectively, forming a double heterojunction structure to restrict electron migration, and the thickness is directly measured by a step tester.
It enables simultaneous and accurate measurement of the composition ratio and thickness of multiple semiconductor layers, improving measurement efficiency, reducing tedious layer-by-layer testing steps, and enhancing the accuracy and convenience of measurement results.
Smart Images
Figure CN122042718A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of optical chip technology, specifically to a method for detecting semiconductor materials and a method for calibrating growth equipment. Background Technology
[0002] In semiconductor lasers, the laser chip is the core component. In the process of laser chip fabrication, semiconductor layers such as n-type cladding, waveguide layer, quantum well active region, and p-type cladding are first grown on the substrate to form a multilayer epitaxial structure. Then, a wafer structure is formed through processes such as photolithography, etching, ridge waveguide / mesa, dielectric film, front / back metal electrodes, and cavity surface coating. At this time, thousands to tens of thousands of laser bars or single-tube chips are arranged on the wafer structure. Finally, the entire wafer is divided into individual laser chips by laser dicing.
[0003] In the process of laser chip fabrication, the semiconductor layer grown on the substrate is crucial, and the semiconductor layer has very high requirements for the accuracy of component ratio and thickness. In order to ensure the accurate growth of the semiconductor layer in terms of component ratio and thickness, the growth equipment needs to be calibrated.
[0004] The existing calibration process involves growing a semiconductor layer on a substrate, then using XRD (X-ray diffraction) to fit the composition and thickness, measuring the actual composition and thickness of the semiconductor layer, comparing it with preset composition and thickness information to determine its accuracy, and adjusting the calibration equipment based on the comparison results. However, during testing, it is usually necessary to grow semiconductor layers with different composition and thickness for detection. The existing calibration process requires growing and testing each layer one by one, i.e., growing one layer, measuring one layer, removing one layer, and then growing again on the substrate and measuring again, which is a rather cumbersome testing procedure.
[0005] Furthermore, when using XRD testing, the thickness of the layer structure significantly affects both the thickness and composition ratio. When the same composition ratio is achieved with a thicker layer, the main peak is more prominent while the interference fringes are weaker, resulting in more accurate composition ratio information during fitting, but with a larger thickness error. Conversely, when the grown layer structure is thinner, the interference fringes are more prominent while the main peak is less obvious, providing more accurate thickness information, but with a larger error in the composition ratio information. Therefore, it is impossible to simultaneously and accurately measure both the composition ratio and thickness of the layer structure. Summary of the Invention
[0006] (a) The purpose of this invention is to provide a detection method that can accurately measure the thickness and composition of the target layer structure formed by semiconductor materials on a substrate and has more accurate and efficient testing results.
[0007] (II) Technical Solution To address the aforementioned technical problems, one embodiment of the present invention provides a method for detecting semiconductor materials, comprising: A substrate is provided; multiple first semiconductor layers and multiple second semiconductor layers are grown on one side of the substrate, with the second semiconductor layers and the first semiconductor layers growing alternately in sequence, and the layer closest to the substrate being the first semiconductor layer; the conduction band bottom of the second semiconductor layer is lower than that of the first semiconductor layer, and the valence band top of the second semiconductor layer is higher than that of the first semiconductor layer; the first semiconductor layer and the second semiconductor layer have bidirectional orthogonal selectivity for etching solvents; the first semiconductor layer and the second semiconductor layer corresponding to the target area are etched sequentially from the side away from the substrate to determine the target thickness of the second semiconductor layer and its target component ratio, or the second semiconductor layer and the first semiconductor layer corresponding to the target area are etched sequentially from the side away from the substrate to determine the target thickness of the second semiconductor layer and its target component ratio.
[0008] According to one embodiment of the present invention, XRD and / or PL are used to test the target component percentage of each second semiconductor layer.
[0009] According to one embodiment of the present invention, the plurality of first semiconductor layers are composed of the same multi-component compound semiconductor material system; the plurality of second semiconductor layers are composed of the same multi-component compound semiconductor material system, and the preset component proportions of the plurality of second semiconductor layers are different.
[0010] According to one embodiment of the present invention, in any two adjacent second semiconductor layers, the proportion of a target element in the second semiconductor layer closer to the substrate is less than the proportion of a target element in the second semiconductor layer farther from the substrate.
[0011] According to one embodiment of the present invention, the substrate is a gallium arsenide substrate, and the second semiconductor layer is an aluminum gallium arsenide layer; the molar ratio between aluminum, gallium and arsenic in the second semiconductor layer is X:(1-X):1, where X is greater than 0.
[0012] According to one embodiment of the present invention, when 0 < X < 0.4, the first semiconductor layer is an indium gallium phosphide layer; The target component percentage of the second semiconductor layer was measured using a PL at room temperature.
[0013] According to one embodiment of the present invention, when 0.4 < X < 0.45, the first semiconductor layer is an indium gallium phosphide layer, and the target component ratio of the second semiconductor layer is measured by measuring the lattice coefficient of the second semiconductor layer by XRD; or, when 0.4 < X < 0.45, the first semiconductor layer is an aluminum arsenide layer, and the target component ratio of the second semiconductor layer is measured by PL at room temperature.
[0014] According to one embodiment of the present invention, when 0.45 < X < 0.5, the first semiconductor layer is an indium gallium phosphide layer; The target component percentage of the second semiconductor layer can be measured by XRD to measure the lattice coefficient, or by PL to measure the target component percentage of the second semiconductor layer at a temperature below 77K.
[0015] According to one embodiment of the present invention, the substrate is an indium phosphide substrate; The first semiconductor layer is an indium gallium arsenide phosphide layer, and the second semiconductor layer is an indium gallium aluminum arsenide layer; or, the first semiconductor layer is an indium aluminum arsenide layer, and the second semiconductor layer is an indium gallium arsenide phosphide layer.
[0016] According to one embodiment of the present invention, the second semiconductor layer is located at the farthest side of the substrate. Before sequentially etching the second semiconductor layer and the first semiconductor layer in the target area from the side furthest from the substrate, the method further includes: A protective layer is grown on the second semiconductor layer located on the farthest side of the substrate.
[0017] According to one embodiment of the present invention, after growing the protective layer, the method further includes: S10, Open a window on the protective layer; S20, Use a second etching solution to etch the second semiconductor layer in the window area and determine the target thickness of the second semiconductor layer; S30, Use a first etching solution to etch the first semiconductor layer below it in the window area and measure the thickness of the first semiconductor layer; Repeat steps S20 and S30 above until the target thickness of all the second semiconductor layers to be measured is completed.
[0018] According to one embodiment of the present invention, before growing the protective layer, the method further includes: The percentage of the target component in the second semiconductor layer furthest from the substrate is measured by XRD.
[0019] According to an embodiment of the present invention, when determining the target thickness of the upper second semiconductor layer, the method further includes: The target component percentage of the second semiconductor layer is measured using PL.
[0020] According to one embodiment of the present invention, the theoretical thickness of the plurality of first semiconductor layers is the same; The theoretical thickness of the first semiconductor layer is H1, and the theoretical thickness of the second semiconductor layer is H2, where H1:H2 = 2.5-25.
[0021] According to one embodiment of the present invention, the theoretical thickness of each of the first semiconductor layers is 20-200 mm, and the theoretical thickness of the second semiconductor layer is 50-500 nm.
[0022] According to one embodiment of the present invention, a step tester is used to measure the target thickness of the first semiconductor layer and the second semiconductor layer.
[0023] Another embodiment of the present invention provides a growth equipment calibration method for calibrating parameters of a growth equipment for growing semiconductor layers, the method comprising: Using the semiconductor material detection method described in any of the above embodiments, at least the target component ratio and target thickness of each second semiconductor layer are determined; the determined target component ratio of each second semiconductor layer is compared with the preset component ratio of each second semiconductor layer, and the determined target thickness of each second semiconductor layer is compared with the theoretical thickness of each second semiconductor layer; the parameters of the growth equipment are adjusted according to the comparison results of the target component ratio, preset component ratio, target thickness and theoretical thickness of each second semiconductor layer.
[0024] The beneficial effects of this invention are as follows: The semiconductor material detection method provided by this invention grows multiple first semiconductor layers and multiple second semiconductor layers on one side of a substrate. The second semiconductor layers and the first semiconductor layers are grown alternately, with the first semiconductor layer being the layer closest to the substrate. The conduction band bottom of the second semiconductor layer is lower than that of the first semiconductor layer, and the valence band top of the second semiconductor layer is higher than that of the first semiconductor layer. Therefore, a second semiconductor layer sandwiched between two first semiconductor layers forms a double heterojunction structure. The middle second semiconductor layer acts as a potential well for electrons, while the first semiconductor layers on both sides act as potential barriers. Electrons spontaneously fall from the first semiconductor layer into the second semiconductor layer and are difficult to migrate back from the second semiconductor layer to the first semiconductor layer. This method can restrict electron migration between the substrate and the second semiconductor layer, as well as between two adjacent second semiconductor layers. The target component ratio information of the second semiconductor layer located between two first semiconductor layers can be obtained by measuring the spectrum of this layer using a PL meter, without being affected by the substrate, resulting in more accurate measurement of the target component ratio information.
[0025] Furthermore, the first and second semiconductor layers exhibit bidirectional orthogonal selectivity in their etching solvents, meaning that the etching solvents for the first and second semiconductor layers are different, allowing the first semiconductor layer to serve as a stop layer for the second semiconductor layer. Therefore, when measuring the thickness of the second semiconductor layer, different solvents can be used to etch the first and second semiconductor layers separately. A step tester can be used to directly measure the thickness of each second semiconductor layer, resulting in more accurate measurements. Moreover, the thickness of multiple second semiconductor layers can be measured sequentially in a single growth operation, eliminating the need for layer-by-layer growth and testing, making measurement more convenient and efficient. As the uppermost second semiconductor layer is relatively far from the substrate, its main peak does not overlap with the substrate's main peak during XRD testing, minimizing substrate influence; therefore, its thickness can be measured using XRD. Thus, the semiconductor material detection method provided in this application can simultaneously and accurately measure the thickness and composition information of multiple second semiconductor layers, resulting in higher testing efficiency and more accurate measurement results. Attached Figure Description
[0026] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0027] Figure 1 A flowchart of the semiconductor material detection method provided by the present invention; Figure 2 A flowchart of one step in the semiconductor material detection method provided by the present invention; Figure 3 A schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention; Figure 4 A schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention; Figure 5 A schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention; Figure 6 A schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention; Figure 7 A schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention; Figure 8 This is a schematic diagram of a semiconductor structure formed after one step of the semiconductor material detection method provided by the present invention.
[0028] Icon: 1 - Substrate; 2-First semiconductor layer; 21-First semiconductor layer; 22-Second semiconductor layer; 23-Third semiconductor layer; 24-Fourth semiconductor layer; 3-Second semiconductor layer; 31-First second semiconductor layer; 32-Second second semiconductor layer; 33-Third second semiconductor layer; 34-Fourth second semiconductor layer; 4-Protective layer; 5-Window. Detailed Implementation
[0029] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Unless otherwise specified, the embodiments and features described in these embodiments can be combined with each other. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0030] One embodiment of the present invention provides a method for detecting semiconductor materials, such as... Figure 1 As shown, the method includes setting a substrate 1; Multiple first semiconductor layers 2 and multiple second semiconductor layers 3 are grown on one side of the substrate 1, with the second semiconductor layers 3 and the first semiconductor layers 2 growing alternately in sequence, and the layer closest to the substrate 1 being the first semiconductor layer 2; the conduction band bottom of the second semiconductor layer 3 is lower than that of the first semiconductor layer 2, and the valence band top of the second semiconductor layer 3 is higher than that of the first semiconductor layer 2; the first semiconductor layer 2 and the second semiconductor layer 3 have bidirectional orthogonal selectivity for etching solvents; the first semiconductor layer 2 and the second semiconductor layer 3 corresponding to the target area are etched sequentially from the side away from the substrate 1 to determine the target thickness of the second semiconductor layer 3 and its target component ratio, or the second semiconductor layer 3 and the first semiconductor layer 2 corresponding to the target area are etched sequentially from the side away from the substrate 1 to determine the target thickness of the second semiconductor layer 3 and its target component ratio.
[0031] In existing technologies, XRD (X-ray diffraction) is used to simultaneously measure the thickness and composition of the second semiconductor layer 3. Specifically, the second semiconductor layer 3 is grown directly on the substrate 1. Therefore, electron migration occurs between the substrate 1 and the second semiconductor layer 3, making it impossible to accurately obtain the composition information of the second semiconductor layer 3 by measuring its spectrum. Furthermore, the close proximity of the second semiconductor layer 3 to the substrate 1 means that if the second semiconductor layer 3 is too thin, the main peak will be indistinct, resulting in a large error in the composition information; conversely, if the second semiconductor layer 3 is too thick, the interference fringes will be indistinct, leading to a large error in the thickness information. Therefore, it is impossible to simultaneously and accurately measure both composition and thickness information.
[0032] The semiconductor material detection method provided by this invention involves growing multiple layers of first semiconductor layer 2 and multiple layers of second semiconductor layer 3 on one side of a substrate 1. The second semiconductor layer 3 and the first semiconductor layer 2 are grown alternately in sequence, with the layer closest to the substrate 1 being the first semiconductor layer 2. The conduction band bottom of the second semiconductor layer 3 is lower than that of the first semiconductor layer 2, and the valence band top of the second semiconductor layer 3 is higher than that of the first semiconductor layer 2. Therefore, a second semiconductor layer 3 sandwiched between two first semiconductor layers 2 forms a double heterojunction structure. The second semiconductor layer 3 in the middle is a potential well for electrons, while the first semiconductor layers 2 on both sides are potential barriers. Electrons will spontaneously fall from the first semiconductor layer 2 into the second semiconductor layer 3 and are difficult to migrate back from the second semiconductor layer 3 to the first semiconductor layer 2. The first semiconductor layer 2 can restrict the outward migration of electrons in the second semiconductor layer 3. Therefore, the second semiconductor layer 3 located between the two first semiconductor layers 2 can obtain the target component ratio information of the layer by measuring the spectrum of the layer with a PL (photoluminescence) tester, without being affected by the substrate 1, and the target component ratio information measurement is more accurate.
[0033] Furthermore, in the semiconductor material testing method provided in this application, the first semiconductor layer 2 and the second semiconductor layer 3 possess bidirectional orthogonal selectivity for the etching solvents, meaning that the etching solvents for the first semiconductor layer 2 and the second semiconductor layer 3 are different, and the first semiconductor layer 2 can serve as a stop layer for the second semiconductor layer 3. Therefore, when measuring the thickness of the second semiconductor layer 3, different solvents can be used to etch the first semiconductor layer 2 and the second semiconductor layer 3 respectively, and a step tester can be used to directly measure the thickness of each layer of the second semiconductor layer 3, resulting in more accurate measurement results. Moreover, the thickness of multiple second semiconductor layers 3 can be measured sequentially through a single growth process, eliminating the need for layer-by-layer growth and testing fitting, making the measurement more convenient and efficient. Since the uppermost second semiconductor layer 3 is relatively far from the substrate 1, its main peak will not overlap with the main peak of the substrate 1 during XRD testing, and it is less affected by the substrate 1, allowing for XRD measurement of its thickness. Therefore, the semiconductor material testing method provided in this application can simultaneously and accurately measure the thickness and composition information of multiple layers of second semiconductor layers 3, resulting in higher testing efficiency and more accurate measurement results.
[0034] The semiconductor material testing method provided in this application can use XRD to test the target component ratio of each layer of the second semiconductor layer 3, or use PL to test the target component ratio of each layer of the second semiconductor layer 3, or use both XRD and PL to test the target component ratio of the second semiconductor layer 3 simultaneously. For example, a portion of the second semiconductor layer 3 can be measured using XRD to measure its target component ratio, while another portion of the second semiconductor layer 3 can be measured using PL to measure its target component ratio.
[0035] In this application, the first semiconductor layer 2 is composed of a multi-component compound semiconductor material system. Multiple layers of the first semiconductor layer 2 can be composed of the same multi-component compound semiconductor material system. For example, each layer of the first semiconductor layer 2 may be an indium gallium phosphide layer, an aluminum arsenide layer, or an indium gallium arsenide phosphide layer, etc. The molar percentages of each element in each layer of the first semiconductor layer 2 are also identical, meaning that each layer of the first semiconductor layer 2 has the same composition and the same component percentages. In some embodiments, the composition of multiple first semiconductor layers 2 is different. For example, the topmost first semiconductor layer 2 may be an aluminum arsenide layer, while the remaining first semiconductor layers 2 may be indium gallium phosphide layers.
[0036] In this application, multiple second semiconductor layers 3 are composed of the same multi-component compound semiconductor material system, and the preset component ratios of multiple second semiconductor layers 3 are different. That is, all second semiconductor layers 3 have the same component composition, but the preset component ratios are different.
[0037] In the above embodiments of this application, the target component ratio of the second semiconductor layer 3 represents the actual molar ratio of the target element in the entire elemental composition of the second semiconductor layer 3. For example, if the second semiconductor layer 3 is an aluminum-gallium-arsenic layer and the target element is "aluminum," then the target component ratio is the actual molar ratio between "aluminum," "arsenic," and "gallium" in the second semiconductor layer 3. The preset component ratio refers to the preset molar ratio of the target element in each layer of the second semiconductor layer 3 in the entire elemental composition. For example, if the second semiconductor layer 3 is an aluminum-gallium-arsenic layer, the preset molar ratio of aluminum, gallium, and arsenic in the second semiconductor layer 3 closest to the substrate 1 is 0.4:0.6:1, while the molar ratio of aluminum, gallium, and arsenic in the layer above it is 0.41:0.59:1, and so on. Each layer of the second semiconductor layer 3 has the same elemental composition, but the preset component ratio is different.
[0038] In this application, the predetermined proportion of the target element in the second semiconductor layer 3 closer to the substrate 1 is less than the predetermined proportion of the target element in the second semiconductor layer 3 farther from the substrate 1 in any two adjacent layers. That is, the predetermined proportion of the target element in the second semiconductor layer 3 gradually increases from the side closer to the substrate 1 to the side farther from the substrate 1.
[0039] According to one embodiment of this application, such as Figures 3 to 8 As shown, the substrate 1 is a gallium arsenide substrate 1, and the second semiconductor layer 3 is an aluminum gallium arsenide layer; the molar ratio of aluminum, gallium, and arsenic in the second semiconductor layer 3 is X:(1-X):1, where X is greater than 0. The value of X gradually increases from the side closer to the substrate 1 to the side farther away from the substrate 1; as... Figures 2 to 8 As shown, the second semiconductor layer 3 near the substrate 1 is the first second semiconductor layer 31. From the direction away from the substrate 1 to the direction closer to the substrate 1, the second semiconductor layers 3 are successively the first second semiconductor layer 31, the second second semiconductor layer 32, the third second semiconductor layer 33 and the fourth second semiconductor layer 34, and so on. Therefore, X is 0.38 in the first second semiconductor layer 31, X is 0.35 in the second second semiconductor layer 32, and X is 0.30 in the third second semiconductor layer 33.
[0040] In this embodiment, when 0 < X < 0.4, the first semiconductor layer 2 is an indium gallium phosphide layer; the target component ratio of the second semiconductor layer 3 is measured by PL at room temperature. In this embodiment, the molar ratio of indium, gallium, and phosphorus elements in the first semiconductor layer 2 is K: (1 - K): 1, where 0.48 < K < 0.50, and its bandgap width is greater than that of aluminum gallium arsenide when X < 0.4. Therefore, the specific value of X can be calculated by converting the aluminum gallium arsenide fluorescence spectrum through PL testing at room temperature, and the proportion of aluminum element in aluminum gallium arsenide can be quickly calculated to obtain the accurate component ratio of aluminum gallium arsenide.
[0041] In this embodiment, when 0.4 < X < 0.45, the first semiconductor layer 2 is an indium gallium phosphide layer. Since the second semiconductor layer 3 with 0.4 < X < 0.45 is far from the substrate 1, the lattice coefficient of the second semiconductor layer 3 is measured by XRD to measure the target component ratio of this layer, so as to obtain the accurate value of aluminum element X in each second semiconductor layer 3, that is, the accurate molar ratio between aluminum, gallium, and arsenic elements in aluminum gallium arsenide can be obtained.
[0042] Optionally, when 0.4 < X < 0.45, the first semiconductor layer 2 is an aluminum arsenide layer. Since the bandgap width of aluminum gallium arsenide is greater than that of indium gallium phosphide when 0.4 < X < 0.45, it is impossible to measure the accurate target component ratio of aluminum gallium arsenide by PL. Therefore, in this embodiment, when 0.4 < X < 0.45, the first semiconductor layer 2 adopts an aluminum arsenide layer, and the bandgap width of the aluminum arsenide layer is greater than that of the aluminum gallium arsenide layer when 0.4 < X < 0.45. At this time, the specific value of X can be calculated by converting the aluminum gallium arsenide fluorescence spectrum through PL testing at room temperature, and the proportion of aluminum element in aluminum gallium arsenide can be quickly calculated to obtain the accurate component ratio of aluminum gallium arsenide.
[0043] In another embodiment of the present application, when 0.45 < X < 0.5, the first semiconductor layer 2 is an indium gallium phosphide layer. When 0.45 < X < 0.5, aluminum gallium arsenide becomes an indirect bandgap semiconductor. At this time, the diffraction peak of aluminum gallium arsenide in the XRD test has moved away from the substrate 1 peak, and the component X of aluminum gallium arsenide can be obtained through the XRD test, that is, the lattice coefficient of the second semiconductor layer 3 can be measured by XRD to measure the target component ratio of this layer.
[0044] Of course, in this embodiment, when 0.45 < X < 0.5, the target component ratio of the second semiconductor layer 3 can be measured by PL in an environment where the temperature is less than 77K, and then converted into the specific value of X at room temperature.
[0045] According to an embodiment of the present application, as Figures 3 to 8As shown, the second semiconductor layer 3 is located at the farthest side of the substrate 1. Before etching the second semiconductor layer 3 and the first semiconductor layer 2 sequentially within the target area from the side furthest from the substrate 1, a protective layer 4 is provided on the uppermost second semiconductor layer 3 to prevent damage to the second semiconductor layer 3 in other areas when etching the second semiconductor layer 3 within the target area. Optionally, the protective layer 4 in this application is a silicon dioxide layer. In this embodiment, the target area can be located in the middle of the second semiconductor layer 3 or on the left and right edges of the second semiconductor layer 3.
[0046] According to one embodiment of this application, after growing the protective layer 4, the semiconductor material detection method further includes: S10, open window 5 on protective layer 4; the area corresponding to window 5 is the target area; S20, the second semiconductor layer 3 is etched in the area corresponding to window 5 using the second etching solution, and the thickness of the second semiconductor layer 3 is determined. In step S30, the first semiconductor layer 2 below the window 5 is etched using the first etching solution, and the thickness of the first semiconductor layer 2 is measured. Steps S20 and S30 are repeated until the target thickness of all the second semiconductor layers 3 to be measured is completed. The second semiconductor layer 3 farthest from the substrate 1 is obtained by direct measurement using a profilometer, and the specific thickness of the multiple layers of second semiconductor layers 3 below it can be obtained by calculation.
[0047] like Figure 4 and Figure 5 As shown, after opening a window 5 on the protective layer 4, the thickness of the protective layer 4 is measured as d1 using a step tester. Then, the second semiconductor layer 3 below the protective layer 4 is etched using a second etching solution. The total thickness d2 of the protective layer 4 and the second semiconductor layer 3 is then measured using a step tester. Therefore, the thickness z1 of the uppermost second semiconductor layer 3 is z1 = d2 - d1. Next, the first semiconductor layer 2 below the uppermost second semiconductor layer 3 is etched in the area corresponding to window 5, and the total thickness d3 of the protective layer 4, the second semiconductor layer 3, and the first semiconductor layer 2 is measured using a step tester. Therefore, the thickness h1 of the uppermost first semiconductor layer 2 is h1 = d3 - d2. The second semiconductor layer 3 below the uppermost first semiconductor layer 2 is etched using a second etching solution, and the total thickness d4 is measured using a step tester. Therefore, the thickness z2 of the second semiconductor layer 32 is z2 = d4 - d3. The above steps are repeated until the target thickness measurement of all second semiconductor layers 3 is completed. Wherein, as... Figures 5 to 8As shown, in this embodiment, the edges of the second semiconductor layer 3 and the first semiconductor layer 2 etched in the area corresponding to window 5 from top to bottom coincide. That is, the edges of the second semiconductor layer 3 and the first semiconductor layer 2 are flush after being etched by the corresponding etching solution. Therefore, the total thickness after etching can be measured by a step meter, and the thickness information of each second semiconductor layer 3 and the first semiconductor layer 2 can be obtained by calculation.
[0048] It is understood that in this embodiment, when S20 and S30 use the corresponding etching solution to etch the semiconductor layer in window 5, the process further includes: using the corresponding etching solution to etch the corresponding semiconductor layer to form an etching window. According to the growth method of the semiconductor layer, the projection of the etching window of the semiconductor layer on the side away from the substrate 1 in any two adjacent semiconductor layers on the plane of the substrate 1 is greater than the projection of the etching window of the semiconductor layer on the side closer to the substrate 1 on the plane of the substrate 1. That is, after the protective layer 4, the second semiconductor layer 3, and the first semiconductor layer 2 are etched sequentially from top to bottom, they are in a stepped shape. At this time, the target thickness information of each second semiconductor layer 3 and the first semiconductor layer 2 can be directly measured by a step meter.
[0049] According to one embodiment of this application, before growing the protective layer 4, the target component percentage of the second semiconductor layer 3 furthest from the substrate 1 is measured by XRD. At this time, the diffraction peak of the second semiconductor layer 3 furthest from the substrate 1 is far away from the substrate peak, and the component X value of the second semiconductor layer 3 can be obtained by XRD testing. Specifically, when determining the thickness of the previous second semiconductor layer 3, the target component percentage of the next second semiconductor layer 3 is measured by PL.
[0050] According to one embodiment of the present invention, the theoretical thickness of the plurality of first semiconductor layers 2 is the same; the theoretical thickness of the first semiconductor layer 2 is H1, and the theoretical thickness of the second semiconductor layer 3 is H2, H1:H2=2.5-25; optionally, in this embodiment, the theoretical thickness of each first semiconductor layer 2 is 20-200mm, and the theoretical thickness of the second semiconductor layer 3 is 50-500nm.
[0051] The following example, using a gallium arsenide substrate 1 and an aluminum gallium arsenide layer 3 as an example, illustrates the specific process of the semiconductor material detection method provided by this invention.
[0052] Select gallium arsenide substrate 1 and fix it.
[0053] like Figure 3As shown, four first semiconductor layers 2 and four second semiconductor layers 3 are sequentially grown on one side of a gallium arsenide substrate 1. The second semiconductor layer 3 is located on the side furthest from the substrate 1. The first semiconductor layer 2 is indium gallium phosphide, and the second semiconductor layer 3 is aluminum gallium arsenide. The thickness of the first semiconductor layer 2 is 20 nm, and the thickness of the second semiconductor layer 3 is 50 nm. The four second semiconductor layers 3, from top to bottom, are: a first second semiconductor layer 31, a second second semiconductor layer 32, a third second semiconductor layer 33, and a fourth second semiconductor layer 34. Similarly, the four first semiconductor layers 2, from top to bottom, are: a first first semiconductor layer 21, a second first semiconductor layer 22, a third first semiconductor layer 23, and a fourth first semiconductor layer 24. The fourth first semiconductor layer 24 is grown on the substrate 1.
[0054] In each second semiconductor layer 3, the molar ratio of aluminum, gallium, and arsenic is X:(1-X):1, where X is greater than 0.4 in the first second semiconductor layer 31, and less than 0.4 in the second, third, and fourth second semiconductor layers 32, 33, and 34. Optionally, in this embodiment, X is equal to 0.46 in the first second semiconductor layer 31, 0.38 in the second second semiconductor layer 32, 0.35 in the third second semiconductor layer 33, and 0.3 in the fourth second semiconductor layer 34.
[0055] First, the target component ratio of the first and second semiconductor layers 31 is measured by XRD, that is, the actual value of X in the first and second semiconductor layers 31 is measured by XRD.
[0056] Optionally, in this step, if the range of the first second semiconductor layer 31 is greater than 0.4 and less than 0.45, for example, X equals 0.44, then the topmost layer is the first semiconductor layer 2. In this case, there are five first semiconductor layers 2 and four second semiconductor layers 3. Along the top-to-bottom direction, the composition of the first first semiconductor layer 21 and the second first semiconductor layer 22 is aluminum arsenic. In this case, the target composition ratio of the first second semiconductor layer 31 can be tested using PL. When X is greater than 0.45, only the composition ratio of the first second semiconductor layer 31 is tested using XRD.
[0057] After measuring the target component ratio of the first and second semiconductor layers 31 by XRD, such as Figure 4As shown, a protective layer 4 is deposited on the upper side of the first semiconductor layer 31. Specifically, SiO2 (silicon dioxide) is deposited by PECVD (plasma-enhanced chemical vapor deposition) as the protective layer 4, which protects the first semiconductor layer 2 and the second semiconductor layer 3. In this embodiment, the protective layer 4 can also be a silicon nitride layer.
[0058] After growing the protective layer 4, a window 5 is opened on the protective layer 4, such as... Figure 5 As shown, a window 5 is opened in the middle of the protective layer 4. The area corresponding to window 5 is the target area. The thickness information d1 of the protective layer 4 is measured using a profilometer. Figure 6 As shown, the first layer of the second semiconductor layer 31 is etched in the area corresponding to window 5 using the second etching solution, and the total thickness d2 of the protective layer 4 and the first layer of the second semiconductor layer 31 is measured using a step meter. Then the thickness z1 of the first layer of the second semiconductor layer 31 is z1 = d2 - d1.
[0059] like Figure 7 As shown, the first semiconductor layer 21 in the region corresponding to window 5 is etched with the first etching solution, and the total thickness d3 of the protective layer 4, the first second semiconductor layer 31 and the first semiconductor layer 21 is measured by a step meter. Then the thickness h1 of the first semiconductor layer 21 is h1 = d3 - d2. At the same time, when measuring the first second semiconductor layer 31, the target component ratio of the second semiconductor layer 32 is measured by PL.
[0060] like Figure 8 As shown, the second semiconductor layer 32 is then etched with a second etching solution, and the total thickness d4 of the protective layer 4, the first semiconductor layer 31, the first semiconductor layer 21, and the second semiconductor layer 32 is measured using a profilometer. The thickness z2 of the second semiconductor layer 32 is then calculated as z2 = d4 - d3. Simultaneously, the target component percentage of the third semiconductor layer 33 is measured using a PL (Profilometer Lens). The above steps are repeated until the thickness and target component percentage measurements of the third semiconductor layer 33 and the fourth semiconductor layer 34 are completed.
[0061] In the above embodiments of this application, when the substrate 1 is a gallium arsenide substrate, the first semiconductor layer 2 is an indium gallium phosphide layer, and the second semiconductor layer 3 is an aluminum gallium arsenide layer, the first etching solution is a mixed solution of hydrochloric acid and phosphoric acid, and the second etching solution is a mixed solution of hydrogen peroxide and hydrochloric acid.
[0062] It should be noted that the components of the substrate 1, the first semiconductor layer 2 and the second semiconductor layer 3 described in this application are not limited to the above-described configuration.
[0063] According to another embodiment of this application, the substrate 1 is an indium phosphide substrate, the first semiconductor layer 2 is an indium gallium arsenide phosphide layer, and the second semiconductor layer 3 is an indium gallium aluminum arsenide layer, or the first semiconductor layer 2 is an indium aluminum arsenide layer and the second semiconductor layer 3 is an indium gallium arsenide phosphide layer. In this embodiment, the first etching solution is a mixed solution of hydrochloric acid and hydrogen peroxide, and the second etching solution is a mixed solution of hydrochloric acid and sulfuric acid.
[0064] Another embodiment of this application also provides a growth equipment calibration method for calibrating parameters of a growth equipment for growing semiconductor layers, the method comprising: Using the semiconductor material detection method described in any of the above embodiments, at least the target component ratio and target thickness of each second semiconductor layer 3 are determined; the determined target component ratio of each second semiconductor layer 3 is compared with the preset component ratio of each second semiconductor layer 3, and the determined target thickness of each second semiconductor layer 3 is compared with the theoretical thickness of each second semiconductor layer 3; the parameters of the growth equipment are adjusted according to the comparison results of the target component ratio, preset component ratio, target thickness and theoretical thickness of each second semiconductor layer 3.
[0065] The growth equipment calibration method provided in this application is used in the semiconductor material detection method provided in the above embodiments. Therefore, it can detect the target component ratio and target thickness of multiple second semiconductor layers 3 at one time. Compared with the existing schemes that use XRD to detect the target thickness and target component ratio, since the etching solutions of the first semiconductor layer 2 and the second semiconductor layer 3 are different, the first semiconductor layer 2 can be used as the stop layer of the second semiconductor layer 3. Therefore, the thickness of each second semiconductor layer 3 can be measured by a step meter, which is simpler and more accurate.
[0066] The conduction band bottom of the second semiconductor layer 3 is lower than that of the first semiconductor layer 2, and the valence band top of the second semiconductor layer 3 is higher than that of the first semiconductor layer 2. A second semiconductor layer 3 sandwiched between the two first semiconductor layers 2 forms a double heterojunction structure. The middle second semiconductor layer 3 acts as an electron potential well, while the two first semiconductor layers 2 on either side act as potential barriers. Electrons spontaneously fall from the first semiconductor layer 2 into the second semiconductor layer 3 and are difficult to migrate back from the second semiconductor layer 3 to the first semiconductor layer 2. This effectively restricts electron migration between the substrate 1 and the second semiconductor layer 3, as well as between two adjacent second semiconductor layers 3. The second semiconductor layer 3 located between the two first semiconductor layers 2 can have its target component ratio information obtained by measuring its spectrum using a PL meter, without being affected by the substrate 1, resulting in more accurate measurement of the target component ratio information.
[0067] It should be understood that the growth equipment calibration method provided in this application is also applicable to calibrating the parameters of the growth equipment for growing the first semiconductor layer 2; in practical application scenarios, there are also cases where the first semiconductor layer 2 and the second semiconductor layer 3 are grown based on the same growth equipment, in which case the growth equipment calibration method provided in this application is also applicable.
[0068] In the description of this invention, it should be noted that the terms "upper" and "lower," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0069] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for detecting semiconductor materials, characterized in that, include: Set up a substrate (1); Multiple first semiconductor layers (2) and multiple second semiconductor layers (3) are grown on one side of the substrate (1). The second semiconductor layers (3) and the first semiconductor layers (2) are grown alternately in sequence, with the first semiconductor layer (2) being the layer closest to the substrate (1). The conduction band bottom of the second semiconductor layer (3) is lower than that of the first semiconductor layer (2), and the valence band top of the second semiconductor layer (3) is higher than that of the first semiconductor layer (2). The first semiconductor layer (2) and the second semiconductor layer (3) have bidirectional orthogonal selectivity for etching solvents. The target thickness and target component ratio of the second semiconductor layer (3) are determined by sequentially etching the first semiconductor layer (2) and the second semiconductor layer (3) corresponding to the target area from the side away from the substrate (1), or by sequentially etching the second semiconductor layer (3) and the first semiconductor layer (2) corresponding to the target area from the side away from the substrate (1).
2. The semiconductor material detection method according to claim 1, characterized in that, The target component percentage of each second semiconductor layer (3) is tested using XRD and / or PL.
3. The semiconductor material detection method according to claim 2, characterized in that, Multiple first semiconductor layers (2) are composed of the same multi-component compound semiconductor material system; Multiple second semiconductor layers (3) are composed of the same multi-component compound semiconductor material system, and the preset component ratios of the multiple second semiconductor layers (3) are different.
4. The semiconductor material detection method according to claim 3, characterized in that, In any two adjacent second semiconductor layers (3), the proportion of the target element in the second semiconductor layer (3) closer to the substrate (1) is less than the proportion of the target element in the second semiconductor layer (3) farther from the substrate (1).
5. The semiconductor material detection method according to claim 4, characterized in that, The substrate (1) is a gallium arsenide substrate, and the second semiconductor layer (3) is an aluminum gallium arsenide layer; The molar ratio of aluminum, gallium and arsenic in the second semiconductor layer (3) is X:(1-X):1, where X is greater than 0.
6. The semiconductor material detection method according to claim 5, characterized in that, When 0 < X < 0.4, the first semiconductor layer (2) is an indium gallium phosphide layer; The target component percentage of the second semiconductor layer (3) was measured using PL at room temperature.
7. The semiconductor material detection method according to claim 5, characterized in that, When 0.4 < X < 0.45, the first semiconductor layer (2) is an indium gallium phosphide layer, and the target component ratio of the second semiconductor layer (3) is measured by XRD to measure the lattice coefficient of the second semiconductor layer (3). Alternatively, when 0.4 < X < 0.45, the first semiconductor layer (2) is an aluminum arsenic layer, and the target component ratio of the second semiconductor layer (3) is measured using PL at room temperature.
8. The semiconductor material detection method according to claim 5, characterized in that, When 0.45 < X < 0.5, the first semiconductor layer (2) is an indium gallium phosphide layer; The target component percentage of the second semiconductor layer (3) can be measured by XRD, or by PL at a temperature less than 77K.
9. The semiconductor material detection method according to claim 1, characterized in that, The substrate (1) is an indium phosphide substrate; The first semiconductor layer (2) is an indium gallium arsenide phosphide layer, and the second semiconductor layer (3) is an indium gallium aluminum arsenide layer; Alternatively, the first semiconductor layer (2) is an indium aluminum arsenide layer, and the second semiconductor layer (3) is an indium gallium arsenide phosphide layer.
10. The semiconductor material detection method according to claim 1, characterized in that, The second semiconductor layer (3) is located on the farthest side of the substrate (1). Before etching the second semiconductor layer (3) and the first semiconductor layer (2) in the target area sequentially from the side away from the substrate (1), the method further includes: A protective layer (4) is grown on the second semiconductor layer (3) located on the farthest side of the substrate (1).
11. The semiconductor material detection method according to claim 10, characterized in that, After growing the protective layer (4), the method further includes: S10, open a window (5) on the protective layer (4); S20, the second semiconductor layer (3) is etched in the window (5) area using a second etching solution, and the target thickness of the second semiconductor layer (3) is determined; S30, the first semiconductor layer (2) below the window (5) is etched using the first etching solution, and the thickness of the first semiconductor layer (2) is measured; S40, repeat steps S20 and S30 above until the target thickness of all the second semiconductor layers (3) to be measured is completed.
12. The semiconductor material detection method according to claim 10, characterized in that, Before the growth protective layer (4), the method further includes: The target component percentage of the second semiconductor layer (3) furthest from the substrate (1) is measured by XRD.
13. The semiconductor material detection method according to any one of claims 1 to 12, characterized in that, When determining the target thickness of the upper second semiconductor layer (3), the method further includes: The target component percentage of the next layer, the second semiconductor layer (3), is measured by PL.
14. The semiconductor material detection method according to any one of claims 1 to 12, characterized in that, The theoretical thickness of the multiple first semiconductor layers (2) is the same; The theoretical thickness of the first semiconductor layer (2) is H1, and the theoretical thickness of the second semiconductor layer (3) is H2, where H1:H2 = 2.5-25.
15. The semiconductor material detection method according to claim 14, characterized in that, The theoretical thickness of each of the first semiconductor layers (2) is 20-200 mm, and the theoretical thickness of the second semiconductor layer (3) is 50-500 nm.
16. The semiconductor material detection method according to any one of claims 1 to 12, characterized in that, The target thickness of the first semiconductor layer (2) and the second semiconductor layer (3) was measured using a step tester.
17. A method for calibrating a growth device, characterized in that, The method for calibrating parameters of a growth apparatus for growing semiconductor layers includes: Using the semiconductor material detection method as described in any one of claims 1 to 16, at least the target component percentage and target thickness of each second semiconductor layer (3) are determined; The target component ratio of each second semiconductor layer (3) is determined and compared with the preset component ratio of each second semiconductor layer (3). The target thickness of each second semiconductor layer (3) is determined and compared with the theoretical thickness of each second semiconductor layer (3). The parameters of the growth apparatus are adjusted based on the comparison results of the target component ratio and preset component ratio, target thickness and theoretical thickness of each second semiconductor layer (3).