Chip manufacturing method

Abstract

To provide a chip manufacturing method capable of manufacturing chips by dividing a wafer without developing undercuts.SOLUTION: After a damaged portion near the side and bottom surfaces of a groove formed in a groove forming step is removed in the first plasma etching step, the side surface of the groove is covered with a second protective film formed in the second coating step. Thereby, in a dividing step in which a wafer is subjected to plasma etching, undercuts that proceed from the side surface of the groove can be suppressed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a method for manufacturing chips by dividing a wafer on which a plurality of devices are formed along the boundaries of the plurality of devices.

Background Art

[0002] Chips of devices such as ICs (Integrated Circuits) are essential components in various electronic devices such as mobile phones and personal computers. Such chips are manufactured, for example, by dividing a wafer on which a plurality of devices are formed along the boundaries of the plurality of devices.

[0003] As a method for dividing such a wafer, it has been proposed to perform plasma etching on the wafer after providing a mask so that the boundary is exposed (see, for example, Patent Document 1). This mask is formed, for example, by covering the entire surface of the wafer with a water-soluble protective film and then irradiating the wafer with a laser beam along the boundary to remove a part of the protective film.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the mask is formed as described above, grooves are also formed on the surface of the wafer, and the portions near the side surfaces and bottom surfaces of these grooves are damaged. Therefore, when plasma etching is performed on the wafer so as to divide the wafer along the boundaries of the plurality of devices, etching (undercut) may proceed in a direction parallel to the surface of the wafer from the damaged portions near the side surfaces and bottom surfaces of the grooves.

[0006] Furthermore, as undercutting progresses, a portion of the mask formed on the wafer surface may be removed, potentially making it difficult to protect the devices formed on the wafer. In view of this, an object of the present invention is to provide a chip manufacturing method that allows for the division of a wafer and the production of chips without causing undercutting to progress. [Means for solving the problem]

[0007] According to one aspect of the present invention, a method for manufacturing a chip by dividing a wafer on which a plurality of devices are formed along the boundaries of the plurality of devices, comprising: a first coating step of covering the surface of the wafer with a first water-soluble protective film; a groove forming step, after the first coating step, irradiating the wafer with a laser beam of a wavelength absorbed by the wafer through the first protective film so that the region of the first protective film overlapping the boundaries and the region on the surface side of the wafer are removed and grooves are formed in the wafer; and after the groove forming step, with the grooves exposed, the wafer is removed from the surface side of the wafer. A first plasma etching step of performing isotropic plasma etching on the groove; a second coating step after the first plasma etching step of covering the sides and bottom of the groove with a second protective film; a second plasma etching step after the second coating step of performing anisotropic plasma etching on the wafer from the surface side of the wafer so as to expose the bottom of the groove; a third plasma etching step of performing isotropic plasma etching on the wafer from the surface side of the wafer; and covering the sides and bottom of the groove with a third protective film thinner than the second protective film. It is carried out over a predetermined period of time. A method for manufacturing a chip is provided, comprising a third coating step and a splitting step, which is repeated sequentially until the wafer is split along the boundary.

[0008] According to another aspect of the present invention, a method for manufacturing a chip is provided, which involves dividing a wafer on which a plurality of devices are formed along the boundaries of the plurality of devices, comprising: a first coating step of covering the surface of the wafer with a first water-soluble protective film; a groove-forming step, after the first coating step, of irradiating the wafer with a laser beam of a wavelength absorbed by the wafer through the first protective film so that a region of the first protective film overlapping the boundaries and a region of the wafer on the surface side of the wafer are removed and a groove is formed in the wafer; a first plasma etching step, after the groove-forming step, of performing isotropic plasma etching on the wafer from the surface side of the wafer with the grooves exposed; a second coating step, after the first plasma etching step, of covering the sides and bottom of the grooves with a second protective film; and a division step, after the second coating step, of performing anisotropic plasma etching on the wafer from the surface side of the wafer until the wafer is divided along the boundaries.

[0009] Furthermore, in another aspect of the present invention, a second plasma etching step is further provided, after the second coating step and before the splitting step, in which anisotropic plasma etching is performed on the wafer from the surface side of the wafer to expose the bottom surface of the groove, wherein the conditions for anisotropic plasma etching are preferably different between the second plasma etching step and the splitting step.

[0010] Furthermore, in the present invention, it is preferable that the wafer has a substrate and an insulating layer provided between the substrate and the plurality of devices.

[0011] Furthermore, in the present invention, it is preferable that the second protective film has insulating properties.

[0012] Furthermore, in the present invention, it is preferable that the second protective film contains fluorinated carbon.

[0013] Furthermore, in the present invention, it is preferable that the thickness of the second protective film is 20 nm or more. [Effects of the Invention]

[0014] In this invention, after removing damaged portions near the sides and bottom of the grooves formed in the groove formation step in the first plasma etching step, the sides of the grooves are covered with a second protective film formed in the second coating step. This makes it possible to suppress undercuts progressing from the sides of the grooves during the splitting step in which plasma etching is performed on the wafer. [Brief explanation of the drawing]

[0015] [Figure 1] Figure 1(A) is a schematic perspective view showing an example of a frame unit including a wafer, and Figure 1(B) is a schematic cross-sectional view showing a cross-section of the frame unit shown. [Figure 2] Figure 2 is a schematic flowchart illustrating an example of a chip manufacturing method in which a wafer is divided along the boundaries of multiple devices to produce chips. [Figure 3] Figure 3(A) is a schematic cross-sectional view showing the first coating step, and Figure 3(B) is a schematic partially enlarged cross-sectional view showing the wafer after the first coating step. [Figure 4] Figure 4(A) is a schematic cross-sectional view showing the groove formation step, and Figure 4(B) is a schematic enlarged cross-sectional view showing the wafer after the groove formation step. [Figure 5] Figure 5 is a schematic diagram showing an example of a plasma generation device. [Figure 6] Figure 6(A) is a schematic partially enlarged cross-sectional view showing the wafer after the first plasma etching step, and Figure 6(B) is a schematic partially enlarged cross-sectional view showing the wafer after the second coating step. [Figure 7] Figure 7 is a flowchart that schematically shows a specific example of the division steps. [Figure 8]FIG. 8 is a partially enlarged cross-sectional view schematically showing a wafer after the dividing step.

DETAILED DESCRIPTION OF THE INVENTION

[0016] Embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1(A) is a perspective view schematically showing an example of a frame unit including a wafer, and FIG. 1(B) is a cross-sectional view schematically showing a cross-section of the frame unit shown in FIG. 1(A). The frame unit 11 shown in FIGS. 1(A) and 1(B) includes a wafer 13 used for manufacturing chips.

[0017] This wafer 13 has a substrate 15 made of, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). An insulating layer 17 made of, for example, silicon oxide (SiO2) or silicon nitride (Si3N4) is provided on the surface of this substrate 15.

[0018] Furthermore, a plurality of independent devices 19 are provided on the front surface side of the wafer 13. The plurality of devices 19 are arranged in a matrix on the surface of the insulating layer 17. That is, the boundaries of the plurality of devices 19 extend in a grid pattern.

[0019] Also, a central region of a disk-shaped tape 21 having a diameter longer than that of the substrate 15 is adhered to the back surface of the wafer 13, that is, the back surface of the substrate 15. This tape 21 has, for example, a flexible film-like base material layer and an adhesive layer (paste layer) provided on one surface (the surface on the substrate 15 side) of the base material layer.

[0020] Specifically, this base material layer is made of polyolefin (PO), polypropylene (PP), polyethylene terephthalate (PET), polyvinyl chloride (PVC), or polystyrene (PS). Also, this adhesive layer is made of an ultraviolet curable silicone rubber, an acrylic material, or an epoxy material.

[0021] Furthermore, an annular frame 23 is attached to the outer periphery of the tape 21, with a circular opening 23a having a diameter longer than that of the wafer 13. This frame 23 is made of a metallic material such as aluminum (Al).

[0022] Figure 2 is a schematic flowchart illustrating an example of a chip manufacturing method in which a wafer 13 is divided along the boundaries of multiple devices 19 to produce chips. In this method, first, the surface of the wafer 13 is covered with a water-soluble protective film (first protective film) (first coating step: S1).

[0023] Figure 3(A) is a schematic side view showing the first coating step (S1), and Figure 3(B) is a schematic partially enlarged cross-sectional view showing the wafer 13 after the first coating step (S1). This first coating step (S1) is carried out, for example, using the coating apparatus 2 shown in Figure 3(A). This coating apparatus 2 has a holding table 4.

[0024] The holding table 4 has a disc-shaped frame 6 made of ceramics or the like. This frame 6 has a disc-shaped bottom wall 6a and cylindrical side walls 6b that rise from the outer edge of the bottom wall 6a. That is, a disc-shaped recess is formed on the upper surface of the frame 6, defined by the bottom wall 6a and the side walls 6b.

[0025] A disc-shaped porous plate 8, having a diameter approximately equal to the diameter of the recess formed on the upper surface of the frame 6, is fixed to the recess. This porous plate 8 is made of, for example, porous ceramics. When the frame unit 11 is brought into the coating apparatus 2, the wafer 13 is placed on the upper surface of the holding table 4 via the tape 21.

[0026] Furthermore, multiple clamps 9 are provided around the holding table 4. The multiple clamps 9 are provided at roughly equal intervals along the circumferential direction of the holding table 4. When the frame unit 11 is brought into the coating device 2, the multiple clamps 9 grip the frame 23 at a position lower than the upper surface of the holding table 4.

[0027] Furthermore, the porous plate 8 of the holding table 4 communicates with a suction source (not shown), such as an ejector, through a through hole formed in the bottom wall 6a of the frame 6. When the suction source is operated with the frame unit 11 loaded into the coating apparatus 2, a suction force acts on the wafer 13 via the tape 21, and the wafer 13 is held in place by the holding table 4.

[0028] Furthermore, the holding table 4 and the multiple clamps 9 are connected to a rotational drive source (not shown), such as a motor. When this rotational drive source is operated, the holding table 4 and the multiple clamps 9 rotate around a straight line passing through the center of the upper surface of the porous plate 8 and along the Z-axis.

[0029] Furthermore, a resin supply nozzle 10 is provided above the holding table 4 to supply liquid resin L to the surface of the wafer 13 contained in the frame unit 11 held by the holding table 4. This liquid resin L is a solution containing, for example, a water-soluble resin such as polyvinylpyrrolidone or polyvinyl alcohol and an organic solvent such as propylene glycol monomethyl ether.

[0030] Furthermore, the water-soluble resin is the main component of the protective film formed by drying the liquid resin L. In addition, the organic solvent reduces the surface tension of the liquid resin L, thereby reducing uneven coating when the liquid resin L is applied to the wafer 13.

[0031] Furthermore, the liquid resin L may contain a light-absorbing agent such as ferulic acid. This light-absorbing agent absorbs the laser beam, as described later, and causes laser ablation in the protective film.

[0032] In the coating apparatus 2 described above, a protective film is formed on the surface of the wafer 13 held on the holding table 4 via the tape 21 by a spin coating method. Specifically, a predetermined amount of liquid resin L is supplied from the resin supply nozzle 10 to the vicinity of the center of the wafer 13 surface, and then the holding table 4 is rotated at a predetermined speed (for example, 1500 rpm to 3000 rpm).

[0033] This coats the entire surface of the wafer 13 with liquid resin L. Then, the rotation of the holding table 4 is stopped, and the liquid resin L is allowed to dry. As a result, a water-soluble protective film (first protective film) 25 is formed that covers the surface of the wafer 13 (see Figure 3(B)).

[0034] After the first coating step (S1), a laser beam is irradiated onto the wafer 13 through a protective film (first protective film) 25 so that the surface area of ​​the wafer 13 is removed and grooves are formed on the wafer 13 (groove formation step: S2). Figure 4(A) is a schematic cross-sectional view showing the groove formation step (S2), and Figure 4(B) is a schematic partially enlarged cross-sectional view showing the wafer 13 after the groove formation step (S2).

[0035] This groove forming step (S2) is carried out, for example, using the laser processing apparatus 12 shown in Figure 4(A). This laser processing apparatus 12 has a holding table 14 having a structure similar to the holding table 4 described above, and a clamp 16 having a structure similar to the clamp 9 described above. The holding table 14 is also in communication with a suction source (not shown), such as an ejector, similar to the holding table 4 described above.

[0036] Furthermore, the holding table 14 is connected to a horizontal movement mechanism (not shown). This horizontal movement mechanism includes, for example, a ball screw and a motor. When this horizontal movement mechanism is operated, the holding table 14 moves along the horizontal direction (for example, the front-to-back direction and / or the left-to-right direction).

[0037] Furthermore, a laser irradiation unit head 18 is provided above the holding table 14. This laser irradiation unit has a laser oscillator (not shown) that generates a laser beam LB with a wavelength (e.g., 355 nm) absorbed by the wafer 13. This laser oscillator has, for example, Nd:YAG as the laser medium.

[0038] The head 18 also houses optical systems such as a focusing lens and mirrors. When a laser beam LB is generated by the laser oscillator, the laser beam LB is irradiated towards the holding table 14 through the optical system housed in the head 18.

[0039] In the laser processing apparatus 12 described above, a wafer 13 with a first protective film 25 formed on its surface is held on a holding table 4 via a tape 21, and grooves 27 are formed on the surface of the wafer 13 by irradiating it with a laser beam LB along the boundaries of multiple devices 19. Specifically, while irradiating the wafer 13 with a laser beam LB from the head 18, the horizontal movement mechanism is operated so that the laser beam LB is irradiated onto the wafer 13 along the boundaries of the multiple devices 19 (see Figure 4(A)).

[0040] As a result, laser ablation occurs near the surface of the wafer 13, removing the area of ​​the first protective film 25 that overlaps with the boundaries of the multiple devices 19 and the area near the surface of the wafer 13 (the area of ​​the insulating layer 17 and the area near the surface of the substrate 15). Consequently, a groove 27 is formed in the wafer 13, and the sides and bottom portions 29 of this groove are damaged (see Figure 4(B)).

[0041] Following the groove formation step (S2), isotropic plasma etching is performed on the wafer 13 from the surface side (first plasma etching step: S3). Figure 5 is a schematic diagram showing an example of a plasma generation apparatus used to carry out the plasma etching step (S3).

[0042] The plasma generator 20 shown in Figure 5 has a chamber 22 made of a conductive material and grounded. The chamber 22 has an inlet / outlet 22a for loading the frame unit 11 into and unloading the frame unit 11 from the inside.

[0043] The loading / unloading port 22a is equipped with a gate valve 24 that can either block or allow communication between the internal and external spaces of the chamber 22. The chamber 22 also has an exhaust port 22b for exhausting its internal space.

[0044] This exhaust port 22b is connected to an exhaust device 28 such as a vacuum pump via piping 26, etc. Furthermore, a support member 30 is provided on the inner surface of the chamber 22, and this support member 30 supports the table 32.

[0045] An electrostatic chuck (not shown) is provided on the top of the table 32. Inside the table 32, a disc-shaped electrode 32a is provided, located below the electrostatic chuck. This electrode 32a is connected to the high-frequency power supply 36 via a matching unit 34.

[0046] Furthermore, a disc-shaped opening is formed in the chamber 22 at a position opposite the upper surface of the table 32, and a gas ejection head 40 is provided in this opening, supported by the chamber 22 via a bearing 38. This gas ejection head 40 is made of a conductive material and is connected to a high-frequency power supply 44 via a matching unit 42.

[0047] Furthermore, a cavity (gas diffusion space) 40a is formed inside the gas ejection head 40. In addition, a plurality of gas outlets 40b are formed in the inner part of the gas ejection head 40 (for example, the lower part) that connect the gas diffusion space 40a with the internal space of the chamber 22. In addition, two gas supply ports 40c and 40d are formed in the outer part of the gas ejection head 40 (for example, the upper part) for supplying a predetermined gas to the gas diffusion space 40a.

[0048] Furthermore, the gas supply port 40c is connected via piping 46a, etc., to a gas supply source 48a that supplies, for example, carbon fluoride-based gases such as C4F8 and / or sulfur fluoride-based gases such as SF6. Also, the gas supply port 40d is connected via piping 46b, etc., to a gas supply source 48b that supplies, for example, inert gases such as Ar and O2 gas.

[0049] In the plasma generation apparatus 20 described above, isotropic plasma etching of the wafer 13 from the surface side is performed, for example, as follows. Specifically, first, the frame unit 11 is brought onto the table 32 with the tape 21 facing downwards, while the gate valve 24 connects the internal and external spaces of the chamber 22.

[0050] Next, the wafer 13 is held via the tape 21 by the electrostatic chuck of the table 32. Then, the internal space of the chamber 22 is evacuated by the exhaust device 28 to create a vacuum. Then, for a predetermined period of time, gas containing SF6 is supplied to the internal space of the chamber 22 from the gas supply source 48a, and Ar gas is supplied from the gas supply source 48b, while high-frequency power is supplied to the gas ejection head 40 from the high-frequency power supply 44.

[0051] This completes the first plasma etching step (S3). Figure 6(A) is a schematic partially enlarged cross-sectional view showing the wafer 13 after the first plasma etching step (S3).

[0052] In this first plasma etching step (S3), the wafer 13 is isotropically etched by F-based radicals and the like generated in the internal space of the chamber 22. As a result, damaged portions 29 near the sides and bottom of the grooves 27 formed on the surface of the wafer 13 are removed.

[0053] After the first plasma etching step (S2), the sides and bottom of the grooves 27 formed on the surface of the wafer 13 are covered with a second protective film (second covering step: S4). This second covering step (S4) is carried out, for example, using the plasma generation apparatus 20 described above, as follows.

[0054] Specifically, first, with the wafer 13 held by the electrostatic chuck of the table 32 via the tape 21, the internal space of the chamber 22 is evacuated to create a vacuum. Then, for a predetermined period of time, gas containing C4F8 is supplied to the internal space of the chamber 22 from the gas supply source 48a, and Ar gas is supplied from the gas supply source 48b, while high-frequency power is supplied to the gas ejection head 40 from the high-frequency power supply 44.

[0055] This completes the second coating step (S3). Figure 6(B) is a schematic partially enlarged cross-sectional view showing the wafer 13 after the second coating step (S4). In this second coating step (S4), an insulating second protective film 31 is formed on the surface side of the wafer 13.

[0056] Specifically, CF radicals are deposited on the upper surface of the first protective film 25 and on the side and bottom surfaces of the groove 27 to form a film containing fluorinated carbon. It is preferable that the thickness of this second protective film 31 be 20 nm or more in order to suppress the progression of undercuts when the wafer 13 is divided.

[0057] Following the second coating step (S4), the wafer 13 is divided along the boundaries of the multiple devices 19 using plasma etching (division step: S5). Figure 7 is a flowchart schematically showing a specific example of the division step (S5). In short, in the division step (S5) shown in Figure 7, the wafer 13 is divided using the so-called Bosch process.

[0058] This splitting step (S5) is carried out, for example, using the plasma generation apparatus 20 described above, as follows. Specifically, first, with the wafer 13 held by the electrostatic chuck of the table 32 via the tape 21, the internal space of the chamber 22 is evacuated to create a vacuum.

[0059] Next, anisotropic plasma etching is performed on the wafer 13 from the surface side so as to expose the bottom surface of the groove 27 formed on the surface of the wafer 13 (second plasma etching step: S51).

[0060] Specifically, for a predetermined period, gas containing SF6 is supplied to the internal space of the chamber 22 from the gas supply source 48a, and Ar gas is supplied from the gas supply source 48b. At the same time, high-frequency power is supplied from the high-frequency power supply 36 to the electrode 32a located inside the table 32, and high-frequency power is supplied from the high-frequency power supply 44 to the gas ejection head 40.

[0061] In this second plasma etching step (S51), F-based ions and the like generated in the internal space of the chamber 22 are accelerated toward the table 32, causing the wafer 13 to be etched anisotropically. As a result, the portion of the second protective film 31 that covers the sides of the groove 27 remains, while the portion that covers the bottom surface is removed, exposing the bottom surface of the groove 27.

[0062] Next, isotropic plasma etching is performed on the wafer 13 from the surface side (third plasma etching step: S52). Specifically, for a predetermined period of time, gas containing SF6 is supplied from gas supply source 48a to the internal space of the chamber 22, and Ar gas is supplied from gas supply source 48b, while high-frequency power is supplied to the gas ejection head 40 from high-frequency power supply 44.

[0063] In this third plasma etching step (S52), similar to the first plasma etching step (S3), the wafer 13 is isotropically etched by F-based radicals and the like generated in the internal space of the chamber 22. As a result, the area near the bottom of the exposed groove 27 is isotropically removed.

[0064] Then, in the third plasma etching step (S52), if the wafer 13 is not divided along the boundaries of the multiple devices 19 (S53: No), the sides and bottom of the groove 27 are covered with a third protective film that is thinner than the second protective film 31 (third covering step: S54).

[0065] Specifically, over a predetermined period, a gas containing C4F8 is supplied to the internal space of the chamber 22 from the gas supply source 48a, and a gas containing Ar is supplied from the gas supply source 48b, while high-frequency power is supplied to the gas ejection head 40 from the high-frequency power supply 44.

[0066] In this third coating step (S54), CF radicals are deposited on the side and bottom surfaces of the groove 27 to form a film containing fluorinated carbon. The thickness of this third protective film is, for example, 10 nm or less.

[0067] Furthermore, in the splitting step (S5) shown in Figure 7, the second plasma etching step (S51), the third plasma etching step (S52), and the third coating step (S54) are repeated until the wafer 13 is split along the boundaries of the multiple devices 19.

[0068] Then, once the wafer 13 is divided along the boundaries of multiple devices 19 (S53: Yes), multiple chips are manufactured. Figure 8 is a schematic enlarged cross-sectional view showing chips manufactured from wafer 13 divided in the division step (S5) shown in Figure 7. When wafer 13 is divided by the division step (S5) shown in Figure 7, chips 33 having an uneven surface are manufactured.

[0069] In the chip manufacturing method described above, after removing the damaged portions 29 near the sides and bottom of the groove 27 formed in the groove formation step (S2) in the first plasma etching step (S3), the sides of the groove 27 are covered with a second protective film 31 formed in the second coating step (S4). This makes it possible to suppress undercuts progressing from the sides of the groove 27 in the splitting step (S5) in which plasma etching is performed on the wafer 13.

[0070] It should be noted that the above description represents only one aspect of the present invention, and the present invention is not limited to the above description. For example, the wafer used in the present invention may be a wafer that does not include an insulating layer 17, and in which the device 19 is directly formed on the surface of the substrate 15.

[0071] Furthermore, in the second coating step (S4) described above, an oxide film formed using oxygen plasma may be used as the second protective film. Specifically, in the second coating step (S4) described above, the film may be formed by supplying a gas containing O2 and Ar from a gas supply source 48b to the internal space of the chamber 22 for a predetermined period of time, while providing high-frequency power from a high-frequency power supply 44 to the gas ejection head 40. In this case, an oxide film formed by the reaction of the material constituting the wafer 13 (e.g., silicon) with oxygen ions on the side and bottom surfaces of the groove 27 can be used as the second protective film.

[0072] Furthermore, in the division step (S5) described above, the conditions for anisotropic plasma etching to remove the second protective film 31 covering the bottom surface of the groove 27 and expose the bottom surface may be different from the conditions for anisotropic plasma etching to remove the third protective film covering the bottom surface of the groove 27 and expose the bottom surface.

[0073] In other words, in the division step (S5) described above, the conditions for anisotropic plasma etching may be different between the first second plasma etching step (S51) and the second and subsequent second plasma etching steps (S51). For example, the predetermined period during which the first second plasma etching step (S51) is performed may be longer than the predetermined period during which the second and subsequent second plasma etching steps (S51) are performed.

[0074] Furthermore, in the division step (S5) described above, the wafer 13 may be divided without performing the third plasma etching step (S52) and the third coating step (S54). That is, in the division step (S5) described above, anisotropic plasma etching may be performed on the wafer 13 from the surface side until the wafer 13 is divided along the boundaries of the plurality of devices 19.

[0075] Furthermore, if only anisotropic plasma etching is performed in the splitting step (S5), the conditions for anisotropic plasma etching to remove the second protective film 31 covering the bottom surface of the groove 27 and expose the bottom surface may be different from the conditions for anisotropic plasma etching to remove the region overlapping with the boundaries of the multiple devices 19 on the wafer 13 and split the wafer 13.

[0076] Furthermore, the structures and methods of the embodiments described above can be modified as appropriate without departing from the scope of the present invention. [Explanation of Symbols]

[0077] 2: Coating device 4: Holding Table 6: Frame (6a: Frame, 6b: Porous plate) 8: Porous board 9: Clamp 10: Resin supply nozzle 11: Frame Unit 12: Laser processing equipment 13: Wafer 14: Holding Table 15: Circuit board 16: Clamp 17: Insulating layer 18: Head 19: Device 20: Plasma generator 21: Tape 22: Chamber (22a: Inlet / Outlet, 22b: Exhaust Port) 23: Frame 24: Gate valve 25: First protective layer 26: Piping 27: Groove 28: Exhaust system 29 :part 30: Support member 31: Second protective layer 32: Table (32a: Electrode) 33: Tip 34: Matching box 36:High frequency power supply 38: Bearing 40: Gas ejection head (40a: Gas diffusion space, 40b: Gas outlet, 40c, 40d: Gas supply port) 42: Matching box 44:High frequency power supply 46a, 46b: Piping 48a, 48b: Gas supply source

Claims

1. A method for manufacturing a chip, which involves dividing a wafer on which multiple devices are formed along the boundaries of the multiple devices to produce a chip, A first coating step of covering the surface of the wafer with a water-soluble first protective film, After the first coating step, a groove forming step is performed, in which a laser beam of a wavelength absorbed by the wafer is irradiated onto the wafer through the first protective film so that the region of the first protective film overlapping the boundary and the region of the wafer on the surface side of the wafer are removed and grooves are formed on the wafer. A first plasma etching step is performed on the wafer from the surface side of the wafer with the grooves exposed, after the groove formation step, A second coating step is performed, in which the sides and bottom of the groove are covered with a second protective film, after the first plasma etching step. A dividing step which is repeated in order until the wafer is divided along the boundary, the following steps: a second plasma etching step in which anisotropic plasma etching is performed on the wafer from the surface side of the wafer so as to expose the bottom surface of the groove; a third plasma etching step in which isotropic plasma etching is performed on the wafer from the surface side of the wafer; and a third coating step performed over a predetermined period of time so as to cover the sides and bottom surface of the groove with a third protective film thinner than the second protective film. A method for manufacturing a chip equipped with the following features.

2. A method for manufacturing a chip, which involves dividing a wafer on which multiple devices are formed along the boundaries of the multiple devices to produce a chip, A first coating step of covering the surface of the wafer with a water-soluble first protective film, After the first coating step, a groove forming step is performed, in which a laser beam of a wavelength absorbed by the wafer is irradiated onto the wafer through the first protective film so that the region of the first protective film overlapping the boundary and the region of the wafer on the surface side of the wafer are removed and grooves are formed on the wafer. A first plasma etching step is performed on the wafer from the surface side of the wafer with the grooves exposed, after the groove formation step, A second coating step is performed, in which the sides and bottom of the groove are covered with a second protective film, after the first plasma etching step. Following the second coating step, a splitting step is performed, in which anisotropic plasma etching is applied to the wafer from the surface side until the wafer is split along the boundary. A method for manufacturing a chip equipped with the following features.

3. The method further comprises a second plasma etching step, which is performed after the second coating step and before the splitting step, in which anisotropic plasma etching is performed on the wafer from the surface side of the wafer so as to expose the bottom surface of the groove. The method for manufacturing a chip according to claim 2, wherein the conditions for anisotropic plasma etching are different in the second plasma etching step and the division step.

4. A method for manufacturing a chip according to any one of claims 1 to 3, wherein the wafer comprises a substrate and an insulating layer provided between the substrate and the plurality of devices.

5. The method for manufacturing a chip according to any one of claims 1 to 4, wherein the second protective film is insulating.

6. The method for manufacturing a chip according to any one of claims 1 to 5, wherein the second protective film contains fluorinated carbon.

7. The method for manufacturing a chip according to any one of claims 1 to 6, wherein the thickness of the second protective film is 20 nm or more.

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