Semiconductor memory device and method for manufacturing a semiconductor device.

Abstract

To provide a semiconductor storage device capable of improving electric characteristics, and a method for manufacturing a semiconductor device.SOLUTION: In a semiconductor storage device, a memory cell array comprises a first bit line BL-1, a second bit line BL-2, a first insulation layer 80, a first layer part 81, a first insulation part 91, and a plurality of vias 73. The first layer part 81 includes a first portion 81-1, a second portion 81-2, and a third portion 82. The first portion is laminated on the first bit line. The second portion is laminated on the second bit line. The third portion is located on the opposite side of the first bit line and the second bit line with respect to the first portion and the second portion. The via includes a first portion 73a in contact with the first bit line through the third and first portions of the first insulation layer, and a second portion 73b in contact with the first insulation part through the third portion of the first insulation layer and having a step between itself and the first portion of the via.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing a semiconductor device.

Background Art

[0002] A semiconductor memory device having a stack in which word lines and insulating layers are alternately stacked, a memory pillar penetrating the stack, and a bit line connected to the memory pillar is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Non-Patent Documents

[0004]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] One embodiment of the present invention provides a semiconductor memory device that can improve electrical characteristics, and a method for manufacturing a semiconductor device. [Means for solving the problem]

[0006] The semiconductor memory device of the embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulating portion, and a conductive portion. The first wiring extends in a first direction. The second wiring extends away from the first wiring in a second direction intersecting the first direction and extends in the first direction. The first insulating layer includes a first portion, a second portion, and a third portion. The first portion is laminated on the first wiring in a third direction intersecting the first and second directions. The second portion is laminated on the second wiring in the third direction. The third portion is located on the opposite side of the first and second portions from the first and second wiring and extends at least in the second direction so as to span the first and second portions. The first insulating portion includes a portion located between the first and second portions of the first insulating layer in the second direction. The conductive portion extends toward the first insulating layer from the opposite side of the first wiring to the first insulating layer. The conductive portion includes a first portion that penetrates the third portion of the first insulating layer and the first portion in the third direction and is in contact with the first wiring, and a second portion that penetrates the third portion of the first insulating layer in the third direction and is in contact with the first insulating portion, and has a step between it and the first portion of the conductive portion. The first insulating portion includes a first insulating material containing oxygen. The first and second portions of the first insulating layer include a second insulating material containing nitrogen. The third portion of the first insulating layer includes a third insulating material that contains nitrogen and is different from the second insulating material. [Brief explanation of the drawing]

[0007] [Figure 1] A block diagram showing part of the configuration of the semiconductor memory device of the embodiment. [Figure 2] A diagram showing an equivalent circuit of a portion of the memory cell array of the embodiment. [Figure 3] A cross-sectional view showing a part of the semiconductor memory device of the embodiment. [Figure 4]A cross-sectional view showing the region enclosed by line F4 of the memory cell array shown in Figure 3. [Figure 5] A cross-sectional view of the memory cell array shown in Figure 4, along the F5-F5 line. [Figure 6] A cross-sectional view showing the region enclosed by line F6 of the memory cell array shown in Figure 3. [Figure 7] Figure 6 shows an enlarged cross-sectional view of a portion of the cross-section along the F7-F7 line of the memory cell array. [Figure 8] A cross-sectional view of the memory cell array shown in Figure 6, along the F8-F8 line. [Figure 9] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to an embodiment. [Figure 10] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to an embodiment. [Figure 11] A cross-sectional view illustrating the manufacturing method of a semiconductor memory device according to an embodiment. [Figure 12] A cross-sectional view showing a portion of the memory cell array of a first modified embodiment. [Figure 13] A cross-sectional view showing a portion of a memory cell array in a second modified example of the embodiment. [Modes for carrying out the invention]

[0008] The semiconductor memory device and semiconductor device manufacturing method of the embodiments will be described below with reference to the drawings. In the following description, components having the same or similar functions will be denoted by the same reference numeral. Duplication of these components may be omitted. In the following description, reference numerals or letters at the end of reference numerals may be omitted if they do not need to be distinguished from each other.

[0009] In this application, terms are defined as follows: “Parallel,” “orthogonal,” or “same” may include “approximately parallel,” “approximately orthogonal,” or “approximately the same,” respectively. “Connection” may include electrical connections, not just mechanical ones. That is, “connection” may include cases where two elements to be connected are directly connected, not just cases where two elements are connected with another element in between. “Adjacent” may include cases where two elements are adjacent, not just cases where two elements are touching, not just cases where two elements are separated from each other (for example, when another element is interposed between two elements). “Layer” and “membrane” are terms used for convenience to distinguish between components and mean substantially the same thing. For this reason, in the following description, “layer” and “membrane” may be read as interchangeable.

[0010] The X, Y, +Z, and -Z directions are defined as follows: The X direction is the direction in which the word line WL (see Figure 3), described later, extends. The Y direction is the direction that intersects (e.g., is orthogonal to) the X direction. The Y direction is the direction in which the bit line BL (see Figure 3), described later, extends. The +Z and -Z directions are the directions that intersect (e.g., are orthogonal to) the X and Y directions. The +Z direction is the direction from the stacked body 40 toward the bit line BL (see Figure 3), described later. The -Z direction is the direction opposite to the +Z direction. When the +Z and -Z directions are not distinguished, they are simply referred to as the "Z direction". In the following explanation, the position in the Z direction may be referred to as "height". However, this expression is for the convenience of explanation and does not define the direction of gravity. The Y direction is an example of the "first direction". The X direction is an example of the "second direction". The Z direction is an example of the "third direction".

[0011] (Embodiment) <1. Configuration of semiconductor memory devices> FIG. 1 is a block diagram showing a part of the configuration of the semiconductor memory device 1. The semiconductor memory device 1 is, for example, a non-volatile semiconductor memory device and is a NAND type flash memory. The semiconductor memory device 1 can be connected to, for example, an external host device and is used as a storage space of the host device. The semiconductor memory device 1 includes, for example, a memory cell array 11, a command register 12, an address register 13, a control circuit (sequencer) 14, a driver module 15, a row decoder module 16, and a sense amplifier module 17.

[0012] The memory cell array 11 includes a plurality of blocks BLK0 to BLK(k - 1) (k is an integer of 1 or more). A block BLK is a set of a plurality of memory cell transistors that store data non-volatily. A block BLK is used as an erasure unit of data. The memory cell array 11 is provided with a plurality of bit lines and a plurality of word lines. Each memory cell transistor is associated with one bit line and one word line.

[0013] The command register 12 holds a command CMD received by the semiconductor memory device 1 from the host device. The address register 13 holds address information ADD received by the semiconductor memory device 1 from the host device. The control circuit 14 is a circuit that controls various operations of the semiconductor memory device 1. For example, the control circuit 14 executes a data write operation, a read operation, an erase operation, etc. based on the command CMD held in the command register 12.

[0014] The driver module 15 includes a voltage generation circuit and generates voltages used in various operations of the semiconductor memory device 1. The row decoder module 16 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line. The sense amplifier module 17 applies a desired voltage to each bit line in a write operation. In a read operation, the sense amplifier module 17 determines the data value stored in each memory cell transistor based on the voltage or current of each bit line and transfers the determination result to the host device as read data DAT.

[0015] <2. Electrical Configuration of Memory Cell Array> Next, the electrical configuration of the memory cell array 11 will be described. FIG. 2 is a diagram showing an equivalent circuit of a part of the memory cell array 11. FIG. 2 shows one block BLK included in the memory cell array 11. The block BLK includes a plurality of string units SU0 to SUQ (Q is an integer of 1 or more).

[0016] Each string unit SU includes a plurality of NAND strings NS respectively associated with bit lines BL0 to BLm (m is an integer of 1 or more). Each NAND string NS includes, for example, a plurality of memory cell transistors MT0 to MTn (n is an integer of 1 or more), one or more drain side selection transistors STD, and one or more source side selection transistors STS.

[0017] In each NAND string NS, the memory cell transistors MT0 to MTn are electrically connected in series. Each memory cell transistor MT includes a control gate and a charge storage part. The control gate of the memory cell transistor MT is electrically connected to any one of word lines WL0 to WLn. Each memory cell transistor MT accumulates charge in the charge storage part according to the voltage applied to the control gate via the word line WL, and holds the data value in a non-volatile manner.

[0018] The drain of the drain-side selection transistor STD is electrically connected to the bit line BL corresponding to the NAND string NS. The source of the drain-side selection transistor STD is electrically connected to one end of the electrically series-connected memory cell transistors MT0 to MTn. The control gate of the drain-side selection transistor STD is electrically connected to one of the drain-side selection gate lines SGD0 to SGDQ. The drain-side selection transistor STD is electrically connected to the row decoder module 16 via the drain-side selection gate line SGD. The drain-side selection transistor STD electrically connects the NAND string NS and the bit line BL when a predetermined voltage is applied to the corresponding drain-side selection gate line SGD.

[0019] The drain of the source-side selection transistor STS is electrically connected to the other end of the electrically series-connected memory cell transistors MT0 to MTn. The source of the source-side selection transistor STS is electrically connected to the source line SL. The control gate of the source-side selection transistor STS is electrically connected to the source-side selection gate line SGS. The source-side selection transistor STS electrically connects the NAND string NS and the source line SL when a predetermined voltage is applied to the source-side selection gate line SGS.

[0020] In the same block BLK, the control gates of memory cell transistors MT0 to MTn are commonly connected to their respective word lines WL0 to WLn. The control gates of drain-side selection transistors STD in each string unit SU0 to SUQ are commonly connected to their respective selection gate lines SGD0 to SGDQ. The control gate of source-side selection transistor STS is commonly connected to the selection gate line SGS. In the memory cell array 11, the bit line BL is shared by NAND strings NS, each assigned the same column address in each string unit SU.

[0021] <3. Physical Configuration of Semiconductor Memory Devices> Next, the physical configuration of the semiconductor memory device 1 will be described. Figure 3 is a cross-sectional view showing a part of the semiconductor memory device 1. The semiconductor memory device 1 includes, for example, a first chip 2 and a second chip 3.

[0022] <3.1 First Chip> First, let's describe the first chip 2. The first chip 2 is a circuit chip that includes peripheral circuits 22. The first chip 2 includes, for example, a semiconductor substrate 21, peripheral circuits 22, an insulating section 23, and a plurality of pads 24.

[0023] The semiconductor substrate 21 is, for example, the substrate that forms the base of the first chip 2. At least a portion of the semiconductor substrate 21 is plate-shaped along the X and Y directions. The semiconductor substrate 21 is formed of a semiconductor material such as silicon.

[0024] The peripheral circuit 22 is a circuit for making the memory cell array 11 described above functional. The peripheral circuit 22 includes one or more of the command register 12, address register 13, control circuit 14, driver module 15, row decoder module 16, and sense amplifier module 17 described above. The peripheral circuit 22 includes, for example, multiple transistors 31, multiple contacts 32, multiple wiring layers 33, and multiple vias 34.

[0025] Multiple transistors 31 are provided on a semiconductor substrate 21. Each transistor 31 includes, for example, a source region and a drain region formed on the upper surface of the semiconductor substrate 21. Multiple contacts 32 are conductive and extend in the Z direction. Each contact 32 is in contact with the source region, drain region, or gate electrode of the transistor 31.

[0026] Multiple wiring layers 33 are arranged at multiple heights. Each wiring layer 33 contains multiple wirings 33a extending in the X or Y direction. Each via 34 extends in the Z direction. Multiple vias 34 include, for example, a via 34 connecting two wirings 33a located at different heights, and a via 34 connecting a wiring 33a to a pad 24.

[0027] The insulating portion 23 covers multiple transistors 31, multiple contacts 32, multiple wiring layers 33, and multiple vias 34. Multiple pads 24 are provided on the surface of the insulating portion 23. Each pad 24 is electrically connected to the wiring 33a via 34.

[0028] <3.2 Second Chip> First, let's describe the second chip 3. The second chip 3 is an array chip that includes a memory cell array 11. The second chip 3 has, for example, a memory cell array 11, an insulating section 35, and a plurality of pads 36. Here, we will describe the insulating section 35 and the plurality of pads 36, and the memory cell array 11 will be described later.

[0029] The insulating portion 35 covers the memory cell array 11. Multiple pads 36 are provided on the surface of the insulating portion 35. Each pad 36 is electrically connected to a wire (for example, wire 72 or wire 74) included in the wiring portion 70 of the memory cell array 11, which will be described later. In this embodiment, the first chip 2 and the second chip 3 are integrated by bonding the multiple pads 24 of the first chip 2 and the multiple pads 36 of the second chip 3 facing each other.

[0030] <4. Physical configuration of the memory cell array> Next, the physical configuration of the memory cell array 11 will be described. As shown in Figure 3, the memory cell array 11 includes a stacked body 40, a source line SL, a plurality of memory pillars 50, a plurality of contacts 61 for the memory pillars (only one is shown in Figure 3), a plurality of contacts 62 for the conductive layer (only one is shown in Figure 3), and a wiring section 70.

[0031] <4.1 Laminates> First, let me explain the laminate 40. Figure 4 is a cross-sectional view showing the region enclosed by the F4 line of the memory cell array 11 shown in Figure 3. Note that Figure 4 is a view rotated upside down compared to Figure 3. For the sake of explanation, in the following, the side where the bit line BL is located (i.e., the +Z direction side) as viewed from the stack 40 may be referred to as "up," and the opposite side (i.e., the -Z direction side) may be referred to as "down." However, these expressions do not define the direction of gravity of the semiconductor memory device 1.

[0032] The laminate 40 includes a plurality of conductive layers 41 and a plurality of insulating layers 42. The plurality of conductive layers 41 and the plurality of insulating layers 42 are stacked alternately one layer at a time in the Z direction.

[0033] The conductive layer 41 is oriented along the X and Y directions. Each conductive layer 41 is formed of a conductive material, such as tungsten. The conductive layer 41 is an example of a "gate electrode layer".

[0034] One or more conductive layers 41 located in the upper part of the multiple conductive layers 41 function as drain-side selection gate lines SGD. The drain-side selection gate lines SGD are provided in common for multiple memory pillars 50 arranged in the X or Y direction. The intersection of the drain-side selection gate lines SGD and the channel layer 52 (described later) of each memory pillar 50 functions as the drain-side selection transistor STD described above.

[0035] One or more of the conductive layers 41 located at the bottom of the multiple conductive layers 41 function as a source-side selection gate line SGS. The source-side selection gate line SGS is provided in common for multiple memory pillars 50 aligned in the X or Y direction. The intersection of the source-side selection gate line SGS and the channel layer 52 of each memory pillar 50 functions as the source-side selection transistor STS described above.

[0036] Of the multiple conductive layers 41, at least a portion of the remaining conductive layers 41 provided between the conductive layers 41 that function as the drain-side selected gate line SGD and the source-side selected gate line SGS functions as a word line WL. The word line WL is provided in common for multiple memory pillars 50 aligned in the X and Y directions. In this embodiment, the intersection of the word line WL and the channel layer 52 of each memory pillar 50 functions as a memory cell transistor MT. The memory cell transistor MT will be described in detail later.

[0037] The insulating layer 42 is an interlayer insulating film provided between two adjacent conductive layers 41 in the Z direction, insulating the two conductive layers 41. The insulating layer 42 is oriented along the X and Y directions. The insulating layer 42 is formed of an insulating material such as a film containing silicon and oxygen (e.g., an SiO2 film). The insulating layer 42 is an example of a "second insulating layer".

[0038] <4.2 Source Line> The source wire SL is positioned on the -Z side relative to the laminate 40. The source wire SL is a plate-like conductive layer extending in the X and Y directions. The source wire SL is formed of a conductive material such as a conductive layer containing polysilicon or tungsten.

[0039] <4.3 Memory Pillar> Multiple memory pillars 50 extend in the Z direction and penetrate the laminate 40. The lower end 50a of each memory pillar 50 is in contact with the source line SL. On the other hand, the upper end 50b of each memory pillar 50 is in contact with the contact 61, which will be described later. The memory pillars 50 are an example of a "columnar body".

[0040] Figure 5 is a cross-sectional view of the memory cell array 11 shown in Figure 4 along the F5-F5 line. The memory pillar 50 has, for example, a memory film (multilayer film) 51, a channel layer 52, an insulating core 53, and a cap portion 54 (see Figure 4).

[0041] The memory film 51 is provided on the outer periphery of the channel layer 52. The memory film 51 is located between the multiple conductive layers 41 and the channel layer 52. The memory film 51 includes, for example, a tunnel insulating film 57, a charge trap film 58, and a block insulating film 59.

[0042] The tunnel insulating film 57 is provided between the channel layer 52 and the charge trap film 58. The tunnel insulating film 57 is, for example, annular along the outer circumferential surface of the channel layer 52 and extends in the Z direction along the channel layer 52. The tunnel insulating film 57 extends, for example, along the entire length of the memory pillar 50 in the Z direction. The tunnel insulating film 57 is a potential barrier between the channel layer 52 and the charge trap film 58. The tunnel insulating film 57 is formed from a film containing silicon and oxygen, or a film containing silicon, oxygen, and nitrogen.

[0043] The charge trap film 58 is provided on the outer periphery of the tunnel insulating film 57. The charge trap film 58 is located between the tunnel insulating film 57 and the block insulating film 59. The charge trap film 58 extends in the Z direction. For example, the charge trap film 58 extends along the entire length of the memory pillar 50 in the Z direction. The charge trap film 58 is a functional film having numerous crystal defects (trapping levels) and capable of trapping charges in these crystal defects. The charge trap film 58 is formed from a film containing silicon and nitrogen, for example. The portion of the charge trap film 58 adjacent to each word line WL is an example of a "charge storage section" capable of storing information by accumulating charge.

[0044] The block insulating film 59 is provided on the outer periphery of the charge trap film 58. The block insulating film 59 is located between the multiple conductive layers 41 and the charge trap film 58. The block insulating film 59 is an insulating film that suppresses back tunneling. Back tunneling is a phenomenon in which charge returns from the word line WL to the charge trap film 58. The block insulating film 59 extends in the Z direction. The block insulating film 59 extends, for example, along the entire length of the memory pillar 50 in the Z direction. The block insulating film 59 is a laminated structure film in which multiple insulating films are stacked, for example, a film containing silicon and oxygen or a film containing metal and oxygen. An example of a film containing metal and oxygen is aluminum oxide. The block insulating film 59 may also contain a high-dielectric constant material (High-k material) such as silicon nitride or hafnium oxide.

[0045] The channel layer 52 is located inside the memory film 51. The channel layer 52 is formed in an annular shape. The channel layer 52 extends in the Z direction. The channel layer 52 extends, for example, along the entire length of the memory pillar 50 in the Z direction. The channel layer 52 is made of a semiconductor material such as polysilicon. The channel layer 52 may be doped with impurities. When a voltage is applied to the word line WL, the channel layer 52 forms a channel that electrically connects the bit line BL and the source line SL.

[0046] As a result, at the same height as each word line WL, a MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell transistor MT is formed by the end of the word line WL adjacent to the memory pillar 50, the block insulating film 59, the charge trap film 58, the tunnel insulating film 57, and the channel layer 52. The memory film 51 may have a floating gate type charge storage unit (floating gate electrode) instead of the charge trap film 58 as a charge storage unit. The floating gate electrode is formed, for example, from polysilicon containing impurities.

[0047] The insulating core 53 is located inside the channel layer 52. The insulating core 53 fills a portion of the interior of the channel layer 52. The insulating core 53 is formed of an insulating material such as a film containing silicon and oxygen. A portion of the insulating core 53 is formed in an annular shape along the inner circumferential surface of the channel layer 52 and may have an internal space (air gap) S. The insulating core 53 extends in the Z direction. The insulating core 53 extends over most of the Z direction of the memory pillar 50, for example, except for the upper end of the memory pillar 50 (see Figure 4).

[0048] Next, returning to Figure 4, the cap portion 54 will be described. The cap portion 54 is located above the insulating core 53. The cap portion 54 is a semiconductor portion formed of a semiconductor material such as amorphous silicon or polysilicon. The cap portion 54 may be doped with impurities. The cap portion 54 is positioned on the inner circumference side of the upper end of the memory film 51 and is formed integrally with the channel layer 52. Together with the upper end of the channel layer 52, the cap portion 54 forms the upper end of the memory pillar 50. The contact 61 for the memory pillar is in contact with the cap portion 54 in the Z direction.

[0049] <4.4 Contacts for memory pillars> Next, the contacts 61 for the memory pillars will be described. The contacts 61 are electrical connections that electrically connect the memory pillars 50 to the bit lines BL included in the wiring section 70. When viewed from above, the multiple contacts 61 are positioned to correspond to the multiple memory pillars 50. Each contact 61 extends in the Z direction. The lower end of each contact 61 is in contact with the upper end 50b of the memory pillar 50. On the other hand, the upper end of each contact 61 is connected to the bit lines BL via a via 71 (described later) provided above the contact 61.

[0050] <4.5 Contacts for conductive layers> Next, returning to Figure 3, we will describe the contacts 62 for the conductive layer. The contacts 62 are electrical connections that electrically connect the conductive layer 41 and the wiring 74 included in the wiring section 70. The multiple contacts 62 are arranged, for example, in the laminate 40, corresponding to the stepped region where the ends of the multiple conductive layers 41 are arranged in a stepped manner. When viewed from above, the multiple contacts 62 are positioned at locations corresponding to the multiple conductive layers 41. The multiple contacts 62 extend in the Z direction, and their lengths in the Z direction differ from one another.

[0051] <4.6 Wiring section> Next, the wiring section 70 will be described. The wiring section 70 is located, for example, between the laminate 40 and the semiconductor substrate 21 (see Figure 3). The wiring section 70 includes, for example, a plurality of bit lines BL, a plurality of vias 71, a plurality of wirings 72, a plurality of vias 73, and a plurality of wirings 74.

[0052] Each bit line BL is a wire whose voltage application state is controlled to select a memory pillar 50. Multiple bit lines BL are arranged side by side in the X direction with spacing between them. Multiple bit lines BL extend parallel to each other in the Y direction. Each bit line BL is positioned so as to overlap at least a portion with the contact 61 for the corresponding memory pillar in the Z direction. A via 71 is provided between the bit line BL and the contact 61 to connect the bit line BL and the contact 61. The bit lines BL are electrically connected to the channel layer 52 of the memory pillar 50 via the via 71 and the contact 61. This allows selection of any memory cell transistor MT from among multiple memory cell transistors MT arranged in three dimensions by the combination of the word line WL and the bit lines BL. The bit lines BL will be described in more detail later.

[0053] Each wire 72 is an electrical connection for electrically connecting the bit line BL to the pad 36. Multiple wires 72 are arranged, for example, on the +Z side with respect to multiple bit lines BL. Each wire 72 extends, for example, in the X or Y direction. Vias 73 are provided between the wire 72 and the bit line BL to connect the wire 72 and the bit line BL. The wires 72 and vias 73 will be described in detail later.

[0054] Each wiring 74 is a wiring whose voltage application state is controlled in order to select the conductive layer 41 (word wire WL, drain-side selectable gate wire SGD, or source-side selectable gate wire SGS). Each wiring 74 is an electrical connection that electrically connects the contact 62 and the pad 36.

[0055] <5. Connection structure of bit lines and wiring> Next, we will explain the connection structure between bit line BL and wiring 72. Figure 6 is a cross-sectional view showing the region enclosed by the F6 line of the memory cell array 11 shown in Figure 3. Note that Figure 6 is rotated upside down compared to Figure 3. As shown in Figure 6, the memory cell array 11 has the aforementioned multiple bit lines BL, an insulating layer 80, a first insulating section 91, the aforementioned multiple wirings 72, multiple vias 73 (only one is shown in Figure 6), and a second insulating section 92. These will be described in detail below.

[0056] <5.1 bit line> Multiple bit lines BL are arranged in the X direction with space between them. For the sake of explanation, one bit line BL-1 included in multiple bit lines BL will be referred to as "first bit line BL-1," and one bit line BL adjacent to first bit line BL-1 will be referred to as "second bit line BL-2." First bit line BL-1 is an example of "first wiring." Second bit line BL-2 is an example of "second wiring."

[0057] The bit wire BL is formed from a wiring material that can be processed by, for example, reactive ion etching (RIE). The bit wire BL is formed from, for example, tungsten, molybdenum, chromium, or ruthenium.

[0058] As shown in Figure 6, each bit line BL has a first end 101a and a second end 101b in a single cross section along the X and Z directions. The first end 101a is the end on the side where the insulating layer 80 is located in the Z direction. The first end 101a is in contact with the first layer portion 81 of the insulating layer 80, which will be described later, in the Z direction. The second end 101b is the end on the opposite side from the first end 101a in the Z direction. That is, the second end 101b is the end on the side where the laminate 40 is located. The second end 101b is in contact with the via 71 in the Z direction.

[0059] In this embodiment, multiple bit lines BL are patterned by reactive ion etching. Therefore, for each bit line BL, the width W2 in the X direction of the second end 101b of the bit line BL is greater than the width W1 in the X direction of the first end 101a of the bit line BL. Each bit line BL has a trapezoidal shape in a single cross section along the X and Z directions, where the width in the X direction gradually increases as it approaches the side where the laminate 40 is located.

[0060] In this embodiment, each bit wire BL does not have a barrier metal layer. In other words, each bit wire BL has a first side end 101c and a second side end 101d located opposite the first side end 101c in a single cross section along the X and Z directions. The first side end 101c is in contact with the first insulating portion 91. The second side end 101d is in contact with the first insulating portion 91 at a different position from the first side end 101c. The interior of the bit wire BL is uniform from the first side end 101c to the second side end 101d. That is, the interior of the bit wire BL is continuously made of the same material (e.g., tungsten or molybdenum) from the first side end 101c to the second side end 101d.

[0061] <5.2 Insulating Layer> The insulating layer 80 is, for example, an insulating layer that suppresses the effects of misalignment of vias 73 relative to bit lines BL. The insulating layer 80 is positioned on the opposite side of the laminate 40 (i.e., the +Z direction side) relative to multiple bit lines BL. The insulating layer 80 has, for example, multiple first layers 81 and second layers 82. In Figure 6, for the sake of explanation, different hatching is applied to the first layers 81 and second layers 82. However, the first layers 81 and second layers 82 contain, for example, the same material and exist as a single unit. Therefore, the boundary between the first layers 81 and second layers 82 disappears, and they exist as one insulating layer 80. The insulating layer 80 is an example of a "first insulating layer".

[0062] <5.2.1 First Layer> Multiple first layers 81 are provided corresponding to multiple bit lines BL. The first layer 81 is the part of the insulating layer 80 that is responsible for, for example, electrical insulation (withstand voltage). The first layer 81 is located on the +Z side with respect to the corresponding bit line BL. The first layer 81 is laminated on the bit line BL. The first layer 81 extends in the Y direction along the surface of the bit line BL (see Figure 8). Multiple first layers 81 are spaced apart from each other in the X direction. The first layer 81 laminated on the first bit line BL-1 (first layer 81-1) is an example of the "first part of the first insulating layer". The first layer 81 laminated on the second bit line BL-2 (first layer 81-2) is an example of the "second part of the first insulating layer".

[0063] The first layer 81 includes, for example, an insulating material G2 containing nitrogen. The insulating material G2 is, for example, a film containing silicon and nitrogen (e.g., SiN), a film containing silicon, carbon and nitrogen (e.g., SiCN), or a film containing silicon, oxygen and nitrogen (e.g., SiON). When considering the etching selectivity ratio between the first insulating portion 91 and the first layer 81, which will be described later, silicon nitride (SiN) or silicon carbonitride (SiCN) is preferred as the insulating material G2.

[0064] Furthermore, when considering the interlayer capacitance between the wiring 72 and the bit line BL (when it is desirable to reduce the interlayer capacitance), silicon carbonitride (SiCN) is preferred over silicon nitride (SiN) as the insulating material G2. On the other hand, when further considering the etching selectivity ratio between the first insulating part 91 and the first layer part 81 (when it is desirable to increase the selectivity ratio), silicon nitride (SiN) is preferred over silicon carbonitride (SiCN) as the insulating material G2. The insulating material G2 is an example of a "second insulating material".

[0065] In this embodiment, the maximum width W3 in the X direction of the first layer 81 (for example, the same as the width W1 in the X direction of the first end 101a of the bit line BL) is greater than the thickness T1 in the Z direction of the first layer 81. Multiple first layers 81 are patterned together with the bit line BL by reactive ion etching, for example. Therefore, the width W3 in the X direction on the first end 101a side of the first layer 81 is greater than the width in the X direction on the second layer 82 side. In a single cross-section along the X and Z directions, the first layer 81 has a trapezoidal shape in which the width in the X direction gradually increases as it approaches the side where the laminate 40 is located.

[0066] In this embodiment, voids and film seams do not exist inside the first layer 81, except for unintended voids and film seams caused by variations in the manufacturing process. In other words, if the boundary B1 between the second layer 82 and the first insulating layer 91, described later, is extended in the X direction in a single cross section along the X and Z directions, and the first virtual line L1 is defined as such, then the interior of the insulating layer 80 is uniform in at least the region between the first virtual line L1 and the second bit line BL-2 in the Z direction (region R1 shown by a dashed line in Figure 6). That is, voids and film seams do not exist in this region R1, except for unintended voids and film seams caused by variations in the manufacturing process.

[0067] <5.2.2 Second Layer> The second layer 82 is a portion that functions as a stopper layer against the machining of holes, for example, when machining holes to form vias 73. The second layer 82 is located on the +Z side with respect to the plurality of first layers 81. That is, the second layer 82 is located on the opposite side of the plurality of bit lines BL with respect to the plurality of first layers 81. The second layer 82 extends at least in the X direction so as to span the plurality of first layers 81. In this embodiment, the second layer 82 extends along the X and Y directions. The thickness T2 of the second layer 82 in the Z direction is, for example, the same as the thickness T1 of the first layer 81 in the Z direction. In other words, the maximum width W3 of the first layer 81 in the X direction is greater than the thickness T2 of the second layer 82 in the Z direction. The second layer 82 is an example of a "third portion of the first insulating layer".

[0068] The second layer 82 includes, for example, the same insulating material G2 as the first layer 81. That is, the second layer 82 includes, for example, a film containing silicon and nitrogen (e.g., SiN), a film containing silicon, carbon and nitrogen (e.g., SiCN), or a film containing silicon, oxygen and nitrogen (e.g., SiON). In this embodiment, the first layer 81 and the second layer 82 are formed from the same material.

[0069] In this embodiment, the second layer 82 has a first surface S1 in contact with the first insulating portion 91 in the Z direction, and a second surface S2 located on the opposite side from the first surface S1. The second surface S2 is a flat surface along the X and Y directions. In other words, in a single cross section along the X and Z directions, the second surface S2 does not have depressions with a depth of more than 10 nm in the Z direction in the region that overlaps with the first wiring when viewed from the Z direction (i.e., the region R2 shown by the dashed line in Figure 6).

[0070] <5.3 First Insulation Section> The first insulating portion 91 is positioned on the -Z direction side with respect to the insulating layer 80. The first insulating portion 91 includes a portion 91a located between a plurality of bit lines BL in the X direction and a portion 91b located between a plurality of first layer portions 81 of the insulating layer 80 in the X direction. The portion 91b of the first insulating portion 91 is in contact with the first surface S1 of the second layer portion 82 of the insulating layer 80 in the Z direction. The first insulating portion 91 includes, for example, an insulating material G1 containing oxygen. The insulating material G1 is, for example, a film containing silicon and oxygen (e.g., SiO2). The insulating material G1 is an example of the "first insulating material".

[0071] <5.4 Wiring> Multiple wires 72 are positioned on the +Z side relative to the insulating layer 80. In the example shown in Figure 6, the wires 72 extend in the Y direction. Alternatively, the wires 72 may extend in the X direction.

[0072] Among the multiple wirings 72, wiring 72-1 connected to the first bit line BL-1 is an example of a "third wiring". Wiring 72-1 is positioned on the opposite side of via 73 from the first bit line BL-1. Wiring 72-1 is connected to via 73 and electrically connected to the first bit line BL-1 via via 73. In this application, "connected to a via (conductive part)" is not limited to cases where the via (conductive part) and the wiring are formed separately and connected, but also includes cases where the via (conductive part) and the wiring are formed integrally and are connected to each other.

[0073] Among the multiple wires 72, wire 72-2, which is not connected to the first bit line BL-1, is an example of a "fourth wire". Wire 72-2 is located, for example, next to wire 72-1 in the X direction.

[0074] In this embodiment, the wiring 72 includes a surface layer 72m and a main portion 72n provided inside the surface layer 72m. The surface layer 72m is, for example, a barrier metal layer. The surface layer 72m is formed of a conductive material, for example, titanium. The main portion 72n is formed of a conductive material, for example, a metallic material. The main portion 73n is formed of, for example, tungsten, molybdenum, or copper.

[0075] <5.5 Beer> Via 73 is an electrical connection that electrically connects wiring 72 and bit line BL (for example, wiring 72-1 and first bit line BL-1). Via 73 is positioned between wiring 72 and bit line BL in the Z direction and extends in the Z direction. Via 73 extends toward the insulating layer 80 from the side opposite to the first bit line BL-1 with respect to the insulating layer 80. Via 73 is an example of a "conductive portion". Via 73 has, for example, a first portion 73a and a second portion 73b.

[0076] The first portion 73a is the part of via 73 that overlaps with the bit line BL when viewed from the Z direction. The first portion 73a penetrates the second layer 82 and the first layer 81 of the insulating layer 80 in the Z direction and contacts the bit line BL. The first portion 73a electrically connects the wiring 72 and the bit line BL.

[0077] The second portion 73b, when viewed from the Z direction, is the portion of via 73 that is separated from the bit line BL. The second portion 73b is adjacent to the first portion 73a in the X direction. The second portion 73b penetrates the second layer 82 of the insulating layer 80 in the Z direction and contacts the first insulating portion 91. The -Z side end 73be of the second portion 73b is located, for example, at the boundary B1 between the second layer 82 and the first insulating portion 91 of the insulating layer 80. A step 73s in the Z direction is formed between the first portion 73a and the second portion 73b. The second portion 73b is separated from the unconnected second bit line BL-2 by a distance greater than the Z-direction thickness T1 of the first layer 81 of the insulating layer 80.

[0078] Figure 7 is an enlarged cross-sectional view of a portion of the memory cell array 11 shown in Figure 6, along the F7-F7 line. In this embodiment, the via 73 is elliptical in cross-section along the X and Y directions, with its minor axis in the X direction and its major axis in the Y direction. The step 73s between the first portion 73a and the second portion 73b extends in the Y direction along the boundary B2 between the first layer 81 and the first insulating portion 91.

[0079] Returning to Figure 6, the explanation continues. In this embodiment, the via 73 includes a surface layer 73m and a main portion 73n provided inside the surface layer 73m. The surface layer 73m is, for example, a barrier metal layer. The surface layer 73m is formed of a conductive material, for example, titanium. The main portion 73n is formed of a conductive material, for example, a metallic material. The main portion 73n is formed of, for example, tungsten, molybdenum, or copper.

[0080] <5.6 Second Insulation Section> The second insulating portion 92 is positioned on the +Z direction side with respect to the insulating layer 80. The second insulating portion 92 extends in the X and Y directions along the second surface S2 of the second layer portion 82 of the insulating layer 80. The second insulating portion 92 includes, for example, an insulating material G4 containing oxygen. The insulating material G4 is, for example, a film containing silicon and oxygen (e.g., SiO2). The insulating material G4 may be the same as or different from the insulating material G1. The insulating material G4 is an example of the "fourth insulating material".

[0081] Figure 8 is a cross-sectional view along the F8-F8 line of a portion of the memory cell array 11 shown in Figure 6. A portion of the second insulating portion 92 is located between the wiring 72 (e.g., wiring 72-1) and the second layer portion 82 of the insulating layer 80, away from the via 73. In this embodiment, the Z-direction thickness T4 of the second insulating portion 92 between the wiring 72 (e.g., wiring 72-1) and the second layer portion 82 of the insulating layer 80 is greater than the Z-direction thickness T3 of the insulating layer 80. The Z-direction thickness T3 of the insulating layer 80 is, for example, the sum of the Z-direction thickness T1 of the first layer portion 81 and the Z-direction thickness T2 of the second layer portion 82.

[0082] As shown in Figure 6, another portion of the second insulating portion 92 is positioned between the wiring 72 (e.g., wiring 72-2) and the second layer portion 82 of the insulating layer 80. The thickness T4 in the Z direction of the second insulating portion 92 between the wiring 72 (e.g., wiring 72-2) and the second layer portion 82 of the insulating layer 80 is greater than the thickness T3 in the Z direction of the insulating layer 80.

[0083] <6. Manufacturing method> Next, we will explain the manufacturing method of the semiconductor memory device 1. Figures 9 to 11 are cross-sectional views illustrating the manufacturing method of the semiconductor memory device 1. Note that the laminate 40, memory pillars 50, contacts 61, and vias 71 of the semiconductor memory device 1 can be manufactured by known methods. The following sections will describe the parts relating to the bit lines BL, insulating layer 80, wiring 72, and vias 73.

[0084] First, as shown in Figure 9(a), a structure 210 is formed, which includes a laminate 40, memory pillars 50, contacts 61, and vias 71. Next, a metal layer 211 is formed on the structure 210 by chemical vapor deposition (CVD). The metal layer 211 is plate-like, oriented in the X and Y directions. The metal layer 211 is the metal layer on which bit lines BL are formed in a later process. Next, an insulating film 212 is formed on the metal layer 211. The insulating film 212 is oriented in the X and Y directions. The insulating film 212 is the insulating film on which a plurality of first layers 81 are formed in a later process. Next, a material such as amorphous silicon is formed on the insulating film 212 to form a functional layer 213, which will be the basis for the hard mask.

[0085] Next, as shown in Figure 9(b), a predetermined process is performed on the functional layer 213, thereby forming a hard mask M corresponding to the arrangement of the bit lines BL from the functional layer 213.

[0086] Next, as shown in Figure 9(c), reactive ion etching is performed using a hard mask M to remove unwanted portions of the metal layer 211 and the insulating film 212. That is, the metal layer 211 is divided in the X direction by reactive ion etching, forming multiple bit lines BL from the metal layer 211. Also, the insulating film 212 is divided in the X direction along with the metal layer 211 by the same reactive ion etching, forming multiple first layers 81 from the insulating film 212. The first layer 81 stacked on the first bit line BL-1 is an example of a "first insulating film". The first layer 81 stacked on the second bit line BL-2 is an example of a "second insulating film".

[0087] Next, as shown in Figure 9(d), insulating portions 220 are provided to fill the multiple bit lines BL and the multiple first layer portions 81. The insulating portions 220 are formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4)).

[0088] Next, as shown in Figure 10(e), the upper end of the insulating portion 220 is removed by a planarization process (CMP: Chemical Mechanical Polishing), thereby forming the first insulating portion 91 from the insulating portion 220. As a result, the upper surface of the first insulating portion 91 lies on the same plane as the upper surfaces of the multiple first layer portions 81. This forms a structure 230 including multiple bit lines BL, multiple first layer portions 81, and the first insulating portion 91.

[0089] Next, as shown in (f) in Figure 10, a second layer 82 is formed so as to cover the upper surfaces of the multiple first layer portions 81 and the upper surface of the first insulating portion 91. As a result, an insulating layer 80 is formed by the multiple first layer portions 81 and the second layer portions 82. The second layer portion 82 is an example of a "third insulating film".

[0090] Next, as shown in (g) in Figure 10, a second insulating layer 92 is formed on the insulating layer 80. The second insulating layer 92 is formed using, for example, TEOS (tetraethyl orthosilicate (Si(OC2H5)4)).

[0091] Next, as shown in (h) in Figure 10, a mask (not shown) is provided, and holes H for providing vias 73 are formed in the second insulating portion 92. The holes H are formed, for example, by reactive ion etching. The etching to form the holes H is first performed under a first condition. The first condition is an etching condition in which the second insulating portion 92 is removed, but the insulating layer 80 is not removed as much as the second insulating portion 92. As a result, holes H1 are first formed that penetrate the second insulating portion 92 in the Z direction and reach the second surface S2 of the insulating layer 80.

[0092] Next, as shown in (i) in Figure 11, etching to form the hole H is performed by switching the etching conditions from the first condition to the second condition. The second condition is an etching condition in which the insulating layer 80 is removed, but the first insulating portion 91 is not removed compared to the insulating layer 80.

[0093] This forms a hole H containing a first portion Ha and a second portion Hb. The first portion Ha is the portion of the hole H that overlaps with the bit line BL when viewed from the Z direction. The first portion Ha penetrates the second layer 82 and the first layer 81 of the insulating layer 80 in the Z direction and reaches the surface of the bit line BL (e.g., the first bit line BL-1). The second portion Hb is the portion of the hole H that is outside the bit line BL when viewed from the Z direction. The second portion Hb penetrates the second layer 82 of the insulating layer 80 in the Z direction and remains on the upper surface of the first insulating portion 91. A step Hs exists in the Z direction between the first portion Ha and the second portion Hb.

[0094] Next, as shown in (j) in Figure 11, a mask (not shown) is provided, and grooves G for forming wiring 72 are formed by the upper surface of the second insulating portion 92. The grooves G are formed, for example, by reactive ion etching.

[0095] Next, as shown in (k) in Figure 11, a barrier metal layer 241 is formed on the inner surfaces of the groove G and the hole H, which will become the surface layer 72m of the wiring 72 and the surface layer 72m of the via 73. Next, conductive material is supplied into the groove G and the hole H, forming the main portion 72n of the wiring 72 and the main portion 73n of the via 73. As a result, the wiring 72 and the via 73 are formed inside the groove G and the hole H, respectively. At this time, the first portion 73a of the via 73 is formed in the first portion Ha of the hole H, and the second portion 73b of the via 73 is formed in the second portion Hb of the hole H.

[0096] <7. Advantages> As Comparative Example 1, we consider an example in which, instead of forming the bit line BL and the first layer portion 81 by reactive ion etching, a groove is formed on the upper surface of the insulating portion, and the bit line and insulating portion are formed inside this groove. In this Comparative Example 1, for example, a groove is formed on the upper surface of the insulating portion made of silicon oxide (SiO2), a bit line is formed in the lower part of the groove, and an insulating layer containing silicon nitride (SiN) is formed in the upper part of the groove and on the upper surface of the insulating portion. With such a configuration, a step can be provided at the bottom of the via, similar to the embodiment described above.

[0097] However, in the configuration of Comparative Example 1, in order to ensure withstand voltage (i.e., to ensure the distance between the via and the unconnected second bit line when the via is connected to the first bit line), a thick insulating layer is required in the groove. In this case, it becomes necessary to fill the space in the groove with a large amount of silicon nitride. However, silicon nitride generally has poor embedding properties, and voids tend to form inside the silicon oxide when silicon nitride is embedded in the groove. In addition, when silicon nitride is embedded in the groove, large depressions (depressions exceeding 10 nm) tend to form on the upper surface of the insulating layer region above the groove, sloping inward towards the groove. For this reason, it may be difficult to improve withstand voltage or other electrical properties in the configuration of Comparative Example 1.

[0098] Next, as Comparative Example 2, we consider a structure utilizing a thick silicon nitride layer. In this Comparative Example 2, first, a metal layer that will form the basis of the bit lines is formed, and a thick silicon nitride layer is formed on the metal layer. These metal layers and the thick silicon nitride layer are separated in a specific direction by reactive ion etching to form multiple bit lines and multiple first insulating parts provided on the multiple bit lines. The multiple first insulating parts correspond one-to-one with the multiple bit lines and have the thickness of the thick silicon nitride layer described above. Next, a second insulating part is formed that fills the multiple bit lines and the multiple first insulating parts. The second insulating part contains silicon oxide. Next, the portion of the multiple first insulating parts corresponding to the position where vias are formed is removed by reactive ion etching, and vias are formed in the space formed in the second insulating part by this removal, and wiring connected to the vias (hereinafter referred to as "specific wiring") is formed on the remaining multiple first insulating parts and second insulating parts. With this configuration, positional misalignment of vias relative to the bit lines is suppressed.

[0099] However, in the configuration of Comparative Example 2, the distance in the Z direction between the bit line and the specific wiring is determined by the thickness of the first insulating layer, which is made of silicon nitride. Therefore, a thick first insulating layer is required to ensure the distance between the bit line and the specific wiring. However, if the first insulating layer is thick, when the metal layer and the thick silicon nitride layer are divided into multiple parts by reactive ion etching, processing at a high aspect ratio is required, which may cause the thick first insulating layer to collapse. For this reason, it is difficult to increase the thickness of the first insulating layer. For this reason, it is difficult to improve the withstand voltage in the configuration of Comparative Example 2.

[0100] Furthermore, in the configuration of Comparative Example 2, each of the multiple first insulating parts is formed by reactive ion etching, resulting in a trapezoidal shape (hereinafter referred to as "pure tapered trapezoidal shape") where the width of the first insulating part widens as it approaches the bit line. As a result, when the first insulating part at the position where a via is to be formed is removed by reactive ion etching, and this removal creates a space for forming a via within the second insulating part, the space becomes a pure tapered trapezoidal shape following the outer shape of the first insulating part, resulting in a narrower entrance for supplying conductive material and a wider interior space. As a result, there is a possibility of poor embedding inside the via.

[0101] Furthermore, in the configuration of the second comparative example, since the space between the bit line and the specific wiring is filled with silicon nitride, the interlayer capacitance increases, which may lead to RC delay and other deteriorations in electrical characteristics.

[0102] On the other hand, in this embodiment, the insulating layer 80 includes a first layer portion 81 (first part) laminated on the first bit line BL-1 in the Z direction, a first layer portion 81 (second part) laminated on the second bit line BL-2 in the Z direction, and a second layer portion 82 (third part) located on the opposite side of the bit line BL from the plurality of first layer portions 81 and extending at least in the X direction. The first insulating portion 91 includes a portion 91b located between the plurality of first layer portions 81 of the insulating layer 80. The via 73 includes a first portion 73a that penetrates the second layer portion 82 and the first layer portion 81 of the insulating layer 80 in the Z direction and is in contact with the first bit line BL-1, and a second portion 73b that penetrates the second layer portion 82 of the insulating layer 80 in the Z direction and is in contact with the first insulating portion 91, with a step 73s between it and the first portion 73a.

[0103] With this configuration, the first layer 81 and the second layer 82 are provided, allowing the via 73 to have a step 73s at its bottom. This ensures that when the via 73 is connected to the first bit line BL-1, a distance is secured between the via 73 and the unconnected second bit line BL-2, thereby improving the voltage withstand capability. This improves the electrical characteristics of the semiconductor memory device 1.

[0104] Furthermore, according to the above configuration of this embodiment, compared to the configuration of Comparative Example 2, processing with a high aspect ratio is not required, and the collapse of the thick first insulating portion can be suppressed. In other words, according to the above configuration of this embodiment, the voltage resistance can be improved by a wiring process with low processing difficulty.

[0105] Furthermore, according to the above configuration of this embodiment, unlike the configuration of Comparative Example 2, it is not necessary to supply conductive material to the trapezoidal space of the pure tapered shape. Therefore, it is possible to suppress the occurrence of embedding defects inside the via 73.

[0106] Furthermore, according to the above configuration of this embodiment, unlike the configuration of Comparative Example 2, the thickness T1 of the first layer 81 (the thickness of the insulating part responsible for withstand voltage) can be adjusted according to the required withstand voltage. Therefore, by adjusting the thickness T1 of the first layer 81 according to the required withstand voltage, the distance between the bottom of the via 73 and the second bit line BL-2 can be adjusted.

[0107] Furthermore, according to the above configuration of this embodiment, by reactive ion etching, the insulating film 212 is divided in the X direction together with the metal layer 211, thereby forming multiple bit lines BL from the metal layer 211 and multiple first layer portions 81 from the insulating film 212. In this case, the process of embedding silicon nitride in the grooves becomes unnecessary. As a result, compared to the first comparative example, voids are less likely to occur inside the first layer portion 81, and depressions are less likely to occur on the second surface S2 of the second layer portion 82. As a result, compared to comparative example 1, the thickness T1 of the first layer portion 81 can be increased, and the withstand voltage can be easily ensured. This makes it possible to further improve the electrical characteristics of the semiconductor memory device 1.

[0108] In this embodiment, the first insulating portion 91 includes an insulating material G1 containing oxygen. The first layer portion 81 and the second layer portion 82 of the insulating layer 80 include an insulating material G2 containing nitrogen. With this configuration, depending on the etching selectivity ratio of the insulating material G1 and the insulating material G2, it becomes easier to form holes H in which vias 73 are provided, with a step difference Hs between the first portion Ha and the second portion Hb.

[0109] In this embodiment, the wiring 72 is positioned in the Z direction opposite to the first bit line BL-1 relative to the insulating layer 80 and is connected to the via 73. The second insulating portion 92 is positioned away from the via 73 and is located between the wiring 72 and the insulating layer 80, and includes an oxygen-containing insulating material G4. With this configuration, the second insulating portion 92, which includes the oxygen-containing insulating material G4, exists between the wiring 72 and the bit line BL. The oxygen-containing insulating material G4 (e.g., silicon oxide) has a lower dielectric constant than silicon nitride. Therefore, the interlayer capacitance between the wiring 72 and the bit line BL can be reduced compared to, for example, Comparative Example 2. This makes it possible to suppress, for example, RC delay and improve the electrical characteristics of the semiconductor memory device 1.

[0110] <8. Variation> Next, we will describe some modified examples. Note that, apart from the descriptions below, the configurations in each modified example are the same as those in the above embodiment.

[0111] <8.1 First Variation> Figure 12 is a cross-sectional view showing a portion of the memory cell array 11 of the first modified example. In the first modified example, the first layer 81 of the insulating layer 80 includes, for example, an insulating material G2 containing nitrogen. The insulating material G2 is, for example, one of silicon nitride (SiN), silicon carbonitride (SiCN), and silicon oxynitride (SiON).

[0112] On the other hand, the second layer 82 of the insulating layer 80 contains an insulating material G3 containing nitrogen. Insulating material G3 is a different insulating material from insulating material G2. Insulating material G3 is, for example, another one of silicon nitride (SiN), silicon carbonitride (SiCN), and silicon oxynitride (SiON). Insulating material G3 is an example of a "third insulating material".

[0113] With this configuration, the insulating layer 80 is formed by multiple insulating materials with different properties, which may improve the electrical characteristics of the semiconductor memory device 1.

[0114] <8.2 Second Variation> Figure 13 is a cross-sectional view showing a part of the memory cell array 11 of the second modified example. In the second modified example, the thickness T1 of the first layer 81 in the Z direction is greater than the thickness T2 of the second layer 82 in the Z direction. With this configuration, when high voltage resistance is required, further improvement in voltage resistance can be achieved. In this modified example, since the multiple first layers 81 are formed by the insulating film 212 being divided by reactive ion etching, even when a thick first layer 81 is provided, voids are less likely to occur inside the first layer 81, and depressions are less likely to occur on the second surface S2 of the second layer 82.

[0115] Although one embodiment and several variations have been described above, the embodiments and variations are not limited to the above example. For example, the thickness T1 in the Z direction of the first layer 81 may be smaller than the thickness T2 in the Z direction of the second layer 82.

[0116] The embodiments and modifications described above are applicable to semiconductor memory devices other than NAND flash memory (for example, NOR memory, MRAM (Magnetoresistive Random Access Memory), resistive random-access memory, and DRAM (Dynamic Random Access Memory)). Furthermore, the embodiments and modifications described above are applicable to semiconductor devices other than semiconductor memory devices (for example, processors such as CPUs (Central Processing Units) and various IC (Integrated Circuit) components). In this application, terms indicating order, such as "first" and "second," may be changed as appropriate.

[0117] According to at least one embodiment described above, the semiconductor memory device of the embodiment includes a first wiring, a second wiring, a first insulating layer, a first insulating portion, and a conductive portion. The first insulating layer includes a first portion, a second portion, and a third portion. The first portion is laminated on the first wiring. The second portion is laminated on the second wiring. The third portion is located on the opposite side of the first and second wiring from the first and second portions. The conductive portion includes a first portion that penetrates the third portion and the first portion of the first insulating layer and is in contact with the first wiring, and a second portion that penetrates the third portion of the first insulating layer and is in contact with the first insulating portion, and has a step between it and the first portion of the conductive portion. With such a configuration, electrical characteristics can be improved.

[0118] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0119] 1...Semiconductor memory device, BL...Bit line, BL-1...First bit line (first wiring), BL-2...Second bit line (second wiring), 40...Laminate, 41...Conductive layer (gate electrode layer), 42...Insulating layer (second insulating layer), 50...Memory pillar (columnar body), 51...Memory film, 52...Channel layer, 53...Insulating core, 72...Wiring, 72-1...Wiring (third wiring), 80...Insulating layer (first Insulating layer), 81...First layer, 81-1...First layer (first part, first insulating film), 81-2...Second layer (second part, second insulating film), 82...Second layer (third part, third insulating film), 91...First insulating part, 92...Second insulating part, 101c...First side edge, 101d...Second side edge, S1...First surface, S2...Second surface, Hole...H, 211...Metal layer, 212...Insulating film, L1...First virtual line.

Claims

1. A first wiring extending in the first direction, A second wiring separates from the first wiring in a second direction that intersects with the first direction, and a second wiring extends in the first direction, A first insulating layer comprising: a first portion laminated on the first wiring in a third direction intersecting the first and second directions; a second portion laminated on the second wiring in the third direction; and a third portion located on the opposite side of the first and second wiring from the first and second portions, and extending at least in the second direction so as to span the first and second portions; A first insulating portion including a portion located between the first and second portions of the first insulating layer in the second direction, A conductive portion extending toward the first insulating layer from the side opposite to the first wiring with respect to the first insulating layer, comprising: a first portion that penetrates the third and first portions of the first insulating layer in the third direction and is in contact with the first wiring; and a second portion that penetrates the third portion of the first insulating layer in the third direction and is in contact with the first insulating portion, having a step between it and the first portion of the conductive portion; Equipped with, The first insulating portion includes a first insulating material containing oxygen, The first and second portions of the first insulating layer include a second insulating material containing nitrogen, and the third portion of the first insulating layer includes a third insulating material that contains nitrogen and is different from the second insulating material. Semiconductor memory device.

2. A third wiring is positioned on the opposite side of the conductive portion from the first wiring, connected to the conductive portion, and extending in the first or second direction, Displaced between the third wiring and the first insulating layer at a position away from the conductive portion, the second insulating portion includes a fourth insulating material containing oxygen, It also has, The semiconductor memory device according to claim 1.

3. The first wiring has a first end located on the side of the first insulating layer in the third direction, and a second end located on the opposite side from the first end. The width of the second end in the second direction is greater than the width of the first end in the second direction. The semiconductor memory device according to claim 1.

4. The first wiring has a trapezoidal shape in a cross-section along the second and third directions, where the width in the second direction gradually increases from the first end to the second end. The semiconductor memory device according to claim 3.

5. A laminate comprising a plurality of gate electrode layers and a plurality of second insulating layers, arranged on the opposite side of the first and second wiring from the first insulating layer, wherein the plurality of gate electrode layers and the plurality of second insulating layers are alternately stacked one layer at a time in the third direction, A columnar body extending in the third direction within the laminate, comprising an insulating core, a channel layer disposed between the plurality of gate electrode layers and the insulating core, and a memory film disposed between the plurality of gate electrode layers and the channel layer, Furthermore, it is equipped with A semiconductor memory device according to any one of claims 1 to 4.

6. The first wiring is a bit wire electrically connected to the channel layer of the columnar body. The semiconductor memory device according to claim 5.

7. The first wiring has, in a cross-section along the second and third directions, a first side end in contact with the first insulating portion and a second side end located on the opposite side from the first side end. The interior of the first wiring is uniform from the first end to the second end. The semiconductor memory device according to claim 5.

8. In a cross-section along the second and third directions, if the boundary between the third portion of the first insulating layer and the first insulating portion is defined as a line extended in the second direction, then the interior of the first insulating layer is uniform in at least the region between the first virtual line and the second wiring in the third direction. The semiconductor memory device according to claim 5.

9. The third portion of the first insulating layer has a first surface in contact with the first insulating portion in the third direction and a second surface located on the opposite side from the first surface. In one cross-section along the second and third directions, the second surface does not have a depression in the region that overlaps with the second wiring when viewed from the first direction, with a depth in the third direction exceeding 10 nm. The semiconductor memory device according to claim 5.

10. A structure is formed that includes a first wiring extending in a first direction, a second wiring extending in the first direction and separating from the first wiring in a second direction intersecting the first direction, a first insulating film laminated on the first wiring in a third direction intersecting the first and second directions, a second insulating film laminated on the second wiring in the third direction, and a first insulating portion including a portion located between the first insulating film and the second insulating film in the second direction. By providing a third insulating film extending at least in the second direction on the first insulating film, the second insulating film, and the first insulating portion, a first insulating layer is formed including a first portion formed by the first insulating film, a second portion formed by the second insulating film, and a third portion formed by the third insulating film. A second insulating portion is formed on the first insulating layer. A hole that penetrates the second insulating portion and the first insulating layer in the third direction, comprising a first portion that penetrates the third portion and the first portion of the first insulating layer in the third direction and reaches the first wiring, and a second portion that penetrates the third portion of the first insulating layer in the third direction and reaches the first insulating portion, having a step between it and the first portion, A conductive part is formed inside the aforementioned hole. This includes, The first insulating portion includes a first insulating material containing oxygen, The first and second portions of the first insulating layer include a second insulating material containing nitrogen, and the third portion of the first insulating layer includes a third insulating material that contains nitrogen and is different from the second insulating material. A method for manufacturing a semiconductor device.

11. The first and second wirings are formed by the separation of metal layers along the first and second directions in the second direction by reactive ion etching. A method for manufacturing a semiconductor device according to claim 10.

12. The first insulating film and the second insulating film are formed by the insulating films formed on the metal layer along the first and second directions being separated in the second direction together with the metal layer by reactive ion etching. A method for manufacturing a semiconductor device according to claim 11.

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