Profile shaping for the retraction section of the control gate

Abstract

Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate of an etching process, forming a second portion of the first semiconductor layer characterized by a second etch rate that is slower than the first etch rate of the etching process, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is faster than the second etch rate. The processing method may further include etching an opening through the first semiconductor layer, the opening having a height and a width, the opening characterized by a change in width between a midpoint of the height of the opening and an end point of the height of the opening of about 5 Å or less.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims priority to U.S. Patent Application No. 17 / 073,060, filed on 16 October 2020, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0002] Technical field

[0002] This technology relates to semiconductor processing and materials. More specifically, this technology relates to a method for forming a control gate recess having a substantially straight contour. [Background technology]

[0003]

[0003] Integrated circuits are made possible by the process of forming intricately patterned material layers on the surface of a substrate. Creating patterned material on a substrate requires a controlled method for forming and removing exposed material. Stacked memories such as vertical or 3D NAND may involve forming a series of alternating layers of dielectric and semiconductor material into which numerous memory holes or openings are etched. The material properties of the layers, as well as the processing conditions and etching materials, can affect the uniformity and integrity of the formed structure. As the scale of devices continues to increase, conventional technologies may no longer be able to adequately process them.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. This technology addresses these and other needs. [Overview of the Initiative]

[0005]

[0005] The present invention includes embodiments of a semiconductor processing method for forming and etching a semiconductor layer having a substantially straight profile with respect to its recessed surface. In the embodiments, the semiconductor layer may be formed with increased etching resistance in the center of the layer compared to the edges of the layer. This etching resistance profile counteracts the tendency of dry etching operations to etch the center of the semiconductor layer at a faster rate than the edges of the layer that are in contact with adjacent layers made of other materials. When the embodiments of the semiconductor layer are etched, the profile of the recessed surface of the layer may be characterized by substantially less concavity than that of a conventional semiconductor layer having substantially uniform etching resistance throughout the depth of the layer. An example of application of the present invention includes the formation of a control gate recess in a multilayer oxide polysilicon stack used in floating gate 3D-NAND devices.

[0006]

[0006] Embodiments of the present technology include a semiconductor processing method comprising forming a first portion of a first semiconductor layer characterized by a first etching rate of an etching process. Embodiments of the method further include forming a second portion of the first semiconductor layer characterized by a second etching rate slower than the first etching rate of the etching process. In embodiments, the method may further include forming a third portion of the first semiconductor layer characterized by a third etching rate faster than the second etching rate. The method further includes etching through the first semiconductor layer to an opening having height and width. The opening may be characterized by a variation in width between the midpoint of the opening height and the endpoint of the opening being about 5 Å or less.

[0007]

[0007] In additional embodiments, the first semiconductor layer may contain polysilicon and may be formed between two dielectric layers. In further embodiments, the dielectric layer may be formed from silicon oxide. In yet another embodiment, the second portion of the first semiconductor layer may be characterized by a higher percentage of phosphorus atoms than the first or third portion of the semiconductor layer. In yet another embodiment, the second portion of the first semiconductor layer may be characterized by a higher stress amount than the first or third portion of the semiconductor layer. In yet another embodiment, the method may further include forming the second semiconductor layer after forming the first semiconductor layer. The second semiconductor layer may have an average etching rate of an etching process that is slower than the average etching rate of the first semiconductor layer. In embodiments, the second semiconductor layer may have at least three portions characterized by different etching rates of the etching process.

[0008]

[0008] The technology may further include a semiconductor processing method comprising flowing a deposition precursor into a substrate processing region of a semiconductor processing chamber. In embodiments, the deposition precursor may include a silicon-containing precursor and a doping precursor. The deposition precursor can deposit a first portion of a doped polysilicon layer on a substrate in the substrate processing region of the semiconductor processing chamber. Following the deposition of the first portion of the doped polysilicon layer, the flow rate ratio of the doping precursor to the silicon-containing precursor may be increased. The deposition precursor with the changed flow rate ratio can deposit a second portion of the doped polysilicon layer on the substrate. The second portion may be characterized by a slower etching rate in the etching process than the first portion of the doped polysilicon layer. The method may further include decreasing the flow rate ratio of the doping precursor to the silicon-containing precursor and depositing a third portion of the doped polysilicon layer on the substrate using the deposition precursor. The third portion of the polysilicon layer may be characterized by a faster etching rate in the etching process than the second portion of the doped polysilicon layer.

[0009]

[0009] In additional embodiments, the silicon-containing precursor may include silane (SiH4). In yet another embodiment, the doping precursor may include a phosphorus-containing precursor. In yet another embodiment, the method may include etching the openings through the doped polysilicon layer. The openings may have height and width, characterized by a variation in width between the midpoint of the opening height and the endpoint of the opening being less than about 5 Å. In additional embodiments, the substrate may include a first dielectric layer on which a first portion of the doped polysilicon layer is deposited. In yet another embodiment, the method may include depositing a second dielectric layer on the doped polysilicon layer.

[0010]

[0010] The technology may include embodiments of semiconductor structures. In embodiments, these structures may include at least one pair of layers comprising a dielectric layer and a semiconductor layer. In further embodiments, the semiconductor layer may include a first portion characterized by a first etching rate of the etching process, a second portion characterized by a second etching rate slower than the first etching rate, and a third portion of the semiconductor layer characterized by a third etching rate faster than the second etching rate.

[0011]

[0011] In additional embodiments, the dielectric layer may contain silicon oxide. In yet further embodiments, the semiconductor layer may contain doped polysilicon. In yet further embodiments, the second portion of the semiconductor layer may be characterized by a higher percentage of phosphorus atoms than the first or third portion of the semiconductor layer. In yet further embodiments, the second portion of the semiconductor layer may be characterized by a higher stress level than the first or third portion of the semiconductor layer. In yet further embodiments, at least one pair of layers in the semiconductor structure may be greater than about 50 pairs of layers.

[0012]

[0012] Such a technique can bring many advantages compared to conventional semiconductor processing methods and structures. For example, this method can generate a film characterized by a more straight retreat edge profile in etching a semiconductor layer. Additionally, as a result of the improved accuracy of the profile of the control gate by the operation of embodiments of this technology, semiconductor devices such as floating gate 3D-NAND devices with reduced critical dimensions can be manufactured. These embodiments and other embodiments, along with their many advantages and features, will be described in detail together with the following description and the accompanying drawings.

[0013]

[0013] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0014] [Figure 1] A top view of an exemplary processing system according to some embodiments of the present technology is shown. [Figure 2A] A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown. [Figure 2B] A schematic cross-sectional view of an exemplary processing chamber according to some embodiments of the present technology is shown. [Figure 3] Exemplary operations in a method of forming a semiconductor structure according to some embodiments of the present technology are shown. [Figure 4A] A schematic cross-sectional view of a substrate during a forming operation according to some embodiments of the present technology is shown. [Figure 4B] A schematic cross-sectional view of a substrate during a forming operation according to some embodiments of the present technology is shown. [Figure 4C] A schematic cross-sectional view of a substrate during a forming operation according to some embodiments of the present technology is shown. [Figure 4D] A schematic cross-sectional view of a substrate during a forming operation according to some embodiments of the present technology is shown. [Figure 5] A schematic cross-sectional view of a substrate during a forming operation according to additional embodiments of the present technology is shown. [Modes for carrying out the invention]

[0015]

[0020] Some drawings are included as schematic diagrams. Please understand that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Additionally, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may contain exaggerated material for illustrative purposes.

[0016]

[0021] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0017]

[0022] This technology includes a semiconductor processing system, structure, and method for forming substantially straight recessed surfaces in semiconductor layers located between dielectric layers. In embodiments, the recessed surfaces can form a portion of a recess etched from a channel opening aligned perpendicular to the layer to the edge of the semiconductor layer. The dielectric layers positioned between the semiconductor layers can form a surface opposing the recess, substantially perpendicular to the recessed surface. In embodiments, these sets of recesses can be formed in a set of semiconductor layers along the length of orthogonally aligned channel openings. In subsequent operations, material can be filled into the recesses to form the floating gate portion of a control gate. The substantially straight recessed surfaces etched into the semiconductor layers can define the shape of the interface between the floating gate portion and the rest of the control gate. In embodiments, the set of control gates formed along the length of the channel openings may be part of a floating gate 3D-NAND memory device.

[0018]

[0023] Embodiments of this technology address the problems of conventional methods for etching the recessed surface of semiconductor layers. In many conventional methods, the etching process results in uneven etching of the recessed surface between the center of the semiconductor layer and the edges of the layer that are in contact with adjacent dielectric layers. Uneven etching typically involves a faster etching rate of the semiconductor material in the center of the layer compared to the etching rate of the edges of the layer. As a result, the recessed surface is formed as a concave shape, with the center of the layer etched deeper than the edges. In some cases, the difference in depth of the recessed surface between the center of the surface and one of the edges of the surface can be about 10 Å or more, about 12.5 Å or more, about 15 Å or more, about 17.5 Å or more, about 20 Å or more, about 22.5 Å or more, about 25 Å or more, about 27.5 Å or more, about 30 Å or more, or more. The larger this difference in depth (i.e., the greater the concavity of the recessed surface), the greater the amount of space required for the control gate. In applications such as 3D-NAND memory devices, as device size continues to shrink, further size reduction may be limited by the concave shape of the control gate's recessed surface.

[0019]

[0024] Embodiments of this technology address these and other problems in forming recessed surfaces in semiconductor layers by forming layers at different etching rates in different parts of the layer. In embodiments, the tendency of the etching process to etch the center of the semiconductor layer faster than the edges is offset by forming layers with higher etching resistance in the center of the layer compared to the edges of the layer. In some embodiments, different etching rates are generated within a layer by changing the compositional or physical properties of one or more different parts of the layer. In embodiments, the center of the semiconductor layer may have a higher molar percentage of doping material than the edges of the layer. The doping material is selected such that the etching resistance of the semiconductor layer increases as the molar percentage of doping material increases. In additional embodiments, the center of the semiconductor layer may have higher stress than the edges of the layer. As the amount of stress increases, the etching resistance of the semiconductor layer increases. In further embodiments, the effects of increasing the etching rate of the etching process and increasing the etching resistance of a portion of the semiconductor layer balance each other out to produce an etching front with substantially the same etching rate at all points along the recessed surface. As a result, the recessed surface formed in the semiconductor layer is nearly straight. In the embodiment, the difference in depth of the recessed surface between the central part of the surface and one end of the surface may be about 5 Å or less, about 4 Å or less, about 3 Å or less, about 2 Å or less, about 1 Å or less, or less.

[0020]

[0025] The remaining disclosures periodically identify specific deposition and removal processes that utilize the disclosed techniques to manufacture certain structures such as memory, but it will be readily apparent that the systems and methods are equally applicable to several other processes and semiconductor structures. Therefore, the techniques should not be considered limited to use in conjunction with the described deposition and etching processes, or in the chamber alone. Furthermore, while exemplary chambers and systems are described to provide the basis for the techniques, it should be understood that the techniques can be applied to substantially any semiconductor processing chamber capable of enabling the described operations.

[0021]

[0026] Figure 1 shows a top view of one embodiment of a processing system 100 comprising a deposition chamber, an etching chamber, an annealing chamber, and other processing chambers according to an embodiment. In the drawing, substrates of various sizes are supplied by a pair of front-opening unified pods 102. The substrates are received by a robotic arm 104 and placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a to 108f, which are positioned in tandem sections 109a to 109c. A second robotic arm 110 can be used to transport the substrate wafer from the holding area 106 to the substrate processing chambers 108a to 108f and back from the substrate processing chambers 108a to 108f to the holding area 106. Each substrate processing chamber 108a to 108f can be equipped to perform many substrate processing operations, including dry etching, removal, atomic layer deposition, chemical vapor deposition, physical vapor deposition, general etching, pre-cleaning, degassing, orientation, and other substrate processing, as well as deposition processes described herein.

[0022]

[0027] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films on a substrate wafer. In one configuration, two pairs of processing chambers (e.g., 108c and 108d and 108e and 108f) may be used to deposit dielectric material onto the substrate, and a third pair of processing chambers (e.g., 108a and b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-108f) may be configured to etch the dielectric film on the substrate. Any one or more of the described processes may be carried out in one or more chambers separated from the manufacturing system shown in different embodiments. It will be understood that further configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for dielectric films are being considered in system 100.

[0023]

[0028] Figure 2A is a cross-sectional view of an exemplary processing chamber 200 according to several embodiments of the present technology. This figure may illustrate a system incorporating one or more aspects of the present technology, and / or a system that can be specifically configured to perform one or more operations according to embodiments of the present technology. Further details of the chamber 200, or the methods performed within a specifically configured chamber, will be described further below. While the chamber 200 may be used to form a film layer according to several embodiments of the present technology, it should be understood that the method can be similarly performed in any chamber in which film formation may occur. The processing chamber 200 may include a chamber body 202, a substrate support 204 disposed inside the chamber body 202, and a lid assembly 206 connected to the chamber body 202 and surrounding the substrate support 204 in a processing space 220. The substrate 203 may be provided to the processing space 220 via an opening 226 that can conventionally be sealed for processing, using a slit valve or door. The substrate 203 may be rested on the surface 205 of the substrate support during processing. The substrate support 204 may be rotatable along the axis 247 on which the shaft 244 of the substrate support 204 is located, as indicated by arrow 245. Alternatively, the substrate support 204 may be lifted to rotate as needed during the deposition process.

[0024]

[0029] A plasma profile modulator 211 may be located in the processing chamber 200 to control the plasma distribution across a substrate 203 placed on a substrate support 204. The plasma profile modulator 211 may include a first electrode 208 located adjacent to the chamber body 202, which can separate the chamber body 202 from other components of the lid assembly 206. The first electrode 208 may be part of the lid assembly 206 or a separate sidewall electrode. The first electrode 208 may be an annular or ring-shaped member and can be a ring electrode. The first electrode 208 may be a continuous member along the periphery of the processing chamber 200 surrounding the processing space 220, or may be discontinuous at locations selected as desired. The first electrode 208 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a plate electrode, such as in a secondary gas distributor.

[0025]

[0030] One or more isolators 210a, 210b, which may be dielectric materials such as ceramics or metal oxides, e.g., aluminum oxide and / or aluminum nitride, can electrically and thermally contact and isolate the first electrode 208 from the gas distributor 212 and the chamber body 202. The gas distributor 212 may define an opening 218 for distributing the processing precursor to the processing space 220. The gas distributor 212 may be connected to a first power source 242, such as an RF generator, RF power supply, DC power supply, pulsed DC power supply, pulsed RF power supply, or any other power supply that can be connected to the processing chamber. In some embodiments, the first power source 242 may be an RF power supply. In some embodiments, the first power source 242 may be an inductively coupled plasma coil extending around the inlet 214, which may be used to generate or deliver plasma effluent into the processing space 220.

[0026]

[0031] The gas distributor 212 may be a conductive gas distributor or a non-conductive gas distributor. Furthermore, the gas distributor 212 may be formed from conductive and non-conductive components. For example, the body of the gas distributor 212 may be conductive, while the faceplate of the gas distributor 212 is non-conductive. The gas distributor 212 may be powered by a first power source 242, as shown in Figure 2, or, in some embodiments, the gas distributor 212 may be grounded.

[0027]

[0032] The first electrode 208 may be connected to a first tuning circuit 228 that can control the grounding path of the processing chamber 200. The first tuning circuit 228 may include a first electronic sensor 230 and a first electronic controller 234. The first electronic controller 234 may be a variable capacitor or other circuit element, or may include them. The first tuning circuit 228 may be one or more inductors 232, or may include them. The first tuning circuit 228 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing space 220 during processing. In some embodiments as illustrated, the first tuning circuit 228 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 230. The first circuit leg may include a first inductor 232a. The second circuit leg may include a second inductor 232b connected in series with the first electronic control unit 234. The second inductor 232b may be located between the first electronic controller 234 and a node connecting both the first and second circuit legs to the first electronic sensor 230. The first electronic sensor 230 may be a voltage or current sensor and may be connected to the first electronic controller 234, and can control to some extent the closed loop of the plasma state in the processing space 220.

[0028]

[0033] The second electrode 222 may be connected to the substrate support 204. The second electrode 222 may be embedded within the substrate support 204 and connected to the surface of the substrate support 204. The second electrode 222 may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The second electrode 222 may be a tuning electrode and may be connected to a second tuning circuit 236 by a conduit 246, such as a cable having a selected resistance of, for example, 50 ohms, located within the shaft 244 of the substrate support 204. The second tuning circuit 236 may have a second electronic sensor 238 and a second electronic controller 240, which may be a second variable capacitor. The second electronic sensor 238 may be a voltage sensor or a current sensor and may be connected to the second electronic controller 240 for further control over plasma conditions in the processing space 220.

[0029]

[0034] A third electrode 224, which may be a bias electrode and / or an electrostatic chucking electrode, may be connected to a substrate support 204. The third electrode may be connected to a second power source 250 via a filter 248, which may be an impedance matching circuit. The second power source 250 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 250 may be RF bias power.

[0030]

[0035] The lid assembly 206 and substrate support 204 of Figure 1 can be used with any processing chamber for plasma processing or heat processing. During operation, the processing chamber 200 can control the plasma state in the processing space 220 in real time. The substrate 203 may be placed on the substrate support 204, and the processing gas may be flowed through the lid assembly 206 using the inlet 214 according to any desired flow plan. The gas can exit the processing chamber 200 through the outlet 252, which can be connected to a pump such as any exhaust pump, including a turbomolecular pump in some embodiments. Power may be connected to a gas distributor 212 to establish plasma in the processing space 220. In some embodiments, the substrate may be exposed to an electrical bias using a third electrode 224.

[0031]

[0036] When current is applied to the plasma in the processing space 220, a potential difference can be established between the plasma and the first electrode 208. A potential difference may also be established between the plasma and the second electrode 222. Next, the flow characteristics of the ground path, represented by two tuning circuits 228 and 236, can be adjusted using electronic controllers 234 and 240. Setpoints are given to the first tuning circuit 228 and the second tuning circuit 236, resulting in independent control of the deposition rate and the uniformity of plasma density from the center to the edges. In embodiments where both electronic controllers are variable capacitors, the electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0032]

[0037] Each of the tuning circuits 228 and 236 may have a variable impedance that can be adjusted using their respective electronic controllers 234 and 240. If the electronic controllers 234 and 240 are variable capacitors, the capacitance range of each variable capacitor and the inductances of the first inductor 232a and the second inductor 232b may be selected to provide an impedance range. This range may depend on the frequency and voltage characteristics of the plasma and may have a minimum value in the capacitance range of each variable capacitor. Thus, when the capacitance of the first electronic controller 234 is at its minimum or maximum, the impedance of the first tuning circuit 228 becomes high, which may result in a plasma shape with minimal air coverage or lateral coverage on the substrate support. As the capacitance of the first electronic controller 234 approaches the value that minimizes the impedance of the first tuning circuit 228, the air coverage of the plasma is maximized, effectively covering the entire working area of ​​the substrate support 204. If the capacitance of the first electronic control unit 234 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, reducing the air coverage of the substrate support. The second electronic control unit 240 can have a similar effect, increasing and decreasing the air coverage of the plasma on the substrate support, since its capacitance can be changed.

[0033]

[0038] Electronic sensors 230 and 238 may be used to tune their respective circuits 228 and 236 in a closed loop. Depending on the type of sensor used, a setpoint for current or voltage is attached to each sensor, and each sensor is provided with control software that determines the adjustment to the corresponding electronic controllers 234 and 240 to minimize deviation from the setpoint. As a result, the shape of the plasma can be selected and dynamically controlled during processing. The foregoing description is based on electronic controllers 234 and 240, which may be variable capacitors, but it should be understood that tuning circuits 228 and 236 with adjustable impedance can be provided using any electronic component having adjustable characteristics.

[0034]

[0039] Figure 2B is a schematic cross-sectional view of a plasma chamber 260 according to several embodiments of the present technology. This figure may illustrate a system that incorporates one or more aspects of the present technology and / or a system that can be specifically configured to perform one or more operations according to embodiments of the present technology, such as utilizing an inductively coupled plasma source. When using a chamber incorporating an inductively coupled plasma, additional plasma parameters can be controlled, which may affect the resulting film. For example, the chamber can have a lower processing pressure, which may affect the formation and characteristics of the film. The plasma chamber 260 may include a chamber body 262 and a lid assembly 264 that can be coupled to the chamber body. The lid assembly 264 may include a precursor delivery assembly 266 and a lid 268. The lid 268 may define an opening or vent 270 that can provide access to one or more processing precursor gases within the processing chamber.

[0035]

[0040] A precursor delivery assembly 266 is positioned on a lid 268 and may extend through an opening 270. The precursor delivery assembly 266 is connected to a precursor source 272, which can supply one or more processing precursors into the substrate processing area 275 by providing precursors through an inlet 274. The substrate 276 may be positioned within the substrate processing area 275 or extend within the substrate processing area 275 and be positioned on a substrate support 278 connected to a bias power supply or other materials or electrical components. One or more processing precursor gases may be discharged from the substrate processing area 275 via an exhaust ring 280 which may be connected to an exhaust pump 282. In some embodiments, the pump 282 may be a turbomolecular pump and may enable operating pressures of about 1 Torr or less, about 500 mTorr or less, about 100 mTorr or less, about 50 mTorr or less, about 20 mTorr or less, about 5 mTorr or less, or below.

[0036]

[0041] The lid assembly 264 may be coupled with one or more coils for energizing the precursor and generating plasma effluent. The coils may include several sets of coils, such as an inner coil 284, an intermediate coil 286, and an outer coil 288, all of which may be positioned close to the lid 268 and may extend, for example, around the opening 270. The inner coil 284 and the outer coil 288 may be electrically coupled to the RF power supply 290 via a matching circuit 292. Power applied from the RF power supply 290 to the outer coil 446 is inductively coupled via the lid 268 to generate plasma from the processing precursor provided from the precursor source 272 in the substrate processing area 275. The RF power supply 290 can supply current at several different frequencies to control the plasma density, such as the number of ions per unit volume in the plasma, and can define the density of the ion flux corresponding to the plasma density over time. A bias power supply can control the voltage between the substrate 276 and the generated plasma, and thus can control the energy and directionality of the ions, such as attracting ions toward the substrate. As a result, the plasma chamber 260 can independently control both ion flux and ion energy.

[0037]

[0042] The heater assembly 294 can be positioned adjacent to the lid 268, and in some embodiments, it can be positioned between the lid and the coil as shown. The heater assembly 294 can be secured to the lid 408 using a clamp member 296. The substrate surface can be maintained in a temperature range of about 100°C to about 500°C or higher. The plasma chamber 260 can be used in any number of embodiments to produce films, as will be further described below.

[0038]

[0043] Figure 3 shows an exemplary operation of processing method 300 according to several embodiments of the present technology. This method can be performed in various processing chambers, including the processing chamber 200 described above, which can be incorporated into, for example, system 100. Method 300 may include several optional operations, which may or may not be specifically associated with some embodiments of the method according to the present technology. For example, many operations, while described to provide a broader range of structure formation, may be performed by alternative methods that are not critical to the technology or that are easily understood. Method 300 can describe operations schematically shown in Figures 4A to 4D, which are described in conjunction with the operation of Method 300. It should be understood that the figures are only partial schematics, and the substrate may include any number of structural sections having the configuration shown in the figures, as well as alternative structural configurations that may still benefit from the operation of the present technology.

[0039]

[0044] Method 300 may include additional operations before commencing the enumerated operations. For example, additional processing operations may include forming a structure on the semiconductor substrate, including both forming and removing material. Pre-processing operations may be performed in the chamber in which Method 300 is performed, or processing may be performed in one or more other processing chambers before the substrate is transported to the semiconductor processing chamber in which Method 300 is performed. Nevertheless, Method 300 may optionally include transporting the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 200 described above, or another chamber that may include the components described above. The substrate may be a pedestal, such as a substrate support 204, and may be deposited on a substrate support that may be present in the processing area of ​​a chamber, such as the processing space 220 described above. An exemplary substrate 411 is shown in Figure 4A, which is or may include an embodiment of a substrate on which the operation according to this technique is performed.

[0040]

[0045] The substrate 411 may be any number of materials on which material can be deposited. The substrate may be a dielectric material containing silicon, germanium, silicon oxide, or silicon nitride, a metallic material, or any number of combinations of these materials, and may contain these materials, or may be the substrate 411, or a material formed on the substrate 411. In some embodiments, any processing operation, such as pretreatment, can be performed to prepare the surface of the substrate 411 for deposition. In addition, any other operation can be performed to remove material, such as reduction of native oxides or etching of the material, or to prepare one or more exposed surfaces of the substrate 411 for deposition.

[0041]

[0046] In the embodiments shown in Figures 4A to 4D, the first dielectric layer 413 may be formed on the substrate 411. In further embodiments, the first dielectric layer 413 may be a silicon oxide layer. The dielectric layer 413 may be formed from a silicon-containing precursor and / or an oxygen-containing precursor.

[0042]

[0047] In the embodiment, a semiconductor layer 415 may be formed on a dielectric layer 413. The dielectric layer 415 may be characterized by an etching resistance gradient to etching processes, including a peak etching resistance in the center of the layer and lower etching resistance at both ends of the layer closest to and furthest from the dielectric layer 413. In the embodiment, this etching resistance profile of the semiconductor layer 415 can withstand etching processes that etch the ends of the semiconductor layer at a faster rate than the center of the layer. In the embodiment, the balance between the etching rate of the etching process and the etching resistance profile of the semiconductor layer 415 results in an etching profile of the semiconductor layer that is substantially straight and recessed with little or no concavity.

[0043]

[0048] In embodiments of this technology, the etching resistance gradient within the semiconductor layer 415 can be generated by altering one or more properties of the layer during deposition. In embodiments, these properties may include a gradient of the atomic percentage of dopants within the layer. Generally, a higher atomic percentage of dopants in the semiconductor layer 415 correlates with higher etching resistance to the etching process used to recess the layer. In further embodiments, these properties may include a gradient of stress levels within the semiconductor layer 415. Generally, a higher stress level within the semiconductor layer 415 correlates with higher etching resistance to the etching process used to recess the layer.

[0044]

[0049] In some embodiments, the semiconductor layer 415 may include a gradient of atomic percentages of dopants incorporated into the layer. Embodiments of the gradient may include the dopants with the highest atomic percentages in the central part of the semiconductor layer 415, and the dopants with the lowest atomic percentages at opposing ends of the layer closest to the dielectric layer 413 and the layer furthest from the dielectric layer 413. In some embodiments, the gradient may be dopants whose atomic percentages vary continuously across the thickness of the semiconductor layer 415, but in additional embodiments, the gradient may include multiple portions, each characterized by dopants with substantially the same atomic percentage. In further embodiments, the multiple portions may include a midpoint through the thickness of the semiconductor layer 415 and a central portion that may be characterized by dopant atomic percentages higher than those of dopants in any other portion of the layer. In yet another embodiment, the multiple portions may include a pair of opposing ends, one closest to the dielectric layer 413 and the other furthest from the dielectric layer 413, at least one of which is characterized by dopants with the lowest atomic percentages in the semiconductor layer 415. In yet another embodiment, opposing edges of the semiconductor layer 415 may have dopants of the same or different atomic percentages. In the embodiment, the plurality of parts may include about three or more parts, about four or more parts, about five or more parts, about six or more parts, about seven or more parts, about eight or more parts, or more parts.

[0045]

[0050] In additional embodiments, the semiconductor layer 415 may include a plurality of portions that can be independently characterized in that portion by dopants with an atomic percentage gradient or by dopants with substantially the same atomic percentage. In some embodiments, the plurality of portions may include at least three portions in which the central portion of the semiconductor layer 415 is characterized by dopants with substantially the same atomic percentage, while the opposing ends are characterized by dopants with an atomic percentage gradient.

[0046]

[0051] Method 300 shown in Figure 3 includes one embodiment of a processing method for forming a semiconductor layer 415 from at least three portions. In this embodiment, the first portion 415a of the semiconductor layer may have lower etching resistance to etching than the second portion 415b of the semiconductor layer. In an additional embodiment, the third portion 415c of the semiconductor layer may have lower etching resistance to etching than the second portion 415b of the semiconductor layer. In yet another embodiment, the first portion 415a and the third portion 415c of the semiconductor layer may have substantially similar etching resistance to etching. In yet another embodiment, the first portion 415a, the second portion 415b, and the third portion 415c of the semiconductor layer may be independently characterized by an atomic percentage gradient of dopants or by dopants with substantially the same atomic percentages.

[0047]

[0052] Embodiments of Method 300 include forming a first portion of a semiconductor layer on a substrate in operation 305. As shown in Figure 4A, the first portion 415a of the semiconductor layer may be formed on a dielectric layer 413 present on the substrate 411. In embodiments, the semiconductor layer may be a silicon-containing layer such as polysilicon. In further embodiments, the semiconductor layer may be a doped polysilicon layer. In even further embodiments, the initial and subsequent portions of the semiconductor layer may be formed by chemical vapor deposition of a portion of the layer on the substrate. In embodiments, chemical vapor deposition may include generating a plasma from a deposition precursor and depositing the initial and subsequent portions of the semiconductor layer from the emissions of the deposition plasma.

[0048]

[0053] In further embodiments, the deposition of the initial and subsequent portions of the semiconductor layer on the substrate may include injecting a deposition precursor into the substrate processing area of ​​a semiconductor processing chamber in which the substrate is present. The deposition precursor may include one or more silicon-containing precursors and one or more doping precursors. In embodiments, the silicon-containing precursor may include silicon-hydrogen-containing precursors such as silane (SiH4) and disilane (Si2H6). In further embodiments, the doping precursor may include phosphorus-containing doping precursors such as phosphine (PH3). In yet another embodiment, the doping precursor may include nitrogen-containing doping precursors such as ammonia (NH3) and nitrous oxide (N2O). In yet another embodiment, the additional deposition precursor may include carrier gases such as He, Ar, and molecular nitrogen (N2). The additional deposition precursor may include molecular hydrogen (H2).

[0049]

[0054] In one embodiment, a first portion 415a of the semiconductor layer may be formed by flowing a deposition precursor into a semiconductor processing chamber at a first flow rate ratio of doping precursor to silicon-containing precursor. In a further embodiment, this first flow rate ratio may be lower than a second flow rate ratio used to deposit a second portion of the semiconductor layer. In one embodiment, the first flow rate ratio of doping precursor to silicon-containing precursor may be about 1:1 or less, about 1:2 or less, about 1:3 or less, about 1:4 or less, about about 1:5 or less, about 1:6 or less, about 1:7 or less, about 1:8 or less, about 1:9 or less, about 1:10 or less, or lower. In additional embodiments, the flow rate of the doping precursor during the deposition of the first portion of the semiconductor layer may be about 5000 sccm or less, about 4000 sccm or less, about 3000 sccm or less, about 2000 sccm or less, about 1000 sccm or less, about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 200 sccm or less, about 100 sccm or less, or less. In further additional embodiments, the flow rate of the silicon-containing precursor may be about 100 sccm or more, about 250 sccm or more, about 500 sccm or more, about 750 sccm or more, about 1000 sccm or more, or more. In some embodiments, the flow rate of the silicon-containing precursor may remain constant during the deposition of the semiconductor layer. In additional embodiments, the flow rate of the silicon-containing precursor may change with changes in the flow rate ratio of the doping precursor to the silicon-containing precursor. In further embodiments, the flow rate of the silicon-containing precursor may vary, while the flow rate of the dopant precursor remains constant throughout the deposition of the semiconductor layer. In even further embodiments, the deposition precursor may further contain a carrier gas characterized by a flow rate of about 500 sccm or more, about 1000 sccm or more, about 1500 sccm or more, about 2000 sccm or more, or higher.

[0050]

[0055] In additional embodiments, the first portion 415a of the semiconductor layer may be formed in a period of about 90 seconds or less, about 60 seconds or less, about 45 seconds or less, about 30 seconds or less, or less. In yet another embodiment, the first portion 415a of the semiconductor layer may be formed to a thickness of about 500 Å or less, about 400 Å or less, about 200 Å or less, about 100 Å or less, or less.

[0051]

[0056] Embodiments of Method 300 may further include forming a second portion of the semiconductor layer on a substrate in operation 310. As shown in Figure 4B, the second portion 415b of the semiconductor layer may be formed on a first portion 415a of the semiconductor layer that has been pre-deposited on the substrate 411. In embodiments, the second portion 415b of the semiconductor layer may be formed under the same deposition conditions as the first portion 415a of the semiconductor layer, except for a change in the flow rate ratio of the doping precursor to the silicon-containing precursor. In embodiments, the second flow rate ratio of the doping precursor to the silicon-containing precursor used to deposit the second portion 415b of the semiconductor layer may be greater than the first flow rate ratio used to deposit the first portion 415a of the semiconductor layer. In further embodiments, the second flow rate ratio of the doping precursor to the silicon-containing precursor may be about 1:10 or more, about 1:9 or more, about 1:8 or more, about 1:7 or more, about 1:6 or more, about 1:5 or more, about 1:4 or more, about 1:3 or more, about 1:2 or more, about 1:1 or more, or greater than these. In additional embodiments, the increase in the second flow rate ratio compared to the first flow rate ratio may be about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, or greater than these. In embodiments, the change in the flow rate ratio of the doping precursor to the silicon-containing precursor during the deposition of the first portion 415a and the second portion 415b of the semiconductor layer may be a continuous change or a stepwise change.

[0052]

[0057] In additional embodiments, the flow rate of the doping precursor during the deposition of the second portion of the semiconductor layer may be about 100 sccm or more, about 250 sccm or more, about 300 sccm or more, or about 400 sccm, about 500 sccm or more, about 1000 sccm or more, or more. In yet additional embodiments, the flow rate of the silicon-containing precursor may be about 1000 sccm or less, about 750 sccm or less, about 500 sccm or less, about 250 sccm or less, about 100 sccm or less, or less.

[0053]

[0058] In additional embodiments, the second portion 415b of the semiconductor layer may be formed over a period of about 1 second or more, about 10 seconds or more, about 30 seconds or more, about 45 seconds or more, about 60 seconds or more, about 90 seconds or more, or longer. In yet another embodiment, the second portion 415b of the semiconductor layer may be formed to a thickness of about 50 Å or more, about 100 Å or more, about 200 Å or more, about 300 Å or more, about 300 Å or more, about 400 Å or more, about 500 Å or more, about 1000 Å or more, or longer.

[0054]

[0059] Embodiments of Method 300 may further include forming a third portion of the semiconductor layer on a substrate in operation 315. As shown in Figure 4C, the third portion 415c of the semiconductor layer may be formed on a second portion 415b of the semiconductor layer that has been pre-deposited on the substrate 411. In embodiments, the third portion 415c of the semiconductor layer may be formed under the same deposition conditions as the first portion 415a and the second portion 415b of the semiconductor layer, except for another change in the flow rate ratio of the doping precursor to the silicon-containing precursor. In embodiments, the third flow rate ratio of the doping precursor to the silicon-containing precursor used to deposit the second portion 415b of the semiconductor layer may be smaller than the second flow rate ratio used to deposit the second portion 415b of the semiconductor layer. In further embodiments, the third flow rate ratio of the doping precursor to the silicon-containing precursor may be about 1:1 or less, about 1:2 or less, about 1:3 or less, about 1:4 or less, about 1:5 or less, about 1:6 or less, about 1:7 or less, about 1:8 or less, about 1:9 or less, about 1:10 or less, or less. In embodiments, the change in the flow rate ratio of the doping precursor to the silicon-containing precursor during the deposition of the first portion 415a and the second portion 415b of the semiconductor layer may be a continuous change or a stepwise change. In additional embodiments, the decrease in the third flow rate ratio compared to the second flow rate ratio may be about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, or more. In some embodiments, the change in the flow rate ratio of the doping precursor to the silicon-containing precursor during the deposition of the second portion 415b and the third portion 415c of the semiconductor layer may be a continuous change or a stepwise change. In some embodiments, the third flow rate ratio may be the same as the first flow rate ratio.

[0055]

[0060] In additional embodiments, the flow rate of the doping precursor during the deposition of the third portion of the semiconductor layer may be about 500 sccm or less, about 400 sccm or less, about 300 sccm or less, about 200 sccm or less, about 100 sccm or less, about 50 sccm or less, or less. In yet additional embodiments, the flow rate of the silicon-containing precursor may be about 100 sccm or more, about 250 sccm or more, about 500 sccm or more, about 750 sccm or more, about 1000 sccm or more, or more.

[0056]

[0061] In additional embodiments, the third portion 415c of the semiconductor layer may be formed in a period of about 90 seconds or less, about 60 seconds or less, about 45 seconds or less, about 30 seconds or more, or less. In yet other embodiments, the third portion 415c of the semiconductor layer may be formed to a thickness of about 500 Å or less, about 400 Å or less, about 200 Å or less, about 100 Å or less, or less.

[0057]

[0062] In some embodiments of this technology, different portions of a semiconductor layer may be formed at different stress levels. These different stress levels may correlate with different etching rates in each portion of the layer. In some embodiments, an increase in the stress level in a deposited portion of the semiconductor layer may correlate with an increase in the etching resistance (i.e., a decrease in the etching rate) of that portion. In additional embodiments, instead of changing the atomic percentage of the dopant to change the etching rate, the stress level of the deposited portion of the semiconductor layer may be changed. In further embodiments, both the stress level and the atomic percentage of the dopant may be used to form portions of the semiconductor layer characterized by different etching rates.

[0058]

[0063] In embodiments, a portion of the semiconductor layer including the depth at the midpoint of the level may be characterized by a higher stress level than the portion of the semiconductor layer at the edge of the level. Referring to Figures 4A to 4D, embodiments may include a second portion 415b of the semiconductor layer characterized by a higher stress level than the first portion 415a or the third portion 415c of the level. In additional embodiments, the percentage difference in stress levels between the second portion and the first or third portion may be about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, or more. In yet another embodiment, the second portion 415b of the level may have a stress level of about 100 MPa or more, about 500 MPa or more, about 1 GPa or more, about 1.5 GPa or more, or more. In further embodiments, the semiconductor-level first portion 415a and third portion 415 may have stress levels of about 1 GPa or less, about 500 MPa or less, about 100 MPa or less, about 50 MPa or less, about 10 MPa or less, or lower.

[0059]

[0064] In some embodiments, the pressure in the processing chamber during semiconductor layer formation may be about 30 Torr or less, about 20 Torr or less, about 15 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or lower. In some embodiments, such as a processing chamber including an inductively coupled plasma source and / or turbomolecular pump, the processing pressure may be further about 100 mTorr or less, about 90 mTorr or less, about 80 mTorr or less, about 70 mTorr or less, about 60 mTorr or less, about 50 mTorr or less, about 40 mTorr or less, about 30 mTorr or less, about 20 mTorr or less, about 10 mTorr or less, about 5 mTorr or less, about 2 mTorr or less, or lower.

[0060]

[0065] In the embodiment, the temperature of the substrate during semiconductor layer formation may be about 200°C or higher, and may be about 250°C or higher, about 300°C or higher, about 350°C or higher, about 400°C or higher, about 450°C or higher, about 500°C or higher, or higher. Various plasma outputs and other chamber conditions can also be changed during semiconductor layer formation.

[0061]

[0066] Embodiments of Method 300 may optionally include forming a dielectric layer on the deposited semiconductor layer in operation 320. In the embodiment shown in Figure 4D, the deposited dielectric layer is shown as a second dielectric layer 420 formed on the semiconductor layer 415. In embodiments, the first dielectric layer 413 and the second dielectric layer 420 may be formed by introducing a dielectric deposition precursor into the substrate processing area of ​​a semiconductor processing chamber. In embodiments, these dielectric deposition precursors may include silicon-containing precursors, in particular silicon-containing precursors such as silane (SiH4), disilane (Si2H6), organosilane, silicon tetrafluoride (SiF4), silicon tetrachloride (SiCl4), dichlorosilane (SiH2Cl2), and tetraethyl orthosilicate (TEOS). Dielectric deposition precursors may also include oxygen-containing precursors used in any operation as described throughout this technique, which may include O2, N2O, NO2, O3, H2O, and oxygen-containing precursors that can be used for silicon oxide film formation or other film formation. In some embodiments, the dielectric precursor may include oxygen-containing precursors, particularly nitrogen-containing precursors such as N2, N2O, NO2, NH3, and N2H2. In any of the formation operations, one or more additional precursors may be included, such as inert precursors that may include Ar, He, Xe, Kr, nitrogen, hydrogen, or other precursors.

[0062]

[0067] In some embodiments, the dielectric layers 413 and 420 may be silicon oxide layers. In additional embodiments, the properties of the layers can be enhanced by adjusting the stoichiometric composition of silicon oxide within the layers. By enhancing the silicon-like properties of the layers, structural integrity can be improved compared to other silicon oxide layers. In some embodiments, the supply of the dielectric deposition precursor can be modified from standard silicon oxide deposition conditions in order to increase the stoichiometric composition ratio of the dielectric layers formed. For example, in some embodiments, the silicon-to-oxide atomic ratio can be as high as 1:7 during some processing. In the formation methods according to some embodiments of the Art, the silicon-to-oxide ratio may be adjusted to about 1:7 or less, about 1:6 or less, about 1:5 or less, about 1:4 or less, about 1:3 or less, about 1:2 or less, about 1:1 or less, or lower. By providing a formation process that is relatively oxygen-deficient compared to other formation processes, the ratio of oxygen to silicon in the resulting film may be approximately 2.0:1 or less, approximately 1.9:1 or less, approximately 1.8:1 or less, approximately 1.7:1 or less, approximately 1.6:1 or less, approximately 1.5:1 or less, or even lower.

[0063]

[0068] By increasing the incorporation of silicon into the dielectric layer, the Young's modulus of the modified oxide layer can be increased to approximately 100 GPa or higher, and can be increased to approximately 110 GPa or higher, approximately 120 GPa or higher, approximately 125 GPa or higher, approximately 130 GPa or higher, approximately 135 GPa or higher, approximately 140 GPa or higher, approximately 145 GPa or higher, approximately 150 GPa or higher, approximately 155 GPa or higher, approximately 160 GPa or higher, or even higher. In addition, the hardness of the dielectric layer may be increased to approximately 12 GPa or higher, and can be increased to approximately 13 GPa or higher, approximately 14 GPa or higher, approximately 15 GPa or higher, approximately 16 GPa or higher, approximately 17 GPa or higher, or even higher.

[0064]

[0069] In some embodiments, the dielectric layers 413 and 420 may function to electrically insulate the semiconductor structure formed within the semiconductor layer 415. In further embodiments, the dielectric layers 413 and 420 may have an electrical conductivity of approximately 1 × 10⁻¹⁶ -6 A / cm 2 Below, approximately 8×10 -7A / cm 2 Hereinafter, about 5×10 -7 A / cm 2 Hereinafter, about 2×10 -7 A / cm 2 Hereinafter, about 1×10 -7 A / cm 2 Hereinafter, about 9×10 -8 A / cm 2 Hereinafter, about 8×10 -8 A / cm 2 Hereinafter, about 7×10 -8 A / cm 2 Hereinafter, about 6×10 -8 A / cm 2 Hereinafter, about 5×10 -8 A / cm 2 Hereinafter, about 4×10 -8 A / cm 2 Hereinafter, about 3×10 -8 A / cm 2 Hereinafter, about 2×10 -8 A / cm 2 Hereinafter, about 1.5×10 -8 A / cm 2 Hereinafter, about 1.2×10 -8 A / cm 2 Hereinafter, about 1×10 -8 A / cm 2 Hereinafter, it may be characterized by a leakage current density maintained at or below this value.

[0065]

[0070] In an additional embodiment, the dielectric layers 413 and 420 may be characterized by a breakdown voltage of about 6.0 MV / cm or more, about 7.0 MV / cm or more, about 7.5 MV / cm or more, about 7.5 MV / cm or more, about 8.0 MV / cm or more, about 8.5 MV / cm or more, about 9.0 MV / cm or more, about 9.5 MV / cm or more, about 10.0 MV / cm or more, about 10.5 MV / cm or more, about 11.0 MV / cm or more, about 11.5 MV / cm or more, about 12.0 MV / cm or more, about 12.5 MV / cm or more, or above this value. As a result, the present technology can produce dielectric layers that can be characterized by strong resistance to deformation and breakdown during wet etching or other removal processes.

[0066]

[0071] Embodiments of method 300 may further include etching the opening through the semiconductor layer in operation 325. In the embodiment shown in Figure 4D, the aforementioned portion of the semiconductor layer 415 is shown as a single layer characterized by a higher percentage of dopants in the central part of the layer than at the edges of the layer in contact with the dielectric layers 413 and 420. The opening 422 formed in the semiconductor layer 415 is also formed in the dielectric layers 413 and 420 flanking the semiconductor layer 415.

[0067]

[0072] In embodiments, the opening 422 etched into the semiconductor layer 415 also includes recessed portions extending into the region between the dielectric layer 413 and the dielectric layer 420. Each recessed portion may include a pair of opposing sides defined by the opposing surfaces of the dielectric layers 413 and 420. Each recessed portion may also include sides formed by the etching front of the etching operation that forms the recessed portion. In embodiments, each recessed portion may be described as an opening having a height that can be measured as the extent to which the semiconductor layer 415 has been etched back from the perpendicularly aligned opening 422, and a width that can be measured as the distance between the opposing surfaces of the dielectric layers 413 and 420.

[0068]

[0073] In further embodiments, the sides of these recessed openings formed by the etching front may be substantially straight, with little or no concavity between the midpoint and the edge of the side. In yet another embodiment, the sides of these recessed openings formed by the etching front are characterized by a variation in width between the midpoint and any edge of the side being about 5 Å or less, about 4 Å or less, about 3 Å or less, about 2 Å or less, about 1 Å or less, or less. The reduction in concavity of the sides of the recessed openings formed by the etching front allows for a reduction in the size of the device including the interface between the side and the unetched portion of the semiconductor layer 415. This size reduction removes the limitations on reducing the size of the device including the interface, making it possible to increase the device density on the substrate.

[0069]

[0074] In some embodiments, the etching operation 325 may include selective etching of the semiconductor layer 415 on adjacent dielectric layers 413 and 420. In additional embodiments, the removal of a portion of the semiconductor layer 415 may include a silicon removal operation performed using one or more precursors, including a fluorine-containing precursor, and may also include a hydrogen-containing precursor, and one or more additional precursors. The precursors may include an inert gas or noble gas such as helium or argon, or other materials that facilitate the etching process. In some embodiments, one or both of the fluorine-containing precursor or the hydrogen-containing precursor can be flowed into a remote plasma region of the dry etching chamber. For example, the remote plasma region may be fluidly connected to the processing region containing the substrate, but this region may be physically separated by a showerhead or the like that can act as an electrode within the remote plasma region. The remote plasma system may also be connected outside the chamber to supply plasma emissions into the chamber.

[0070]

[0075] The plasma emissions of the precursor are delivered to the processing area and come into contact with the semiconductor layer 415, allowing for the selective removal of portions of the layers on the adjacent dielectric layers 413 and 420. In embodiments, the processing conditions may consist of one or more methods that provide selective etching of silicon to the oxide, characterized by a selectivity of about 100:1 or greater. For example, the processing chamber, pedestal, or substrate may be maintained at a temperature between about 40°C and about 150°C during etching or removal operations, and the pressure in the processing chamber may be maintained, for example, below about 12 Torr. Furthermore, in some embodiments, the flow rates of the fluorine-containing precursor and / or hydrogen-containing precursor may be adjusted to maintain the flow rate ratio between the precursors.

[0071]

[0076] For example, in some embodiments, the removal can be carried out while maintaining an atomic flow ratio of hydrogen to fluorine of about 10:1 or greater. Such a process can maintain a hydrogen-terminated surface, which may allow fluorine to selectively remove silicon on the oxide. Exemplary hydrogen-containing precursors may include one or more hydrogen-containing precursors, such as diatomic hydrogen, ammonia, hydrocarbons, or other hydrogen-containing precursors. Exemplary fluorine-containing precursors may include, in non-limiting examples, one or more precursors containing atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, fluorinated hydrocarbons, sulfur hexafluoride, or xenon difluoride. Subsequently, the silicon layer can be removed, and further processing may be carried out, including the deposition of a floating gate semiconductor material into a recessed region formed by the etching operation.

[0072]

[0077] In some embodiments of this technology, additional processing operations can be performed following the etching operation. In embodiments, the annealing operation may be performed at temperatures of, for example, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, or above. Annealing can be performed using a heated precursor, for example, an inert precursor containing nitrogen.

[0073]

[0078] In embodiments of the semiconductor structure 400 shown in Figures 4A to 4D, the thickness of the layers of structure 400 may be within a range of thicknesses for manufacturing memory or other semiconductor structures, or may include such a range. For example, in some embodiments, the semiconductor layer 415 and the dielectric layers 413 and 420 may be about 100 nm or less, about 90 nm or less, about 80 nm or less, about 70 nm or less, about 60 nm or less, about 50 nm or less, about 45 nm or less, about 40 nm or less, about 35 nm or less, about 30 nm or less, about 25 nm or less, about 20 nm or less, about 15 nm or less, about 10 nm or less, or less. In some embodiments, the layers may be substantially the same thickness, but in additional embodiments, the layers may have different thicknesses. In some embodiments, the dielectric layers 413 and 420 may be thick enough to limit crosstalk or leakage between the developed cells. In additional embodiments, the semiconductor layer 415 may be characterized by being less than or equal to the approximate thickness of one or both of the dielectric layers 413 and 420.

[0074]

[0079] Additional embodiments of this technology may include semiconductor structures having two or more pairs of layers, including dielectric layers and semiconductor layers. One embodiment of these structures is shown in Figure 5, which shows a structure 500 comprising multiple pairs of dielectric layers 513 and semiconductor layers 515 formed on a substrate 511. In the illustrated embodiment, an opening 522 is formed through the stacking of the pairs of layers. The semiconductor layer 515 recedes from the opening 522, forming a recessed opening between adjacent dielectric layers 513. In the embodiment, the number of pairs of layers 513 and 515 in structure 500 may be about 10 pairs or more, about 25 pairs or more, about 50 pairs or more, about 100 pairs or more, about 200 pairs or more, or more.

[0075]

[0080] In further embodiments, the sides of these recessed openings formed by the etching front of the semiconductor layer 515 may be substantially straight, with little or no concavity between the midpoint and the edge of the side. In yet another embodiment, the sides of these recessed openings formed by the etching front are characterized by a variation in width between the midpoint and any edge of the side being about 5 Å or less, about 4 Å or less, about 3 Å or less, about 2 Å or less, about 1 Å or less, or less. The reduction in concavity of the sides of the recessed openings formed by the etching front allows for a reduction in the size of the device including the interface between the side and the unetched portion of the semiconductor layer 515. This size reduction eliminates limitations on reducing the size of the device including the interface, making it possible to increase the device density on the substrate.

[0076]

[0081] The above description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0077]

[0082] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be considered to limit the scope of the Art. In addition, while methods or processes may be described sequentially or stepwise, it should be understood that operations may be performed simultaneously or in an order different from that described.

[0078]

[0083] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intermediary value between the upper and lower limits of that range is, of course, specifically disclosed down to the smallest unit of the lower limit. Any narrow range between any listed or unlisted intermediary values ​​within the listed range, and any other listed or intermediary values ​​within that listed range, are also included. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which either or both limit values ​​are included in a narrower range, or neither is included in a narrower range, is further included in this art and covers any limit values ​​that are specifically excluded from the listed range. If a listed range contains one or more limit values, it also includes ranges that exclude any or both of these included limit values.

[0079]

[0084] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” refers to multiple such precursors, and “the layer” refers to one or more layers and equivalents known to those skilled in the art, and the same applies to other forms.

[0080]

[0085] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integer values, components, or operations, but not to exclude the presence or addition of one or more other features, integer values, components, operations, behaviors, or groups.

Claims

1. A semiconductor processing method, To form a first portion of a first semiconductor layer characterized by a first etching rate of the etching process, A second portion of the first semiconductor layer is formed on the first portion of the first semiconductor layer, characterized by a second etching rate slower than the first etching rate of the etching process. A third portion of the first semiconductor layer is formed on the second portion of the first semiconductor layer, characterized by a third etching rate faster than the second etching rate. Etching an opening through the first semiconductor layer, wherein the opening has a height and a width, and the opening is characterized by the change in width between the midpoint of the height of the opening and the endpoint of the opening being 5 Å or less, Includes, The first, second, and third etching rates are determined, respectively, by the etching resistance of the material in the first, second, and third portions of the first semiconductor layer. Semiconductor processing method.

2. The semiconductor processing method according to claim 1, wherein the first semiconductor layer includes polysilicon.

3. The semiconductor processing method according to claim 1, wherein the first semiconductor layer is formed between two dielectric layers.

4. The semiconductor processing method according to claim 3, wherein the dielectric layer contains silicon oxide.

5. The semiconductor processing method according to claim 1, wherein the second portion of the first semiconductor layer has a higher percentage of phosphorus atoms than the first portion or the third portion of the first semiconductor layer.

6. The semiconductor processing method according to claim 1, wherein the second portion of the first semiconductor layer has a greater stress amount than the first portion or the third portion of the first semiconductor layer.

7. The semiconductor processing method according to claim 1, further comprising forming a second semiconductor layer after forming the first semiconductor layer, wherein the second semiconductor layer has an average etching rate of the etching process that is slower than the average etching rate of the first semiconductor layer.

8. The semiconductor processing method according to claim 7, wherein the second semiconductor layer includes at least three portions having different etching rates for the etching process.

9. A semiconductor processing method, The deposition precursor containing silicon-containing precursor and doping precursor is flowed into the substrate processing area of ​​the semiconductor processing chamber. A first portion of the doped polysilicon layer is deposited on the substrate within the substrate processing area of ​​the semiconductor processing chamber. The process involves increasing the flow rate ratio of the doping precursor to the silicon-containing precursor, and depositing a second portion of the doped polysilicon layer onto the first portion of the doped polysilicon layer on the substrate, wherein the second portion of the polysilicon layer is characterized by a slower etching rate in the etching process than the first portion of the doped polysilicon layer. The process involves reducing the flow rate ratio of the doping precursor to the silicon-containing precursor, and depositing a third portion of the doped polysilicon layer onto the second portion of the doped polysilicon layer on the substrate, wherein the third portion of the polysilicon layer is deposited at a faster etching rate than the second portion of the doped polysilicon layer. The etching further comprises etching an opening through the doped polysilicon layer, wherein the opening has a height and a width, and the opening is characterized by the change in the width between the midpoint of the height of the opening and the endpoint of the opening being 5 Å or less. Includes, The etching rates in the first, second, and third portions of the doped polysilicon layer are determined by the etching resistance of the material in the first, second, and third portions, respectively. Semiconductor processing method.

10. The semiconductor processing method according to claim 9, wherein the silicon-containing precursor contains silane.

11. The semiconductor processing method according to claim 9, wherein the doping precursor includes a phosphorus-containing precursor.

12. The semiconductor processing method according to claim 9, wherein the substrate comprises a first dielectric layer, and the first portion of the doped polysilicon layer is deposited on the first dielectric layer.

13. The semiconductor processing method according to claim 12, further comprising depositing a second dielectric layer on the doped polysilicon layer.

14. A semiconductor structure comprising at least one pair of layers including a dielectric layer and a semiconductor layer, wherein the semiconductor layer is A first portion of the semiconductor layer characterized by a first etching rate of the etching process, A second portion of the semiconductor layer located on the first portion of the semiconductor layer, characterized by a second etching rate slower than the first etching rate of the etching process, A third portion of the semiconductor layer located on the second portion of the semiconductor layer, characterized by a third etching rate faster than the second etching rate, An opening formed through the semiconductor layer, wherein the opening has a height and a width, and the opening is characterized by the fact that the change in the width between the midpoint of the height of the opening and the endpoint of the opening is 5 Å or less, Equipped with, The first, second, and third etching rates are determined by the etching resistance of the material in the first, second, and third portions of the semiconductor layer, respectively. Semiconductor structure.

15. The semiconductor structure according to claim 14, wherein the dielectric layer contains silicon oxide.

16. The semiconductor structure according to claim 14, wherein the semiconductor layer includes doped polysilicon.

17. The semiconductor structure according to claim 14, wherein the second portion of the semiconductor layer is characterized by having a higher percentage of phosphorus atoms than the first or third portion of the semiconductor layer.

18. The semiconductor structure according to claim 14, wherein the second portion of the semiconductor layer is characterized by a higher stress amount than the first or third portion of the semiconductor layer.

19. The semiconductor structure according to claim 14, wherein at least one pair of layers comprises 50 or more pairs of layers.

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