Calibration circuit

Abstract

The purpose of the present invention is to suppress an increase in power consumed during steady-state operation, while also preventing oscillation pausing during calibration of an LC oscillator.　This calibration circuit comprises a reference voltage generation unit, a voltage comparison unit, and an amplitude adjustment unit. The reference voltage generation unit generates a plurality of different reference voltages. The voltage comparison unit compares the plurality of different reference voltages and a detected value of an oscillation amplitude that was detected using an oscillation signal from the LC oscillator, on a side having the same polarity of the oscillation amplitude. The amplitude adjustment unit adjusts the oscillation amplitude on the basis of comparison results from the voltage comparison unit. The calibration circuit may comprise a frequency adjustment unit that adjusts the oscillation frequency of the LC oscillator.

Description

Technical Field

[0001] This technology relates to a calibration circuit. Specifically, this technology relates to a calibration circuit for an LC oscillator.

Background Art

[0002] An LC oscillator may be used to generate a clock. Since the oscillation frequency and oscillation amplitude of an LC oscillator vary under the influence of temperature, power supply voltage, element variations, etc., calibration may be performed at startup. For example, a configuration has been proposed in which the maximum and minimum values of the oscillation output are detected, and a control voltage is output that changes the bias current of the voltage-controlled oscillator circuit so that the difference between those values becomes equal to the reference voltage (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The oscillation amplitude of an LC oscillator increases and decreases in proportion to its oscillation frequency. Therefore, in the above-described conventional technology, if frequency calibration is performed following amplitude calibration of the LC oscillator, there is a risk that oscillation will stop during frequency calibration. On the other hand, if the reference voltage for setting the difference between the maximum and minimum values of the oscillation output is increased to prevent oscillation from stopping during frequency calibration, the oscillation amplitude of the LC oscillator increases, which may lead to an increase in power consumption and phase noise during steady operation.

[0005] This technology was created in view of such a situation, and an object thereof is to prevent oscillation from stopping during calibration of an LC oscillator while suppressing an increase in power consumption during steady operation. [Means for solving the problem]

[0006] This technology was developed to solve the aforementioned problems, and its first aspect is a calibration circuit comprising a reference voltage generation unit that generates multiple different reference voltages, a voltage comparison unit that compares the detected value of the oscillation amplitude detected from the oscillation signal of the LC oscillator with the multiple different reference voltages on the same polarity side of the oscillation amplitude, and an amplitude adjustment unit that adjusts the oscillation amplitude based on the comparison result by the voltage comparison unit. This results in the oscillation amplitude of the LC oscillator being adjusted in steps.

[0007] Furthermore, the first aspect is that the side of the oscillation amplitude with the same polarity may be either the positive or negative side of the oscillation amplitude. This results in the effect that the detected value of the oscillation amplitude detected from the oscillation signal of the LC oscillator and the multiple different reference voltages are compared on the side of the oscillation amplitude with the same polarity.

[0008] Furthermore, the first aspect may further include a frequency adjustment unit for adjusting the oscillation frequency of the LC oscillator. This results in the oscillation frequency being adjusted while the oscillation amplitude of the LC oscillator is adjusted in steps.

[0009] Furthermore, the first aspect may further include a detection circuit that detects the detected value of the oscillation amplitude of the LC oscillator on the same polarity side based on the detection of the oscillation signal of the LC oscillator. This results in the detection of the oscillation amplitude, which is compared with multiple different reference voltages on the same polarity side of the oscillation amplitude, being detected from the oscillation signal of the LC oscillator.

[0010] Furthermore, according to the first aspect, the detection circuit may include a full-wave rectifier circuit that performs full-wave rectification of the oscillation signal of the LC oscillator, and a smoothing circuit that smooths the waveform that has been full-wave rectified by the full-wave rectifier circuit. This results in the setting of values ​​on the same polarity side of the oscillation amplitude that are compared with a plurality of different reference voltages.

[0011] Furthermore, according to the first aspect, the reference voltage may include a first reference voltage, a second reference voltage greater than the first reference voltage, and a third reference voltage greater than the second reference voltage. The amplitude adjustment unit adjusts the oscillation amplitude during the first amplitude calibration period so that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is greater than or equal to the third reference voltage. The frequency adjustment unit adjusts the oscillation frequency during the frequency calibration period after the first amplitude calibration period so that the frequency error of the LC oscillator is less than or equal to an allowable value. The amplitude adjustment unit may also adjust the oscillation amplitude during the second amplitude calibration period after the frequency calibration period so that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is greater than or equal to the first reference voltage and less than the second reference voltage. This results in the oscillation amplitude during steady-state operation of the LC oscillator being smaller than the oscillation amplitude during the frequency calibration period.

[0012] Furthermore, the first aspect may further comprise a state management unit that manages the first amplitude calibration period, the frequency calibration period, and the second amplitude calibration period. This results in the setting of a frequency calibration period between the first amplitude calibration period and the second amplitude calibration period. [Brief explanation of the drawing]

[0013] [Figure 1] This figure shows an example of the configuration of a calibration circuit according to the first embodiment. [Figure 2] This figure shows an example of the comparator output value according to the first embodiment. [Figure 3] This is a timing chart showing an example of the calibration operation according to the first embodiment. [Figure 4] This flowchart shows an example of the first amplitude calibration operation according to the first embodiment. [Figure 5]This flowchart shows an example of frequency calibration operation according to the first embodiment. [Figure 6] This flowchart shows an example of the second amplitude calibration operation according to the first embodiment. [Figure 7] This figure shows an example of the configuration of a calibration circuit according to the second embodiment. [Modes for carrying out the invention]

[0014] The following describes the embodiments for implementing this technology. The description will proceed in the following order. 1. First Embodiment (An example configuration in which the detected oscillation amplitude value on the positive terminal side of the oscillation amplitude of an LC oscillator is compared with three different reference voltages, and calibration is performed based on the comparison result) 2. Second Embodiment (An example in which a detection circuit and voltage comparison section of a calibration circuit are configured using a field-effect transistor)

[0015] <1. First Embodiment> In the first embodiment, the detected value Vdet of the oscillation amplitude Vosc detected from the oscillation signal Vsd of the LC oscillator 100 is compared with the reference voltages Vref1 to Vref3 on the same polarity side of the oscillation amplitude Vosc. In the first embodiment, the case in which this same polarity side of the oscillation amplitude Vosc is the positive electrode side of the oscillation amplitude Vosc is taken as an example.

[0016] Figure 1 shows an example of the configuration of a calibration circuit according to the first embodiment.

[0017] In the figure, the LC oscillator 100 generates an oscillation signal Vsd based on the resonance of the capacitor bank 113 and the inductor 114. The oscillation signal Vsd is a differential output signal. The LC oscillator 100 includes transistors 111, 112, a capacitor bank 113, an inductor 114, and a variable resistor 115. The transistors 111, 112 are N-channel field-effect transistors. The capacitor bank 113 can switch the capacitance value based on a command from the frequency calibration unit 109. The variable resistor 115 can change the resistance value based on a command from the amplitude calibration unit 106.

[0018] The capacitor bank 113 and the inductor 114 are connected in parallel with each other. The drains of the transistors 111, 112 are connected to both ends of the capacitor bank 113. Also, the drain of the transistor 111 is connected to the gate of the transistor 112, and the drain of the transistor 112 is connected to the gate of the transistor 111. The sources of the transistors 111, 112 are connected to the ground potential via the variable resistor 115. The intermediate tap of the inductor 114 is connected to the power supply potential Vdd.

[0019] The calibration circuit 101 includes a detection circuit 102, a reference voltage generation unit 103, and a voltage comparison unit 104. Also, the calibration circuit 101 includes an amplitude calibration unit 106, a frequency division circuit 107, a counter 108, a frequency calibration unit 109, and a state management unit 110.

[0020] The detection circuit 102 detects a detected value Vdet on the positive electrode side of the oscillation amplitude Vosc of the LC oscillator 100 based on the detection of the oscillation signal Vsd of the LC oscillator 100. The detection circuit 102 includes a full-wave rectification circuit 121 and a smoothing circuit 122. The full-wave rectification circuit 121 performs full-wave rectification of the oscillation signal Vsd of the LC oscillator 100. The smoothing circuit 122 generates a detected value Vdet on the positive electrode side of the oscillation amplitude Vosc by smoothing the waveform full-wave rectified by the full-wave rectification circuit 121. Note that the detected value Vdet on the positive electrode side of the oscillation amplitude Vosc is an average value obtained by averaging the instantaneous values on the positive electrode side of the oscillation amplitude Vosc over a certain period.

[0021] The reference voltage generation unit 103 generates three different reference voltages Vref1 to Vref3. At this time, the reference voltages Vref1 to Vref3 can have a relationship of Vref1 < Vref2 < Vref3. The reference voltage generation unit 103 includes resistors 131 to 133 and a current source 134. The resistors 131 to 133 are connected in series with each other, the other end of the resistor 133 is connected to the power supply potential Vdd, and the other end of the resistor 131 is connected to the ground potential via the current source 134.

[0022] The voltage comparison unit 104 compares the detected value Vdet of the oscillation amplitude Vosc detected from the oscillation signal Vsd of the LC oscillator 100 with reference voltages Vref1 to Vref3 on the positive side of the oscillation amplitude Vosc. The voltage comparison unit 104 includes comparators 141 to 143. Comparator 141 compares the detected value Vdet on the positive side of the oscillation amplitude Vosc detected by the detection circuit 102 with reference voltage Vref1. Comparator 142 compares the detected value Vdet on the positive side of the oscillation amplitude Vosc detected by the detection circuit 102 with reference voltage Vref2. Comparator 143 compares the detected value Vdet on the positive side of the oscillation amplitude Vosc detected by the detection circuit 102 with reference voltage Vref3. At this time, the output voltages Vout1 to Vout3 of each comparator 141 to 143 take a logic level of '0' or '1'. Then, as shown in Figure 2, inputs In<2:0>, corresponding to the logic levels of the output voltages Vout1 to Vout3, are input to the amplitude calibration unit 106 as comparator outputs out. In this figure, the value of the comparator output out is set to 3 when the input In<2:0> is '111', and the value of the comparator output out is set to 2 when the input In<2:0> is '011'. Also, the value of the comparator output out is set to 1 when the input In<2:0> is '001', and the value of the comparator output out is set to 0 when the input In<2:0> is '000'.

[0023] The amplitude calibration unit 106 adjusts the oscillation amplitude Vosc of the LC oscillator 100 based on the comparison result from the voltage comparison unit 104. For example, before frequency calibration, the amplitude calibration unit 106 can adjust the oscillation amplitude Vosc of the LC oscillator 100 so that the detected value Vdet on the positive side of the oscillation amplitude Vosc is greater than or equal to the reference voltage Vref3. Alternatively, after frequency calibration, the amplitude calibration unit 106 can adjust the oscillation amplitude Vosc of the LC oscillator 100 so that the detected value Vdet on the positive side of the oscillation amplitude Vosc is greater than or equal to the reference voltage Vref1 and less than the reference voltage Vref2. Note that the amplitude calibration unit 106 is an example of the amplitude adjustment unit described in the claims.

[0024] The amplitude calibration unit 106 can adjust the resistance value of the variable resistor 115 to adjust the oscillation amplitude Vosc of the LC oscillator 100. In this case, the bias current Ibc of the LC oscillator 100 changes according to the resistance value of the variable resistor 115, and the oscillation amplitude Vosc of the LC oscillator 100 changes.

[0025] The frequency divider circuit 107 divides the oscillation signal Vsd of the LC oscillator 100. The counter 108 outputs a count value corresponding to the frequency of the oscillation signal Vsd of the LC oscillator 100, based on the output of the frequency divider circuit 107.

[0026] The frequency calibration unit 109 adjusts the oscillation frequency fosc of the LC oscillator 100. For example, the frequency calibration unit 109 can adjust the oscillation frequency fosc so that the frequency error of the LC oscillator 100 is below an acceptable value. In this case, the frequency calibration unit 109 can switch the capacitance value of the capacitance bank 113 in order to adjust the oscillation frequency fosc of the LC oscillator 100. Note that the frequency calibration unit 109 is an example of a frequency adjustment unit as described in the claims.

[0027] The state management unit 110 manages the amplitude calibration period of the amplitude calibration unit 106 and the frequency calibration period of the frequency calibration unit 109. At this time, the state management unit 110 can adjust the LC oscillator 100 so that the detected value Vdet on the positive side of the oscillation amplitude Vosc is greater than or equal to the reference voltage Vref3 during the amplitude calibration period, and then transition to the frequency calibration period. After the frequency calibration period, the state management unit 110 can transition back to the amplitude calibration period and adjust the LC oscillator 100 so that the detected value Vdet on the positive side of the oscillation amplitude Vosc is greater than or equal to the reference voltage Vref1 and less than the reference voltage Vref2.

[0028] The state management unit 110 may be implemented by reading a program related to the state management of the calibration circuit 101 from memory and having a processor such as a CPU (Central Processing Unit) execute it. Alternatively, the state management unit 110 may be implemented using hardware such as a logic circuit.

[0029] Figure 3 is a timing chart showing an example of the calibration operation according to the first embodiment. In the figure, a indicates the state ST of the calibration circuit 101. In the figure, b indicates the change in the oscillation amplitude Vosc according to the state ST of the calibration circuit 101. In the figure, c indicates the value of the comparator output out according to the state ST of the calibration circuit 101. In the figure, d indicates the oscillation frequency fosc of the oscillation signal Vsd according to the state ST of the calibration circuit 101.

[0030] In the figure, at point a, the state management unit 110 manages the oscillator startup period ST1, amplitude calibration period ST2, frequency calibration period ST3, and amplitude calibration period ST4 as states ST of the calibration circuit 101.

[0031] During the oscillator startup period ST1, the LC oscillator 100 is started. At this time, the voltage across the parallel circuit of the capacitance bank 113 and the inductor 114 is applied as a differential input to the gates of transistors 111 and 112, and the differentialized oscillation signal Vsd is output from the drains of transistors 111 and 112 to the detection circuit 102. At this time, the oscillation signal Vsd alternates between the positive and negative waveforms. Here, as shown in figure b, the positive side of the oscillation amplitude Vosc is shown as PoS, and the negative side of the oscillation amplitude Vosc is shown as NeS.

[0032] In the detection circuit 102, the detection value Vdet at the positive side PoS of the oscillation amplitude Vosc is detected from the oscillation signal Vsd output from the LC oscillator 100 and input to each of the comparators 141 to 143. In addition, in the reference voltage generation unit 103, the current generated by the current source 134 flows through the resistors 131 to 133, and reference voltages Vref1 to Vref3 are generated based on the voltage drop across each of the resistors 131 to 133 and input to each of the comparators 141 to 143.

[0033] In each of the comparators 141 to 143, the detected value Vdet at the positive side PoS of the oscillation amplitude Vosc is compared with the reference voltages Vref1 to Vref3, respectively. The output voltages Vout1 to Vout3 of each of the comparators 141 to 143 are then input to the amplitude calibration unit 106 as comparator outputs out.

[0034] Next, when the oscillator startup period ST1 ends, the state management unit 110 transitions to the amplitude calibration period ST2 and starts the amplitude calibration unit 106. Then, in the amplitude calibration unit 106, as shown in b and c of the figure, the oscillation amplitude Vosc of the LC oscillator 100 is adjusted so that the comparator output out is 3 or more. At this time, when the comparator output out is 3 or more, the detected value Vdet at the positive side PoS of the oscillation amplitude Vosc becomes 3 or more than the reference voltage Vref3.

[0035] Next, when the amplitude calibration period ST2 ends, the state management unit 110 transitions to the frequency calibration period ST3 and activates the frequency divider circuit 107, the counter 108, and the frequency calibration unit 109. At this time, the frequency divider circuit 107 divides the oscillation signal Vsd of the LC oscillator 100, and then the counter 108 generates a count value corresponding to the frequency of the oscillation signal Vsd of the LC oscillator 100, which is input to the frequency calibration unit 109. Then, in the frequency calibration unit 109, as shown in d in the figure, the oscillation frequency fosc of the LC oscillator 100 is adjusted to match the target value Th.

[0036] Here, the relationship between the oscillation amplitude Vosc and oscillation frequency fosc of the LC oscillator 100 can be calculated as follows. Assuming that the LC oscillator 100 operates in Class B, the fundamental wave component Itk of the current flowing through the capacitance bank 113 and inductor 114 when the LC oscillator 100 oscillates can be given by the following equation. Itk = 2 / π·Ibs

[0037] Furthermore, the resonant impedance Rtk between the capacitance bank 113 and the inductor 114 at the oscillation frequency fosc can be given by the following equation. Rtk=ωLQ=2πfosc·LQ However, Q is the Q value of inductor 114.

[0038] Therefore, the oscillation amplitude Vosc can be given by the following equation. Vosc=2Itk·Rtk=8Ibs·fosc·LQ

[0039] From the above equation, the oscillation amplitude Vosc increases or decreases in proportion to the oscillation frequency fosc. Therefore, as the oscillation frequency fosc decreases, the oscillation amplitude Vosc decreases, and if the oscillation frequency fosc becomes too small, the oscillation of the LC oscillator 100 stops. For this reason, the reference voltage generation unit 103 can set the reference voltage Vref3 so that the oscillation of the LC oscillator 100 does not stop during the frequency calibration period ST3.

[0040] Next, when the frequency calibration period ST3 ends, the state management unit 110 transitions to the amplitude calibration period ST4 and restarts the amplitude calibration unit 106. Then, in the amplitude calibration unit 106, as shown in b and c of the figure, the oscillation amplitude Vosc of the LC oscillator 100 is adjusted so that the comparator output out is between 1 and 2. At this time, when the comparator output out is between 1 and 2, the detected value Vdet at the positive side PoS of the oscillation amplitude Vosc is between the reference voltage Vref1 and the reference voltage Vref2.

[0041] After the detected value Vdet at the positive side PoS of the oscillation amplitude Vosc is set to be greater than or equal to the reference voltage Vref1 and less than the reference voltage Vref2, the LC oscillator 100 transitions to steady-state operation. At this time, the reference voltage Vref1 of the LC oscillator 100 can be set to operate stably during the steady-state operation of the LC oscillator 100. Furthermore, in order to suppress the current consumption of the LC oscillator 100, it is preferable that the reference voltage Vref2 be as small as possible. In this case, the reference voltage Vref2 may be set to match the reference voltage Vref1. However, increasing the reference voltage Vref2 can shorten the time it takes for the detected value Vdet at the positive side PoS of the oscillation amplitude Vosc to converge to greater than or equal to the reference voltage Vref1 and less than the reference voltage Vref2, thereby shortening the amplitude calibration period ST4.

[0042] Figure 4 is a flowchart showing an example of the first amplitude calibration operation according to the first embodiment.

[0043] In the figure, when amplitude calibration is activated, the amplitude calibration unit 106 checks the comparator output out (step S911).

[0044] Next, the amplitude calibration unit 106 determines whether the comparator output out is 3 or greater (step S912). If the comparator output out is 3 or greater (Yes in step S912), the amplitude calibration unit 106 terminates. On the other hand, if the comparator output out is not 3 or greater (No in step S912), the amplitude calibration unit 106 adjusts the resistance value of the variable resistor 115 to change the bias current Ibc of the LC oscillator 100 (step S913).

[0045] Next, the amplitude calibration unit 106 waits until the oscillation amplitude Vosc of the LC oscillator 100 is settled (step S914), and then returns to the process in step S911.

[0046] Figure 5 is a flowchart showing an example of frequency calibration operation according to the first embodiment.

[0047] In the figure, when frequency calibration is activated, the frequency calibration unit 109 checks the oscillation frequency fosc of the LC oscillator 100 (step S921).

[0048] Next, the frequency calibration unit 109 determines whether the error in the oscillation frequency fosc of the LC oscillator 100 is below the allowable value (step S922). If the error in the oscillation frequency fosc of the LC oscillator 100 is below the allowable value (Yes in step S922), the frequency calibration unit 109 terminates. On the other hand, if the error in the oscillation frequency fosc of the LC oscillator 100 is not below the allowable value (No in step S922), the frequency calibration unit 109 switches the capacitance value of the capacitance bank 113 to change the oscillation frequency fosc of the LC oscillator 100 (step S923).

[0049] Next, the frequency calibration unit 109 waits until the oscillation frequency fosc of the LC oscillator 100 is settled (step S924), and then returns to the process of step S921.

[0050] Figure 6 is a flowchart showing an example of the second amplitude calibration operation according to the first embodiment.

[0051] In the figure, when amplitude calibration is started again, the amplitude calibration unit 106 checks the comparator output out (step S931).

[0052] Next, the amplitude calibration unit 106 determines whether the comparator output out is 1 or more and less than 2 (step S932). If the comparator output out is 1 or more and less than 2 (Yes in step S932), the amplitude calibration unit 106 terminates. On the other hand, if the comparator output out is not 1 or more and less than 2 (No in step S932), the amplitude calibration unit 106 adjusts the resistance value of the variable resistor 115 to change the bias current Ibc of the LC oscillator 100 (step S933).

[0053] Next, the amplitude calibration unit 106 waits until the oscillation amplitude Vosc of the LC oscillator 100 is settled (step S934), and then returns to the process of step S931.

[0054] As described above, in the first embodiment, the detected value Vdet at the positive side Pos of the oscillation amplitude Voc of the LC oscillator 100 is compared with a plurality of different reference voltages Vref1 to Vref3. This allows the oscillation amplitude Voc of the LC oscillator 100 to be adjusted in steps, and the oscillation amplitude Voc during steady-state operation of the LC oscillator 100 can be made smaller than the oscillation amplitude Voc during the frequency calibration period ST3. As a result, it is possible to prevent the oscillation of the LC oscillator 100 from stopping during frequency calibration while suppressing an increase in power consumption during steady-state operation. Furthermore, it is no longer necessary to increase the oscillation amplitude Voc during steady-state operation to prevent the oscillation of the LC oscillator 100 from stopping during frequency calibration, and the phase noise of the LC oscillator 100 can be reduced.

[0055] <2. Second Embodiment> In the first embodiment described above, the detected value Vdet of the oscillation amplitude Vosc detected from the oscillation signal Vsd of the LC oscillator 100 was compared with the reference voltages Vref1 to Vref3 at the positive side Pos of the oscillation amplitude Vosc. In this second embodiment, a field-effect transistor is used to configure the detection circuit 102 and the voltage comparison unit 104 of the calibration circuit 101.

[0056] Figure 7 shows an example of the configuration of a calibration circuit according to the second embodiment.

[0057] In the figure, the detection circuit 102 comprises transistors 221 to 223 and a capacitor 224. Each of the transistors 221 to 223 is an N-channel field-effect transistor.

[0058] The drains of transistors 221 and 222 are connected to the power supply potential Vdd, and the sources of transistors 221 and 222 are connected to ground potential Gnd via transistor 223. The gates of transistors 221 and 222 are input to the differential oscillator signal Vsd as differential inputs Vinp and Vinn. Capacitor 224 is connected in parallel to transistor 223.

[0059] The reference voltage generator 103 comprises resistors 230 to 233, transistors 224 and 235, and a capacitor 236. Each of the transistors 234 and 235 is an N-channel field-effect transistor. Transistor 235 can operate as a current source 134. Transistor 235 is connected in series with transistor 234, the drain of transistor 234 is connected to the power supply potential Vdd, and the source of transistor 235 is connected to the ground potential Gnd. The gate of transistor 234 is connected to the center tap of inductor 114. At this time, the power supply potential Vdd is applied to the gate of transistor 234 as the input voltage Vct.

[0060] Resistors 230 to 233 are connected in series with one end of resistor 233 connected to the power supply potential Vdd, and the other end of resistor 230 connected to the ground potential Gnd via transistor 235. Capacitor 236 is connected in parallel to transistor 235.

[0061] The voltage comparison unit 104 includes transistors 241 to 247, 251 to 257, and 261 to 267. Each of the transistors 241, 242, 245, 246, 251, 252, 255, 256, 261, 262, 265, and 266 is an N-channel field-effect transistor. Each of the transistors 243, 244, 247, 253, 254, 257, 263, 264, and 267 is a P-channel field-effect transistor.

[0062] In comparator 141, transistors 241 and 242 are connected in series with transistors 243 and 244. The sources of transistors 241 and 242 are connected to ground potential Gnd via transistor 245. The gate of transistor 241 is connected to the source of transistor 222, and the gate of transistor 242 is connected to the connection point of resistors 230 and 231. The gates of transistors 243 and 244 are connected to the drain of transistor 243. Transistor 246 is connected in series with transistor 247. The source of transistor 246 is connected to ground potential Gnd. The source of transistor 247 is connected to the power supply potential Vdd, and the gate of transistor 247 is connected to the drain of transistor 244. The output voltage Vout1 is output from the drain of transistor 247.

[0063] In comparator 142, transistors 251 and 252 are connected in series with transistors 253 and 254. The sources of transistors 251 and 252 are connected to ground potential Gnd via transistor 255. The gate of transistor 251 is connected to the source of transistor 222, and the gate of transistor 252 is connected to the connection point of resistors 231 and 232. The gates of transistors 253 and 254 are connected to the drain of transistor 253. Transistor 256 is connected in series with transistor 257. The source of transistor 256 is connected to ground potential Gnd. The source of transistor 257 is connected to the power supply potential Vdd, and the gate of transistor 257 is connected to the drain of transistor 254. The output voltage Vout2 is output from the drain of transistor 257.

[0064] In comparator 143, transistors 261 and 262 are connected in series with transistors 263 and 264. The sources of transistors 261 and 262 are connected to ground potential Gnd via transistor 265. The gate of transistor 261 is connected to the source of transistor 222, and the gate of transistor 262 is connected to the connection point of resistors 232 and 233. The gates of transistors 263 and 264 are connected to the drain of transistor 263. Transistor 266 is connected in series with transistor 267. The source of transistor 266 is connected to ground potential Gnd. The source of transistor 267 is connected to the power supply potential Vdd, and the gate of transistor 267 is connected to the drain of transistor 264. The output voltage Vout3 is output from the drain of transistor 267.

[0065] Furthermore, transistor 202 is connected between the power supply potential Vdd and the ground potential Gnd via a current source 201. Transistor 202 is an N-channel field-effect transistor. The gates of transistors 202, 223, 235, 245, 246, 255, 256, 265, and 266 are connected to the drain of transistor 202. In this configuration, transistors 202, 223, 235, 245, 246, 255, 256, 265, and 266 can perform current mirror operation.

[0066] Then, in the detection circuit 102, the differentialized oscillation signal Vsd is input to the gates of transistors 221 and 222 as differential inputs Vinp and Vinn, and the oscillation signal Vsd is full-wave rectified based on the differential operation of transistors 221 and 222. The full-wave rectified waveform is then smoothed by capacitor 236 to detect the value Vdet on the positive side of the oscillation amplitude Vosc, which is then applied to the gates of transistors 241, 251, and 261.

[0067] Furthermore, in the reference voltage generation unit 103, the current generated by transistor 235 flows through resistors 230 to 233, generating reference voltages Vref1 to Vref3, which are then applied to the gates of transistors 242, 252, and 262.

[0068] Here, if the resistance values ​​of each resistor 230 to 233 are R0 to R3, the reference voltages Vref1 to Vref3 can be given by the following equations. Vref1=Vdd-(R1+R2+R3)·Vgs / (R0+R1+R2+R3) Vref2=Vdd-(R2+R3)·Vgs / (R0+R1+R2+R3) Vref3=Vdd-(R3)·Vgs / (R0+R1+R2+R3)

[0069] However, Vgs is the gate / source voltage when transistors 221 and 222 are in an equilibrium state. At this time, the current of transistor 235 can be set so that the gate / source voltage of transistor 234 is equal to the gate / source voltage of each of transistors 221 and 222.

[0070] Then, based on the current mirror operation of transistors 243 and 244, the drain currents of each of transistors 241 and 242 are set. Then, according to the magnitude relationship between the detected value Vdet of the oscillation amplitude Vosc and the reference voltage Vref1, the drain potential of transistor 242 changes, and when this drain potential is applied to the gate of transistor 247, the on and off states of transistor 247 are switched. At this time, when Vdet > Vref1, transistor 247 turns on and the output voltage Vout1 becomes high level, and when Vdet < Vref1, transistor 247 turns off and the output voltage Vout1 becomes low level.

[0071] Also, based on the current mirror operation of transistors 253 and 254, the drain currents of each of transistors 251 and 252 are set. Then, according to the magnitude relationship between the detected value Vdet of the oscillation amplitude Vosc and the reference voltage Vref2, the drain potential of transistor 252 changes, and when this drain potential is applied to the gate of transistor 257, the on and off states of transistor 257 are switched. At this time, when Vdet > Vref2, transistor 257 turns on and the output voltage Vout2 becomes high level, and when Vdet < Vref2, transistor 257 turns off and the output voltage Vout2 becomes low level.

[0072] Also, based on the current mirror operation of transistors 263 and 264, the drain currents of transistors 261 and 262 are set. Then, according to the magnitude relationship between the detected value Vdet of the oscillation amplitude Vosc and the reference voltage Vref3, the drain potential of transistor 262 changes, and when this drain potential is applied to the gate of transistor 267, the on and off states of transistor 267 are switched. At this time, when Vdet > Vref3, transistor 267 turns on and the output voltage Vout3 becomes high level, and when Vdet < Vref3, transistor 267 turns off and the output voltage Vout3 becomes low level.

[0073] Thus, in the above-described second embodiment, the detection circuit 102 and the voltage comparison unit 104 of the calibration circuit 101 are configured using field effect transistors. Thereby, the calibration circuit 101 can be integrated, and the size reduction and cost reduction of the calibration circuit 101 can be achieved.

[0074] In the above-described embodiment, the configuration in which the detected value of the oscillation amplitude is compared with three different reference voltages on the positive side of the oscillation amplitude of the LC oscillator has been described. In addition to this, a configuration in which the detected value of the oscillation amplitude is compared with two or four or more different reference voltages on the positive side of the oscillation amplitude of the LC oscillator may also be used. Also, in the above-described embodiment, the configuration in which the oscillation amplitude of the LC oscillator is compared with a plurality of different reference voltages on the positive side of the oscillation amplitude of the LC oscillator has been described. In addition to this, a configuration in which the oscillation amplitude of the LC oscillator is compared with a plurality of different reference voltages on the negative side of the oscillation amplitude of the LC oscillator may also be used.

[0075] Furthermore, the embodiments described above are merely examples of how to realize the present technology, and there is a corresponding relationship between the matters in the embodiments and the inventive features in the claims. Similarly, there is a corresponding relationship between the inventive features in the claims and the matters in the embodiments of the present technology that bear the same name. However, the present technology is not limited to the embodiments and can be realized by making various modifications to the embodiments without departing from the gist of the present technology. Also, the effects described herein are merely examples and are not limiting, and there may be other effects.

[0076] Furthermore, this technology can also be configured as follows. (1) A reference voltage generating unit that generates multiple different reference voltages, A voltage comparison unit compares the detected value of the oscillation amplitude detected from the oscillation signal of the LC oscillator with the plurality of different reference voltages on the same polarity side of the oscillation amplitude. An amplitude adjustment unit adjusts the oscillation amplitude based on the comparison result from the voltage comparison unit. A calibration circuit equipped with the following features. (2) The side of the oscillation amplitude with the same polarity is the positive or negative side of the oscillation amplitude. The calibration circuit described in (1) above. (3) The calibration circuit according to (1) or (2), further comprising a frequency adjustment unit for adjusting the oscillation frequency of the LC oscillator. (4) The calibration circuit according to any one of (1) to (3), further comprising a detection circuit that detects a detected value on the same polarity side of the oscillation amplitude of the LC oscillator based on the detection of the oscillation signal of the LC oscillator. (5) The detection circuit is, A full-wave rectifier circuit that performs full-wave rectification of the oscillation signal of the LC oscillator, The system includes a smoothing circuit that smooths the waveform rectified by the full-wave rectifier circuit. The calibration circuit described in (4) above. (6) The reference voltage comprises a first reference voltage, a second reference voltage greater than the first reference voltage, and a third reference voltage greater than the second reference voltage. The amplitude adjustment unit adjusts the oscillation amplitude during the first amplitude calibration period so that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is equal to or greater than the third reference voltage. The frequency adjustment unit adjusts the oscillation frequency during the frequency calibration period after the first amplitude calibration period so that the frequency error of the LC oscillator is less than or equal to an allowable value. The amplitude adjustment unit adjusts the oscillation amplitude during the second amplitude calibration period after the frequency calibration period such that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is greater than or equal to the first reference voltage and less than the second reference voltage. A calibration circuit as described in any of (1) to (5) above. (7) The calibration circuit according to (6), further comprising a state management unit for managing the first amplitude calibration period, the frequency calibration period, and the second amplitude calibration period. [Explanation of Symbols]

[0077] 100 LC oscillator 101 Calibration Circuit 111, 112 transistors 113 Capacity Banks 114 Inductors 115 Variable resistor 102 Detection circuit 121 Full wave rectifier circuit 122 Smoothing circuit 103 Reference voltage generation unit 131-133 Resistors 134 Current source 104 Voltage Comparison Section 141-143 Comparators 106 Amplitude Calibration Section 107 Frequency divider circuit 108 counters 109 Frequency Calibration Section 110 State Management Department

Claims

1. A reference voltage generating unit that generates multiple different reference voltages, A voltage comparison unit compares the detected value of the oscillation amplitude detected from the oscillation signal of the LC oscillator with the plurality of different reference voltages on the same polarity side of the oscillation amplitude. An amplitude adjustment unit that adjusts the oscillation amplitude based on the comparison result from the voltage comparison unit, The system comprises a frequency adjustment unit for adjusting the oscillation frequency of the LC oscillator, The aforementioned reference voltage comprises a first reference voltage, a second reference voltage greater than the first reference voltage, and a third reference voltage greater than the second reference voltage. The amplitude adjustment unit adjusts the oscillation amplitude during the first amplitude calibration period so that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is equal to or greater than the third reference voltage. The frequency adjustment unit adjusts the oscillation frequency during the frequency calibration period after the first amplitude calibration period so that the frequency error of the LC oscillator is less than or equal to an allowable value. The amplitude adjustment unit adjusts the oscillation amplitude during the second amplitude calibration period after the frequency calibration period such that the detected value of the oscillation amplitude on the same polarity side of the oscillation amplitude is greater than or equal to the first reference voltage and less than the second reference voltage. Calibration circuit.

2. The side of the oscillation amplitude with the same polarity is either the positive or negative side of the oscillation amplitude. The calibration circuit according to claim 1.

3. The calibration circuit according to claim 1, further comprising a detection circuit that detects a detected value on the same polarity side of the oscillation amplitude of the LC oscillator based on the detection of the oscillation signal of the LC oscillator.

4. The aforementioned detection circuit is, A full-wave rectifier circuit that performs full-wave rectification of the oscillation signal of the LC oscillator, The system includes a smoothing circuit that smooths the waveform rectified by the full-wave rectifier circuit. The calibration circuit according to claim 3.

5. The calibration circuit according to claim 4, further comprising a state management unit for managing the first amplitude calibration period, the frequency calibration period, and the second amplitude calibration period.

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