Wiring board

Abstract

To improve the degree of freedom of wiring arrangement and electrical characteristics in wiring boards.SOLUTION: A wiring board 1 includes a plurality of stacked insulating layers 111, 112 and a plurality of conductor layers 12, 121, and has a first plane FA that intersects the stacking direction of these layers. The wiring board 1 further has a first region A and a second region B, which are constituted by the insulating layers 111, 112 and portions of the conductor layers 12, 121, respectively, and the plurality of conductor layers 12, 121 each include a first conductor layer 12 formed across the first region A and second region B and a second conductor layer 121 formed only in the second region B, the plurality of insulating layers 111, 112 include a first insulating layer 112 in contact with the first conductor layer 12 at the top surface 112a and a second insulating layer 111 in contact with the second conductor layer 121 at the top surface 111a, and the first insulating layer 112 and the second insulating layer 111 have different surface roughnesses on the top surfaces 111a and 112a.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a wiring board.

Background Art

[0002] Patent Document 1 discloses a wiring board including a first wiring member composed of an insulating layer and a wiring layer laminated on each surface of a core layer, and a second wiring member having a smaller layer thickness and a higher wiring density than the first wiring member and laminated outside the first wiring member.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the wiring board disclosed in Patent Document 1, for each of the wiring that requires a high-density arrangement and the wiring that does not require a high-density arrangement, the degree of freedom in the arrangement position may be low. For example, it may not be possible to provide both the wiring that requires a high-density arrangement and the other wiring in the vicinity of either the front or back outer surface or in the vicinity of the core substrate. Also, for example, it may be difficult to provide wirings having different desired distances from an adjacent wiring layer for realizing desired electrical characteristics in the same wiring layer. Further, wirings having different wiring densities and electrical characteristics required may not be provided on insulating layers having preferable forms and characteristics for each of them.

Means for Solving the Problems

[0005] The wiring board of the present invention includes a plurality of laminated insulating layers and a plurality of conductor layers laminated via any of the plurality of insulating layers, and has a first surface as an outer surface intersecting the lamination direction of the plurality of insulating layers. The wiring board further has a first region and a second region adjacent to each other, each composed of a portion of the plurality of insulating layers and the plurality of conductor layers, and the plurality of conductor layers include a first conductor layer formed across the first region and the second region, and a second conductor layer formed only within the second region and alternately laminated with the first conductor layer in the second region with any of the plurality of insulating layers in between, and the plurality of insulating layers include a first insulating layer in contact with the first conductor layer on its upper surface facing the first surface, and a second insulating layer in contact with the second conductor layer on its upper surface facing the first surface, and the surface roughness of the upper surfaces of the first insulating layer and the second insulating layer are different from each other.

[0006] According to embodiments of the present invention, the degree of freedom in wiring placement can be increased for each wiring that has different requirements regarding placement density and electrical characteristics. Furthermore, wiring with such different requirements can be formed on an insulating layer suitable for each wiring, and as a result, good electrical characteristics can be obtained. [Brief explanation of the drawing]

[0007] [Figure 1] A cross-sectional view showing an example of a wiring board according to one embodiment of the present invention. [Figure 2] A plan view showing an example of a wiring board in a plan view, as shown in Figure 1. [Figure 3] Enlarged view of part III in Figure 1. [Figure 4] An enlarged view of an example of part IV in Figure 3. [Figure 5A] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5B] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5C] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5D]A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5E] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5F] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5G] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5H] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5I] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5J] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5K] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5L] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5M] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Figure 5N] A cross-sectional view showing an example of the manufacturing process for a wiring board according to one embodiment. [Modes for carrying out the invention]

[0008] A wiring board according to one embodiment of the present invention will be described with reference to the drawings. Figure 1 shows a cross-sectional view of a wiring board 1, which is an example of a wiring board of this embodiment. Figure 2 shows an example of a plan view of the wiring board 1 from the first surface FA side. Figure 1 is a cross-sectional view taken along line II in Figure 2. "Plan view" means viewing the object from a line of sight along the thickness direction of the wiring board 1. Furthermore, Figure 3 shows an enlarged view of part III in Figure 1. Note that the wiring board 1 is merely an example of a wiring board of the embodiment. For example, the number of conductor layers and insulating layers included in the wiring board of the embodiment is not limited to the number of conductor layers and insulating layers included in the wiring board 1 in Figure 1. Also, in the drawings referenced in the following description, certain parts may be enlarged to make the disclosed embodiment easier to understand, and the size and length of each component may not be depicted in the exact proportions between them.

[0009] The wiring board 1 shown in Figure 1 includes a core substrate 100 having two main surfaces (first main surface F1 and second main surface F2) that are substantially perpendicular to the thickness direction of the wiring board 1. The core substrate 100 includes an insulating layer 101, a conductor layer 102 formed on both sides of the insulating layer 101, and a through-hole conductor 103 connecting the two conductor layers 102. The first main surface F1 and the second main surface F2 are formed by the exposed portions of the two surfaces of the insulating layer 101 that are substantially perpendicular to the thickness direction of the wiring board 1. The interior of the through-hole conductor 103 is filled with a resin body 103i containing epoxy resin or the like.

[0010] The wiring board 1 further includes a first build-up section 10 and a second build-up section 20, which are respectively composed of a plurality of insulating layers and a plurality of conductive layers that are sequentially formed and laminated on each main surface of the core substrate 100 from the core substrate 100 side. The wiring board 1 has a first surface FA as an outer surface (outermost surface) that intersects with the lamination direction of the plurality of insulating layers laminated in the thickness direction of the wiring board 1, and a second surface FB which is the outer surface opposite to the first surface FA. In the example in Figure 1, the first surface FA and the second surface FB are substantially perpendicular to the thickness direction of the wiring board 1, that is, the lamination direction of the plurality of insulating layers.

[0011] In the wiring board 1 of the example of FIG. 1, on the first main surface F1 of the core substrate 100, two insulating layers 11, and three insulating layers 111 and insulating layer 112 are stacked respectively. In addition, on the first main surface F1, a conductor layer 120, four conductor layers 12, and three conductor layers 121 are stacked with one or two of these insulating layers interposed therebetween. An insulating layer 111 and an insulating layer 112 are interposed between each of the four conductor layers 12. An insulating layer 112 is interposed between each of the three conductor layers 121 and the conductor layer 12 on the first surface FA side of the wiring board 1. An insulating layer 111 is interposed between each of the three conductor layers 121 and the conductor layer 12 on the side opposite to the first surface FA side of the wiring board 1. On the other hand, on the second main surface F2 of the core substrate 100, five insulating layers 21, and five conductor layers 22 are stacked with any one of these insulating layers interposed therebetween.

[0012] Thus, the wiring board 1 of the embodiment includes a plurality of insulating layers stacked like the insulating layers 111 and 112, and a plurality of conductor layers like the conductor layer 12 and the conductor layer 121 stacked through any one of these plurality of insulating layers. The first build-up portion 10 is formed on the first main surface F1 of the core substrate 100 by the insulating layers 11, 111, 112, and the conductor layers 120, 12, 121, and the second build-up portion 20 is formed on the second main surface F2 by the insulating layer 21 and the conductor layer 22.

[0013] In the description of the wiring board of this embodiment, the side farther from the insulating layer 101 is also referred to as "upper", "upper side", "outer side", or "outer", and the side closer to the insulating layer 101 is also referred to as "lower", "lower side", "inner side", or "inner". Also, in each component, the surface facing away from the insulating layer 101 is also referred to as the "upper surface", and the surface facing the insulating layer 101 side is also referred to as the "lower surface". Therefore, the surface facing the first surface FA side in each conductor layer and each insulating layer in the first build-up portion 10 is also referred to as the "upper surface", and the surface facing the second surface FB side in each conductor layer and each insulating layer in the second build-up portion 20 is also referred to as the "upper surface". Note that the thickness direction of the wiring board 1, that is, the stacking direction of the plurality of insulating layers and the plurality of conductor layers, is also referred to as the "Z direction".

[0014] The insulating layers 101, 11, 111, 112, 21 can each be formed using an insulating resin. Examples of the insulating resin include thermosetting resins such as epoxy resin, bismaleimide triazine resin (BT resin), or phenolic resin, and thermoplastic resins such as fluororesin, liquid crystal polymer (LCP), ethylene fluoride (PTFE) resin, polyester (PE) resin, and modified polyimide (MPI) resin. Each of these insulating layers may contain a reinforcing material (core material), not shown, such as glass fiber. In the example of FIG. 1, the insulating layer 101 contains a reinforcing material 101r. Also, as will be described later, each of these insulating layers may contain inorganic fillers such as silica and alumina.

[0015] The wiring board 1 of FIG. 1 further includes a solder resist 110 formed on the first build-up portion 10 and a solder resist 210 formed on the second build-up portion 20. The solder resist 110 has an opening 110a that exposes the conductor pad 12p included in the conductor layer 12 on the first surface FA side. The solder resist 210 has an opening 210a that exposes a part of the conductor layer 22. The second surface FB of the wiring board 1 is formed by the upper surface of the solder resist 210 and the exposed portion of the upper surface of the conductor layer 22. The solder resists 110, 210 are each formed using, for example, a photosensitive epoxy resin or polyimide resin.

[0016] The wiring board 1 in Figure 1 further includes conductor posts BM. The conductor posts BM are formed on conductor pads 12p and protrude from the upper surface of the solder resist 110 through openings 110a in the solder resist 110. The upper surfaces of the conductor posts BM and the solder resist 110 each constitute the first surface FA of the wiring board 1. The conductor posts BM connect the components mounted on the wiring board 1 (first component E1 and second component E2 in the example of Figure 1) to the conductor pads 12p. That is, in the wiring board 1 of Figure 1, the first surface FA can be a component mounting surface on which external components such as the first component E1 are mounted. Therefore, the first surface FA has component mounting areas MA1 and MA2, as shown in Figures 1 and 2. In the example of Figure 1, the first component E1 is placed in component mounting area MA1 and the second component E2 is placed in component mounting area MA2. The components mounted on the wiring board 1 may be electronic components such as semiconductor integrated circuit devices such as microcontrollers and memory.

[0017] On the other hand, the exposed portion of the conductive layer 22 exposed at the opening 210a of the solder resist 210 is connected to a conductor (not shown) outside the wiring board 1, such as a pad on a wiring board other than the wiring board 1, like a motherboard of an electronic device, or any conductive mechanical component.

[0018] The conductor layers 12, 102, 120, 121, 22, and the conductor post BM, as well as the via conductors 13, 131, 23 described later, are formed using any metal, such as copper or nickel. Although each of these conductor layers, each via conductor, and the conductor post BM is shown in a simplified form as a single layer in Figure 1, they may each contain two or more metal films formed by plating or sputtering, as shown in the enlarged view in Figure 3.

[0019] The wiring board 1 of this embodiment has a first region A and a second region B, which are respectively composed of a plurality of insulating layers such as insulating layers 111 and 112, and a portion of a plurality of conductive layers such as conductive layers 12 and 121. As shown in Figures 1 to 3, the first region A and the second region B are adjacent and continuous. Specifically, in the example in Figures 1 to 3, insulating layer 111 and insulating layer 112 are continuous between the first region A and the second region B, respectively, and the portion of insulating layer 111 and insulating layer 112 within the first region A and the portion within the second region B are connected.

[0020] In the examples shown in Figures 1 to 3, the second region B occupies a part of the first build-up section 10. Specifically, the second region B occupies a part of the first build-up section 10 that is farther from the core substrate 100 in the Z direction, and also occupies a part of the first build-up section 10 in a plan view. On the other hand, the first region A is the area of ​​the wiring board 1 other than the second region B. In the examples shown in Figures 1 to 3, the first region A is shown as occupying a part of the first build-up section 10 other than the second region B. However, in this embodiment, the area occupied by the first region A may be the entire part of the first build-up section 10 other than the second region B, or it may be the entire part of the wiring board 1 other than the second region B.

[0021] In this embodiment, the "second region" may be a region formed by a laminate of one or more conductive layers formed only in a specific region of the wiring board of the embodiment in a plan view, a portion of the insulating layer in contact with the conductive layer that overlaps with the specific region in a plan view, and a portion of the conductive layer in contact with the insulating layer that overlaps with the specific region in a plan view. The "specific region" may be, for example, a region that occupies an area of ​​10% to 40% of the area of ​​the wiring board of the embodiment in a plan view at any position.

[0022] In the examples in Figures 1 to 3, the conductor layer 121 is formed only within a specific region, the second region B, while the conductor layer 12 is formed across both the first region A and the second region B. Therefore, in the examples in Figures 1 to 3, the second region B is composed of the conductor layer 12, the insulating layer 111, and the insulating layer 112, each of which overlaps with the conductor layer 121 in a plan view, and the conductor layer 121 itself. On the other hand, the first region A is composed of the conductor layer 12, the insulating layer 111, and the insulating layer 112, each of which is not within the second region B. In Figures 1 and 3, the conductor patterns of the conductor layer 12 are drawn separately in the first region A and the second region B, respectively, but the conductor patterns in the conductor layer 12 within the first region A and the conductor patterns in the second region B may be connected.

[0023] As described above, the multiple conductor layers constituting the wiring board 1 of this embodiment include a conductor layer 12 (first conductor layer) formed across the first region A and the second region B, and a conductor layer 121 (second conductor layer) formed only within the second region B. Only the second region B includes the conductor pattern of conductor layer 121 along with the conductor pattern of conductor layer 12, while the first region A does not include the conductor pattern of conductor layer 121. In the second region B, conductor layer 12 and conductor layer 121 are alternately stacked with one of the multiple insulating layers constituting the wiring board 1 (insulating layer 111 or insulating layer 112 in the example of Figure 1) sandwiched between them. That is, in the second region B, the stacking of conductor layers and insulating layers is repeated in the order of conductor layer 12, insulating layer 111, conductor layer 121, and insulating layer 112, moving from the core substrate 100 side toward the first surface FA side of the wiring board 1. In the first region A, the conductor layer and insulating layer are repeatedly stacked in the order of conductor layer 12, insulating layer 111, and insulating layer 112, moving from the core substrate 100 side toward the first surface FA side of the wiring substrate 1.

[0024] In Figures 1 to 3, conductor layers other than conductor layer 12 and conductor layer 121, such as conductor layer 120, are not included in either the first region A or the second region B. However, as mentioned above, the first region A may occupy all of the parts other than the second region B. Therefore, the multiple conductor layers constituting the wiring board of the embodiment may include conductor layers that are not included in either the first region A or the second region B, such as conductor layer 120, or they may include conductor layers that are included only in the first region A.

[0025] In the first region A, via conductors 13 are formed that continuously penetrate the insulating layers 111 and 112 interposed between the two conductor layers 12. The via conductors 13 in the first region A connect the conductor layers 12 to each other. Via conductors 13 are also formed in parts of the first build-up section 10 other than the first region A and the second region B, and these via conductors 13 penetrate the insulating layer 11 to connect the conductor layer 120 to the conductor layer 12, or connect the conductor layer 120 to the conductor layer 102. On the other hand, in the second region B, via conductors 131 are formed that penetrate the insulating layer 111 or the insulating layer 112 and connect the conductor layer 121 to the conductor layer 12. In the second build-up section 20, via conductors 23 are formed that penetrate the insulating layer 21 to connect the conductor layer 22 to the conductor layer 102, or connect the conductor layers 22 to each other.

[0026] In the first region A, a conductor layer 12 is formed on the upper surface of the insulating layer 112, while no conductor layer is formed on the upper surface of the insulating layer 111. On the other hand, in the second region B, similar to the first region A, a conductor layer 12 is formed on the upper surface of the insulating layer 112, and a conductor layer 121 is formed on the upper surface of the insulating layer 111. Thus, the plurality of insulating layers constituting the wiring board 1 of this embodiment include an insulating layer 112 (first insulating layer) that is in contact with the conductor layer 12 on the upper surface facing the first surface FA of the wiring board 1, and an insulating layer 111 (second insulating layer) that is in contact with the conductor layer 121 on the upper surface facing the first surface FA.

[0027] In the second region B, there is one insulating layer (insulating layer 111 or insulating layer 112) between two adjacent conductor layers (conductor layer 121 and conductor layer 12) in the Z direction. On the other hand, in the first region A, there are two insulating layers (insulating layer 111 and insulating layer 112) between two adjacent conductor layers (both conductor layers 12) in the Z direction. That is, the distance between adjacent conductor layers in the Z direction in the second region B (conductor layer 121 and conductor layer 12) is smaller than the distance between adjacent conductor layers in the Z direction in the first region A (two conductor layers 12). Therefore, the second region B may be defined as a region within which the distance between adjacent conductor layers in the Z direction is smaller than the distance between adjacent conductor layers in the first region A.

[0028] In the example shown in Figure 1, the thicknesses of the insulating layers 111 and 112 are smaller than the thickness of the insulating layer 11 interposed between the conductor layer 120 and the conductor layer 12 or conductor layer 102, and the insulating layer 21 interposed between the conductor layers 22 in the second build-up section 20. In other words, in the example shown in Figure 1, the spacing between adjacent conductor layers in the second region B in the Z direction is smaller than the spacing between any adjacent conductor layers in the Z direction in the parts of the wiring board 1 other than the second region B.

[0029] In the wiring board 1 of the embodiment, the conductor layer 121 formed only in the second region B is formed separately from the conductor layer 12 formed across the first region A and the second region B, and can therefore be formed using a different method than that used for the conductor layer 12. As a result, the conductor layer 121 and the conductor layer 121 may have different structures and / or characteristics. For example, the conductor layer 121 may be formed using a method suitable for high-density wiring pattern arrangement, while the conductor layer 12 may be formed using a method that is easier or less expensive than a method that enables high-density wiring pattern arrangement. Furthermore, in the wiring board of the embodiment, as shown in the example of Figure 1 where the conductor layer 121 and the conductor layer 12 are alternately stacked in the second region B, the conductor layer on which a high-density wiring pattern can be arranged, and other conductor layers, can be stacked at any position in the thickness direction of the wiring board. For example, as shown in the example of Figure 1, both the conductor layer 121 and the conductor layer 12 can be stacked near the first surface FA of the wiring board 1, or both the conductor layer 121 and the conductor layer 12 can be stacked closer to the core substrate 100 than the first surface FA. In other words, for each type of wiring, which has different requirements regarding placement density and electrical characteristics, there is a high degree of freedom in positioning within the thickness direction of the wiring board.

[0030] Furthermore, in the wiring board 1 of this embodiment, the conductor layer 121 is formed only in the second region B, so, for example, wiring requiring high density can be formed only in a limited area of ​​the wiring board. In the first region A, which does not include the conductor layer 121, the spacing between adjacent conductor layers can be wider than the spacing between adjacent conductor layers in the second region B. Therefore, for example, multiple wiring patterns with a wider range of characteristic impedances can be formed on a single conductor layer 12. Consequently, a wiring board with a smaller thickness composed of fewer conductor layers can be obtained compared to the case where a conductor layer is provided for each wiring pattern with different spacing requirements between adjacent conductor layers.

[0031] Conductor layers 12, 102, 120, 121, and 22 all contain arbitrary conductor patterns. For example, as mentioned above, the conductor layer 12 closest to the first face FA contains a conductor pad 12p. In the examples in Figures 1 and 2, the conductor pad 12p and the conductor post BM on it are all located inside the component mounting area MA1 or component mounting area MA2. In Figure 1, the second and fourth conductor layers 12 from the first face FA side contain wiring patterns DW. The three conductor layers 121 each contain multiple wiring patterns FW. In Figure 2, the wiring pattern FW of the conductor layer 121 closest to the first face FA side is shown as a dashed line.

[0032] The wiring patterns FW and DW, although not shown in the figures, are both signal lines that connect any conductor pads contained in either the conductor layer 12 or conductor layer 121 to propagate electrical signals. The wiring pattern FW may also connect two conductor pads 12p via a via conductor 131. For example, a portion of the wiring pattern FW shown in Figure 2 connects a conductor post BM located in the component mounting area MA1 to a conductor post BM located in the component mounting area MA2 via a via conductor 131. Therefore, when the wiring board 1 is used, the electrodes of components placed in the component mounting area MA1 and the electrodes of components placed in the component mounting area MA2 are electrically connected via the wiring pattern FW.

[0033] In other words, the second region B, on which the conductor layer 121 including the wiring pattern FW is formed, spans between two component mounting regions (component mounting regions MA1 and MA2) in a plan view and partially overlaps with each of the two component mounting regions. A portion of the wiring pattern FW extends between component mounting region MA1 and component mounting region MA2. Any number of components can be mounted on the wiring board 1. Therefore, the first surface FA may have one or any number of component mounting regions. If the first surface FA has two or more component mounting regions, the second region B may span between at least two of those regions in a plan view and partially overlap with each of those at least two regions.

[0034] As shown in Figure 3, the wiring pattern FW included in the conductor layer 121 formed only in the second region B has a wiring width W1 and a spacing G between adjacent wiring patterns FW. For example, the minimum wiring width of multiple wiring patterns such as the wiring pattern FW included in the conductor layer 121 may be smaller than the minimum wiring width of multiple wiring patterns such as the wiring pattern DW included in the conductor layer 12. Also, the minimum spacing between each wiring pattern in the multiple wiring patterns included in the conductor layer 121 may be smaller than the minimum spacing between wiring patterns included in the conductor layer 12. It is possible to provide wiring patterns arranged at a fine pitch only in a specific region.

[0035] In the wiring board of the embodiment, the minimum value of the wiring width of the wiring pattern included in the conductor layer 121 may be 1 μm or more and 5 μm or less, and the minimum value of the spacing G between the wiring patterns may be 3 μm or more and 7 μm or less. That is, the conductor layer 121 may include wiring patterns having a wiring width of 5 μm or less and spacing of 7 μm or less between adjacent wiring patterns. In the example in Figure 3, the width W1 of the wiring pattern FW may be 1 μm or more and 5 μm or less, and the spacing G between the wiring patterns FW may be 3 μm or more and 7 μm or less. When the wiring pattern FW has such a fine minimum wiring width and fine minimum wiring spacing, it is thought that components such as the first component E1 and the second component E2 in Figure 1 are connected by multiple signal lines with a small occupied area. Therefore, the wiring board 1 of the embodiment may be realized in a smaller size than conventional wiring boards.

[0036] In addition, in the wiring board 1 of this embodiment, wiring patterns included in the conductor layer 121, such as wiring patterns FW which may have such fine wiring widths, may have a thickness greater than their wiring width. Therefore, in this embodiment, wiring patterns included in the conductor layer 121 may have a relatively large aspect ratio (for example, thickness T of wiring pattern FW / width W1 of wiring pattern FW). For example, the aspect ratio of each of the multiple wiring patterns included in the conductor layer 121 may be 2.0 or more and 4.0 or less.

[0037] Wiring patterns with such aspect ratios can have low conductor resistance relative to their small wiring width. Therefore, for example, the insertion loss of the wiring pattern FW may be low. As a result, signals can be propagated with less transmission loss. Furthermore, for example, a desired characteristic impedance can be easily obtained in the wiring pattern FW, and insertion loss can be further reduced. The thickness T of the wiring pattern FW, i.e., the thickness of the conductor layer 121, can be 4 μm or more and 7 μm or less. When such a thickness is obtained, effects such as the reduction of insertion loss described above can be obtained without significantly increasing the thickness of the wiring board of the embodiment.

[0038] In the wiring board of the embodiment, the surface 121a of the conductor layer 121 formed in the second region B, facing the first surface FA of the wiring board 1, may be a polished surface. In that case, the surface 121a may have a surface roughness lower than, for example, the surface roughness of a plating film formed by metal deposition. Therefore, in the wiring pattern FW included in the conductor layer 121, a decrease in signal transmission characteristics and an increase in voltage drop due to an increase in substantial conductor resistance caused by the skin effect observed in high-frequency signal transmission may be less likely to occur. Furthermore, if the surface 121a is a polished surface, the thickness of the wiring pattern FW tends to be approximately constant over its entire length, and thus, fluctuations in the characteristic impedance of the wiring pattern FW are less likely to occur. Therefore, reflection loss in the wiring pattern 121 may be suppressed. For example, the polished surface that the conductor layer 121 has as surface 121a may have an arithmetic mean roughness (Ra) of 0.3 μm or less. When such a surface roughness is obtained, the above-mentioned desirable effects regarding transmission characteristics may be obtained.

[0039] In the example shown in Figure 3, the conductor layers 12, 120, 121, via conductors 13, 131, and conductor post BM are composed of a lower layer 12a and an upper layer 12b formed on the lower layer 12a. The upper layer 12b is entirely formed on the lower layer 12a, that is, on the first surface FA side of the wiring board 1 relative to the lower layer 12a. The surface of the upper layer 12b constituting the conductor layer 121 on the first surface FA side may be the polished surface described above. The lower layer 12a is interposed between the upper layer 12b and the insulating layer immediately below the upper layer 12b (for example, between the upper layer 12b constituting the conductor layer 121 and the insulating layer 111, or between the upper layer 12b constituting the conductor layer 12 and the insulating layer 11 or insulating layer 112). The lower layer 12a is formed directly on the surface of each insulating layer, such as the upper surface 111a of the insulating layer 111 or the upper surface 112a of the insulating layer 112, which is on the first surface FA side.

[0040] The upper layer 12b consists of a plating film formed by electroplating. On the other hand, the lower layer 12a consists of a metal film formed by any method. In particular, the lower layer 12a constituting the conductive layer 121 may be a sputtered film formed by sputtering, for example. On the other hand, the lower layer 12a constituting the conductive layer 12 may be an electroless plating film formed by electroless plating. The lower layer 12a is an electrode that conducts the plating current during the formation of the upper layer 12b by electroplating, and functions as a seed layer (or power supply layer) that can promote the deposition of the plating metal.

[0041] When the lower layer 12a is made of a sputtered film, the sputtered film is easily formed to a thin and uniform thickness, so the upper surface of the conductor layer, such as the conductor layer 121, may have high flatness. In addition, when the lower layer 12a is made of a sputtered film, strong adhesion between the conductor layer, such as the conductor layer 121, and the insulating layer, such as the insulating layer 111, may be obtained. Furthermore, since the sputtered film can adhere strongly to each insulating layer in this way, the upper surface of each insulating layer (for example, the upper surface 111a of the insulating layer 111) may not have large irregularities in order to obtain a so-called anchoring effect. As a result, unnecessary parts of the seed layer during the formation of the conductor layer, such as the conductor layer 121, can be removed quickly and sufficiently, and effects such as preventing short circuits, ensuring desired electrical characteristics, and suppressing a decrease in the width and thickness of the wiring pattern may be obtained in the conductor layer 121, etc.

[0042] As described above, each insulating layer constituting the wiring board of the embodiment is mainly composed of an insulating resin such as a thermosetting resin or a thermoplastic resin, and may optionally contain an inorganic filler such as silica. However, in the wiring board of the embodiment, the surface roughness of the upper surfaces 111a and 112a of insulating layer 111 and insulating layer 112 are different from each other. As described above, insulating layer 111 is an insulating layer (second insulating layer) that is in contact with a conductor layer formed only in the second region B, such as conductor layer 121, at its upper surface 111a, and insulating layer 112 is an insulating layer (first insulating layer) that is in contact with a conductor layer formed in regions other than the second region B, such as conductor layer 12, at its upper surface 112a.

[0043] Furthermore, insulating layers 111 and 112 may differ from each other in terms of their constituent materials, in addition to the difference in surface roughness of their upper surfaces 111a and 112a. For example, insulating layers 111 and 112 may differ in terms of the composition ratio of the main component such as epoxy resin, the content of the inorganic filler mentioned above, the particle size of the inorganic filler, and / or the properties such as relative permittivity, dielectric loss tangent, and thermal expansion coefficient based on these. The conductor layer 121 formed on the upper surface 111a of insulating layer 111 and the conductor layer 12 formed on the upper surface 112a of insulating layer 112 may have different requirements regarding the arrangement density of the wiring pattern and electrical characteristics, as mentioned above. In the wiring board of the embodiment, insulating layers 111 and 112, each formed on their respective upper surfaces, differ in terms of the state of their upper surfaces 111a and 112a. Furthermore, insulating layers 111 and 112 may differ from each other in terms of their constituent materials. Therefore, the required wiring pattern density and electrical characteristics for each conductor layer are more easily achieved.

[0044] Figure 4 shows an enlarged example of a portion corresponding to part IV in Figure 3, where insulating layers 111 and 112 each contain inorganic fillers 3s and 3b, respectively, with different particle sizes for inorganic fillers 3s and 3b. Insulating layers 111 and 112 also differ from each other in terms of the surface roughness of their upper surfaces 111a and 112a. In the example in Figure 4, insulating layer 111 contains an insulating resin 11m, such as epoxy resin, and granular inorganic fillers 3s added to the insulating resin 11m. Similarly, in the example in Figure 4, insulating layer 112 also contains an insulating resin 11m, such as epoxy resin, and granular inorganic fillers 3b added to the insulating resin 11m.

[0045] Furthermore, the maximum particle size of the inorganic filler 3s contained in the insulating layer 111 is smaller than the maximum particle size of the inorganic filler 3b in the insulating layer 112. Note that the "particle size" of each inorganic filler 3s and 3b is the longest distance between two points on the surface of each inorganic filler. For example, the insulating layer 111 may contain multiple inorganic fillers 3s having a maximum particle size of 1 μm or less. If the particle size of the inorganic filler 3s contained in the insulating layer 111 is small, short-circuit failures due to leakage paths along the inorganic filler 3s may be less likely to occur, for example, between wiring patterns arranged at a fine pitch, such as wiring pattern FW. In addition, it may be easier to form minute via conductors 131 (see Figure 3).

[0046] Furthermore, the insulating layer 111 and the insulating layer 112 may have different concentrations of inorganic fillers 3s and 3b. For example, the concentration of inorganic filler 3s in the insulating layer 111 may be, for example, 50% or more and 70% or less.

[0047] For example, the relative permittivity and dielectric loss tangent of insulating layer 111 and insulating layer 112 may differ depending on the content and particle size of the inorganic fillers 3s and 3b, as described above. For example, from the viewpoint of realizing the characteristic impedance required for the conductor patterns of conductor layer 11 and conductor layer 121, it is preferable that insulating layer 111 and insulating layer 112 each have their own unique relative permittivity. Also, for example, when a signal with a higher frequency than the signal propagating through wiring pattern DW (see Figure 3) propagates through wiring pattern FW, it is preferable that insulating layer 111 has a lower permittivity and smaller dielectric loss than insulating layer 112 in order to obtain good transmission characteristics of the high-frequency signal. In such cases, the relative permittivity of insulating layer 111 may be lower than that of insulating layer 112, and the dielectric loss tangent of insulating layer 111 may be smaller than that of insulating layer 112. For example, at a frequency of 5.8 GHz, the relative permittivity of the insulating layer 111 may be approximately 3.0 or more and 4.0 or less, and the dielectric loss tangent may be approximately 0.001 or more and 0.005 or less.

[0048] Furthermore, in the example shown in Figure 4, the surface roughness of the upper surface 111a of the insulating layer 111 is lower than that of the upper surface 112a of the insulating layer 112. As mentioned above, the lower layer 12a of the conductor layer 121 formed on the upper surface 111a of the insulating layer 111 may be a sputtered film. Since strong adhesion is obtained between the lower layer 12a, which is made of a sputtered film, and the insulating layer 111, the upper surface 111a of the insulating layer 111 does not necessarily need to have large irregularities, i.e., high surface roughness, in order to obtain a so-called anchoring effect. Rather, an upper surface 111a with low surface roughness may allow for the appropriate and rapid removal of the metal film that functions as a seed layer (power supply layer) and partially constitutes the lower layer 12a during the formation of the conductor layer 121, as described later. This may also suppress thinning of the wiring pattern FW during the etching removal of the metal film. Therefore, it is sometimes preferable that the upper surface 111a of the insulating layer 111 has a surface roughness lower than that of the upper surface 112a of the insulating layer 112. For example, the insulating layer 111 may have a root mean square roughness (Rq) of 0.08 μm or less as the surface roughness of the upper surface 111a.

[0049] Next, with reference to Figures 5A to 5N, an example of a method for manufacturing a wiring board according to one embodiment will be described, using the case where the wiring board 1 shown in Figure 1 is manufactured as an example. Unless otherwise stated, each component may be formed using any of the materials previously described for each component of the wiring board 1.

[0050] As shown in Figure 5A, a core substrate 100 is prepared. For example, a double-sided copper-clad laminate is prepared in which a metal foil is provided on the surface of an insulating layer 101. Through holes 103h are formed in this double-sided copper-clad laminate, for example, by drilling. An electroless plating film is formed on the inner wall of the through holes 103h and the upper surface of the metal foil, and then an electrolytic plating film is formed using this electroless plating film as a power supply layer. As a result, a through-hole conductor 103 covering the inner wall of the through holes 103h is formed.

[0051] The interior of the through-hole conductor 103 is filled with a resin body 103i, for example, by injecting epoxy resin. After the filled resin body 103i has solidified, an electroless plating film and an electrolytic plating film are further formed on the upper surface of the resin body 103i and the electrolytic plating film. As a result, a conductor layer 102 is formed on both sides of the insulating layer 101. Then, a core substrate 100 having a predetermined conductor pattern is obtained by patterning the conductor layer 102, for example, by wet etching.

[0052] As shown in Figure 5B, an insulating layer 11 is formed on the first main surface F1 of the core substrate 100, and a conductor layer 120 is formed on the insulating layer 11. An insulating layer 21 is formed on the second main surface F2 of the core substrate 100, and a conductor layer 22 is formed on the insulating layer 21. For example, the insulating layers 11 and 21 are formed by thermocompression bonding a film-like insulating resin onto the core substrate 100. The conductor layers 120 and 22 are formed using any method for forming conductor layers, such as the semi-additive method. Through holes 13a and 23a are formed in the insulating layer 11 and insulating layer 21 directly above the core substrate 100, respectively, by irradiation with carbon dioxide laser light, and via conductors 13 are formed in the through holes 13a and 23 in the through holes 23a, along with the formation of the conductor layers 120 and 22. Subsequently, an insulating layer 11 is formed on the conductive layer 120, and an insulating layer 21 is formed on the conductive layer 22. Through holes 13a and 23a are then formed in these insulating layers 11 and 21, for example, by irradiation with carbon dioxide laser light.

[0053] As shown in circle C, which is an enlarged view of section VB in Figure 5B, in the example of Figure 5B, an insulating layer 11 containing inorganic filler 3b is formed. Preferably, after the formation of the through-hole 13a, a desmear treatment is performed to remove resin residue (smear) present in the through-hole 13a. In the desmear treatment, for example, the inside of the through-hole 13a and the upper surface 11a of the insulating layer 11 are exposed to a solution containing alkaline permanganate. In the example shown in Figure 5B, as shown in circle C, the upper surface 11a of the insulating layer 11 is roughened to have a desired surface roughness by this desmear treatment, or by a roughening treatment performed separately from this desmear treatment. Note that the desmear treatment of the upper surface 11a of the insulating layer 11 may be performed using a plasma gas as described later, instead of using the specific solution described above. The roughening treatment improves the adhesion between the metal film formed as a seed layer in the formation of the conductor layer 120 and / or conductor layer 12 (see Figure 5C) by the semi-additive method and the insulating layer 11.

[0054] As shown in Figure 5C, a conductor layer 12 is formed on top of the insulating layer 11 covering the conductor layer 120. The conductor layer 12 is formed, for example, by a semi-additive method, similar to the formation of the conductor layer 120 described above. A conductor layer 22 is also formed on the second main surface F2 side of the core substrate 100. After the formation of the conductor layers 12 and 22, until the formation of the conductor post BM shown in Figure 5M is completed, the exposed surfaces of the conductor layer 22 and insulating layer 21 on the second main surface F2 side of the core substrate 100 may be appropriately protected using, for example, a PET film (not shown).

[0055] As shown in Figure 5D, an insulating layer 111 is formed on the conductor layer 12 and the insulating layer 11. The insulating layer 111 can be formed, for example, by thermocompressing a film-like epoxy resin onto the conductor layer 12 and the insulating layer 11, similar to the formation of the insulating layer 11. Through holes 132 are formed in the insulating layer 111 at the locations where via conductors 131 (see Figure 1) are formed by irradiation with carbon dioxide laser light or the like.

[0056] Figure 5E shows an enlarged view of the VE section in Figure 5D. Figures 5F to 5I, which are referenced below, show enlarged views of the portion corresponding to the VE section shown in Figure 5D after the processes described with reference to these figures. As shown in Figure 5E, an insulating layer 111 is formed containing inorganic filler 3s having a maximum particle size smaller than the particle size of inorganic filler 3b contained in the insulating layer 11.

[0057] After the through-hole 132 is formed, a desmear treatment is preferably performed to remove any remaining resin debris in the through-hole 132. In the example shown in Figure 5E, the desmear treatment slightly roughens the upper surface 111a of the insulating layer 111. However, as shown in Figure 5E, the surface roughness of the upper surface 111a of the insulating layer 111 may be lower than the surface roughness of the upper surface 11a of the insulating layer 11.

[0058] Desmear treatment may be a wet treatment using a chemical solution such as a permanganate solution, as mentioned above, but it may also be a dry treatment. For example, plasma treatment using plasma gases such as argon, methane tetrafluoride, a mixture of methane tetrafluoride and oxygen, or sulfur hexafluoride may be performed as a dry treatment. In desmear treatment by plasma treatment, erosion of the upper surface 111a of the insulating layer 111 is suppressed compared to wet treatment, and therefore, the increase in surface roughness of the upper surface 111a through desmear treatment may be suppressed.

[0059] As shown in Figure 5F, a metal film 12aa made of, for example, copper or nickel is formed inside the through hole 132 and on the entire surface of the upper surface 111a of the insulating layer 111 by, for example, sputtering or electroless plating. The metal film 12aa is a metal film that functions as a seed layer (power supply layer) when forming the electroplated film 12ba (see Figure 5G), which will be described later. For example, when the metal film 12aa is formed by sputtering, a seed layer that exhibits high adhesion with the insulating layer 111 may be formed. Therefore, as mentioned above, even if the surface roughness of the upper surface 111a of the insulating layer 111 is not very high, that is, even if the so-called anchoring effect is not very strong, it is considered that delamination between the insulating layer 111 and the metal film 12aa is unlikely to occur. A part of the metal film 12aa constitutes the lower layer 12a of the conductor layer 121 (see Figure 3) when the wiring board 1 is completed.

[0060] Furthermore, as shown in Figure 5F, a plating resist R1 having a plurality of groove-shaped openings R11 that expose the metal film 12aa is formed on the metal film 12aa. In the example in Figure 5F, the plating resist R1 is formed which further includes openings R12 that expose through holes 132 covered by the metal film 12aa. The plating resist R1 is formed, for example, by laminating a dry film resist, and the openings R11 and R12 are formed by exposure and development. The openings R11 and R12 are formed in a pattern corresponding to the conductor pattern that the conductor layer 121 (see Figure 5I) formed on the insulating layer 111 should include. In addition, the openings R11 are formed to have a width and spacing corresponding to the width and spacing of the wiring pattern (for example, the wiring pattern FW illustrated in Figure 3) that the conductor layer 121 should have. Preferably, the plating resist R1 is formed which has a thickness (depth of the openings R11) that exceeds the thickness of the conductor layer 121 that is formed.

[0061] As shown in Figure 5G, an electroplated film 12ba is formed in the multiple openings R11 and R12 of the plating resist R1 by electroplating using a metal film 12aa as a power supply layer. Preferably, an electroplated film 12ba thicker than the plating resist R1 is formed. For example, an electroplated film 12ba made of copper or nickel is formed. Via conductors 131 are formed in the through holes 132 of the insulating layer 111. A portion of the electroplated film 12ba constitutes the upper layer 12b (see Figure 3) of the conductor layer 121 formed on the insulating layer 111 when the wiring board 1 is completed. The electroplated film 12ba may be formed to completely fill the openings R11 and R12, as in the example in Figure 5G, and may also have a curved upper surface that protrudes upward from the upper surface of the plating resist R1.

[0062] A portion of the upper surface of the electroplated film 12ba, including the portion of the plating resist R1 that protrudes from the upper surface, is removed by polishing, as shown in Figure 5H. A portion of the upper surface of the plating resist R1 may also be removed by polishing together with a portion of the electroplated film 12ba. Polishing of the electroplated film 12ba and the plating resist R1 is carried out by any method, such as chemical mechanical polishing (CMP). The electroplated film 12ba is polished so that the height of its upper surface (height from the upper surface 111a of the insulating layer 111) is, for example, 4 μm or more and 7 μm or less. As a result of polishing, the upper surface of the electroplated film 12ba may have an arithmetic mean roughness (Ra) of 0.3 μm or less. After polishing the electroplated film 12ba, the plating resist R1 is removed.

[0063] Furthermore, as shown in Figure 5I, portions of the metal film 12aa not covered by the electroplating film 12ba are removed, for example, by quick etching. As mentioned above, if the roughening of the upper surface 111a of the insulating layer 111 is suppressed by desmearing using plasma gas, the unnecessary portions of the metal film 12aa are removed appropriately and quickly. Therefore, it is considered that short-circuit failures and a decrease in insulation performance between adjacent conductor patterns, such as wiring patterns FW, on the upper surface 111a of the insulating layer 111 are less likely to occur.

[0064] As a result of removing the unnecessary portion of the metal film 12aa, a conductor layer 121 is obtained, which includes predetermined conductor patterns that are electrically isolated from each other, such as wiring patterns FW, as shown in Figure 5J. The conductor layer 121 is formed only in a specific region (second region B).

[0065] As shown in Figure 5K, an insulating layer 112 is laminated on the conductor layer 121 and the insulating layer 111, a via conductor 131 is formed within the insulating layer 112, and a conductor layer 12 is formed on the upper surface 112a of the insulating layer 112.

[0066] The insulating layer 112 is formed by thermocompression bonding a film-like insulating resin, such as epoxy resin, onto the conductor layer 121 and the insulating layer 111, similar to the method for forming the insulating layer 11 described above. For example, an insulating layer 112 made of the same constituent materials as the insulating layer 11 is formed. However, in the manufacturing process of the wiring board of this embodiment, an insulating layer 112 with different constituent materials from the insulating layer 111 may be formed. For example, an insulating layer 112 may be formed that includes inorganic filler 3b (see Figure 4) having a particle size larger than the maximum particle size of inorganic filler 3s (see Figure 5E) contained in the insulating layer 111. Furthermore, in the manufacturing process of the wiring board of this embodiment, an insulating layer 112 with a different surface condition from the insulating layer 111 may be formed. For example, after thermocompression bonding of the film-like resin and before the formation of the conductor layer 12 and the via conductor 131, the upper surface 112a of the insulating layer 112 may be roughened by desmearing or roughening treatment using a specific solution as described above. As a result, the upper surface 112a of the insulating layer 112a may have a higher surface roughness than the surface 111a of the insulating layer 111.

[0067] The formation of the conductor layer 12 on the insulating layer 112 and the formation of via conductors 131 within the insulating layer 112 are carried out by a semi-additive method, similar to the method for forming the conductor layer 120 and conductor layer 12 described with reference to Figures 5B and 5C. In this semi-additive method, the metal film (not shown) formed on the insulating layer 112 as a power supply layer for electroplating and constituting the lower layer 12a (see Figure 3) of the conductor layer 12 can be formed by electroless plating or sputtering. As mentioned above, if the upper surface 112a of the insulating layer 112 has a relatively high surface roughness, even if the metal film functioning as a power supply layer is formed by electroless plating, it is considered that a metal film that is difficult to peel off from the insulating layer 112 is formed due to a sufficient anchoring effect.

[0068] In areas where the conductor layer 121 is not formed in a plan view, via conductors 13 that continuously penetrate the insulating layer 111 and the insulating layer 112 are formed along with the formation of the conductor layer 12 on the insulating layer 112.

[0069] As shown in Figure 5L, the formation of the insulating layer 111, the conductive layer 121, the insulating layer 112, and the conductive layer 12 is repeated twice in the same manner as described with reference to Figures 5D to 5K. The formation of the first build-up section 10 is completed.

[0070] As shown in Figure 5M, a solder resist 110 is formed on the first build-up portion 10. For example, a resin film made of a photosensitive epoxy resin is formed by spraying, curtain coating, or lamination. An opening 110a is formed in the resin film by exposure and development, exposing the conductor pad 12p. Conductor posts BM are formed on the conductor pad 12p exposed through the opening 110a, filling the opening 110a and protruding onto the solder resist 110. Conductor posts BM are formed by a method similar to the semi-additive method, i.e., by steps such as electroless plating or sputtering, formation of a plating resist (not shown), electroplating, removal of the plating resist, and quick etching.

[0071] As shown in Figure 5N, the formation of the insulating layer 21 and the conductive layer 22, as described with reference to Figure 5B, is repeated three times on the second main surface F2 side of the core substrate 100. A solder resist 210 having an opening 210a that exposes a portion of the conductive layer 22 is formed on the outermost conductive layer 22 in the same manner as the solder resist 110 formation method described above. Through these steps, the wiring board 1 shown in Figure 1 is completed.

[0072] The wiring boards of the embodiments are not limited to those having the structures illustrated in each drawing, or the structures, shapes, and materials illustrated herein. As stated above, the wiring boards of the embodiments may include any number of conductor layers and insulating layers. The wiring boards of the embodiments do not necessarily include a core substrate and may be so-called coreless wiring boards. The conductor post BM provided in the wiring board 1 illustrated in Figure 1 is not necessarily provided in the wiring boards of the embodiments. In the examples in Figures 1 to 3, the insulating layer 111 and insulating layer 112 do not necessarily contain inorganic fillers. The insulating layer 111 and insulating layer 112 are not necessarily different from each other in terms of the maximum particle size of the inorganic fillers they contain. The wiring boards of the embodiments may have a plurality of second regions. [Explanation of symbols]

[0073] 1 Wiring board 11 Insulating layer 11m insulating resin 111 Insulating layer (second insulating layer) 111a Upper surface of insulating layer 111 112 Insulating layer (first insulating layer) 112a Upper surface of insulating layer 112 12 Conductor layer (First conductor layer) 121 Conductor layer (second conductor layer) 121a Surface of the conductor layer 121 facing the first surface 12a Lower layer of conductor layers 12 and 121 12b Upper layer of conductor layers 12 and 121 3b, 3s Inorganic fillers A 1st area B 2nd area Wiring pattern included in DW conductor layer 12 Multiple wiring patterns included in the FW conductor layer 121 FA Page 1 G Wiring spacing MA1, MA2 component mounting areas W1 Wiring width

Claims

1. Multiple stacked insulating layers, A plurality of conductive layers stacked via any one of the aforementioned plurality of insulating layers, It includes, A wiring substrate having a first surface as an outer surface intersecting the stacking direction of the plurality of insulating layers, The wiring board further comprises a first region and a second region adjacent to each other, each composed of a portion of the plurality of insulating layers and a portion of the plurality of conductive layers. The plurality of conductive layers are, A first conductor layer formed across the first and second regions, The present invention includes a second conductor layer formed only within the second region and alternately stacked with the first conductor layer in the second region, with any of the plurality of insulating layers in between, The plurality of insulating layers include a first insulating layer that contacts the first conductor layer on its upper surface facing the first surface, and a second insulating layer that contacts the second conductor layer on its upper surface facing the first surface. The first insulating layer and the second insulating layer have different surface roughness levels on their upper surfaces facing the first surface.

2. A wiring board according to claim 1, The second insulating layer comprises an insulating resin and granular inorganic fillers added to the insulating resin. The maximum particle size of the inorganic filler is smaller than the maximum particle size of the inorganic filler in the first insulating layer.

3. The wiring board according to claim 1, wherein the surface roughness of the upper surface of the second insulating layer is lower than the surface roughness of the upper surface of the first insulating layer.

4. A wiring board according to claim 1, The relative permittivity of the second insulating layer is lower than that of the first insulating layer. The dielectric loss tangent of the second insulating layer is smaller than the dielectric loss tangent of the first insulating layer.

5. A wiring board according to claim 1, The second conductor layer includes a plurality of wiring patterns, The minimum wiring width of the plurality of wiring patterns is smaller than the minimum wiring width of the wiring pattern included in the first conductor layer. The minimum distance between each of the plurality of wiring patterns is smaller than the minimum distance between the wiring patterns included in the first conductor layer.

6. A wiring board according to claim 5, The minimum wiring width of the aforementioned plurality of wiring patterns is 5 μm or less. The minimum distance between each of the aforementioned multiple wiring patterns is 7 μm or less.

7. The wiring board according to claim 5, wherein the aspect ratio of each of the plurality of wiring patterns is 2.0 or more and 4.0 or less.

8. The wiring board according to claim 1, wherein the surface of the second conductor layer facing the first surface is a polished surface.

9. A wiring board according to claim 1, The first conductor layer and the second conductor layer are each composed of a lower layer directly formed on the upper surface of the first insulating layer or the upper surface of the second insulating layer, and an upper layer formed on the lower layer and consisting of a plating film. The lower layer constituting the second conductor layer is made of a sputtered film.

10. The wiring board according to claim 9, wherein the lower layer constituting the first conductor layer is made of an electroless plating film.

11. A wiring board according to claim 1, The first surface has two or more component mounting areas, each of which a component is placed. The second region, in a plan view, spans between at least two of the two or more component mounting regions and partially overlaps with each of the at least two regions.

12. A wiring board according to claim 1, wherein any two of the plurality of insulating layers are interposed between adjacent first conductor layers in the stacking direction of the plurality of insulating layers in the first region.

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