Semiconductor equipment

Abstract

To suppress a leakage current when causing a gate potential to rise in a switching element including a barrier region and a connection.SOLUTION: A semiconductor device comprises a gate electrode in a trench. A semiconductor substrate includes: a first n-type region in contact with a gate insulator film; a p-type upper body region in contact with the gate insulator film on a side face at a lower side of the first n-type region; an n-type barrier region in contact with the gate insulator film on the side face at a lower side of the upper body region; a p-type lower body region in contact with the gate insulator film on the side face at a lower side of the barrier region; a connection electrically connecting the barrier region and an upper electrode; an n-type drift region in contact with the gate insulator film on the side face at a lower side of the lower body region; and a second n-type region in contact with a lower electrode. A lower side portion of the gate insulator film is thicker than an upper side portion of the gate insulator film.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The technology disclosed in this specification relates to semiconductor devices.

[0002] The semiconductor device disclosed in Patent Document 1 has an IGBT (insulated gate bipolar transistor) and a diode. An n-type drift region is distributed across the IGBT region and the diode region. In the IGBT region, a p-type body region is provided above the drift region. The body region is separated into an upper body region and a lower body region by an n-type barrier region. The barrier region is electrically connected to the upper electrode by a connection part (more specifically, an n-type connection region). In the diode region, a p-type anode region is provided above the drift region, and an n-type cathode region is provided below the drift region. The anode region is in contact with the upper electrode, and the cathode region is in contact with the lower electrode. When the diode is on, holes flow from the anode region through the drift region to the cathode region. At this time, holes also flow from the body region in the IGBT region to the cathode region through the drift. When holes are injected from the body region to the cathode region in this way, losses are likely to occur when the diode then performs a reverse recovery operation. In the semiconductor device of Patent Document 1, by providing a barrier region and a connection part, the flow of holes from the body region in the IGBT region to the drift is suppressed when the diode is on. As a result, the reverse recovery loss is suppressed. Note that in Patent Document 1, although a barrier region and a connection part are provided in a semiconductor device having an IGBT and a diode, a barrier region and a connection part can also be provided in a MOSFET (metal-oxide-semiconductor field effect transistor). When a barrier region and a connection part are provided in a MOSFET, the loss during the reverse recovery operation of the body diode of the MOSFET can be suppressed.

Prior Art Documents

Patent Documents

[0003] [Patent Document 1] International Publication No. WO2015 / 029116 [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] In switching elements having a barrier region and a connection portion, when the gate potential is increased, a small leakage current may occur even if the gate potential has not reached the gate threshold. This specification proposes a technique for suppressing leakage current when the gate potential is increased. [Means for solving the problem]

[0005] The semiconductor device disclosed herein comprises a semiconductor substrate, a gate insulating film, a gate electrode, an upper electrode, and a lower electrode. A trench is provided on the upper surface of the semiconductor substrate. The gate insulating film covers the inner surface of the trench. The gate electrode is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film. The upper electrode is in contact with the upper surface of the semiconductor substrate. The lower electrode is in contact with the lower surface of the semiconductor substrate. The semiconductor substrate comprises a first n-type region, an upper body region, a barrier region, a lower body region, a connection portion, a drift region, and a second n-type region. The first n-type region is in contact with the upper electrode and with the gate insulating film on the side surface of the trench. The upper body region is a p-type region in contact with the gate insulating film on the lower side surface of the first n-type region. The barrier region is an n-type region in contact with the gate insulating film on the lower side surface of the upper body region. The lower body region is a p-type region that is in contact with the gate insulating film on the lower side surface of the barrier region and is separated from the upper body region by the barrier region. The connecting portion electrically connects the barrier region and the upper electrode. The drift region is an n-type region that is in contact with the gate insulating film on the lower side surface of the lower body region. The second n-type region has a higher n-type impurity concentration than the drift region, is located below the drift region, and is in contact with the lower electrode. The lower portion of the gate insulating film that is in contact with the lower body region is thicker than the upper portion of the gate insulating film that is in contact with the upper body region.

[0006] The semiconductor device described above may be a semiconductor device comprising an IGBT and a diode, or it may be a MOSFET. In the semiconductor device comprising an IGBT and a diode, the first n-type region is the emitter region of the IGBT, and the second n-type region is the cathode region of the diode. In the MOSFET, the first n-type region is the source region, and the second n-type region is the drain region. Furthermore, the connection portion may be an n-type connection region extending from the barrier region to the upper electrode, or it may be a conductive member extending from the barrier region to the upper electrode.

[0007] As described above, in conventional switching elements having a barrier region and a connection portion, leakage current is generated when the gate potential is increased. It has been found that this leakage current flows through the channel formed in the lower body region and the connection portion. In contrast, in the semiconductor device disclosed herein, the lower portion of the gate insulating film that is in contact with the lower body region is thicker than the upper portion of the gate insulating film that is in contact with the upper body region. With this configuration, channels are more easily formed in the upper body region than in the lower body region. Therefore, when channels are formed in the lower body region, current flows more easily through the channels in the upper body region and the channels in the lower body region, and leakage current flowing through the connection portion and the channels in the lower body region can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Cross-sectional view of the semiconductor device 10 of the embodiment. [Figure 2] Enlarged cross-sectional view of the area around the trench of the semiconductor device 10 in the embodiment. [Figure 3] Enlarged cross-sectional view of the trench area of ​​the comparative semiconductor device. [Figure 4] A graph showing the rise characteristics of the current Ic of the comparative semiconductor device. [Figure 5] A graph showing the rise characteristics of current Ic for normal and abnormal IGBTs that do not have a barrier region or connection. [Figure 6]Diagram illustrating the method for forming the gate insulating film. [Figure 7] Enlarged cross-sectional view of the area around the trench in the semiconductor device of Modification 1. [Figure 8] Cross-sectional view of the semiconductor device of modified example 2. [Figure 9] Cross-sectional view of the semiconductor device of modified example 3. [Modes for carrying out the invention]

[0009] In one example of a semiconductor device disclosed herein, the gate insulating film may have a thickness-changing portion in which the thickness increases from the upper portion toward the lower portion. In this case, the thickness-changing portion may be located within a range adjacent to the barrier region.

[0010] If the thickness-changing portion is located within the upper or lower body region, the variation in gate thresholds will increase during mass production of semiconductor devices. As described above, if the thickness-changing portion is located within the range adjacent to the barrier region, the variation in gate thresholds can be suppressed.

[0011] In one example semiconductor device disclosed herein, the p-type impurity concentration in the lower body region may be lower than the p-type impurity concentration in the upper body region.

[0012] To suppress electric field concentration around trenches in the off state of a semiconductor device, the p-type impurity concentration in the lower body region can be made lower than that in the upper body region. In this case, channels are more likely to form in the lower body region, and leakage current problems are more likely to occur. Even in this case, as described above, leakage current can be suppressed by making the lower portion of the gate insulating film thicker than the upper portion.

[0013] In one example of a semiconductor device disclosed herein, the semiconductor substrate is located below the drift region and may have a p-type collector region in contact with the lower electrode.

[0014] In one example of a semiconductor device disclosed herein, the connection portion is made of an n-type semiconductor and may be in Schottky contact with the upper electrode.

[0015] With this configuration, leakage current can be further suppressed by the Schottky barrier.

[0016] The Schottky barrier between the connection portion and the upper electrode may be 0.7 eV or less.

[0017] In one example semiconductor device disclosed herein, the upper portion may be made of a different material than the lower portion.

[0018] The semiconductor device 10 of the embodiment shown in FIG. 1 has a semiconductor substrate 12 made of silicon. Note that the semiconductor substrate 12 may be made of other semiconductor materials (e.g., SiC, GaN, etc.). When the semiconductor substrate 12 is viewed from above, an IGBT region 30 and a diode region 50 are provided in the semiconductor substrate 12. An IGBT is provided in the IGBT region 30, and a diode is provided in the diode region 50. The IGBT region 30 and the diode region 50 are adjacent to each other. A plurality of trenches 14 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 14 extends linearly in parallel with each other on the upper surface 12a. Each trench 14 is arranged at an interval. A plurality of trenches 14 are provided in each of the IGBT region 30 and the diode region 50. The inner surface of each trench 14 is covered with a gate insulating film 16. The gate insulating film 16 is made of silicon oxide. A gate electrode 18 is disposed in each trench 14 within the IGBT region 30. Each gate electrode 18 is insulated from the semiconductor substrate 12 by the gate insulating film 16. An electrode 19 is disposed in each trench 14 within the diode region 50. The electrode 19 may be an electrode connected to the gate electrode 18, or may be a dummy electrode having a potential independent of the gate electrode 18. The electrode 19 is insulated from the semiconductor substrate 12 by the gate insulating film 16. The upper surfaces of the gate electrode 18 and the electrode 19 are covered with an interlayer insulating film 20. An upper electrode 22 is disposed on the semiconductor substrate 12. The upper electrode 22 is in contact with the upper surface 12a of the semiconductor substrate 12 within the IGBT region 30 and the diode region 50. The upper electrode 22 is insulated from the gate electrode 18 and the electrode 19 by the interlayer insulating film 20. A lower electrode 24 is disposed under the semiconductor substrate 12. The lower electrode 24 is in contact with the lower surface 12b of the semiconductor substrate 12 within the IGBT region 30 and the diode region 50.

[0019] The semiconductor substrate 12 is provided with a plurality of emitter regions 32, an upper body region 34, a barrier region 36, a lower body region 38, a plurality of connection regions 40, a drift region 42, a collector region 44, and a cathode region 46.

[0020] The plurality of emitter regions 32 are n-type regions and are arranged within the IGBT region 30. Each emitter region 32 is arranged in a range sandwiched between two trenches 14 (hereinafter referred to as the range between trenches). Each emitter region 32 is arranged at a position including the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 22. Each emitter region 32 is in contact with the gate insulating film 16 at the upper end of the side surface of the trench 14. In FIG. 1, although the emitter region 32 is arranged in the IGBT region 30 while the emitter region 32 is not arranged in the diode region 50, the emitter region 32 may be arranged in both the IGBT region 30 and the diode region 50.

[0021] The upper body region 34 is a p-type region and is distributed across the IGBT region 30 and the diode region 50. The upper body region 34 has a plurality of contact regions 34a and a low-concentration region 34b. The low-concentration region 34b has a lower p-type impurity concentration than each contact region 34a. Each contact region 34a is arranged within the range between trenches. Each contact region 34a is arranged at a position including the upper surface 12a of the semiconductor substrate 12 and is in ohmic contact with the upper electrode 22. The low-concentration region 34b is arranged within the range between trenches. The low-concentration region 34b is in contact with the contact region 34a from below. The low-concentration region 34b is electrically connected to the upper electrode 22 through the contact region 34a. Within the IGBT region 30, the low-concentration region 34b is in contact with the emitter region 32 from below. The low-concentration region 34b is in contact with the gate insulating film 16 on the side surface of each trench 14. Within the IGBT region 30, the low-concentration region 34b is in contact with the gate insulating film 16 below the emitter region 32.

[0022] The barrier region 36 is an n-type region and is distributed across the IGBT region 30 and the diode region 50. The barrier region 36 is located within the trench range. The barrier region 36 is located below the low-concentration region 34b. The barrier region 36 is in contact with the gate insulating film 16 on the side of each trench 14. The barrier region 36 is in contact with the gate insulating film 16 below the low-concentration region 34b.

[0023] The lower body region 38 is a p-type region and is distributed across the IGBT region 30 and the diode region 50. The lower body region 38 is located within the trench range. The lower body region 38 is located below the barrier region 36 and is separated from the upper body region 34 by the barrier region 36. The lower body region 38 is in contact with the gate insulating film 16 on the sides of each trench 14. The lower body region 38 is in contact with the gate insulating film 16 below the barrier region 36. The lower body region 38 has a lower p-type impurity concentration than the low-concentration region 34b of the upper body region 34.

[0024] The multiple connection regions 40 are n-type regions. Multiple connection regions 40 are arranged in both the IGBT region 30 and the diode region 50. Each connection region 40 is located within the trench range. Each connection region 40 extends from the barrier region 36 through the upper body region 34 to the upper electrode 22. Each connection region 40 is in Schottky contact with the upper electrode 22. The Schottky barrier at the interface between each connection region 40 and the upper electrode 22 is 0.7 eV or less.

[0025] The drift region 42 is an n-type region having a lower n-type impurity concentration than the emitter region 32. The drift region 42 is distributed across the IGBT region 30 and the diode region 50. The drift region 42 is distributed across the lower part of multiple trenches 14. The upper end of the drift region 42 is distributed within the range between each trench. Within the range between each trench, the drift region 42 is in contact with the lower body region 38 from below. The drift region 42 is in contact with the gate insulating film 16 on the side and bottom surfaces of each trench 14. The drift region 42 is in contact with the gate insulating film 16 below the lower body region 38.

[0026] The collector region 44 is a p-type region and is located within the IGBT region 30. The collector region 44 is in contact with the drift region 42 from below. The collector region 44 is in ohmic contact with the lower electrode 24.

[0027] The cathode region 46 is an n-type region having a higher n-type impurity concentration than the drift region 42. The cathode region 46 is located within the diode region 50. The cathode region 46 is in contact with the drift region 42 from below. The cathode region 46 is in ohmic contact with the lower electrode 24.

[0028] Within the diode region 50, the upper body region 34 and the lower body region 38 function as a p-type anode region. Within the diode region 50, a PIN diode is formed by the upper body region 34, the lower body region 38, the drift region 42, and the cathode region 46. Within the IGBT region 30, an IGBT is formed by the emitter region 32, the upper body region 34, the lower body region 38, the drift region 42, the collector region 44, the gate electrode 18, and the gate insulating film 16.

[0029] Figure 2 is an enlarged cross-sectional view of the trench 14. As shown in Figure 2, the gate insulating film 16 is thicker in the lower part of the trench 14 than in the upper part of the trench 14. In the portion of the gate insulating film 16 that is in contact with the upper body region 34 (hereinafter referred to as the upper portion 16a), the gate insulating film 16 is thinner throughout. The thickness of the gate insulating film 16 increases in a stepped manner within the range in contact with the barrier region 36. In the portion of the gate insulating film 16 that is in contact with the lower body region 38 (hereinafter referred to as the lower portion 16b), the gate insulating film 16 is thicker throughout. In other words, the lower portion 16b is thicker than the upper portion 16a.

[0030] Next, the operation of the semiconductor device 10 will be described. When a higher potential is applied to the upper electrode 22 than to the lower electrode 24, the diode turns on. That is, electrons flow from the cathode region 46 to the upper body region 34 via the drift region 42, the lower body region 38, and the barrier region 36. Also, as shown by arrow 100 in Figure 1, holes flow from the upper body region 34 to the cathode region 46 via the barrier region 36, the lower body region 38, and the drift region 42. Furthermore, at the boundary between the IGBT region 30 and the diode region 50, as shown by arrow 102 in Figure 1, holes flow from the upper body region 34 in the IGBT region 30 to the cathode region 46 in the diode region 50. In this embodiment, a barrier region 36 is provided within the body region, and the barrier region 36 is electrically connected to the upper electrode 22 by the connection region 40, so the flow of holes as shown by arrows 100 and 102 is suppressed.

[0031] Subsequently, when the potential of the upper electrode 22 is lowered to a potential lower than that of the lower electrode 24, the flow of holes and electrons stops. At the same time, holes present in the drift region 42 are discharged to the upper electrode 22 via the lower body region 38, barrier region 36, and upper body region 34. This flow of holes causes a momentary reverse current (so-called reverse recovery current) to flow through the diode. Also, at the boundary between the IGBT region 30 and the diode region 50, a reverse recovery current flows in the opposite direction to arrow 102 in Figure 1. As described above, in this embodiment, the flow of holes into the drift region 42 in the ON state is suppressed. Therefore, the reverse recovery current that occurs when the diode is turned OFF is suppressed. Consequently, the occurrence of losses due to reverse recovery current is suppressed. Also, since the reverse recovery current flowing at the boundary between the IGBT region 30 and the diode region 50 is suppressed, the potential of the body region stabilizes around the boundary. As a result, the operation of the semiconductor device 10 becomes stable.

[0032] When the potential of the upper electrode 22 becomes lower than the potential of the lower electrode 24, a depletion layer spreads from the pn junction at the interface between the lower body region 38 and the drift region 42 to the drift region 42 and the lower body region 38. Almost the entire drift region 42 is depleted. Also, as described above, the p-type impurity concentration in the lower body region 38 is lower than the p-type impurity concentration in the low-concentration region 34b of the upper body region 34. Therefore, almost the entire lower body region 38 is depleted. By depleting almost the entire lower body region 38 in this way, localized electric field concentration within the lower body region 38 is suppressed. Therefore, the semiconductor device 10 has a high breakdown voltage.

[0033] When the potential of the upper electrode 22 is lower than the potential of the lower electrode 24, the IGBT turns on as described below when the potential of the gate electrode 18 is raised to a potential above the gate threshold. Specifically, when the potential of the gate electrode 18 is raised to a potential above the gate threshold, channels are formed in the low-concentration region 34b and the lower body region 38 near the gate insulating film 16. The channel formed in the low-concentration region 34b connects the emitter region 32 and the barrier region 36, and the channel formed in the lower body region 38 connects the barrier region 36 and the drift region 42. Then, electrons flow from the emitter region 32 to the collector region 44 via the channel in the low-concentration region 34b, the barrier region 36, the channel in the lower body region 38, and the drift region 42. Also, holes flow from the collector region 44 to the upper body region 34 via the drift region 42, the lower body region 38, and the barrier region 36. In this way, the IGBT turns on.

[0034] Next, the leakage current generated when the IGBT is turned on will be explained by comparing the comparative example and the example. Figure 3 is an enlarged cross-sectional view of the area around the trench 14 of the semiconductor device of the comparative example. The semiconductor layer of the comparative example differs from the semiconductor device 10 of the example in that the thickness of the gate insulating film 16 is constant. Figure 4 shows the change in collector-emitter current Ic when the potential Vge of the gate electrode 18 is increased while a constant voltage (more specifically, a constant voltage that causes the lower electrode 24 to be at a high potential) is applied between the upper electrode 22 and the lower electrode 24 in the semiconductor device of the comparative example. Note that Figure 4 shows the experimental results for each case in which the Schottky barrier between the connection region 40 and the upper electrode 22 is different. As mentioned above, the lower body region 38 has a lower p-type impurity concentration than the upper body region 34. Also, in the comparative example, the thickness of the gate insulating film 16 is constant. For this reason, when the gate potential Vge is increased from 0V in the semiconductor device of the comparative example, a channel is formed in the lower body region 38 before the upper body region 34. In this state where a channel is formed in the lower body region 38, electrons flow from the upper electrode 22 to the drift region 42 through the channel in the connection region 40, barrier region 36, and lower body region 38, as shown by arrow 110 in Figure 3. That is, leakage current flows along the path shown by arrow 110. Therefore, as shown in Figure 4, current Ic begins to flow when the gate potential Vge is lower than the gate threshold Vth. Subsequently, when the gate potential Vge reaches the gate threshold Vth, a channel is formed in the upper body region 34, and current flows along the path shown by arrow 112 in Figure 3. As shown in Figure 4, in the region where the gate potential Vge exceeds the gate threshold Vth, current Ic increases with increasing gate potential Vge. As explained above, in the comparative example, leakage current flows in the IGBT in the region where the gate potential Vge is lower than the gate threshold Vth, so the graph of the rise characteristic of current Ic has a stepped shape, as shown in Figure 4. Note that the higher the Schottky barrier between the connection region 40 and the upper electrode 22, the smaller the leakage current. However, when increasing the Schottky barrier, the material options for the upper electrode 22 are limited.For example, when using tungsten, which has high embedding properties, as the upper electrode 22, a Ti-based barrier metal is provided at the interface between the upper electrode 22 and the semiconductor substrate 12. However, this configuration does not allow for a high Schottky barrier. Furthermore, even if the Schottky barrier is increased, a certain amount of leakage current will still occur.

[0035] Figure 5 shows the rise characteristics of the current Ic of an IGBT without a barrier region 36 and a connection region 40. Figure 5 shows the characteristics of a normal product and a defective product, respectively. The defective product is an IGBT in which crystal defects exist around the trench. When there is no barrier region 36 and a connection region 40, in a normal product, the current Ic begins to flow when the gate potential Vge reaches the gate threshold Vth. In the defective product, however, leakage current flows before the gate potential Vge reaches the gate threshold Vth, so the rise characteristic graph has a bump shape. The leakage current that occurs at this time is about the same as the leakage current that occurs when the Schottky barrier is 0.7 eV in Figure 4. For this reason, in the comparative example structure shown in Figure 3, if the Schottky barrier is 0.7 eV or less, even if a characteristic abnormality like that of the defective product in Figure 5 occurs due to crystal defects, the characteristic abnormality cannot be detected in the characteristic inspection.

[0036] Next, the current path of the semiconductor device of the embodiment will be described. As described above, in the embodiment, the lower portion 16b of the gate insulating film 16 is thicker than the upper portion 16a. Therefore, when the gate potential Vge is increased, the electric field applied to the lower body region 38 is smaller than the electric field applied to the low-concentration region 34b. Consequently, in the embodiment, when the gate potential Vge is increased from 0V, a channel is formed in the upper body region 34 before the lower body region 38. Even if a channel is formed in the upper body region 34 first, no leakage current occurs. Subsequently, when the gate potential Vge reaches the gate threshold Vth, a channel is formed in the lower body region 38. Since a channel has already been formed in the upper body region 34, electrons flow from the emitter region 32 to the drift region 42 through the channel in the low-concentration region 34b, the barrier region 36, and the channel in the lower body region 38, as shown by arrow 120 in Figure 2. In this way, the semiconductor device 10 of the embodiment can suppress leakage current flowing through the connection region 40 and the barrier region 36. Therefore, it is possible to prevent the graph of the rise characteristics of current Ic from having a stepped shape. In other words, similar to the normal product in Figure 5, the semiconductor device 10 of the embodiment can achieve the characteristic that current Ic starts flowing when the gate potential Vge reaches the gate threshold Vth. For this reason, even when the Schottky barrier is 0.7 eV or less, the abnormal product shown in Figure 5 can be detected by characteristic inspection.

[0037] As described above, according to the semiconductor device 10 of the embodiment, leakage current when the gate potential is increased can be suppressed in a switching element having a barrier region 36 and a connection region 40.

[0038] The gate insulating film 16, in which the lower portion 16b is thicker than the upper portion 16a, can be formed, for example, by the method shown in Figure 6. First, as shown in Figure 6(a), a trench 14 is formed on the upper surface 12a by etching through a mask 90. ​​Next, as shown in Figure 6(b), a protective film 92 made of SiN is formed to cover the inner surface of the trench 14. Next, as shown in Figure 6(c), the protective film 92 covering the bottom surface of the trench 14 is removed by etching. Here, the protective film 92 is left on the side surface of the trench 14. Next, as shown in Figure 6(d), the trench 14 is deepened by etching the bottom surface of the exposed trench 14. Next, as shown in Figure 6(e), the gate insulating film 16 is formed on the lower part of the trench 14 (i.e., the part below the protective film 92) by thermal oxidation. Next, as shown in Figure 6(f), the protective film 92 is removed. Next, as shown in Figure 6(g), the gate insulating film 16 is formed on the entire inner surface of the trench 14 by thermal oxidation. In the lower part of the trench 14, the thickness of the gate insulating film 16 increases. Therefore, the lower portion 16b becomes thicker than the upper portion 16a.

[0039] In the above-described embodiment, the thickness of the gate insulating film 16 changed in a stepped manner. However, in the manufacturing process, as shown in Figure 7, a thickness-changing portion 16c may be formed in which the thickness gradually increases from the upper portion 16a to the lower portion 16b. If the thickness-changing portion 16c is in contact with the low-concentration region 34b or the lower body region 38, it becomes a factor in the variation of the gate threshold Vth during mass production of the semiconductor device 10. As shown in Figure 7, if the thickness-changing portion 16c is located within the range in contact with the barrier region 36, the thickness-changing portion 16c is not in contact with either the low-concentration region 34b or the lower body region 38, so the variation in the gate threshold Vth can be suppressed.

[0040] Furthermore, the embodiments described above described a semiconductor device 10 having an IGBT and a diode. However, as shown in Figure 8, the technology disclosed herein may also be applied to a MOSFET. The structure of the MOSFET shown in Figure 8 is the same as the structure of the IGBT region 30 shown in Figure 1, but with the p-type collector region 44 replaced by an n-type drain region 144. The MOSFET in Figure 8 may or may not have a diode region 50. Inside the MOSFET in Figure 8, a parasitic PIN diode (a so-called body diode) is formed by the upper body region 34, the lower body region 38, the drift region 42, and the drain region 144. In the MOSFET in Figure 8, the reverse recovery current of the body diode is suppressed by the barrier region 36 and the connection region 40. Also, in the MOSFET in Figure 8, since the lower portion 16b is thicker than the upper portion 16a, leakage current flowing through the barrier region 36 and the connection region 40 when the gate potential is increased is suppressed.

[0041] Furthermore, in the embodiment described above, the p-type impurity concentration in the lower body region 38 was lower than the p-type impurity concentration in the low-concentration region 34b. However, the p-type impurity concentration in the lower body region 38 may be the same as or higher than the p-type impurity concentration in the low-concentration region 34b. Even with such a configuration, channels may form in the low-concentration region 34b before the lower body region 38, causing leakage current to flow. In such cases, if the lower portion 16b is made thicker than the upper portion 16a, channels will be less likely to form in the lower body region 38 relative to the low-concentration region 34b, thereby suppressing the generation of leakage current.

[0042] Furthermore, in the above-described embodiment, the trenches 14 extended parallel to each other on the upper surface 12a, but the trenches 14 may be arranged in any manner on the upper surface 12a. For example, the trenches 14 may extend in a grid pattern on the upper surface 12a.

[0043] Furthermore, in the embodiment described above, the barrier region 36 was electrically connected to the upper electrode 22 by an n-type connection region 40. However, as shown in Figure 9, instead of the connection region 40, a connecting member 40a made of metal may be provided. The connecting member 40a electrically connects the barrier region 36 to the upper electrode 22. The connecting member 40a is in Schottky contact with the barrier region 36.

[0044] Furthermore, the upper portion 16a and the lower portion 16b may be made of different materials. For example, the upper portion 16a may be made of one selected from a group with a dielectric constant lower than SiO2, such as SiOC or SiOF, and the lower portion 16b may be made of another selected from the above group.

[0045] The components of the technology disclosed herein are listed below. (Composition 1) A semiconductor device, A semiconductor substrate with a trench on its upper surface, A gate insulating film covering the inner surface of the trench, A gate electrode, disposed within the trench and insulated from the semiconductor substrate by the gate insulating film, The upper electrode in contact with the upper surface of the semiconductor substrate, A lower electrode in contact with the lower surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate A first n-type region is in contact with the upper electrode and is in contact with the gate insulating film on the side surface of the trench, The upper body region of type p, which is in contact with the gate insulating film on the lower side surface of the first n-type region, An n-type barrier region in contact with the gate insulating film on the lower side surface of the upper body region, A p-shaped lower body region is in contact with the gate insulating film on the lower side surface of the barrier region and is separated from the upper body region by the barrier region, A connection portion that electrically connects the barrier region and the upper electrode, An n-type drift region in contact with the gate insulating film on the lower side surface of the lower body region, A second n-type region having a higher n-type impurity concentration than the aforementioned drift region, located below the aforementioned drift region, and in contact with the lower electrode, It has, The lower portion of the gate insulating film, which is the part that is in contact with the lower body region, is thicker than the upper portion of the gate insulating film, which is the part that is in contact with the upper body region. Semiconductor equipment. (Configuration 2) The gate insulating film has a thickness-changing portion in which the thickness increases from the upper portion toward the lower portion. The thickness-changing portion is located within the range in contact with the barrier region. The semiconductor device described in Configuration 1. (Composition 3) The semiconductor device according to configuration 1 or 2, wherein the p-type impurity concentration in the lower body region is lower than the p-type impurity concentration in the upper body region. (Composition 4) The semiconductor device according to any one of configurations 1 to 3, wherein the semiconductor substrate is located below the drift region and has a p-type collector region in contact with the lower electrode. (Composition 5) The semiconductor device according to any one of configurations 1 to 4, wherein the connecting portion is made of an n-type semiconductor and is in Schottky contact with the upper electrode. (Composition 6) The semiconductor device according to configuration 5, wherein the Schottky barrier between the connection portion and the upper electrode is 0.7 eV or less. (Composition 7) A semiconductor device according to any one of configurations 1 to 6, wherein the upper portion is made of a different material from the lower portion.

[0046] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of Symbols]

[0047] 12: Semiconductor substrate, 14: Trench, 16: Gate insulating film, 16a: Upper portion, 16b: Lower portion, 18: Gate electrode, 34: Upper body region, 36: Barrier region, 38: Lower body region, 40: Connection region

Claims

1. A semiconductor device, A semiconductor substrate (12) having a trench (14) on its upper surface, A gate insulating film (16) covering the inner surface of the trench, A gate electrode (18) is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film, The upper electrode (22) in contact with the upper surface of the semiconductor substrate, A lower electrode (24) in contact with the lower surface of the semiconductor substrate, It has, The aforementioned semiconductor substrate A first n-type region (32) is in contact with the upper electrode and is in contact with the gate insulating film on the side surface of the trench, The lower side surface of the first n-type region is a p-type upper body region (34) that is in contact with the gate insulating film, An n-type barrier region (36) in contact with the gate insulating film on the lower side surface of the upper body region, A p-shaped lower body region (38) is in contact with the gate insulating film on the lower side surface of the barrier region and is separated from the upper body region by the barrier region, A connection portion (40) that electrically connects the barrier region and the upper electrode, An n-type drift region (42) in contact with the gate insulating film on the lower side surface of the lower body region, A second n-type region (46, 144) having a higher n-type impurity concentration than the drift region, positioned below the drift region, and in contact with the lower electrode, It has, The lower portion (16b) of the gate insulating film, which is the part that is in contact with the lower body region, is thicker than the upper portion (16a) of the gate insulating film, which is the part that is in contact with the upper body region. Semiconductor equipment.

2. The gate insulating film has a thickness-changing portion (16c) in which the thickness increases from the upper portion toward the lower portion. The thickness-changing portion is located within the range in contact with the barrier region. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1 or 2, wherein the p-type impurity concentration in the lower body region is lower than the p-type impurity concentration in the upper body region.

4. The semiconductor device according to claim 1 or 2, wherein the semiconductor substrate is disposed below the drift region and has a p-type collector region (44) in contact with the lower electrode.

5. The semiconductor device according to claim 1 or 2, wherein the connecting portion is made of an n-type semiconductor and is in Schottky contact with the upper electrode.

6. The semiconductor device according to claim 5, wherein the Schottky barrier between the connection portion and the upper electrode is 0.7 eV or less.

7. The semiconductor device according to claim 1 or 2, wherein the upper portion is made of a different material from the lower portion.

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