Communication control device, wireless access system, communication control method and program

Abstract

Provided is a communication control device (100) that processes a wireless access signal, the communication control device (100) comprising: a communication quality information acquisition unit (101) that acquires communication quality information; a processing time estimation unit (113) that calculates an estimated processing time for each CPU frequency from the acquired communication quality information; and a frequency control unit (114) that lowers the CPU frequency below the currently set CPU frequency when the estimated processing time is equal to or less than the processing time of the time slot. The communication quality information acquisition unit (101) includes an MCS acquisition unit (111), a radio wave condition acquisition unit (112), a MAC schedule analysis unit (115), and a delay time acquisition unit (116).

Description

Technical Field

[0001] The present invention relates to a communication control device, a radio access system, a communication control method, and a program.

Background Art

[0002] In a RAN (Radio Access Network), low-latency communication is achieved by sequentially performing data transfer for each specific time interval (time slot). In the RAN, conventionally, communication from a user terminal (UE) to a core network has been mainly realized using dedicated devices. In a vRAN (virtual Radio Access Network) that realizes a base station of a RAN with software and a general-purpose server, in order to execute a highly loaded process, tuning such as utilizing an accelerator or maximizing the CPU frequency is performed to clear a strict time constraint on the order of microseconds.

[0003] <vran> Let me explain vRAN. In mobile communication radio access systems, high latency requirements and throughput are demanded, so it has been common practice for base stations (BBUs) that perform radio signal processing to be handled by dedicated hardware (dedicated equipment). In recent years, with the widespread adoption of general-purpose servers (IA: Intel Architecture servers (Intel: trademark)), the performance of these servers has dramatically improved, and mass production has made them available at low cost. As a result, there is growing interest in using general-purpose servers for processing radio signals in BBUs (Bandbuster Units) in LTE (Long Term Evolution) and 5G wireless access systems, specifically vRAN (Virtual Random Range) solutions.

[0004] In vRAN, inexpensive and readily available general-purpose servers can be used as BBU hardware. Therefore, a BBU pool can be constructed by using regional data centers (DCs) or communication buildings within a radius of several tens of kilometers from an antenna as aggregation points, and setting up server racks and installing multiple general-purpose servers in advance (this concept is sometimes referred to as C-RAN (Centralized-RAN)).

[0005] A BBU pool has the potential advantage of enabling flexible operation, such as rapid hardware replacement (switchover) in the event of hardware failure, and dynamic scale-out / (in the following explanation, " / " means "or") in response to increases or decreases in traffic, because it allows for the preparation of multiple base station hardware (general-purpose servers) in advance.

[0006] In wireless access systems, it is sometimes possible to separate base station functions into RU (Radio Unit), DU (Distributed Unit), and CU (Centralized Unit).

[0007] This section describes the functions of RU / DU / CU. The functions of the RU include PHY-low, AD / DA conversion, iFFT, analog beamforming, and digital beamforming. The functions of the DU include PHY-high, modulation / demodulation, coding / decoding, scrambling, and MAC, and these processes are performed by the DU server. The functions of the CU include the execution of the Packet Data Convergence Protocol, Radio Resource Control, and Service Data Adaptation Protocol.

[0008] In EPC / 5GC mobile communications, the functions of the BBU are placed in the DU and CU, and the functions of the RRH (Remote Radio Head) that handles radio frequency (RF) are placed in the RU. Most general base stations are installed as slave stations that only have an RU as equipment, while base stations equipped with a DU and CU are called master stations and are connected to slave stations by a network called a fronthaul. Furthermore, BBU pools can also be pooled at a smaller unit than the RU, DU, or CU isolation units, such as CPU cores, accelerators, and NICs (Network Interface Cards) in a server.

[0009] This document outlines the vRAN system. Figure 46 is a diagram illustrating the overview of the vRAN system. As shown in Figure 46, the vRAN system (wireless access system) 1 comprises a terminal (UE: User Equipment) 10, an RU 20 with an antenna (base station antenna), a DU server 30, a CU server 40, and a core network 50.

[0010] In a wireless access system, the transmission timing of wireless signals between terminals and base stations is managed by the MAC (Medium Access Control) Scheduler at the base station as a resource multiplexed in the time domain and frequency domain. The DU server 30 manages this by allocating a RE (Resource Element) to each UE10.

[0011] UE10 is a wireless device such as a mobile phone terminal, and connects to RU20 via the wireless section. UE10 converts the data to be transmitted into a radio signal and sends it to RU20. UE10 processes the radio signal received from RU20 and restores it to the data intended by the sender. There are two types of communication between UE10 and RU20: uplink (UE10 ⇒ RU20 ⇒ DU Server 30) (hereinafter referred to as UL as appropriate) and downlink (DU Server 30 ⇒ RU20 ⇒ UE10) (hereinafter referred to as DL as appropriate).

[0012] RU20 is an antenna and transceiver unit that communicates wirelessly with UE10 (hereinafter, "antenna" refers collectively to the antenna, transceiver unit, and its power supply unit). The transmitted and received data is connected to the DU server 30, for example, by a dedicated cable. RU20 acts as a base station for UE10, transmitting and receiving wireless signals to and from UE10. RU20 processes a portion of the wireless signal received from UE10 and then transmits it to DU server 30. RU20 performs the following transmission and reception with UE10. Downlink: Transmits a wireless signal to UE10. Downlink: Signal data is received from the DU server 30 via the fronthaul interface unit (not shown). Uplink: Receives wireless signals from UE10. Uplink: Signal data is transmitted to the DU server 30 via the fronthaul interface unit (not shown).

[0013] The DU server 30 performs wireless signal processing in LTE and 5G (five generation) wireless access systems using a general-purpose server. In vRAN, a general-purpose server that is inexpensive and readily available in large quantities can be used as the DU server 30. The DU server 30 comprises hardware (HW) 31, an OS 32, and a vDU (virtualized Distributed Unit) 33 that runs a base station processing application (APL). The hardware (HW) 31 includes a CPU (Central Processing Unit) 31a, an accelerator 31b consisting of FPGA (Field-Programmable Gate Array) / ASIC (Application Specific Integrated Circuit) / GPU (Graphics Processing Unit), etc., and a NIC (Network Interface Card) 31c.

[0014] Accelerator 31b is accelerator hardware installed in the DU server 30 that is specialized for specific calculations and performs calculations based on instructions from the accelerator offload unit (not shown). The CPU 31a offloads, for example, FEC (Forward Error Correction) processing to accelerator 31b via the accelerator offload unit.

[0015] NIC31c is an input / output mechanism that performs data input and output with accelerator 31b and external devices (RU20).

[0016] The CU server 40 comprises a general-purpose server 41 and a vCU (virtualized Centralized Unit) 42.

[0017] The core network 50 includes EPC (Evolved Packet Core) / 5GC (5G Core Network), etc.

[0018] Figure 47 shows the correspondence between the communication layers of UE10 and RAN (RU20, vDU33, vCU42) in the vRAN system (wireless access system) 1 shown in Figure 46. The PHY (Physical layer) of UE10 is connected to the PHY-low communication layer of RU20.

[0019] The MAC (Media Access Control) of UE10 is connected to the MAC communication layer of vDU33 in DU server 30, and the RLC (Radio Link Control) of UE10 is connected to the RLC communication layer of vDU33 in DU server 30. Note that vDU33 in DU server 30 performs PHY-high processing.

[0020] The PDCP (Packet Data Convergence Protocol) of UE10 is connected to the PDCP communication layer of vCU42, and the SDAP (Service Data Adaptation Protocol) of UE10 is connected to the SDAP communication layer of vCU42.

[0021] The PHY processing is described in Non-Patent Document 1. FIG. 48 is a diagram showing the processing for each time slot of downlink data processing (DL) for transmitting data from vDU33 of DU server 30 to UE10 via RU20 and uplink data processing (UL) for transmitting data from UE10 to vDU33 of DU server 30 via RU20. In the RAN, low-latency communication is realized by sequentially performing data transfer for each specific time interval (time slot). The PHY-high processing of vDU33 in DU server 30 must be processed within a time slot of several 100 us (see arrow a in FIG. 48).

[0022] In the case of TDD (Time Division Duplex), the radio intervals are scheduled so that UL and DL do not overlap (see reference numeral b in FIG. 48).

[0023] FIG. 49 is a diagram showing the breakdown of the PHY-high processing in the UL time slot of vDU33 of DU server 30 in FIG. 48 The time slot shown in FIG. 49 is, for example, several 100 us, and among them, the PHY-high process (UL) occupies a large proportion. The PHY-high process (UL) consists of processes such as demapping 51, demodulation 52, decoding (FEC decoding) 53, and CRC (Cyclic Redundancy Check) check.

[0024] Since the decoding (FEC decoding) process included in the PHY-high process (UL) involves parallel processing that the CPU 31a is not good at, offloading to the accelerator 31b is performed, but it still takes several 100 us, so it has become a bottleneck in achieving in-slot processing.

[0025] FIG. 50 is a diagram for explaining the image (Look-Aside type) of offloading of the PHY-high process (UL) in FIG. 49. The accelerator 31b shown in FIG. 50 is an arithmetic unit specialized for specific processing, mounted on the DU server 30. As a form of connecting the accelerator 31b to the CPU 31a via a bus, there are forms such as an ASIC-mounted accelerator, an FPGA-mounted accelerator, and a GPU.

[0026] The arrow from the CPU 31a to the accelerator 31b in FIG. 50 and then back from the accelerator 31b to the CPU 31a (arrow c in FIG. 50) is the signal path in the case of Look-Aside type ACC offloading. In the Look-Aside type, the data to be processed by the accelerator 31b is input from the CPU 31a. Although not shown in the figure, there is also an In-Line type in which data is directly input from an input / output unit such as the NIC 31c to the accelerator 31b. In the case of In-Line type ACC offloading, it becomes a bidirectional signal line connecting the NIC 31c and the accelerator 31b.

Prior Art Documents

Non-Patent Documents

[0027]

Non-Patent Document 1

[0028] In conventional technology, in order to complete all processing within a time slot under various conditions during uplink PHY-high processing (UL), it was necessary to keep the CPU cores and accelerators set to their highest performance settings at all times. The following describes the challenges related to CPU core frequency control (simply referred to as CPU frequency when not focusing on CPU cores) and PHY-high processing.

[0029] Figure 51 is a diagram illustrating the control of the CPU core frequency. The DU server 30 shown in Figure 46 includes hardware 60, driver 70, and governor 80. Hardware 60 shown in Figure 51 corresponds to HW31 in Figure 46. Furthermore, driver 70 and governor 80 shown in Figure 51 are included in OS 32 in Figure 46. Hardware 60 has a CPU Core 61. Driver 70 has Intel P-state 71 ("Intel" is a registered trademark) and ACPI cpufreq 72. Governor 80 has Intel P-statecpufreq 81 ("Intel" is a registered trademark) and core cpufreq 82.

[0030] There are two ways to control the CPU core frequency (CPU frequency). Governor 80 uses Intel P-statecpufreq 81 to determine the CPU core frequency fluctuation range and fluctuation policy, and instructs Intel P-state 71 on driver 70. Intel P-state 71 controls the frequency of CPU Core 61. Similarly, Governor 80 uses core cpufreq 82 to determine the CPU core frequency fluctuation range and fluctuation policy, and instructs ACPI cpufreq 72 on driver 70. ACPI cpufreq 72 controls the frequency of CPU Core 61. For example, governor80 can run CPU Core61 at its maximum frequency by setting cpufreq_performance. It can also dynamically vary CPU Core61's frequency by setting cpufreq_ondemand. Furthermore, governor80 can run CPU Core61 at its minimum frequency by setting cpufreq_powersave.

[0031] Figure 52 illustrates the PHY-high processing pattern (UL). The upper part of Figure 52 shows time slots where decoding takes a long time, the middle part shows time slots where decoding does not take a long time, and the lower part shows time slots without PHY-high processing (UL). As can be seen by comparing the time slots in the upper and middle sections of Figure 52, in PHY-high processing (UL), in order to complete all processing within a time slot, it was necessary to keep CPU Core61 set to maximum performance at all times. To keep CPU Core61 set to maximum performance at all times, governor80 sets cpufreq_performance using intel P-statecpufreq81 or corecpufreq82.

[0032] Thus, when configuring a vRAN system, high-speed processing is required, and the CPU frequency is expected to operate at its maximum. Because the CPU Core61 operates at its maximum frequency, there is a problem of increased power consumption regardless of whether there is a remaining time buffer (see the middle section of Figure 52) or a time slot without PHY-high processing (UL) (see the lower section of Figure 52).

[0033] In particular, when the uplink PHY-high processing is executed on the CPU, it was necessary to keep the CPU cores and accelerators at their highest performance settings at all times in order to complete all processing within the time slot under various conditions. In this case, the CPU cores and other components operate at their maximum frequency, which leads to increased power consumption, a problem.

[0034] In light of this background, the present invention was made, and its objective is to reduce the power consumption of the CPU and accelerator while meeting the demands for high-speed processing, such as when configuring a vRAN system. [Means for solving the problem]

[0035] To solve the aforementioned problems, a communication control device is provided that is located at a base station that processes wireless access signals, and comprises: a communication quality information acquisition unit that acquires communication quality information; a processing time estimation unit that calculates an estimated processing time for each CPU frequency from the acquired communication quality information; and a frequency control unit that lowers the CPU frequency below the currently set CPU frequency when the estimated processing time is less than or equal to the processing time of the time slot. [Effects of the Invention]

[0036] According to the present invention, when configuring a vRAN system, it is possible to reduce the power consumption of the CPU and accelerator while meeting the demands for high-speed processing. [Brief explanation of the drawing]

[0037] [Figure 1] This is a schematic diagram of a wireless access system according to the first embodiment of the present invention. [Figure 2] This figure shows the UBLER of the Uplink where the CRC check fails for a combination of the SNR of the wireless access system according to the first embodiment of the present invention and the current MCS Index. [Figure 3] This figure shows combinations for selecting the MCS Index from the SNR and UBLER of a wireless access system according to the first embodiment of the present invention. [Figure 4] This flowchart outlines the learning of PHY-high processing time using the MCS Index for a wireless access system according to the first embodiment of the present invention. [Figure 5] This figure shows a learning table of PHY-high processing time for each MCS setting in a wireless access system according to the first embodiment of the present invention. [Figure 6] This flowchart shows the CPU frequency setting process, which involves estimating the PHY-high processing time based on the MCS Index and SINR and lowering the CPU frequency performance setting during operation of a wireless access system according to the first embodiment of the present invention. [Figure 7] This is an explanatory diagram illustrating the operation of point 1 of a wireless access system according to the first embodiment of the present invention. [Figure 8] This figure illustrates the derivation of a configurable CPU frequency based on the estimation of the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 9] This is an explanatory diagram illustrating the operation of point 1 of a wireless access system according to the first embodiment of the present invention. [Figure 10] This figure illustrates the derivation of a configurable CPU frequency based on the estimation of the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 11] This is an explanatory diagram illustrating the operation of point 2 of the wireless access system according to the first embodiment of the present invention. [Figure 12] This diagram shows the processing for each time slot of downlink data processing (DL), which transmits data from the vDU of the DU server to the RU, and uplink data processing (UL), which transmits data from the RU to the vDU of the DU server, in a wireless access system according to the first embodiment of the present invention. [Figure 13] This figure illustrates the derivation of a configurable CPU frequency based on the estimation of the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 14] This figure illustrates the derivation of a configurable CPU frequency based on the estimation of the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 15] This is an explanatory diagram of the operation of point 3 of the wireless access system according to the first embodiment of the present invention. [Figure 16] This figure shows the time slots for PHY-high processing (UL) in the case of MCS:3 of the wireless access system according to the first embodiment of the present invention. [Figure 17] This figure illustrates an example of rewriting the table values ​​of a learning table based on the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 18] This is an example of a mixed database table used in the bidirectional processing time of a wireless access system according to the first embodiment of the present invention. [Figure 19] This is an example of a ULDB table used in the UL-only processing time of a wireless access system according to the first embodiment of the present invention. [Figure 20] This is an example of a DLDB table for a wireless access system according to the first embodiment of the present invention. [Figure 21] This is a CPU frequency setting history table for a wireless access system according to the first embodiment of the present invention. [Figure 22] This is a control target table for a wireless access system according to the first embodiment of the present invention. [Figure 23] This figure shows the time slot handling on the time axis for downlink data processing (DL), which transmits data from the vDU of the DU server to the RU, and uplink data processing (UL), which transmits data from the RU to the vDU of the DU server, in a wireless access system according to the first embodiment of the present invention. [Figure 24] This is an example of a MAC-PHY conversion table for a wireless access system according to the first embodiment of the present invention. [Figure 25] This is an example of a DU server configuration when the UL / DL task of the wireless access system according to the first embodiment of the present invention is performed on all CPU cores of the controlled system. [Figure 26] This is an example of a DU server configuration when the CPU cores installed on each UL / DL of the wireless access system according to the first embodiment of the present invention are separate. [Figure 27] This figure shows the time slots for PHY-high processing (DL) in the case of MCS:3 of the wireless access system according to the first embodiment of the present invention. [Figure 28] This figure illustrates an example of rewriting the table values ​​of a learning table based on the PHY-high processing time of a wireless access system according to the first embodiment of the present invention. [Figure 29] This is a flowchart of the processing time estimation process of the processing time estimation unit of the wireless access system according to the first embodiment of the present invention. [Figure 30] This is a subroutine for estimating processing time when the UL / DL task of a wireless access system according to the first embodiment of the present invention is performed on all CPU cores under control. [Figure 31] This is a subroutine for estimating processing time when the CPU cores installed on each UL / DL of a wireless access system according to the first embodiment of the present invention are separate. [Figure 32] This is a subroutine for feedback processing controlled by the delay time acquisition unit of a wireless access system according to the first embodiment of the present invention. [Figure 33] This is a subroutine for feedback processing executed by the processing time estimation unit of the wireless access system according to the first embodiment of the present invention. [Figure 34] This is an illustrative diagram illustrating the horizontal expansion of the DLDB table of a wireless access system according to the first embodiment of the present invention, including elements other than the MCS Index and CPU frequency. [Figure 35] This is a flowchart of CPU frequency control when the UL / DL task of the wireless access system according to the first embodiment of the present invention is performed on all CPU cores under control. [Figure 36] This is a flowchart of CPU frequency control when the CPU cores installed in each UL / DL of the wireless access system according to the first embodiment of the present invention are separate. [Figure 37] This is a schematic diagram of a wireless access system according to a second embodiment of the present invention. [Figure 38] This is a flowchart of accelerator frequency control by the frequency control unit of a wireless access system according to a second embodiment of the present invention. [Figure 39] This is a schematic diagram of a wireless access system according to a third embodiment of the present invention. [Figure 40] This figure shows the uncore setting table read by the frequency control unit of the wireless access system according to the third embodiment of the present invention. [Figure 41] This figure shows the configuration of a CPU socket having a CPU core and an uncore in a wireless access system according to a third embodiment of the present invention. [Figure 42] This figure shows the delay performance (µs) of the uncore frequency of a wireless access system according to a third embodiment of the present invention. [Figure 43] This is a flowchart of uncore frequency control when the UL / DL task of a wireless access system according to a third embodiment of the present invention is performed on all CPU cores under control. [Figure 44] This is a flowchart of uncore frequency control when the CPU cores installed on each UL / DL of the wireless access system according to the third embodiment of the present invention are separate. [Figure 45] This is a hardware configuration diagram showing an example of a computer that implements the functions of a communication control device for a wireless access system according to an embodiment of the present invention. [Figure 46] This diagram illustrates the overview of the vRAN system. [Figure 47] Figure 46 shows the correspondence between the communication layers of the UE and RAN in the vRAN system. [Figure 48] This diagram shows the processing for each time slot: downstream data processing (DL), which sends data from the DU server's vDU to the UE via the RU, and upstream data processing (UL), which sends data from the UE to the DU server's vDU via the RU. [Figure 49] This figure shows the breakdown of PHY-high processing in the UL time slot of the vDU on the DU server shown in Figure 48. [Figure 50] Figure 49 illustrates the off-road image (Look-Aside type) of the PHY-high processing (UL). [Figure 51] This diagram illustrates the control of CPU core frequency. [Figure 52] This diagram illustrates the PHY-high processing pattern (UL). [Modes for carrying out the invention]

[0038] Hereinafter, a radio access system and the like in a mode for implementing the present invention (hereinafter referred to as "this embodiment") will be described with reference to the drawings. (First Embodiment) [Overview] FIG. 1 is a schematic configuration diagram of a radio access system according to a first embodiment of the present invention. This embodiment is applicable to a radio access system for EPC / 5GC mobile communication. The same components as those in FIG. 46 are denoted by the same reference numerals. This embodiment is an example in which a communication control device that processes radio access signals is applied to a device arranged in a base station that processes radio access signals. In particular, when the present invention is applied in a vRAN environment, the communication quality information can be read as radio quality information. As shown in FIG. 1, the radio access system 1000 includes an RU 20 and a communication control device 100. The communication control device 100 is a radio access device mounted on the DU server 30 in FIG. 46. The communication control device 100 includes a control unit 110, a signal processing unit 120, hardware (HW) 130, and an OS / driver 140.

[0039] [Control Unit 110] The control unit 110 includes an MCS (Modulation and Coding Scheme) acquisition unit 111, a radio wave state acquisition unit 112, a processing time estimation unit 113, a frequency control unit 114, a MAC (Media Access Control) schedule analysis unit 115, and a delay time acquisition unit 116. The above MCS acquisition unit 111, radio wave state acquisition unit 112, MAC schedule analysis unit 115, and delay time acquisition unit 116 correspond to a communication quality information acquisition unit 101 that acquires communication quality information.

[0040] <MCS Acquisition Unit 111> The MCS acquisition unit 111 acquires the MCS Index from the MAC unit 122 of the signal processing unit 120. Specifically, the MCS acquisition unit 111 acquires the MCS Index for UL or DL ​​in a specific MAC time slot from the MAC unit 122 and provides it to the processing time estimation unit 113.

[0041] MCS is an index (called MCSIndex) that uses the spatial stream, modulation scheme, and coding rate as parameters (Non-Patent Document 2). IEEE 802.11n defines 77 levels of MCSIndex.

[0042] <Radio wave condition acquisition unit 112> The radio wave condition acquisition unit 112 acquires UL radio wave quality information (SINR, RSRQ, etc.) from RU20 and provides it to the processing time estimation unit 113. Furthermore, the radio wave condition acquisition unit 112 acquires DL radio wave quality information (SINR, RSRQ, CQI, etc.) from the MAC unit 122 and provides it to the processing time estimation unit 113. Furthermore, the radio wave quality information measured using the CSI reference signal is reported to the MAC unit 122 as a CSI report.

[0043] <Basic functions of the processing time estimation unit 113> The processing time estimation unit 113 calculates the estimated processing time for each CPU frequency from the acquired communication quality information. Specifically, the processing time estimation unit 113 estimates the processing time for each PHY time slot according to the situation of UL / DL bidirectional, UL only, DL only, and neither direction, based on the PHY schedule information. This improves accuracy in both directions by taking DL processing into account, and further reduces power consumption in PHY time slots that do not require attention. The processing time estimation unit 113 modifies the estimation method based on the PHY-high processing time. Additionally, the delay time acquisition unit 116 obtains whether a retransmission request is present from the MAC unit 122 and provides this information to the processing time estimation unit 113. This feedback, which takes server operating status into account, improves the accuracy of CPU control.

[0044] <Processing time estimation by the processing time estimation unit 113 in a specific PHY time slot> The processing time estimation unit 113 acquires MACPHY schedule conversion information. The processing time estimation unit 113 also acquires UL or DL ​​radio wave quality information from the radio wave condition acquisition unit 112. The processing time estimation unit 113 obtains the MCS Index of UL or DL ​​in a specific MAC time slot from the MCS acquisition unit 111 and converts it to the MCS Index of UL or DL ​​in a PHY time slot based on MACPHY schedule conversion information.

[0045] The processing time estimation unit 113 obtains PHY schedule information from the MAC schedule analysis unit 115. Based on the MCS Index of UL or DL ​​in the PHY time slot and the PHY schedule information, it estimates the processing time for each CPU frequency using a specific logic.

[0046] The processing time estimation unit 113 may use UL or DL ​​radio wave quality information for estimation if the MCS Index is unavailable or to improve accuracy. The processing time estimation unit 113 provides the frequency control unit 114 with the MCS Index and the lowest frequency in the PHY time slot.

[0047] <Feedback on the processing time estimation by the processing time estimation unit 113 (Part 1)> The processing time estimation unit 113 can also provide feedback to the PHY-high processing time estimation based on timestamp information and whether or not a retransmission request was made, obtained by the PHY. Specifically, the processing time estimation unit 113 obtains the processing time for each UL PHY-high process and whether or not a UL retransmission request was made from the delay time acquisition unit 116. The processing time estimation unit 113 modifies the processing time estimation logic based on the processing time for each UL PHY-high process. To improve accuracy, information on whether or not a UL retransmission request was made may also be used to modify the logic.

[0048] <Feedback on the processing time estimation by the processing time estimation unit 113 (Part 2)> The processing time estimation unit 113 has a learning table that associates the PHY-high processing time and the CPU frequency for each MCS Index or radio wave quality information. The processing time estimation unit 113 refers to the learning table and determines the lowest frequency among the CPU frequencies in the learning table when the estimated processing time is less than or equal to the processing time of the time slot.

[0049] <Frequency control unit 114> When the estimated processing time is less than or equal to the processing time of the time slot, the frequency control unit 114 reduces the CPU frequency below the currently set CPU frequency. Specifically, the frequency control unit 114 refers to a pre-learned learning table (such as FIGS. 5, 6, 8, etc.) and reduces the CPU frequency to, for example, the CPU frequency read from the PHY-high processing time indicated by the MCS Index. At this time, the set CPU frequency is the CPU frequency (lowest frequency) that allows the processing to complete just within the time slot. Also, the frequency control unit 114 determines the CPU frequency in the corresponding PHY time slot while taking into account a safety factor based on the MCS Index and the frequency (for example, the lowest frequency) presented by the processing time estimation unit 113. The frequency control unit 114 operates the frequency control driver 141 based on the determined CPU frequency to change the CPU frequency.

[0050] <MAC schedule analysis unit 115> The MAC schedule analysis unit 115 acquires wireless resource allocation information (MAC schedule information) from the MAC unit 122 of the signal processing unit 120 and converts it into resource allocation information (PHY schedule information) at PHY-high. The MAC schedule analysis unit 115 provides the PHY schedule information to the processing time estimation unit 113. The MAC schedule analysis unit 115 creates a PHY-MAC conversion table in consideration of the delay between the PHY and the wireless section.

[0051] <Delay time acquisition unit 116> The delay time acquisition unit 116 acquires the actual PHY-high processing time from the PHY unit 121 and provides it to the processing time estimation unit 113. The delay time acquisition unit 116 acquires timestamps for each point in the UL PHY-high processing from the PHY unit 121 of the signal processing unit 120. The delay time acquisition unit 116 calculates the delay time for each process and provides it to the processing time estimation unit 113. The delay time acquisition unit 116 acquires whether or not a UL retransmission request is made from the MAC unit 122 of the signal processing unit 120 and provides it to the processing time estimation unit 113.

[0052] [Signal processing unit 120] The signal processing unit 120 is the vDU33 of the DU server 30 in Figure 46. The signal processing unit 120 comprises a PHY unit 121, a MAC unit 122, and an RLC (Radio Link Control) unit 123, and each unit is implemented by vDU, i.e., software (APL).

[0053] The PHY unit 121 performs processing such as modulation scheme, encoding scheme, and antenna multiplexing in Layer 1.

[0054] The MAC unit 122 performs tasks such as wireless resource allocation, data mapping, and retransmission control at Layer 2.

[0055] The RLC unit 123 performs retransmission control, duplicate detection, and sequence sorting in layer 2.

[0056] [HW130] The HW130 features a CPU core 131, an accelerator 132, memory 133, and a NIC 134. CPU core 131 corresponds to CPU 31a of HW31 in Figure 46, accelerator 132 corresponds to accelerator 31b of HW31 in Figure 46, and NIC 134 corresponds to NIC 31c of HW31 in Figure 46.

[0057] [OS / Driver 140] The OS / driver 140 corresponds to OS32 in Figure 46 and further includes a frequency control driver 141. The frequency control driver 141 corresponds to driver70 in Figure 51.

[0058] [Relationship between MCS, SNR, and BLER] This section explains the relationship between MCS (Multiple Controls), SNR (Signal-to-Noise Ratio), and BLER (Block Error Rate). In this embodiment, the MCS acquisition unit 111 acquires the MCS Index from the MAC unit 122 of the signal processing unit 120 and provides it to the processing time estimation unit 113. In addition, if the MCS Index is unavailable or for improved accuracy, the radio wave condition acquisition unit 112 acquires UL radio wave quality information (SINR, RSRQ, etc.) from the RU20 and provides it to the processing time estimation unit 113 as an alternative to the MCS Index.

[0059] Figure 2 shows the Uplink UBLER (Uplink BLER AS a function of SNR) for a given combination of SNR and current MCS Index that results in a CRC check error. As shown in Figure 2, the UBLER at which the CRC check fails varies depending on the combination of SNR and the current MCS Index. Using UBLER=1 as the baseline in Figure 2, we select an MCS index that satisfies UBLER<0.1. When the SNR is low, the UBLER will be high, so it is necessary to lower the MCS so that the UBLER is within 0.1. When the SNR is high, the UBLER will be low, so by increasing the MCS within a range of 0.1 or less, the amount of information transmitted (spectral efficiency) can be increased.

[0060] Figure 3 shows the combinations of selecting the MCS Index from the SNR and UBLER in Figure 2. The MCS Index is an index of possible combinations of modulation order and target code rate. By specifying the MCS Index, the modulation order, target code rate, and spectral efficiency (information transmission rate) can be determined. For example, MCS:0 means that the values ​​for modulation order and target code rate are small, and the spectral efficiency is also the lowest. The MCS Index is selected based on the radio signal conditions and BLER (Block Error Rate) reported from the UE via DCI (Data Center Interconnection).

[0061] The operation of the communication control device 100 of the wireless access system 1000 configured as described above will be explained below. (Operation overview) In this invention, the time required for FEC decoding and other demodulation processes changes depending on the MCS Index (settings for modulation / demodulation and data redundancy) and SINR (signal-to-noise ratio and interference ratio). Therefore, the PHY-high processing time is learned based on the MCS Index and SINR. During operation, the PHY-high processing time is estimated based on the MCS Index and SINR. If the processing deadline for the time slot is not reached, the CPU frequency and accelerator performance settings are reduced to conserve power. If the CPU frequency is lowered too much and the processing within the time slot is not completed, the learned data will be corrected and the system will operate at a higher frequency thereafter.

[0062] This invention focuses on the data processing portions of channels processed by a defined PHY, specifically PDSCH (Physical Downlink Shared Channel) and PUSCH (Physical Uplink Shared Channel). PHY processing is described in Non-Patent Document 1.

[0063] <Pre-learning> Figure 4 is a flowchart illustrating the overview of PHY-high processing time training using the MCS Index. As shown in Figure 4, in step S1, the MCS acquisition unit 111 (Figure 1) acquires the MCS Index from the MAC unit 122 of the signal processing unit 120.

[0064] In step S2, the processing time estimation unit 113 (Figure 1) learns the PHY-high processing time for each setting of MCS, etc., and then completes the processing of this flow.

[0065] Figure 5 shows a learning table of PHY-high processing time for each MCS setting. The vertical axis of Figure 5 shows the MCS Index, and the horizontal axis shows the estimated PHY-high processing time (us) at a given CPU frequency (GHz). The values ​​given for PHY-high processing time (us) are not measured values, but rather estimated values ​​given when the vertical and horizontal axes were determined. In Figure 5, the shaded area of ​​the learning table indicates the range in which the CPU frequency can be lowered. In other words, the CPU frequency should be set within the range in which the estimated PHY-high processing time (us) in Figure 5 falls within the PHY-high processing time (here, the limit of 500us for processing in PHY-high mode). For example, as shown by the arrow in Figure 5, if the MCS Index is MCS3, the estimated PHY-high processing time will be within 500us if the CPU frequency is 1.2 (GHz) or higher, making it a viable setting. Furthermore, among the configurable CPU frequencies of 1.2 (GHz) to 2.4 (GHz), the CPU frequency is set to 1.2 (GHz) (the lowest frequency in this case) from the perspective of keeping the CPU frequency as low as possible.

[0066] Similarly, when the MCS Index is MCS4, the CPU frequency is set to 1.4 GHz (the lowest frequency in this case), which is the lowest possible CPU frequency among the configurable CPU frequencies of 1.4 GHz to 2.4 GHz that keep the estimated PHY-high processing time within 500 us. When the MCS Index is MCS0 to MCS2, all CPU frequencies between 1.0 GHz and 2.4 GHz will be within 500 us. Therefore, the CPU frequency will be set to 1.0 GHz, which is the lowest possible CPU frequency. As shown in Figure 5, the larger the MCS Index value, the larger the estimated PHY-high processing time (us), and the higher the configurable CPU frequency.

[0067] Here, the PHY-high processing time learning table shown in Figure 5 is an important indicator for when the frequency control unit 114 controls the CPU frequency to be lowered to a level below the processing time of the time slot. It is important that the CPU frequency is not lowered too much so that processing within the time slot is not completed (in this case, a retransmission request may be executed and a delay may occur). For this reason, in this embodiment, (1) a safety factor is added to the set CPU frequency to determine the CPU frequency (including cases where a learning table that takes the safety factor into account in advance is created), and (2) the processing time estimation unit 113 performs feedback by rewriting the table values ​​of the learning table shown in Figure 5 based on the measured value of the PHY-high processing time ("correct the learned content and operate at a higher frequency thereafter").

[0068] Thus, the MCS acquisition unit 111 acquires the PHY-high processing time for each MCS setting in advance, and the processing time estimation unit 113 learns the PHY-high processing time for each MCS setting that was acquired in advance.

[0069] <In operation> Figure 6 is a flowchart showing the CPU frequency setting process, which estimates the PHY-high processing time based on the MCS Index and SINR during operation and then lowers the CPU frequency performance setting. In step S11, the MCS acquisition unit 111 acquires the MCS Index and SINR (radio wave quality information). In step S12, the processing time estimation unit 113 estimates the PHY-high processing time based on the MCS Index and SINR. In step S13, the processing time estimation unit 113 determines whether or not the processing deadline for the time slot has been reached. If the processing deadline for the time slot has not been reached (S13: No), proceed to step S14. If the processing deadline for the time slot has been reached (S13: Yes), proceed to step S15.

[0070] In step S14, the frequency control unit 114 reduces the CPU frequency within the processing time range of the time slot and proceeds to step S15. In step S15, the processing time estimation unit 113 determines whether the processing within the time slot has been completed. If the processing within the time slot has been completed (S15: Yes), the processing of this flow is terminated. If processing within the time slot is not completed (S15: No), in step S16 the processing time estimation unit 113 corrects the learned content and terminates the processing of this flow by operating at a higher CPU frequency.

[0071] Thus, during operation, the processing time estimation unit 113 estimates the PHY-high processing time based on the MCS Index and SINR, and if it is not possible to reach the processing deadline for the time slot, it lowers the CPU frequency performance setting to save power. If the processing time estimation unit 113 lowers the CPU frequency too much and fails to complete the processing within the time slot, it corrects the learned content and operates at a higher frequency thereafter.

[0072] (Operation of each part) The operation of each part will be described below, according to the key points of the present invention. <Point 1> Point 1 is power saving through CPU core frequency determination based on decoding time estimation. • An example of obtaining the MCS Index and estimating the PHY-high processing time based on the MCS Index. Figure 7 is an explanatory diagram of the operation of point 1 of the wireless access system shown in Figure 1. Functional blocks corresponding to the operation of point 1 are shown with thick solid lines, and the flow of operation is shown with white arrows (the same notation will be used in all subsequent figures). As shown in Figure 7, the MCS acquisition unit 111 acquires the MCS Index from the MAC unit 122 of the signal processing unit 120. The processing time estimation unit 113 estimates the future PHY-high processing time based on the MCS Index acquired by the MCS acquisition unit 111 and derives the configurable CPU frequency. The frequency control unit 114 determines the CPU frequency based on the information from the processing time estimation unit 113 and operates the frequency control driver 141 to dynamically change the operating frequency of the CPU core 131.

[0073] Figure 8 illustrates the derivation of configurable CPU frequencies based on the estimation of future PHY-high processing time using the MCS Index acquired by the MCS acquisition unit 111. The vertical axis of Figure 8 represents the MCS, and the horizontal axis represents the estimated PHY-high processing time (us) at a given CPU frequency (GHz). The shaded area in the learning table of Figure 8 indicates the range of CPU frequency settings in which the CPU frequency can be reduced (the same notation will be used in the relevant figures below).

[0074] The MCS acquisition unit 111 acquires the MCS Index from the MAC unit 122. Here, as shown by the symbol aa in Figure 8, the MCS acquisition unit 111 acquires the MCS3 of the MCS Index.

[0075] As shown by the symbol bb in Figure 8, the processing time estimation unit 113 estimates the PHY-high processing time for each frequency based on the MCS Index acquired by the MCS acquisition unit 111. Here, it estimates the PHY-high processing times for each frequency in the case of MCS3: "490", "470", "450", "430", "410", "390", and "370".

[0076] As shown by the symbol cc in Figure 8, the frequency control unit 114 determines the CPU frequency (in this case, a CPU frequency of 1.2 GHz) and performs CPU frequency setting control. In this case, the frequency control unit 114 determines the CPU frequency "1.2" from among the CPU frequencies "1.2", "1.4", "1.6", "1.8", "2.0", "2.2", and "2.4" corresponding to the PHY-high processing times "490", "470", "450", "430", "410", "390", and "370", so that the processing is completed just before the end of the time slot. By lowering the CPU frequency so that the processing is completed just before the end of the time slot, power saving can be achieved.

[0077] • An example of acquiring radio wave quality information and estimating PHY-high processing time based on that information. Figure 9 is an explanatory diagram of the operation of point 1 of the wireless access system shown in Figure 1. As shown in Figure 9, the radio wave condition acquisition unit 112 acquires radio wave quality information from the MAC unit 122 and RU20. The processing time estimation unit 113 estimates the future PHY-high processing time based on the radio wave quality information acquired by the radio wave condition acquisition unit 112, and derives the configurable CPU frequency. The frequency control unit 114 determines the CPU frequency based on the information from the processing time estimation unit 113 and operates the frequency control driver 141 to dynamically change the operating frequency of the CPU core 131.

[0078] Figure 10 illustrates the derivation of configurable CPU frequencies based on the estimation of future PHY-high processing time using radio wave quality information acquired by the radio wave condition acquisition unit 112. The vertical axis of Figure 10 represents SINR, and the horizontal axis represents PHY-high processing time (us) at a given CPU frequency (GHz). The shaded area of ​​the learning table in Figure 10 indicates the range of CPU frequencies that can be lowered.

[0079] As shown by the code dd in Figure 10, the radio wave condition acquisition unit 112 acquires radio wave quality information obtained from the MAC unit 122 and RU20. In this case, the radio wave condition acquisition unit 112 acquires SINR4.

[0080] As shown by the symbol ee in Figure 10, the processing time estimation unit 113 estimates the PHY-high processing time for each frequency based on the radio wave quality information acquired by the radio wave condition acquisition unit 112. Here, the PHY-high processing times for each frequency in the case of SINR4 are estimated as "490", "470", "450", "430", "410", "390", and "370".

[0081] As indicated by the symbol ff in Figure 10, the frequency control unit 114 determines the CPU frequency (in this case, a CPU frequency of 1.2 (GHz) is determined) and performs CPU frequency setting control. In this case, the frequency control unit 114 determines the CPU frequency "1.2", which allows processing to be completed just before the time slot, from among the CPU frequencies "1.2", "1.4", "1.6", "1.8", "2.0", "2.2", and "2.4" corresponding to the PHY-high processing times "490", "470", "450", "430", "410", "390", and "370". By lowering the CPU frequency so that processing is completed just before the time slot, power saving can be achieved.

[0082] The above examples describe how to estimate PHY-high processing time based on the MCS Index and how to estimate PHY-high processing time based on the radio wave quality information. However, processing time estimation can also be performed using only the MCS Index or radio wave quality information. Furthermore, the accuracy of processing time estimation can be improved by using both the MCS Index and radio wave quality information to create, for example, a three-dimensional map and referring to this map.

[0083] <Point 2> Point 2 is improved CPU control accuracy and power saving through MAC schedule analysis. Figure 11 is an explanatory diagram of the operation of point 2 of the wireless access system shown in Figure 1. As shown in Figure 11, the MAC schedule analysis unit 115 acquires wireless resource allocation information (MAC schedule information) from the MAC unit 122 of the signal processing unit 120 and converts it into resource allocation information (PHY schedule information) in PHY-high mode. The processing time estimation unit 113 estimates the processing time for each PHY time slot based on the PHY schedule information, according to the respective situations of UL / DL bidirectional, UL only, DL only, and neither direction. This enables improved accuracy in both directions, taking DL processing into account, and further power savings in PHY time slots that do not require adjustment.

[0084] Figure 12 shows the processing for each time slot in the wireless access system shown in Figure 11, specifically the downlink data processing (DL) that sends data from the DU server's vDU to the RU20, and the uplink data processing (UL) that sends data from the RU20 to the DU server's vDU. The RU20 time slots contain MAC schedule information obtained from the MAC scheduler. The MAC schedule analysis unit 115 acquires MAC schedule information and converts it into PHY schedule information in PHY-high mode. In Figure 12, the time slot of the vDU on the DU server contains the PHY schedule information converted from the MAC schedule information.

[0085] As shown by the symbol gg in Figure 12, the lowest frequency capable of DL processing can be set for the processing time of DL only. As shown by the symbol hh in Figure 12, the lowest frequency can be set for processing time without bidirectional processing. In the two cases described above, when UL processing is not performed, the frequency can be set even lower. This allows for further power savings.

[0086] As indicated by the symbol ii in Figure 12, an explanatory diagram for the UL-only processing time is shown in Figure 13. Figure 13 illustrates the derivation of configurable CPU frequencies based on the estimation of future PHY-high processing time using the MCS Index acquired by the MCS acquisition unit 111. In Figure 13, the vertical axis represents the MCS, and the horizontal axis represents the PHY-high processing time (us) at a given CPU frequency (GHz). The learning table in Figure 13 uses the same values ​​as the learning table in Figure 8.

[0087] As indicated by the symbol jj in Figure 12, an explanatory diagram of the processing time in both UL / DL directions is shown in Figure 14. Figure 14 illustrates the derivation of configurable CPU frequencies based on the estimation of future PHY-high processing time using the MCS Index acquired by the MCS acquisition unit 111. In Figure 14, the vertical axis represents the MCS, and the horizontal axis represents the PHY-high processing time (us) at a given CPU frequency (GHz). The learning table in Figure 14 differs from the learning table in Figure 13 in that it contains different numerical values ​​and in the areas where the CPU frequency can be reduced. When performing simultaneous UL / DL CPU processing, the processing time increases, so the training table itself is changed. By preparing an appropriate training table, accuracy can be improved.

[0088] <Point 3> Point 3 is the improvement of CPU control accuracy through delay time feedback. Figure 15 is an explanatory diagram of the operation of point 3 of the wireless access system shown in Figure 1. As shown in Figure 15, the delay time acquisition unit 116 acquires the actual PHY-high processing time from the PHY unit 121 of the signal processing unit 120 and provides it to the processing time estimation unit 113. The processing time estimation unit 113 rewrites the table values ​​in the learning table (modifies the estimation method) based on the PHY-high processing time provided by the delay time acquisition unit 116.

[0089] Here, the delay time acquisition unit 116 can also acquire whether or not a retransmission request exists from the MAC unit 122 and provide this to the processing time estimation unit 113. If the presence or absence of a retransmission request can be acquired, then if a retransmission request exists, the time required for the retransmission request can be added to the HY-high processing time. In this way, CPU control accuracy can be improved by incorporating feedback that takes into account the server operating status (actual PHY-high processing time, and / or whether a retransmission request was made).

[0090] The following explains a specific example of delay time feedback, which is point 3. Figure 16 shows the time slots for PHY-high processing (UL) in the case of MCS:3. The upper part of Figure 16 shows the time slots for PHY-high processing, and the lower part of Figure 16 shows the processing time (us) for each step of PHY-high processing, namely demapping 80 (us), demodulation 100 (us), decoding (FEC decoding) 260 (us), and CRC check 70 (us). Therefore, the PHY-high processing time is 510 (us) (code kk in Figure 16).

[0091] Figure 17 illustrates an example of rewriting the table values ​​of the training table based on the PHY-high processing time in Figure 16. In Figure 17, the training table before rewriting is shown in Figure 13. As shown by the symbol kk in Figure 17, the processing time estimation unit 113 rewrites the original PHY-high processing time table value 450 in the case of MCS:3 to 510.

[0092] By feeding back the actual PHY-high processing time and rewriting the table values ​​in the learning table, it is possible to set the optimal CPU frequency and improve the accuracy of CPU control.

[0093] [Example Table] An example of a table included in the control unit 110 of the communication control device 100 of the wireless access system 1000 shown in Figure 1 will be described.

[0094] Figure 18 shows an example of a mixed database table used in the bidirectional processing time shown in Figure 14. This mixed database exists for each UL MCS. This mixed database is read / written by the processing time estimation unit 113. The processing time estimation unit 113 reads the estimated processing time for UL tasks at a given CPU frequency when ULDL data is present.

[0095] Figure 19 shows an example of a ULDB table used for UL-only processing time in Figure 13. This ULDB exists for each UL MCS. This ULDB is read / written by the processing time estimation unit 113. The processing time estimation unit 113 reads the estimated processing time for UL tasks at a given CPU frequency when only UL data is present.

[0096] Figure 20 shows an example of a DLDB table. This DLDB exists for each DL MCS. This DLDB is read / written by the processing time estimation unit 113. The processing time estimation unit 113 reads the estimated processing time of a DL task at a given CPU frequency when DL data is present.

[0097] As described above, each DB in Figures 18 to 20 stores the task time for each MCS, and finally the processing time estimation unit 113 sums up the task times to calculate the processing time for each MCS. The processing time estimation unit 113 feeds back the summed processing time for each MCS and rewrites the table values ​​in the learning table.

[0098] Figure 21 is a CPU frequency setting history table, which stores the UL MCS, DL MCS, UL CPU frequency, and DL CPU frequency for each time slot. This CPU frequency setting history table is read by the processing time estimation unit 113 and written by the frequency control unit 114. This CPU frequency setting history table is used during feedback and records the history of MCS Index and CPU frequency for past PHY time slots. (1) When the UL / DL tasks are performed on all 131 CPU cores under control, the UL CPU frequency equals the DL CPU frequency. (2) If the UL / DL each have 131 CPU cores, then the UL CPU frequency is not equal to the DL CPU frequency.

[0099] Figure 22 shows the controlled table, which stores the UL / DL core mask. This control target table is read by the processing time estimation unit 113 and the frequency control unit 114. Note that the core mask is read only, and not written. The processing time estimation unit 113 and the frequency control unit 114 pre-specify the CPU core masks on which the UL and DL tasks are assigned. (1) When the UL / DL tasks are performed on all 131 CPU cores under control, the core mask for UL equals the core mask for DL. (2) If the 131 CPU cores installed in UL / DL are separate, the core masks for UL and DL will be mutually exclusive (the cores will be isolated from each other).

[0100] Figure 23 is a diagram illustrating the time-axis handling of time slots for downstream data processing (DL), which sends data from the DU server's vDU to RU20, and upstream data processing (UL), which sends data from RU20 to the DU server's vDU, in order to illustrate the MAC-PHY conversion table in Figure 24. The RU20 time slots contain MAC schedule information obtained from the MAC scheduler. The MAC schedule analysis unit 115 acquires MAC schedule information and converts it into PHY schedule information in PHY-high mode. In Figure 23, the time slot of the vDU on the DU server contains the PHY schedule information converted from the MAC schedule information. In the UL time slots of RU20 shown in Figure 23, if the central time slot is N on the time axis, the timing of the previous time slot is N-1, and the timing of the next time slot is N+1.

[0101] Figure 24 shows an example of a MAC-PHY conversion table. The MAC-PHY conversion table in Figure 24 is referenced when converting MAC schedule information and PHY schedule information. This MAC-PHY conversion table is read by the processing time estimation unit 113 and the delay time acquisition unit 116, and written by the MAC schedule analysis unit 115. The processing time estimation unit 113 converts MAC schedule information into PHY schedule information by referring to the MAC-PHY conversion table. The PHY time slot and MAC time slot have the following relationship. PHY time slot = MAC time slot + (PHY - MAC)

[0102] [CPU frequency control granularity change] This section explains how to change the granularity of CPU frequency control. The granularity of CPU frequency control can be changed depending on how UL / DL tasks are distributed to CPU cores.

[0103] Figure 25 shows an example configuration of a DU server when UL / DL tasks are performed on all CPU cores under control. The DU server controls all 131 target CPU cores simultaneously if UL / DL tasks are running on all CPU cores under its control.

[0104] Figure 26 shows an example configuration of a DU server where the CPU cores installed are separate for UL and DL. If the DU server has separate CPU cores for UUL / DL, it controls the CPU cores for each UL group and DL group. In the case of Figure 26, the CPU cores are divided into those that perform demapping, demodulation, and CRC checking in the UL group (left side of Figure 26) and those that perform CRC addition, modulation, and mapping in the DL group (right side of Figure 26). In this way, the granularity of CPU frequency control is changed depending on how UL / DL tasks are distributed to the CPU cores.

[0105] [Estimating DL PHY-high time] This explains how to estimate the PHY-high time for deep learning. If the DL processing time fluctuates depending on the DL MCS and DL radio wave information, it is also possible to estimate the DL's PHY-high time. In that case, the controlled object is the DL's operating core. The UL operating core is controlled based on the estimated PHY-high time of the UL.

[0106] Figure 27 shows the time slots for PHY-high processing (DL) in the case of MCS:3. The upper part of Figure 27 shows the time slots for PHY-high processing, and the lower part of Figure 27 shows the processing time (us) for each part of PHY-high processing, namely CRC addition 80 (us), encoding (FEC encoding) 260 (us), modulation 100 (us), and mapping 70 (us). Therefore, the PHY-high processing time is 510 (us) (code ll in Figure 27).

[0107] Figure 28 illustrates an example of rewriting the table values ​​of the training table based on the PHY-high processing time in Figure 27. In Figure 28, the training table before rewriting is shown in Figure 13. As shown by the symbol ll in Figure 28, the processing time estimation unit 113 rewrites the original PHY-high processing time table value 450 in the case of MCS:3 to 510.

[0108] By estimating the PHY-high time of the DL and rewriting the table values ​​in the learning table, it is possible to improve the accuracy of CPU control when the DL processing time fluctuates depending on the DL MCS and DL radio wave information.

[0109] [Flowchart for estimating processing time] <Overall flow of processing time estimation> The processing time estimation process of the processing time estimation unit 113 will be explained below with reference to the flowcharts in Figures 29 to 31. Figure 29 is a flowchart of the processing time estimation process of the processing time estimation unit 113. In step S21, the processing time estimation unit 113 (Figure 1) obtains MAC-PHY schedule conversion information from the MAC-PHY conversion table (Figure 24). In step S22, the processing time estimation unit 113 obtains UL or DL ​​radio wave quality information from the radio wave condition acquisition unit 112. In step S23, the processing time estimation unit 113 obtains the MCS Index for the MAC time slot from the MCS acquisition unit 111.

[0110] In step S24, the processing time estimation unit 113 converts from MAC time slots to PHY time slots. The conversion from MAC time slots to PHY time slots is described in Figures 23 and 24. In step S25, the processing time estimation unit 113 obtains PHY schedule information from the MAC schedule analysis unit 115 (Figure 1).

[0111] In step S26, the processing time estimation unit 113 determines whether the power saving effect of CPU frequency control is greater than the power saving effect of accelerator control (power saving effect of CPU frequency control > power saving effect of accelerator control). If the power saving effect of CPU frequency control is greater than the power saving effect of accelerator control (S26: Yes), in step S27, the processing time estimation unit 113 estimates the processing time for each CPU frequency in the PHY time slot. Details of the processing time estimation for each frequency will be described later in Figures 30 and 31. In step S28, the processing time estimation unit 113 notifies the frequency control unit 114 of the MCS Index, the lowest frequency, and the target group, and proceeds to step S31.

[0112] On the other hand, if the power saving effect of CPU frequency control in step S26 is less than or equal to the power saving effect of accelerator control (S26: No), then in step S29, the processing time estimation unit 113 estimates the processing time for each accelerator setting in the PHY time slot. In step S30, the processing time estimation unit 113 notifies the frequency control unit 114 of the MCS Index and accelerator settings, and proceeds to step S31.

[0113] In step S31, the processing time estimation unit 113 determines whether the processing data is at the end of a frame. If it is not at the end of a frame (S31: No), the unit returns to step S23 and repeats the processing in steps S23 through S30. If it is the end of the frame (S31: Yes), in step S32 the processing time estimation unit 113 determines whether or not there is feedback (whether it is in a mode to execute feedback control / whether it is under feedback control conditions). If feedback is provided (S32: Yes), the feedback process is executed in step S33 to terminate the flow. Details of the feedback process will be described later in Figures 33 and 34. On the other hand, if no feedback is provided (S32: No), the process returns to step S22 and continues.

[0114] <Detailed flow of processing time estimation> This section provides details on processing time estimation. There are two cases: one where the UL / DL task is implemented on all CPU cores under control (Figure 30), and another where each UL / DL task is assigned to a different CPU core (Figure 31).

[0115] Figure 30 shows a subroutine for estimating processing time when the UL / DL task is performed on all controlled CPU cores. It is called and executed by the subroutine call in step S27 of Figure 29. In step S101, the processing time estimation unit 113 (Figure 1) determines whether or not there is UL data in the PHY time slot. If there is UL data in the PHY time slot (S101: Yes), in step S102 the processing time estimation unit 113 determines whether or not there is DL data in the PHY time slot. If there is DL data in the PHY time slot (S102: Yes), in step S103 the processing time estimation unit 113 selects a mixed DB (Figure 18).

[0116] In step S104, the processing time estimation unit 113 sums up the processing times for each task in UL and extracts the minimum CPU frequency that is above the standard. The processing time estimation unit 113 also extracts the accelerator settings. In step S105, the processing time estimation unit 113 corrects the CPU frequency according to the UL radio wave quality information and proceeds to step S112. This CPU frequency correction increases the CPU frequency in anticipation of longer processing times when radio wave quality is poor.

[0117] If there is no DL data in the PHY time slot in step S102 (S102: No), the processing time estimation unit 113 selects ULDB in step S106. In step S107, the processing time estimation unit 113 sums up the processing times for each task in UL and extracts the minimum CPU frequency that is above the standard. The processing time estimation unit 113 also extracts the accelerator settings. In step S108, the processing time estimation unit 113 corrects the CPU frequency according to the UL radio wave quality information and proceeds to step S112. Here again, if the radio wave quality is poor, the CPU frequency is increased, anticipating that the processing time will be longer.

[0118] If there is no UL data in the PHY time slot in step S101 (S101: No), the processing time estimation unit 113 determines in step S109 whether or not there is DL data in the PHY time slot. If DL data is available in the PHY time slot (S109: Yes), in step S110 the processing time estimation unit 113 obtains the lowest frequency during DL processing and proceeds to step S112. The processing time estimation unit 113 also extracts the accelerator settings.

[0119] If there is no DL data in the PHY time slot in step S109 (S109: No), the processing time estimation unit 113 obtains the lowest no-load frequency in step S111 and proceeds to step S112. The processing time estimation unit 113 also extracts the accelerator settings. In step S112, the processing time estimation unit 113 notifies the frequency control unit 114 (Figure 1) of the extracted CPU frequency, MCS Index, and target group (UL), and returns to step S27 in Figure 29.

[0120] Figure 31 shows the subroutine for estimating processing time when the CPU cores installed are separated for UL / DL. It is called and executed by the subroutine call in step S27 of Figure 29. In step S201, the processing time estimation unit 113 (Figure 1) determines whether or not there is UL data in the PHY time slot. If UL data is available in the PHY time slot (S201: Yes), in step S202 the processing time estimation unit 113 selects ULDB (Figure 19).

[0121] In step S203, the processing time estimation unit 113 sums up the processing times for each task in UL and extracts the minimum CPU frequency that is above the standard. The processing time estimation unit 113 also extracts the accelerator settings. In step S204, the processing time estimation unit 113 corrects the CPU frequency according to the UL radio wave quality information and proceeds to step S206. This CPU frequency correction increases the CPU frequency in anticipation of longer processing times when radio wave quality is poor.

[0122] If there is no DL data in the PHY time slot in step S201 (S201: No), the processing time estimation unit 113 obtains the lowest no-load frequency in step S205 and proceeds to step S206. In step S206, the extracted CPU frequency, MCS Index, and target group (UL) are notified to the frequency control unit 114. In step S207, the processing time estimation unit 113 determines whether or not there is DL data in the PHY time slot. If DL data is available in the PHY time slot (S207: Yes), in step S208 the processing time estimation unit 113 selects DLDB.

[0123] In step S209, the processing time estimation unit 113 sums up the processing times for each DL task and extracts the minimum CPU frequency that is above the standard. The processing time estimation unit 113 also extracts the accelerator settings. In step S210, the processing time estimation unit 113 corrects the CPU frequency according to the DL radio wave quality information and proceeds to step S206. This CPU frequency correction increases the CPU frequency in anticipation of longer processing times when radio wave quality is poor.

[0124] If there is no DL data in the PHY time slot in step S207 (S207: No), the processing time estimation unit 113 obtains the lowest no-load frequency in step S211 and proceeds to step S212.

[0125] In step S212, the extracted CPU frequency, MCS Index, and target group (DL) are notified to the frequency control unit, and the process returns to step S27 in Figure 29. The above explains the details of processing time estimation. Next, we will explain the feedback to processing time estimation.

[0126] <Detailed flow of feedback processing> This section details the feedback process used to estimate processing time. The feedback process for processing time estimation consists of the processing of the delay time acquisition unit 116 (Figure 32) and the processing time estimation process of the processing time estimation unit 113 (Figures 33 and 34).

[0127] Figure 32 shows the feedback processing subroutine controlled by the delay time acquisition unit 116. It is called and executed by the subroutine call in step S33 of Figure 29. In step S301, the delay time acquisition unit 116 acquires MAC-PHY schedule conversion information from the MAC-PHY conversion table. In step S302, the delay time acquisition unit 116 obtains from the MAC unit 122 whether or not a retransmission request has been made.

[0128] In step S303, the delay time acquisition unit 116 acquires the timestamps of each point in the UL PHY-high processing from the PHY unit 121. In step S304, the delay time acquisition unit 116 calculates the delay time for each process from the timestamp. In step S305, the delay time acquisition unit 116 sends the processing time estimation unit whether or not a retransmission request is required in the PHY time slot and the delay time for each process, and then returns to step S33 in Figure 29.

[0129] Figure 33 shows a subroutine for feedback processing executed by the processing time estimation unit 113 based on the processing result of the delay time acquisition unit 116 in Figure 32. It is called and executed by the subroutine call in step S33 of Figure 29. In step S401, the processing time estimation unit 113 receives from the delay time acquisition unit whether or not a retransmission request is required in the PHY time slot and the delay time for each process. In step S402, the processing time estimation unit 113 obtains the MCS Index and the set CPU frequency for the corresponding PHY time slot from the CPU frequency setting history.

[0130] In step S403, the processing time estimation unit 113 selects a mixed DB / ULDB based on whether UL / DL tasks are separated and whether UL / DL data is available in the PHY time slot. The method for selecting a mixed DB / ULDB is the same as the processing time estimation details shown in Figures 30 and 31.

[0131] In step S404, the processing time estimation unit 113 overwrites the relevant section if the processing time of each task at a given CPU frequency deviates by more than a certain amount. In step S405, the processing time estimation unit 113 corrects the corresponding parts of the other MCS Index and CPU frequency according to the discrepancy in processing time, and returns to step S33 in Figure 29. Here, the presence or absence of a retransmission request may be used to determine whether or not overwriting is necessary for mixed DB / ULDB / DLDB.

[0132] Figure 34 is an illustrative diagram illustrating the horizontal expansion of the DLDB table in Figure 20 to include parameters other than MCS Index and CPU frequency. It is an explanatory diagram for step S405 in Figure 33. The processing time estimation unit 113 corrects the corresponding parts of other MCS indices and CPU frequencies according to the discrepancy in processing time. For example, if a discrepancy in processing time is found in the flow in Figure 32, the corresponding part of the CPU frequency is corrected from 1.4GHz (symbol mm in Figure 34) where UL MCS=0 is found (symbol nn in Figure 34). The above explains the feedback mechanism for estimating processing time.

[0133] [CPU frequency control flowchart] CPU frequency control involves two processes: one where UL / DL tasks are implemented on all CPU cores under control (Figure 35), and another where UL / DL tasks are assigned to separate CPU cores (Figure 36).

[0134] Figure 35 is a flowchart of CPU frequency control when the UL / DL task is performed on all CPU cores under control. In step S41, the frequency control unit 114 (Figure 1) obtains the CPU frequency, MCS Index, and target group (UL) for the PHY time slot from the MAC schedule analysis unit 115 (Figure 1). In step S42, the frequency control unit 114 determines the UL CPU frequency by adding a safety factor to the lowest frequency. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be dynamically changed according to load conditions, radio wave conditions, etc.

[0135] In step S43, the frequency control unit 114 obtains the UL CPU core from the control target table (Figure 21). In step S44, the frequency control unit 114 instructs the frequency control driver 141 (Figure 1) to set the CPU frequency for the corresponding CPU core. The frequency control unit 114 may also perform uncore frequency determination and control after the core frequency instruction. In step S45, the frequency control unit 114 records the UL MCS Index and CPU frequency in the CPU frequency setting history and terminates the processing of this flow.

[0136] Figure 36 is a flowchart of CPU frequency control when the CPU cores installed are separate for UL / DL. In step S51, the frequency control unit 114 (Figure 1) obtains the CPU frequency, MCS Index, and target group (UL or DL) for the PHY time slot from the MAC schedule analysis unit 115 (Figure 1). In step S52, the frequency control unit 114 determines whether or not UL is included in the target group. If UL is not included in the target group (S52: No), the process proceeds to step S57.

[0137] If the target group includes UL (S52: Yes), in step S53, the frequency control unit 114 determines the UL CPU frequency by adding a safety factor to the lowest frequency. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be changed dynamically depending on the load conditions, radio wave conditions, etc.

[0138] In step S54, the frequency control unit 114 obtains the UL CPU core from the control target table (Figure 21). In step S55, the frequency control unit 114 instructs the frequency control driver 141 (Figure 1) to set the CPU frequency for the relevant CPU core. The frequency control unit 114 may also perform uncore frequency determination and control after the core frequency instruction. In step S56, the frequency control unit 114 records the UL MCS Index and CPU frequency in the CPU frequency setting history.

[0139] In step S57, the frequency control unit 114 determines whether DL is included in the target group. If DL is not included in the target group (S57: No), the processing of this flow is terminated.

[0140] If the target group includes DL (S57: Yes), in step S58, the frequency control unit 114 determines the DL CPU frequency by adding a safety factor to the lowest frequency. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be changed dynamically depending on the load conditions, radio wave conditions, etc.

[0141] In step S59, the frequency control unit 114 obtains the DL CPU core from the control target table (Figure 21). In step S60, the frequency control unit 114 instructs the frequency control driver 141 (Figure 1) to set the CPU frequency for the relevant CPU core. The frequency control unit 114 may also perform uncore frequency determination and control after the core frequency instruction. In step S61, the frequency control unit 114 records the DL MCS Index and CPU frequency in the CPU frequency setting history and terminates the processing of this flow.

[0142] (Second embodiment) The second embodiment aims to reduce power consumption in an accelerator whose accelerator frequency and power saving settings can be controlled. Figure 37 is a schematic diagram of a wireless access system according to a second embodiment of the present invention. The same reference numerals are used for components identical to those in Figure 1, and the explanation of the redundant parts is omitted. As shown in Figure 37, the wireless access system 1000A includes RU20 and communication control device 100A. The communication control device 100A comprises a control unit 110, a signal processing unit 120, hardware (HW) 130A, and an OS / driver 140A.

[0143] HW130A is the same as HW130 in Figure 1, but with the addition of accelerator 135. Accelerator 135 is an accelerator that allows control of accelerator frequency and power saving settings.

[0144] OS / driver 140A is the OS / driver 140 shown in Figure 1, with the addition of an accelerator driver 142 that controls the accelerator 135.

[0145] The frequency control unit 114 of the control unit 110 controls the accelerator 135 via the accelerator driver 142 according to the accelerator settings set by the frequency control unit 114. The frequency control unit 114 controls the accelerator 135, which can control the accelerator frequency and power saving settings, based on the accelerator frequency and estimated processing time for each setting, similar to the CPU frequency control described above (see below). Here, the processing time estimation unit 113 determines the accelerator settings by adding a safety factor when setting the accelerator.

[0146] Here, the frequency control unit 114 prioritizes accelerator control if it offers greater power savings than CPU frequency control. Conversely, it prioritizes CPU frequency control if it does not. The following are some examples of methods for controlling the accelerator 135. Control the accelerator frequency. Clock gating (stopping the accelerator's clock supply) is performed. Power gating (reducing the accelerator's supply voltage) is implemented.

[0147] Figure 38 is a flowchart of accelerator frequency control by the frequency control unit 114. In step S71, the frequency control unit 114 (Figure 37) obtains the accelerator settings from the processing time estimation unit 113. In step S72, the frequency control unit 114 determines the accelerator setting by adding a safety factor to the accelerator setting. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be changed dynamically according to load conditions, radio wave conditions, etc. In step S73, the frequency control unit 114 instructs the accelerator driver to configure the accelerator, and then terminates the processing of this flow.

[0148] (Third embodiment) The third embodiment aims to reduce CPU power consumption by controlling the CPU's uncore frequency. Figure 39 is a schematic diagram of a wireless access system according to a third embodiment of the present invention. The same reference numerals are used for components identical to those in Figure 1, and the explanation of the redundant parts is omitted. As shown in Figure 39, the wireless access system 1000B includes RU20 and communication control device 100B. The communication control device 100B comprises a control unit 110, a signal processing unit 120, hardware (HW) 130B, and an OS / driver 140.

[0149] HW130B is the same as HW130 in Figure 1, but with the addition of an uncore 136 (see below). The frequency control unit 114 of the control unit 110 controls the uncore 136 via the frequency control driver 141 of the OS / driver 140.

[0150] Figure 40 shows the uncore setting table 139 that the frequency control unit 114 reads. This uncore setting table 139 (uncore setting storage unit) is stored in the memory (not shown) of the control unit 110. As shown in Figure 40, the uncore setting table 139 stores setting information for changing the uncore frequency in addition to the CPU core frequency. The frequency control unit 114 obtains the uncore frequency for the CPU core frequency in advance from the uncore setting table 139. The frequency control unit 114 controls the uncore 136 at an uncore frequency that does not cause it to become a bottleneck, based on the setting information in the uncore setting table 139.

[0151] Figure 41 shows the configuration of a CPU socket having CPU cores and uncores. As shown in Figure 41, the HW130B includes a CPU socket 137a, a memory 138a connected to the CPU socket 137a, a CPU socket 137b connected to the CPU socket 137a, and a memory 138b connected to the CPU socket 137b.

[0152] CPU sockets 137 and 137b can accommodate each CPU core. CPU sockets 137 and 137b are equipped with uncores 136a and 136b, which are peripheral devices other than the CPU core. Uncores 136a and 136b include, for example, LLC (Last Level Cache), OCI (On-Chip Interconnect), IMC (Integrated Memory Controller), and PWR (Power Control Logic), and these are controlled by the uncore frequency.

[0153] This section describes the difference between the core frequency and the uncore frequency. Core frequency corresponds to access prior to the physical core's control L2Cache. Uncore frequency corresponds to access prior to the package (socket)'s LLC.

[0154] Figure 42 shows the delay performance (µs) at different uncore frequencies. The horizontal axis represents the uncore frequency (GHz), and the vertical axis represents the L1 delay performance (µs). It can be seen that the higher the uncore frequency, the lower the L1 delay performance (µs). In this embodiment, the frequency at which the uncore becomes a bottleneck relative to the core frequency is measured in advance and stored in the uncore setting table 139 shown in Figure 40. The uncore frequency read from the uncore setting table 139 shown in Figure 40 is the uncore frequency at the bottleneck resolution point, indicated by the circle in Figure 42.

[0155] The operation of the communication control device 100B, configured as described above, will be explained below. This embodiment controls not only the frequency of the CPU core 131 but also the CPU's uncore frequency, assuming that it does not affect time slot processing. Specifically, the uncore frequency is determined after the CPU core 131 frequency for UL / DL tasks is determined. Furthermore, an uncore frequency at which access to LLC does not become a bottleneck for a given CPU core 131 frequency can be measured in advance and used to determine the uncore frequency.

[0156] [Flowchart for uncore frequency control] Uncore frequency control involves two types of processing: one for when UL / DL tasks are implemented on all CPU cores under control (Figure 43), and another for when each UL / DL task is assigned to a different CPU core (Figure 44).

[0157] Figure 43 is a flowchart of uncore frequency control when the UL / DL task is performed on all CPU cores under control. In step S81, the frequency control unit 114 refers to the uncore setting table and obtains the uncore frequency for the core frequency. In step S82, the frequency control unit 114 determines the uncore frequency by adding a safety factor to the uncore frequency. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be changed dynamically according to load conditions, radio wave conditions, etc. In step S83, the frequency control unit 114 instructs the frequency control driver 141 to set the CPU frequency for the uncore, and then terminates the processing of this flow.

[0158] Figure 44 is a flowchart of uncore frequency control when the CPU cores installed are separate for UL / DL. In step S91, the frequency control unit 114 determines whether UL is included in the target group. If UL is not included in the target group (S91: No), the process proceeds to step S93.

[0159] If the target group includes UL (S91: Yes), in step S92 the frequency control unit 114 refers to the uncore setting table and obtains the uncore frequency for UL's CPU core frequency.

[0160] In step S93, the frequency control unit 114 determines whether DL is included in the target group. If DL is not included in the target group (S93: No), the process proceeds to step S95. If DL is included in the target group (S93: Yes), step S94 refers to the uncore setting table and obtains the uncore frequency for DL ​​relative to the CPU core frequency. In step S95, the frequency control unit 114 selects the larger of the uncore frequencies obtained based on the CPU core frequencies of UL or DL. In step S96, the frequency control unit 114 determines the uncore frequency by adding a safety factor to the uncore frequency. The safety factor may be fixed in advance by the maintenance personnel. Alternatively, it may be changed dynamically according to load conditions, radio wave conditions, etc. In step S97, the frequency control unit 114 instructs the frequency control driver 141 to set the CPU frequency for the uncore, and then terminates the processing of this flow.

[0161] [Hardware configuration] The communication control devices 100, 100A, and 100B (Figures 1, 37, and 39) of the wireless access systems 1000, 1000A, and 1000B (Figures 1, 37, and 39) according to the above embodiment are implemented by a computer 900 having a configuration such as that shown in Figure 45. Figure 45 is a hardware configuration diagram showing an example of a computer 900 that implements the functions of the communication control devices 100, 100A, and 100B. The communication control devices 100, 100A, and 100B include a CPU 901, RAM 902, ROM 903, HDD 904, accelerator 905, input / output interface (I / F) 906, media interface (I / F) 907, and communication interface (I / F) 908. Accelerator 905 corresponds to accelerator 132 in Figures 1, 37, and 39, and accelerator 135 in Figure 37.

[0162] Accelerator 905 is an accelerator (device) 132 (Figures 1, 37, and 39) that processes at high speed data from either the communication interface 908 or the RAM 902. Note that accelerator 905 may be of a type that returns the execution result to the CPU 901 or RAM 902 after processing from the CPU 901 or RAM 902 (Look-Aside type). Alternatively, accelerator 905 may be of an in-line type that acts as an intermediary between the communication interface 908 and the CPU 901 or RAM 902 to perform processing.

[0163] The accelerator 905 is connected to the external device 915 via the communication interface 908. The input / output interface 906 is connected to the input / output device 916. The media interface 907 reads and writes data to the recording medium 917.

[0164] The CPU 901 operates based on programs stored in the ROM 903 or HDD 904, and controls the various parts of the communication control devices 100, 100A, and 100B shown in Figures 1, 37, and 39 by executing programs (also called applications or apps) loaded into the RAM 902. This program can also be distributed via a communication line or by recording it on a recording medium 917 such as a CD-ROM. ROM903 stores boot programs executed by CPU901 when the computer 900 starts up, as well as programs that depend on the computer 900's hardware.

[0165] The CPU 901 controls the input / output device 916, which consists of an input unit such as a mouse or keyboard, and an output unit such as a display or printer, via the input / output interface 906. The CPU 901 acquires data from the input / output device 916 via the input / output interface 906 and outputs generated data to the input / output device 916. In addition to the CPU 901, a GPU (Graphics Processing Unit) or the like may also be used as a processor.

[0166] HDD904 stores programs executed by CPU901 and data used by those programs. Communication I / F908 receives data from other devices via a communication network (e.g., NW (Network)) and outputs it to CPU901, and also transmits data generated by CPU901 to other devices via the communication network.

[0167] The media interface 907 reads a program or data stored in the recording medium 917 and outputs it to the CPU 901 via the RAM 902. The CPU 901 loads the program related to the desired processing from the recording medium 917 onto the RAM 902 via the media interface 907 and executes the loaded program. The recording medium 917 can be an optical recording medium such as a DVD (Digital Versatile Disc) or PD (Phase Change Rewritable Disk), a magneto-optical recording medium such as an MO (Magneto Optical Disk), a magnetic recording medium, a conductive memory tape medium, or a semiconductor memory.

[0168] For example, when computer 900 functions as a communication control device 100, 100A, 100B (Figures 1, 37, and 39) configured as one of the devices according to this embodiment, the CPU 901 of computer 900 realizes the functions of the communication control devices 100, 100A, and 100B by executing a program loaded onto RAM 902. Furthermore, data from RAM 902 is stored in HDD 904. CPU 901 reads and executes a program related to the desired processing from the recording medium 917. Alternatively, CPU 901 may read a program related to the desired processing from another device via a communication network.

[0169] [effect] As described above, the communication control device 100 (Figure 1) for processing wireless access signals includes a communication quality information acquisition unit 101 that acquires communication quality information, a processing time estimation unit 113 that calculates an estimated processing time for each CPU frequency from the acquired communication quality information, and a frequency control unit 114 that lowers the CPU frequency below the currently set CPU frequency when the estimated processing time is less than or equal to the processing time of the time slot.

[0170] In this way, the communication control device 100 can achieve power savings by lowering the CPU frequency so that processing is completed just before the time slot expires. In other words, instead of setting the CPU core to the highest performance setting at all times to complete all processing within the time slot, as in conventional examples, it is possible to reduce the power consumption of the server while adhering to the processing deadline by constantly changing the CPU frequency to the optimal setting on a time slot basis. As a result, the communication control device 100 can reduce CPU power consumption while meeting the demands for high-speed processing, such as when configuring a vRAN system. Furthermore, the processing time estimation unit 113 calculates the estimated processing time for each CPU frequency from the acquired communication quality information, so it is possible to set the CPU frequency on a fine timescale of several hundred microseconds without making any changes to the PHY or MAC application.

[0171] In the communication control device 100, the communication quality information acquisition unit 101 is an MCS (Modulation and Coding Scheme) acquisition unit 111 that acquires the MCS Index of UL (UP Link) or DL ​​(Down Link) in the MAC time slot as communication quality information.

[0172] In this way, the communication control device 100 (processing time estimation unit 113) uses the MCS Index as communication quality information (wireless quality information) to estimate the processing time in the PHY-high layer, and from the estimated processing time, it can determine the lowest (or in some cases the lowest) setting for the CPU frequency, etc.

[0173] In the communication control device 100, the communication quality information acquisition unit 101 is a radio wave condition acquisition unit 112 that acquires UL (UP Link) or DL ​​(Down Link) radio wave quality information as communication quality information.

[0174] In this way, the communication control device 100 (processing time estimation unit 113) uses radio wave quality information such as SINR as communication quality information (wireless quality information) to estimate the processing time in the PHY-high layer, and from the estimated processing time, it can determine the lowest (or even the lowest) CPU frequency setting. It can also handle cases where the MCS Index is not obtained or cannot be obtained. Furthermore, by using it in conjunction with the MCS Index, the control accuracy can be further improved.

[0175] In the communication control device 100, the communication quality information acquisition unit 101 is a MAC schedule analysis unit 115 that acquires wireless resource allocation information, including MAC schedule information, as communication quality information.

[0176] By doing so, the communication control device 100 (processing time estimation unit 113) can use MAC schedule information as communication quality information (wireless quality information), thereby improving accuracy in both directions by taking DL processing into account, and further saving power in PHY time slots that do not require any action.

[0177] In the communication control device 100, the communication quality information acquisition unit 101 is a delay time acquisition unit 116 that calculates a delay time from the measured value of the PHY-high processing time and acquires the delay time as communication quality information.

[0178] By doing so, the communication control device 100 (processing time estimation unit 113) uses the delay time based on the measured value of the PHY-high processing time as communication quality information (radio quality information) to estimate the processing time in the PHY-high layer, and from the estimated processing time, a lower (or in some cases, the lowest) CPU frequency setting or the like can be determined.

[0179] In the communication control device 100, the frequency control unit 114 determines the CPU frequency by adding a safety factor to the CPU frequency set by the processing time estimation unit.

[0180] By doing so, the communication control device 100 (frequency control unit 114) can lower the CPU frequency by adding a safety factor to ensure that processing is completed within the time slot. Also, the method of adding a safety factor can be realized without rewriting the learning table that associates the PHY-high processing time with the CPU frequency for each MCS Index or radio quality information.

[0181] In the communication control device 100, the processing time estimation unit 113 has a learning table that associates the PHY-high processing time with the CPU frequency for each MCS Index or radio quality information. The processing time estimation unit 113 refers to the learning table and determines the lowest frequency among the CPU frequencies in the learning table when the estimated processing time is less than or equal to the processing time of the time slot.

[0182] By doing so, the communication control device 100 (frequency control unit 114) can set the CPU frequency at which processing is completed just within the time slot by referring to the learning table.

[0183] In the communication control device 100, the processing time estimation unit 113 has a learning table that associates the PHY-high processing time for each MCS Index or radio wave quality information with the CPU frequency. The processing time estimation unit 113 refers to the learning table and performs feedback by rewriting the table values ​​in the learning table based on the measured PHY-high processing time.

[0184] In this way, the communication control device 100 (processing time estimation unit 113) can rewrite the table values ​​of the learning table with the latest communication status, etc., through feedback. Furthermore, it applies feedback to the PHY-high processing time estimation based on the timestamp information and whether or not a retransmission request was made, which was acquired by the PHY. As a result, the processing time estimation unit 113 can set the CPU frequency so that processing is completed as close to the time slot as possible with even greater accuracy.

[0185] The communication control device 100A (Figure 37) includes an accelerator 135 (Figure 37) that offloads specific processing of an application and performs calculation processing, and an accelerator driver 140A that controls the accelerator 135 (Figure 37) according to the accelerator settings set by the frequency control unit 114. The processing time estimation unit 113 determines the accelerator settings by adding a safety factor when setting the accelerator.

[0186] In this way, the communication control device 100A can reduce the power consumption of the server by constantly changing the accelerator settings to the optimal setting on a time slot basis.

[0187] The communication control device 100B (Figure 39) includes a CPU core 131 (Figure 39), an uncore 136 (Figure 39) which is a peripheral device other than the CPU core, and an uncore setting storage unit (uncore setting table 139) (Figure 39) which stores the uncore frequency relative to the CPU core frequency. The frequency control unit 114 (Figure 39) controls the uncore at an uncore frequency that does not cause a bottleneck, based on the setting information of the uncore setting storage unit.

[0188] In this way, the communication control device 100B can reduce the power consumption of the hardware equipped with the uncore 136 by constantly changing the optimal uncore frequency on a time slot basis.

[0189] A wireless access system (Figure 46: vRAN system 1) comprises a base station that processes wireless access signals and a communication control device 100 (Figure 1) that controls the CPU frequency of a CPU core located in the base station hardware, wherein the communication control device 100 includes a processing time estimation unit 113 that calculates an estimated processing time for each CPU frequency from communication quality information, and a frequency control unit 114 that lowers the CPU frequency within a range where the estimated processing time is less than or equal to the processing time of a time slot.

[0190] In this way, wireless access systems can reduce the power consumption of CPUs and accelerators while meeting the demands for high-speed processing, such as when configuring a vRAN system. In other words, wireless access systems can reduce server power consumption by constantly changing the optimal CPU frequency and accelerator settings on a time slot basis.

[0191] In each of the above embodiments, if FDD (Frequency Division Duplex) is used instead of TDD (Time Division Duplex), the timing of simultaneous processing in both UL / DL directions in the PHY layer increases, but the processing time estimation logic and frequency control method can be applied in the same way as with TDD.

[0192] Furthermore, among the processes described in each of the above embodiments, all or part of the processes described as being performed automatically can be performed manually, or all or part of the processes described as being performed manually can be performed automatically by known methods. In addition, the processing procedures, control procedures, specific names, and information including various data and parameters shown in the above documents and drawings can be changed at will unless otherwise specified. Furthermore, the components of each illustrated device are functionally conceptual and do not necessarily need to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown, and all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0193] Furthermore, each of the above configurations, functions, processing units, and processing means may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above configurations and functions may be implemented in software that allows the processor to interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) card, or an optical disc. [Explanation of Symbols]

[0194] 10 UE (Terminal) 20 RU 30 DU Servers (Base Stations) 33 vDU 100, 100A, 100B Communication Control Device 101 Communication Quality Information Acquisition Unit 110 Control Unit 111 MCS acquisition unit (communication quality information acquisition unit) 112 Radio wave condition acquisition unit (communication quality information acquisition unit) 113 Processing time estimation unit 114 Frequency Control Unit 115 MAC Schedule Analysis Department (Communication Quality Information Acquisition Department) 116. Delay Time Acquisition Unit (Communication Quality Information Acquisition Unit) 120 Signal Processing Unit 121 PHY section 122 MAC section 123 RLC Department 130, 130A, 130B Hardware (HW) 131 CPU Core 132, 135 Accelerator 133 Memory 134 NIC 136 Uncore 139 Uncore Configuration Table (Uncore Configuration Memory Unit) 140, 140A OS / Driver 141 Frequency Control Driver 142 Accelerator Driver 1000, 1000A, 1000B Wireless Access System< / vran>

Claims

1. A communication control device for processing wireless access signals, A communication quality information acquisition unit that acquires communication quality information, A processing time estimation unit calculates the estimated processing time for each CPU frequency from the acquired communication quality information, The system includes a frequency control unit that, when the estimated processing time is less than or equal to the processing time of the time slot, lowers the CPU frequency below the currently set CPU frequency. A communication control device characterized by the following:

2. The aforementioned communication quality information acquisition unit is an MCS (Modulation and Coding Scheme) acquisition unit that acquires the MCS Index of UL (UP Link) or DL ​​(Down Link) in the MAC time slot as the aforementioned communication quality information. The communication control device according to claim 1.

3. The aforementioned communication quality information acquisition unit is a radio wave condition acquisition unit that acquires UL (UP Link) or DL ​​(Down Link) radio wave quality information as the aforementioned communication quality information. The communication control device according to claim 1.

4. The aforementioned communication quality information acquisition unit is a MAC schedule analysis unit that acquires wireless resource allocation information, including MAC schedule information, as the aforementioned communication quality information. The communication control device according to claim 1.

5. The aforementioned communication quality information acquisition unit is a delay time acquisition unit that calculates the delay time from the measured value of the PHY-high processing time and acquires the said delay time as the communication quality information. The communication control device according to claim 1.

6. The frequency control unit determines the CPU frequency by adding a safety factor to the CPU frequency set by the processing time estimation unit. The communication control device according to claim 1.

7. The processing time estimation unit has a learning table that associates the PHY-high processing time for each MCS Index or radio wave quality information with the CPU frequency. The processing time estimation unit refers to the learning table and determines the lowest CPU frequency among the CPU frequencies in the learning table such that the estimated processing time is less than or equal to the processing time of the time slot. The communication control device according to claim 1.

8. The processing time estimation unit has a learning table that associates the PHY-high processing time for each MCS Index or radio wave quality information with the CPU frequency. The processing time estimation unit 113 refers to the learning table and performs feedback by rewriting the table values ​​in the learning table based on the measured PHY-high processing time. The communication control device according to claim 1.

9. An accelerator that offloads specific processing of an application to perform computation, The system includes an accelerator driver that controls the accelerator according to the accelerator settings set by the frequency control unit, The frequency control unit determines the accelerator setting by adding a safety factor when setting the accelerator. The communication control device according to claim 1.

10. CPU cores, The uncore is a peripheral device other than the CPU core, It includes an uncore setting storage unit that stores the uncore frequency relative to the CPU core frequency, The frequency control unit controls the uncore at an uncore frequency that does not become a bottleneck, based on the setting information of the uncore setting storage unit. The communication control device according to claim 1.

11. A wireless access system comprising a base station that processes wireless access signals, and a communication control device that controls the CPU frequency of a CPU core located in the base station hardware, The communication control device is A communication quality information acquisition unit that acquires communication quality information, A processing time estimation unit calculates the estimated processing time for each CPU frequency from communication quality information, The system includes a frequency control unit that lowers the CPU frequency below the currently set CPU frequency within a range where the estimated processing time is less than or equal to the processing time of the time slot. A wireless access system characterized by the following features.

12. A communication control method for a communication control device that processes wireless access signals, The communication control device is Steps to obtain communication quality information, The steps include: calculating the estimated processing time for each CPU frequency from the acquired communication quality information; The estimated processing time is less than or equal to the processing time of the time slot, and the CPU frequency is lowered to a lower CPU frequency than the currently set CPU frequency. A communication control method characterized by the following:

13. A program for causing a computer to function as a communication control device according to any one of claims 1 to 10.

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