Memory devices and their read operations

Abstract

In some aspects, a memory device includes an array of memory cells, word lines each coupled to a row of the memory cells, and peripheral circuitry coupled to the array of memory cells through the word lines and configured to read a selected row of the memory cells, the peripheral circuitry including a word line driver coupled to the selected row through the selected word line and coupled to unselected rows of the row of memory cells through unselected word lines of the word lines, the word line driver configured to apply a passing voltage to the unselected word lines and discharge the unselected word lines from the passing voltage to a first recovery voltage higher than a power supply voltage of the array of memory cells.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the benefit of priority of U.S. Provisional Application No. 63 / 436,433, filed on December 30, 2022, which is hereby incorporated by reference in its entirety.

[0002] This disclosure relates to memory devices and methods of operating them.

Background Art

[0003] Flash memory is a low - cost, high - density, non - volatile solid - state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations such as read, program (write), and erase can be performed by flash memory. In the case of NAND flash memory, the erase operation can be performed at the block level, and the program operation or read operation can be performed at the page level.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, a memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and peripheral circuitry coupled to the array of memory cells through the word lines and configured to read a selected row of the rows of the memory cells. The peripheral circuitry includes a word - line driver coupled to the selected row through a selected word line of the word lines and coupled to a non - selected row of the rows of the memory cells through a non - selected word line of the word lines, and the word - line driver is configured to apply a pass voltage to the non - selected word line and discharge the non - selected word line from the pass voltage to a first recovery voltage higher than the power - supply voltage of the array of memory cells.

[0005] In some implementations, the word line driver is further configured to apply a reading voltage to the selected word line and discharge the selected word line from the reading voltage to a second recovery voltage higher than the power supply voltage.

[0006] In some implementations, the second recovery voltage is lower than the first recovery voltage.

[0007] In some implementations, non-selected wordlines are located immediately next to selected wordlines.

[0008] In some implementations, the wordline driver is configured to start discharging selected and unselected wordlines simultaneously.

[0009] In some implementations, the peripheral circuitry further includes control logic, which is coupled to a word line driver and configured to set the duration for the word line driver to discharge a non-selected word line.

[0010] In some implementations, the peripheral circuitry further includes control logic, which is coupled to a word line driver and configured to set a first recovery voltage for the word line driver to discharge the unselected word line.

[0011] In some implementations, the memory device is a three-dimensional (3D) NAND memory device.

[0012] In another embodiment, a method for reading a memory device is provided. The memory device includes memory cells. A pass-through voltage is applied to an unselected word line coupled to an unselected row of the memory cell. The unselected word line is discharged from the pass-through voltage to a first recovery voltage higher than the power supply voltage of the memory cell.

[0013] In some implementations, a read voltage is applied to a selected word line coupled to a selected row of memory cells, and the selected word line is discharged from the read voltage to a second recovery voltage higher than the power supply voltage.

[0014] In some implementations, the second recovery voltage is lower than the first recovery voltage.

[0015] In some implementations, non-selected wordlines are located immediately next to selected wordlines.

[0016] In some implementations, discharging selected word lines and discharging unselected word lines are initiated simultaneously.

[0017] In some implementations, a duration is set to discharge non-selected wordlines.

[0018] In some implementations, a first recovery voltage is set to discharge the unselected word line.

[0019] In some implementations, the memory device is a 3D NAND memory device.

[0020] In yet another embodiment, the system includes a memory device configured to store data and a memory controller configured to be coupled to the memory device and to control the memory device. The memory device includes an array of memory cells, each of which includes a word line coupled to a row of memory cells, and peripheral circuits coupled to the array of memory cells through the word lines and configured to read selected rows of memory cells. The peripheral circuits include a word line driver coupled to the selected row through the selected word line of the word line and to the unselected row of the memory cell through the unselected word line of the word line, the word line driver being configured to apply a pass voltage to the unselected word line and discharge the unselected word line from the pass voltage to a first recovery voltage higher than the power supply voltage of the array of memory cells.

[0021] In some implementations, the word line driver is further configured to apply a reading voltage to the selected word line and discharge the selected word line from the reading voltage to a second recovery voltage higher than the power supply voltage.

[0022] In some implementations, the second recovery voltage is lower than the first recovery voltage.

[0023] In some implementations, non-selected wordlines are located immediately next to selected wordlines.

[0024] In another embodiment, the memory device includes an array of memory cells, each of which is coupled to a row of memory cells, a word line, and peripheral circuits coupled to the array of memory cells through the word lines and configured to read selected rows of memory cells. The peripheral circuits include a word line driver coupled to the selected row through the selected word line of the word line and to the unselected row of the memory cell through the unselected word line of the word line, the word line driver being configured to apply a first read voltage to the selected word line, and immediately thereafter to apply a second read voltage to the selected word line that is lower than the first read voltage, and to apply a pass voltage to the unselected word lines when the first read voltage is applied to the selected word line and when the second read voltage is applied to the selected word line.

[0025] In some implementations, non-selected wordlines are located immediately next to selected wordlines.

[0026] In another embodiment, a method for reading a memory device is provided. The memory device includes memory cells. A first read voltage is applied to a selected word line coupled to a selected row of memory cells. Immediately after applying the first read voltage, a second read voltage lower than the first read voltage is applied to the selected word line. When the first read voltage is applied to the selected word line, and when the second read voltage is applied to the selected word line, a pass voltage is applied to the unselected word lines.

[0027] In some implementations, the non - selected word lines are immediately adjacent to the selected word lines.

[0028] In another aspect, the system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes an array of memory cells, word lines respectively coupled to rows of the memory cells, and peripheral circuitry coupled to the array of memory cells through the word lines and configured to read a selected row of the rows of the memory cells. The peripheral circuitry includes a word line driver coupled to the selected row through the selected word line of the word lines and coupled to a non - selected row of the rows of the memory cells through the non - selected word line of the word lines. The word line driver is configured to apply a first read voltage to the selected word line and, immediately after applying the first read voltage, apply a second read voltage lower than the first read voltage to the selected word line. When applying the first read voltage to the selected word line and when applying the second read voltage to the selected word line, the word line driver is configured to apply a pass voltage to the non - selected word lines.

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to further explain the principles of the disclosure and to enable a person skilled in the art to make and use the disclosure.

Brief Description of the Drawings

[0030] [Figure 1] FIG. 1 is a schematic diagram of a memory device including peripheral circuitry according to some embodiments of the present disclosure. [Figure 2] FIG. 2 is a side - view cross - section of a memory cell array including a NAND memory string according to some embodiments of the present disclosure. [Figure 3] FIG. 3 is a block diagram of a memory device including a memory cell array and peripheral circuitry according to some embodiments of the present disclosure. [Figure 4]These are schematic perspective views of a three-dimensional (3D) NAND memory string according to some aspects of the present disclosure. [Figure 5] This is a timing diagram for a read operation that includes a recovery phase. [Figure 6] This is a timing diagram of a read operation having a shortened recovery phase according to some aspects of the present disclosure. [Figure 7] This is a timing diagram for a read operation that includes a recovery phase. [Figure 8] This is a timing diagram of a read operation having a shortened recovery phase according to some aspects of the present disclosure. [Figure 9] This is a timing diagram of a read operation without a recovery phase, according to some aspects of the present disclosure. [Figure 10] This is a flowchart of a method for reading a memory device according to some aspects of the present disclosure. [Figure 11] This is a flowchart of another method for reading a memory device according to some aspects of this disclosure. [Figure 12] This is a block diagram of a system having a memory device according to some aspects of the present disclosure. [Figure 13A] This is a diagram of a memory card having a memory device according to some aspects of the present disclosure. [Figure 13B] This is a diagram of a solid-state drive (SSD) having a memory device according to some aspects of the present disclosure. [Figure 14] This figure shows examples of the waveform of the word line voltage applied to the word line during a reading operation, according to some aspects of the present disclosure. [Modes for carrying out the invention]

[0031] This disclosure will be explained with reference to the attached drawings.

[0032] In general, terms may be understood, at least partially, from their usage in context. For example, the term “one or more” as used herein may be used, at least partially contextually, to express any feature, structure, or characteristic in a singular sense, or to express a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a,” “an,” or “the” may, in this case as well, at least partially contextually, be understood to convey either a singular or plural use. In addition, the term “based on” may be understood not necessarily to convey an exclusive set of factors, and instead, in this case as well, at least partially contextually, it may be permitted that the presence of additional factors is not necessarily explicitly expressed.

[0033] Memory devices such as NAND flash memory can store more than a single bit of information in each memory cell within multiple levels (also called states) to increase storage capacity and reduce the cost per bit. As the storage capacity of each memory cell increases, more distinct states are written within the same threshold voltage window, which inevitably worsens the reliability of the stored data. For example, during a read operation, charge may move between adjacent word lines, which can cause read interference and impair data retention, thereby degrading the reliability of the memory device.

[0034] To address one or more of the aforementioned problems, this disclosure introduces a solution that shortens and even eliminates the word line discharge / recovery phase at the end of a read operation. From a device reliability standpoint, residual voltage on the word lines after the read phase can be used to reduce and even prevent charge transfer (also known as charge loss) between adjacent word lines, thereby reducing read interference, making the threshold voltage distribution more stable, and expanding the read window. In the long term, the reduction in charge loss can also improve data retention in memory devices. Moreover, by shortening and even eliminating the recovery phase for read operations, the efficiency of read operations can also be improved.

[0035] Figure 1 shows a schematic circuit diagram of a memory device 100 including peripheral circuits according to several embodiments of the present disclosure. The memory device 100 may include a memory cell array 101 and peripheral circuits 102 coupled to the memory cell array 101. The memory cell array 101 may be a NAND flash memory cell array in which memory cells 106 are provided, each in the form of an array of NAND memory strings 108, each extending vertically over a substrate (not shown). In some implementations, each NAND memory string 108 includes a plurality of memory cells 106 coupled in series and stacked vertically. Each memory cell 106 may hold a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped within the region of the memory cell 106. Each memory cell 106 may be either a floating-gate type memory cell including a floating-gate transistor, or a charge-trap type memory cell including a charge-trap transistor.

[0036] In some implementations, each memory cell 106 is a single-level cell (SLC) having two possible memory states (levels) and therefore capable of storing 1 bit of data. For example, the first memory state "0" can correspond to a first range of threshold voltage, and the second memory state "1" can correspond to a second range of threshold voltage. In some implementations, each memory cell 106 is an xLC capable of storing more than one bit of data by having more than four memory states (levels). For example, an xLC may store 2 bits per cell (MLC), 3 bits per cell (TLC), or 4 bits per cell (QLC). Each xLC has a possible nominal storage value (i.e., 2 bits of N-bit data). N It can be programmed to exhibit a range (corresponding to individual elements). For example, an MLC can be programmed to exhibit one of three possible programming levels from an erased state by writing one of three possible nominal memory values ​​to a cell. A fourth nominal memory value may be used for the erased state.

[0037] As shown in Figure 1, each NAND memory string 108 may also include a source select gate (SSG) transistor 110 at its source end and a drain select gate (DSG) transistor 112 at its drain end. The SSG transistor 110 and DSG transistor 112 may be configured to activate selected NAND memory strings 108 (array columns) during read and program operations. In some implementations, the sources of NAND memory strings 108 within the same block 104 are connected through the same source line (SL) 114, for example, a common SL. In other words, all NAND memory strings 108 within the same block 104 have an array common source (ACS), according to some implementations. The drain of each NAND memory string 108 is connected, according to some implementations, to a respective bit line 116 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 108 is configured to be selected or deselected by applying a selection voltage or deselection voltage to the gate of each DSG transistor 112 through one or more DSG lines 113, and / or by applying a selection voltage or deselection voltage to the gate of each SSG transistor 110 through one or more SSG lines 115.

[0038] As shown in Figure 1, a NAND memory string 108 can be organized into multiple blocks 104, each of which may have a common source line 114, for example, coupled to an ACS. In some implementations, each block 104 is a basic data unit for erase operations, i.e., all memory cells 106 on the same block 104 are erased simultaneously. To erase the memory cells 106 in a selected block 104, the source lines 114 coupled to the selected block 104 and to non-selected blocks 104 in the same plane as the selected block 104 may be biased with an erase voltage (Vers), such as a positive high bias voltage (e.g., 20V or higher). Memory cells 106 of adjacent NAND memory strings 108 may be coupled through word lines 118 that select which rows of the memory cells 106 are acted upon by read and program operations. In some implementations, each word line 118 is coupled to a page 120 of the memory cell 106, which is a basic data unit for read and program operations. The size of one page 120 in bits can relate to the number of NAND memory strings 108 joined by word lines 118 within one block 104. Each word line 118 may include multiple control gates (gate electrodes) in each memory cell 106 within each page 120, and gate lines that join the control gates.

[0039] As shown in Figure 1, the memory cell array 101 can include an array of memory cells 106 in multiple rows and multiple columns within each block 104. According to some implementations, one row of memory cell 106 corresponds to one or more pages 120, and one column of memory cell corresponds to one NAND memory string 108. Multiple rows of memory cell 106 may each be coupled to a word line 118, and multiple columns of memory cell 106 may each be coupled to a bit line 116. Peripheral circuits 102 may be coupled to the memory cell array 101 through the bit line 116 and the word line 118.

[0040] Figure 2 shows a cross-sectional side view of a memory cell array 101 including a NAND memory string 108 according to several embodiments of the present disclosure. As shown in Figure 2, the NAND memory string 108 can extend vertically over the substrate 202 through the memory stack 204. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0041] The memory stack 204 may include interleaved gate conductive layers 206 and intergate dielectric layers 208. The number of pairs of gate conductive layers 206 and intergate dielectric layers 208 in the memory stack 204 can determine the number of memory cells 106 in the memory cell array 101. The gate conductive layers 206 may include, but are not limited to, conductive materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate conductive layer 206 includes a metal layer such as a tungsten layer. In some implementations, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, the gate of a DSG transistor 112, or the gate of an SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between the DSG line 113 and the SSG line 115.

[0042] As shown in Figure 2, the NAND memory string 108 includes a channel structure that extends vertically through the memory stack 204. In some implementations, the channel structure includes channel holes filled with semiconductor material (e.g., as a semiconductor channel) and dielectric material (e.g., as a memory film). It is understood that additional components of the memory cell array 101 may be formed, including, but are not limited to, gate line slits / source contacts, local contacts, interconnection layers, etc., although these are not shown in Figure 2.

[0043] Referring again to Figure 1, the peripheral circuit 102 may be coupled to the memory cell array 101 through bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 may include any suitable analog, digital, and mixed-signal circuits to facilitate the operation of the memory cell array 101 by applying and sensing voltage and / or current signals to and from each selected memory cell 106 through bit lines 116, word lines 118, source lines 114, SSG lines 115, and DSG lines 113. The peripheral circuit 102 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 3 shows some exemplary peripheral circuits including a page buffer / sense amplifier 304, a column decoder / bit line driver 306, a row decoder / word line driver 308, a voltage generator 310, control logic 312, registers 314, an interface (I / F) 316, and a data bus 318. In some examples, it is understood that additional peripheral circuits not shown in Figure 3 may also be included.

[0044] The page buffer / sense amplifier 304 may be configured to sense (read) and program (write) data to and from the memory cell array 101 according to control signals from the control logic 312. In one example, the page buffer / sense amplifier 304 may store one page of program data (write data, referred to herein as a “data page”) to be programmed into one page 120 of the memory cell array 101. In another example, the page buffer / sense amplifier 304 may verify the programmed selected memory cell 106 in each program / verify loop in the program operation to ensure that data is correctly programmed into the memory cell 106 coupled to the selected word line 118. In yet another example, the page buffer / sense amplifier 304 may also sense a low-power signal from the bit line 116 representing the data bits stored in the memory cell 106 and amplify small voltage fluctuations to a recognizable logic level in the read operation.

[0045] The column decoder / bit line driver 306 may be controlled by control logic 312 and configured to select one or more NAND memory strings 108 by applying bit line voltages generated from a voltage generator 310. The row decoder / word line driver 308 may be controlled by control logic 312 and a select / deselect block 104 of the memory cell array 101 and configured to select / deselect the word line 118 of block 104. The row decoder / word line driver 308 may be further configured to drive the word line 118 using the word line voltages generated from the voltage generator 310. In some implementations, the row decoder / word line driver 308 can also select / deselect and drive the SSG line 115 and DSG line 113 as well. The voltage generator 310 may be controlled by control logic 312 and configured to generate word line voltages (e.g., read voltage, program voltage, channel pass voltage, local voltage, verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 101. As described below in detail and in accordance with the scope of this disclosure, in a read operation, after the read phase, the row decoder / word line driver 308 can discharge the word line voltage to a relatively high recovery voltage, i.e., higher than the power supply voltage (Vdd), or even skip discharging the word line voltage, which can reduce or suppress charge loss between adjacent word lines, thereby improving device reliability and read efficiency.

[0046] The control logic 312 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. Registers 314 may be coupled to the control logic 312 and may include a status register, a command register, and an address register for storing status information, command operation codes (opcodes), and command addresses for controlling the operation of each peripheral circuit. Interface 316 may be coupled to the control logic 312 and can function as a control buffer for buffering control commands received from a memory controller (not shown) and / or a host (not shown) and relaying them to the control logic 312, and for buffering status information received from the control logic 312 and relaying it to the memory controller and / or host. Interface 316 may also be coupled to the column decoder / bit line driver 306 via the data bus 318 and can function as a data input / output (I / O) interface and data buffer for buffering and relaying data to and from the memory cell array 101.

[0047] Figure 4 shows a schematic perspective view of a 3D NAND memory string according to several aspects of the present disclosure. Figure 4 shows an example of an array of 3D NAND memory strings (e.g., 108 in Figure 1) in a block (e.g., 104 in Figure 1). As shown in Figure 4, from top to bottom, each 3D NAND memory string is coupled to several lines in different rows, e.g., a DSG line (DSG, e.g., 113 in Figure 1), a dummy DSG line (DMY), a word line (WL, e.g., 118 in Figure 1) in the upper deck of the memory stack, an intermediate deck dummy word line (IDP-DMY), a word line (WL, e.g., 118 in Figure 1) in the lower deck of the memory stack, a dummy SSG line (DMY), an SSG line (SSG, e.g., 115 in Figure 1), and an array common source line (ACS, e.g., 114 in Figure 1). Read operations can be performed between memory cells in different rows, either from bottom to top (i.e., from ACS to DSG) or vice versa (for example, from DSG to ACS).

[0048] Figure 5 shows a timing diagram of a read operation with a recovery phase. As shown in Figure 5, the read operation includes a pre-pulse phase, one or more read phases (e.g., reading a first level, reading the next level, etc.), and a recovery phase. During the pre-pulse phase, the peripheral circuitry 102 is configured to control the selected NAND memory string to be ready for reading. For example, the word line driver 308 is configured to charge the selected DSG line (Sel DSG) and SSG line (SSG) from the power supply voltage (Vss) to a selection voltage (Vsel) that can turn on the DSG and SSG transistors of the selected NAND memory string coupled to the selected DSG line and SSG line, respectively. The word line driver 308 is also configured to charge / discharge the selected word line n (Sel WLn) from the power supply voltage (Vdd) to a first read voltage (Vr1). The selected word line n is coupled to a row of memory cells 106 (selected memory cells) to be read during the read operation. The word line driver 308 is also configured to charge the unselected word lines (WLn-1, WLn-2 and below, WLn+1, and WLn+2 and above) from the power supply voltage (Vdd) to a pass voltage (Vp) that can turn on the memory cells 106 (unselected memory cells) coupled to the unselected word lines. That is, at the end of the prepulse phase, in the selected NAND memory string, the DSG transistors, SSG transistors, and unselected memory cells are all turned on by the peripheral circuit 102.

[0049] During each read phase, the peripheral circuit 102 is configured to keep the DSG transistors, SSG transistors, and unselected memory cells in the selected NAND memory string turned on and to apply the respective read voltages to the selected memory cells in the selected NAND memory string. For example, the word line driver 308 is configured to apply a selection voltage to the selected DSG line and SSG line and to apply a pass voltage to the unselected word line when reading the first and subsequent levels in the first and second read phases. The word line driver 308 is further configured to apply a first read voltage to the selected word line n when reading the first level in the first read phase, and then apply a second read voltage (Vr2) to the selected word line n when reading the subsequent level in the second read phase.

[0050] During the recovery phase, the peripheral circuitry 102 is configured to control the selected NAND memory string so that it recovers from reading and is ready for the next operation. For example, the word line driver 308 is configured to discharge the selected DSG line and SSG line by returning from the selection voltage to the supply voltage (Vss) to turn off the DSG transistor and SSG transistor, respectively. The word line driver 308 is also configured to discharge the selected word line n by returning from the last read voltage (e.g., the second read voltage in Figure 5) to the supply voltage (Vdd). The word line driver 308 is further configured to discharge the unselected word line by returning from the pass voltage to the supply voltage (Vdd). As shown by the dotted line in Figure 5, it is understood that during the recovery phase, the voltage on the selected word line n may be coupled to be the same as the voltage on the unselected word lines (WLn+1 and WLn-1) immediately adjacent to the selected word line n. The same phenomenon may also be observed during the prepulse phase.

[0051] In any case, as shown in Figure 5, at the end of the recovery phase, all word line voltages are recovered back to the power supply voltage (Vdd). However, such relatively low residual voltages (e.g., Vdd) at the end of a read operation may not be sufficient to prevent charge transfer between adjacent word lines, which can affect the short-term and long-term reliability of the memory device. Discharging the word lines back to the power supply voltage also takes a relatively long time, thereby extending the duration of the read operation.

[0052] In accordance with the scope of this disclosure, read operations with or without a shortened recovery phase, performed using the memory devices disclosed herein (e.g., memory device 100), are described in detail below. It is understood that the methods disclosed herein are not limited to read operations and may also be similarly applied to verification processes during program operations.

[0053] Figure 6 shows a timing diagram of a read operation with a shortened recovery phase according to several aspects of the present disclosure. As shown in Figure 6, the read operation includes a pre-pulse phase, one or more read phases (e.g., a first level read, a next level read, etc.), and a shortened recovery phase compared to the recovery phase in Figure 5. During the pre-pulse phase, the peripheral circuit 102 is configured to control the selected NAND memory string to be ready for reading. For example, the word line driver 308 may be configured to charge the selected DSG line (Sel DSG) and SSG line (SSG) from a supply voltage (Vss) to a selection voltage (Vsel) that can turn on the DSG and SSG transistors of the selected NAND memory string coupled to the selected DSG line and SSG line, respectively. In some examples, it will be understood that the selection voltage on the selected DSG line may differ from the selection voltage on the SSG line. The word line driver 308 may also be configured to charge / discharge the selected word line n (Sel WLn) from the power supply voltage (Vdd) to a first read voltage (Vr1). The selected word line n may be coupled to the row of memory cell 106 (selected memory cell) to be read during the read operation. Depending on whether the first read voltage is higher or lower than the power supply voltage, the word line driver 308 may either charge the selected word line n or discharge it during the pre-pulse phase. As shown by the dotted line in Figure 6, it is understood that during the pre-pulse phase, the voltage on the selected word line n may be coupled to be the same as the voltage on the unselected word lines (WLn+1 and WLn-1) immediately adjacent to the selected word line n. The word line driver 308 may be further configured to charge the unselected word lines (WLn-1, WLn-2 and below, WLn+1, and WLn+2 and above) from the power supply voltage (Vdd) to a pass voltage (Vp) that can turn on the memory cells 106 (unselected memory cells) coupled to the unselected word lines.In some cases, it is understood that the pass-through voltage on the unselected word lines (WLn+1 and WLn-1) immediately adjacent to the selected word line n may differ from the pass-through voltage on other unselected word lines (WLn-2 and below, and WLn+2 and above) (for example, higher than that shown in Figure 6). In any case, at the end of the pre-pulse phase, the DSG transistors, SSG transistors, and unselected memory cells in the selected NAND memory string may all be turned on by the peripheral circuit 102.

[0054] During each read phase, the peripheral circuit 102 may be configured to keep the DSG transistors, SSG transistors, and unselected memory cells in the selected NAND memory string turned on and to apply the respective read voltages to the selected memory cells in the selected NAND memory string. For example, the word line driver 308 may be configured to apply a selection voltage to the selected DSG line and SSG line and to apply a pass voltage to the unselected word line when reading the first and subsequent levels in the first and second read phases. The word line driver 308 may be further configured to apply a first read voltage to the selected word line n when reading the first level in the first read phase, and then apply a second read voltage (Vr2) to the selected word line n when reading the subsequent level in the second read phase.

[0055] During the recovery phase, peripheral circuitry 102 may be configured to control the selected NAND memory string to recover from reading and prepare for the next operation. For example, the word line driver 308 may be configured to discharge the selected DSG line and SSG line by returning from the selection voltage to the supply voltage (Vss) to turn off the DSG and SSG transistors, respectively. The word line driver 308 may also be configured to discharge the unselected word line from the pass voltage to a recovery voltage (Vrec) higher than the supply voltage (Vdd). Similarly, the word line driver 308 may be further configured to discharge the selected word line n from the last read voltage (e.g., the second read voltage in Figure 6) to a recovery voltage (Vrec) higher than the supply voltage (Vdd). That is, at the end of the recovery phase in Figure 6, the word line voltage is not recovered back to the supply voltage, but instead, according to some implementations, it is recovered to a recovery voltage higher than the supply voltage. By increasing the residual word line voltage from the power supply voltage at the end of the reading operation, charge transfer between adjacent word lines can be reduced or suppressed, thereby improving short-term and long-term reliability. Furthermore, since the word line voltage is discharged to a voltage higher than the power supply voltage, the duration of the recovery phase can be shortened, and reading efficiency can also be improved.

[0056] Recovery voltages on different word lines may differ. In some implementations, the word line driver 308 is configured to discharge the unselected word lines (WLn-1 and WLn+1) immediately adjacent to the selected word line n from the pass voltage to a first recovery voltage, and to discharge the selected word line n (Sel WLn) from the last reading voltage to a second recovery voltage different from the first recovery voltage. In some implementations, the second recovery voltage is lower than the first recovery voltage because the reading voltage is lower than the pass voltage, and the word line driver 308 is configured to start discharging the selected word line n and the unselected word lines immediately adjacent to it simultaneously. As shown by the dotted line in Figure 6, it is understood that during the recovery phase, the voltage on the selected word line n may be coupled to be the same as the voltage on the unselected word lines immediately adjacent to the selected word line n.

[0057] Various techniques can be applied by the peripheral circuitry 102 to discharge the word line voltage to a recovery voltage higher than the power supply voltage. In some implementations, the control logic 312 is configured to set the duration for the word line driver 308 to discharge the selected word line n and the unselected word line so that the word line voltage does not discharge to the power supply voltage. For example, the duration of the recovery phase (shortened recovery phase) in Figure 6 may be set to be shorter than the duration of the recovery phase in Figure 5 so that there is not enough time for the word line voltage to drop to the power supply voltage. In some implementations, the control logic 312 is configured to set the recovery voltage (e.g., first and second recovery voltages) for the word line driver 308 to discharge the selected word line n and the unselected word line. For example, the recovery voltage in Figure 6 may be set to be higher than the power supply voltage so that the word line driver 308 stops discharging the word line voltage when the word line voltage reaches the recovery voltage before the power supply voltage.

[0058] Figure 14 shows examples of waveforms 1402, 1404, and 1406 of word line voltages applied to a word line during a read operation, according to several aspects of the present disclosure. Waveforms 1402, 1404, and 1406 may correspond to voltage line voltages applied to the same word line (e.g., WL31) when a read operation is performed on different rows (i.e., a read voltage is applied to different word lines). For example, in the case of waveform 1402, WL31 may be a selected word line and a read operation may be performed on rows of memory cells coupled to WL31; in the case of waveform 1404, WL31 may be a non-selected word line and a read operation may be performed on rows of memory cells coupled to WL1; and in the case of waveform 1406, WL31 may be a non-selected word line and a read operation may be performed on rows of memory cells coupled to WL45. In waveform 1402, during the recovery phase, the selected WL31 may be discharged from the reading voltage (Vr) to a recovery voltage (Vrec) higher than the supply voltage (Vdd). In each of waveforms 1404 or 1406, during the recovery phase, the unselected WL31 may be discharged from the pass voltage (Vp) to a recovery voltage (Vrec) higher than the supply voltage (Vdd).

[0059] Figure 10 shows a flowchart of method 1000 for reading a memory device according to several aspects of the present disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. Method 1000 may be implemented by peripheral circuits 102, such as a word line driver 308 and control logic 312. It is understood that the operations shown in method 1000 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than shown in Figure 10. Method 1000 in Figure 10 will be described with reference to the timing diagram in Figure 8.

[0060] Referring to Figure 10, a reading voltage is applied to the selected word line at 1002, and a pass voltage is applied to the unselected word line at 1004. In some implementations, the unselected word line is located immediately next to the selected word line. For example, in Figure 8, reading voltages corresponding to levels 1 (L1) and 5 (L5) may be applied to the selected word line (WL2) by the word line driver 308 between T2 and T3 (reading phase), and simultaneously between T2 and T3, a pass voltage higher than the reading voltage may be applied to each of the unselected word lines (WL1 and WL3) located immediately next to the selected word line.

[0061] Referring to Figure 10, at 1006, the unselected word line is discharged from the pass voltage to a first recovery voltage lower than the power supply voltage of the memory device, and at 1008, the selected word line is discharged from the read voltage to a second recovery voltage lower than the power supply voltage of the memory device. In some implementations, the second recovery voltage is lower than the first recovery voltage. In some implementations, the discharge of the selected and unselected word lines begins simultaneously. In some implementations, a duration is set for discharging the unselected word line. In some implementations, a first recovery voltage is set for discharging the unselected word line.

[0062] For example, in Figure 8, the unselected word lines (WL1 and WL3) may be discharged by the word line driver 308 from the pass voltage at T3 to the first recovery voltage at T4, and the selected word line (WL2) may be discharged by the word line driver 308 from the reading voltage at level 5 (L5) at T3 to the second recovery voltage at T4. In contrast, in Figure 7, the unselected word lines (WL1 and WL3) may be discharged by the word line driver 308 from the pass voltage at T3 to the supply voltage (e.g., Vdd) at T4, and the selected word line (WL2) may likewise be discharged by the word line driver 308 from the reading voltage at level 5 (L5) at T3 to the supply voltage at T4. Comparing the examples in Figure 7 and Figure 8, the first and second recovery voltages in Figure 8 are higher than the supply voltage in Figure 7, and the time between T3 and T4 (e.g., the recovery phase) is shorter in Figure 8 than in Figure 7. As shown in Figures 7 and 8, it is understood that between T3 and T4, the voltage on the selected word line (WL2) may be coupled to become the same as the voltage on the unselected word lines (WL1 and WL3) before discharge. In one example, the control logic 312 may set the time between T3 and T4 such that T4 in Figure 8 appears before T4 in Figure 7, forming a shortened recovery phase between T3 and T4 in Figure 8 compared to the recovery phase between T3 and T4 in Figure 7. In another example, the control logic 312 may set a first recovery voltage and / or a second recovery voltage such that the discharge of the word line voltage stops when the recovery voltage is reached and before the power supply voltage is reached.

[0063] Figures 7 and 8 show an example where the memory cells of a memory device are TLC, which can be programmed to eight levels with three pages of data. Therefore, in some implementations, three read operations are performed sequentially to read at different levels (for example, L1 and L5 in the first read operation, L2, L4, and L6 in the second read operation, and L3 and L7 in the third operation, as shown in Figures 7 and 8). However, as shown in Figure 8, the same read operation scheme with a shortened recovery phase (for example, between T3 and T4) may be applied to each of the three read operations. For example, as shown in Figure 8, after the end of the first read operation at T4, the second operation begins between T4 and T5 with a pre-pulse phase, followed by a read phase between T5 and T6, and a shortened recovery phase between T7 and T8. It is also understood that the same read operation scheme with a shortened recovery phase may be applied to any other type of memory cell, such as QLC.

[0064] According to some aspects of this disclosure, the recovery phase can be completely eliminated to further reduce the read operation duration and increase read efficiency. For example, Figure 11 shows a flowchart of method 1100 for reading a memory device according to some aspects of this disclosure. The memory device may be any suitable memory device disclosed herein, such as memory device 100. Method 1100 may be implemented by peripheral circuits 102, such as a word line driver 308 and control logic 312. It is understood that the operations shown in method 1100 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Furthermore, some of the operations may be performed simultaneously or in a different order than shown in Figure 11. Method 1100 in Figure 11 will be described with reference to the timing diagram in Figure 9.

[0065] Referring to Figure 11, at 1102, a first reading voltage is applied to the selected word line. At 1104, immediately after applying the first reading voltage, a second reading voltage lower than the first reading voltage is applied to the selected word line. At 1106, when the first reading voltage is applied to the selected word line and the second reading voltage is also applied to the selected word line, a pass voltage is applied to the unselected word line. In some implementations, the unselected word line is located immediately next to the selected word line. For example, in Figure 9, a first set of reading voltages corresponding to levels 1 (L1) and 5 (L5) may be applied to the selected word line (WL2) by the word line driver 308 between T2 and T3 (reading phase) in the first reading operation. Immediately following the read phase of a first read operation that does not have any recovery phase, a second read operation may be initiated to discharge the word line voltage on the selected word line (WL2) from the last read voltage (L5) of the first set of read voltages at T3 to a read voltage corresponding to level 2 (L2) that is lower than the last read voltage (L5) at T4. A second set of read voltages corresponding to levels 2 (L2), 4 (L4), and 6 (L6) may be applied to the selected word line (WL2) by the word line driver 308 between T4 and T5 (read phase) in the second read operation. Similarly, immediately after the reading phase of a second reading operation that does not have any recovery phase, a third reading operation may be initiated to discharge the word line voltage on the selected word line (WL2) from the last reading voltage (L6) of the second set of reading voltages at T5 to a reading voltage corresponding to level 3 (L3) that is lower than the last reading voltage (L6) at T6. A third set of reading voltages corresponding to levels 3 (L3) and 7 (L7) may be applied to the selected word line (WL2) by the word line driver 308 between T6 and T7 (reading phase) in the third reading operation.On the other hand, when the first, second, and third sets of reading voltages are applied to the selected word line (WL2) between T2 and T8, a pass voltage higher than the reading voltage may be applied to each of the unselected word lines (WL1 and WL3) immediately adjacent to the selected word line. That is, the word line voltages on the unselected word lines (WL1 and WL3) immediately adjacent to the selected word line may be maintained at the pass voltage without discharge during the reading operation.

[0066] Figure 9 shows an example where the memory cell of a memory device is a TLC that can be programmed to eight levels with three pages of data. Therefore, in some implementations, three read operations are performed sequentially to read at different levels (for example, L1 and L5 in the first read operation, L2, L4, and L6 in the second read operation, and L3 and L7 in the third operation, as shown in Figure 9). Compared to the example in Figure 7, the recovery phase and pre-pulse phase are removed from the read operation. It is understood that the same read operation scheme without a recovery phase may be applied to any other type of memory cell, such as QLC.

[0067] Figure 12 shows a block diagram of a system 1200 having a memory device according to several aspects of the present disclosure. System 1200 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in Figure 12, system 1200 may include a memory system 1202 having a host 1208, and one or more memory devices 100 (shown in Figure 1) and a memory controller 1206. The host 1208 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host 1208 may be configured to send or receive data to and from the memory device 100.

[0068] The memory device 100 may be any memory device disclosed in this disclosure. The memory controller 1206, according to several implementations, is coupled to the memory device 100 and the host 1208 and configured to control the memory device 100. The memory controller 1206 can manage the data stored in the memory device 100 and communicate with the host 1208. In some implementations, the memory controller 1206 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, CompactFlash® (CF) cards, Universal Serial Bus (USB) flash drives, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 1206 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and for enterprise storage arrays. The memory controller 1206 may be configured to control the operation of the memory device 100, such as read operations, erase operations, and program operations. The memory controller 1206 may also be configured to manage various functions relating to data stored in or to be stored in the memory device 100, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some implementations, the memory controller 1206 may be further configured to handle error correction codes (ECC) relating to data read from or written to the memory device 100. Any other preferred functions, such as formatting the memory device 100, may also be performed by the memory controller 1206. The memory controller 1206 may communicate with an external device (e.g., host 1208) according to a specific communication protocol.For example, the memory controller 1206 may communicate with an external device through at least one of various interface protocols, such as the USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Expansion Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0069] The memory controller 1206 and one or more memory devices 100 can be integrated into various types of storage devices, for example, included in the same package such as a Universal Flash Storage (UFS) package or an eMMC package. In other words, the memory system 1202 can be implemented and packaged in different types of final electronic products. In one example, as shown in Figure 13A, the memory controller 1206 and a single memory device 100 may be integrated into a memory card 1302. The memory card 1302 may include PC cards (PCMCIA, International Association for Personal Computer Memory Cards), CF cards, SmartMedia (SM) cards, Memory Sticks, Multimedia Cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1302 may further include a memory card connector 1304 that connects the memory card 1302 to a host (for example, the host 1208 in Figure 12). In another example, as shown in Figure 13B, a memory controller 1206 and multiple memory devices 100 may be integrated into the SSD 1306. The SSD 1306 may further include an SSD connector 1308 that connects the SSD 1306 to a host (for example, the host 1208 in Figure 12). In some implementations, the storage capacity and / or operating speed of the SSD 1306 is greater than that of the memory card 1302.

[0070] The above descriptions of specific implementations may be readily modified and / or adapted for various applications. Such adaptations and modifications shall therefore be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance provided herein.

[0071] The breadth and scope of this disclosure should not be limited by any of the exemplary implementations described above, but should be defined solely by the following claims and their equivalents.

[0072] While specific configurations and arrangements are described, it should be understood that this is done for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure may also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, modified, and rearranged in a manner consistent with the scope of this disclosure. [Explanation of symbols]

[0073] 100 memory devices 101 memory cell array 102 Peripheral Circuits 104 blocks 106 memory cells 108 NAND memory string 110 Source Select Gate (SSG) Transistor 112 Drain-Selected Gate (DSG) Transistor 113 DSG Line 114 Source Line (SL) 115 SSG Line 116-bit line 118 Wordlines 120 pages 202 circuit boards 204 memory stack 206 Gate conductive layer 208 Intergate dielectric layer 304 Page Buffer / Sense Amplifier 306-column decoder / bitline driver 308-line decoder / wordline driver 310 Voltage Generator 312 Control Logic 314 registers 316 Interface (I / F) 318 Data Bus 502 Program / Verify Cycle 504 Program Cycle 506 Verify cycle 1004 counter 1006 Latch 1008 Program / Verify Controller 1010 VFC Controller 1012 VFC standard 1200 System 1202 memory system 1206 Memory Controller 1208 Hosts 1302 Memory Card 1304 Memory card connector 1306 SSD 1308 SSD connector 1402 Word line voltage waveform 1404 Word line voltage waveform 1406 Word line voltage waveform

Claims

1. A memory device, A memory cell array and Each of the following is a word line coupled to the row of the memory cell, A peripheral circuit is connected to the array of memory cells through the word line and configured to read a selected row of the memory cells, wherein the peripheral circuit The word line driver comprises a word line driver which is connected to the selected row of the word line through the selected word line of the word line and connected to the unselected row of the memory cell through the unselected word line of the word line, and the word line driver is A pass voltage is applied to the aforementioned unselected word line, The unselected word line is configured to discharge from the pass voltage to a first recovery voltage that is higher than the power supply voltage of the memory cell array. Memory device.

2. The aforementioned word line driver, A reading voltage is applied to the selected word line. The selected word line is further configured to discharge from the reading voltage to a second recovery voltage higher than the power supply voltage. The memory device according to claim 1.

3. The memory device according to claim 2, wherein the second recovery voltage is lower than the first recovery voltage.

4. The memory device according to claim 2, wherein the non-selected word line is immediately adjacent to the selected word line.

5. The memory device according to claim 4, wherein the word line driver is configured to simultaneously initiate the discharge of the selected word line and the unselected word line.

6. The memory device according to claim 1, further comprising control logic, wherein the peripheral circuit is a control logic coupled to the word line driver and configured to set a duration for the word line driver to discharge the unselected word line.

7. The memory device according to claim 1, further comprising control logic, wherein the peripheral circuit is a control logic coupled to the word line driver and configured to set the first recovery voltage for the word line driver to discharge the unselected word line.

8. The memory device according to claim 1, wherein the memory device is a three-dimensional (3D) NAND memory device.

9. A method for reading a memory device having memory cells, The steps include applying a pass voltage to an unselected word line coupled to an unselected row of the memory cell, The steps include discharging the unselected word line from the pass voltage to a first recovery voltage higher than the power supply voltage of the memory cell, A method that includes this.

10. The steps include applying a read voltage to the selected word line coupled to the selected row of the memory cell, The steps include: discharging the selected word line from the reading voltage to a second recovery voltage higher than the power supply voltage; The method according to claim 9, further comprising:

11. The method according to claim 10, wherein the second recovery voltage is lower than the first recovery voltage.

12. The method according to claim 10, wherein the non-selected word line is immediately adjacent to the selected word line.

13. The method according to claim 12, wherein the step of discharging the selected word line and the step of discharging the unselected word line are started simultaneously.

14. The method according to claim 9, further comprising the step of setting a duration for discharging the non-selected word line.

15. The method according to claim 9, further comprising the step of setting the first recovery voltage for discharging the unselected word line.

16. The method according to claim 9, wherein the memory device is a three-dimensional (3D) NAND memory device.

17. A memory device configured to store data, A memory cell array and Each of the following is a word line coupled to the row of the memory cell, A peripheral circuit is connected to the array of memory cells through the word line and configured to read a selected row of the memory cells, wherein the peripheral circuit The word line driver comprises a word line driver which is connected to the selected row of the word line through the selected word line of the word line and connected to the unselected row of the memory cell through the unselected word line of the word line, and the word line driver is A pass voltage is applied to the aforementioned unselected word line, A memory device configured to discharge the unselected word line from the pass voltage to a first recovery voltage higher than the power supply voltage of the memory cell array, and A memory controller configured to be coupled to the memory device and to control the memory device. A system equipped with these features.

18. The aforementioned word line driver, A reading voltage is applied to the selected word line. The selected word line is further configured to discharge from the reading voltage to a second recovery voltage higher than the power supply voltage. The system according to claim 17.

19. The system according to claim 18, wherein the second recovery voltage is lower than the first recovery voltage.

20. The system according to claim 18, wherein the non-selected word line is immediately adjacent to the selected word line.

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