Arithmetic processing unit and arithmetic processing method

Abstract

To reduce a circuit scale of a conflict determination unit that determines a conflict between an address included in a memory access instruction and an address held in a queue that holds the memory access instruction.SOLUTION: An arithmetic processor includes: a queue configured to hold a memory access instruction including one or more addresses; a contracted address generation unit configured to generate a contracted address by contracting bits of multiple addresses in a case where the memory access instruction includes the multiple addresses; a conflict determination unit configured to determine a conflict between the contracted address and the address held in the queue; and an access control unit configured to control processes of the memory access instruction held in the queue, based on a determination result of the conflict detection unit.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an arithmetic processing unit and an arithmetic processing method.

Background Art

[0002] In an arithmetic processing unit having a SIMD (Single Instruction Multiple Data) arithmetic function, the processing performance is improved by executing the arithmetic operations of a plurality of data in parallel. For example, a plurality of data used for the arithmetic operations of a plurality of data are read out in parallel from a memory using a vector load instruction. That is, an arithmetic processing unit having a SIMD arithmetic function has an architecture that improves data transfer efficiency.

[0003] For example, in this type of arithmetic processing unit, a method of managing address collision is known by executing a check instruction for determining whether there is a memory address in an address hazard state when executing a vector operation (see, for example, Patent Document 1). Further, in the execution of a vector gather instruction, a method is known in which the number of overlapping addresses in one line is obtained to integrate requests, and the integrated value of the number of overlapping addresses between a plurality of lines is notified to a scalar arithmetic unit (see, for example, Patent Document 2). Furthermore, when detecting an overlap between the address range of a vector scatter instruction with an area designation and the address of a subsequent memory access instruction, a method of holding the subsequent memory access instruction is known (see, for example, Patent Document 3).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0005] Incidentally, an arithmetic processing unit that executes instructions out of order has a mechanism to commit instructions in order. When memory access instructions are committed in order, a load-store queue may be provided to hold the addresses included in the memory access instructions. A conflict is then determined between the addresses held in the load-store queue and the addresses included in subsequent or preceding memory access instructions, and based on the determination result, it is decided whether or not to commit the memory access instructions held in the load-store queue.

[0006] For example, when a memory access instruction is executed, its address is stored in the load-store queue and compared with the address of another memory access instruction already stored there. In the case of vector memory access instructions that include multiple addresses, such as gather and scatter instructions, each of the multiple addresses is stored in the load-store queue and compared.

[0007] Therefore, arithmetic processing units capable of executing vector memory access instructions may be equipped with multiple comparators that compare multiple addresses in parallel. When multiple comparators are provided, the circuit size of the arithmetic processing unit increases.

[0008] In one aspect, the present invention aims to reduce the circuit size of the collision detection unit that determines a collision between an address included in a memory access instruction and an address held in a queue that holds memory access instructions. [Means for solving the problem]

[0009] From one perspective, the arithmetic processing unit has a queue that holds memory access instructions containing at least one address, and a memory access instruction Includes discontinuous addressesThe system includes, when multiple addresses are included, a reduced address generation unit that reduces the bits of the multiple addresses to generate a reduced address; a collision determination unit that determines a collision between the reduced address and an address held in the queue; and an access control unit that controls the processing of memory access instructions held in the queue based on the determination result by the collision determination unit. [Effects of the Invention]

[0010] The circuit size of the collision detection unit, which determines the collision between an address included in a memory access instruction and an address held in the queue that holds the memory access instruction, can be reduced. [Brief explanation of the drawing]

[0011] [Figure 1] A block diagram showing an example of the main components of a processing unit in one embodiment. [Figure 2] Figure 1 is an explanatory diagram showing an example of the change in the state of the payload. [Figure 3] Figure 1 is an explanatory diagram showing an example of how the reduced address generation unit generates reduced addresses. [Figure 4] Figure 3 is an explanatory diagram showing an example of an address range represented by a reduced address. [Figure 5] This is an explanatory diagram showing an example of the address determination operation by each match determination circuit in the match determination unit of Figure 1. [Figure 6] An example of another processing unit is shown in the image. [Figure 7] Block diagram showing an example of a processing unit in another embodiment. [Figure 8] Figure 7 is an explanatory diagram showing an example of a payload and an example of a method for generating a reduced address by the reduced address generation unit. [Figure 9] Figure 7 is a circuit diagram showing an example of a matching detection circuit. [Figure 10] A block diagram showing an example of the main components of a processing unit in another embodiment. [Figure 11]It is a block diagram showing an example of the main part of an arithmetic processing unit in another embodiment. [Figure 12] It is a block diagram showing an example of the main part of an arithmetic processing unit in another embodiment. [Figure 13] It is an explanatory diagram showing an example of the operation of the coincidence determination circuit of FIG. 12.

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] FIG. 1 shows an example of an arithmetic processing unit in one embodiment. The arithmetic processing unit 1 shown in FIG. 1 is, for example, a processor such as a CPU (Central Processing Unit) capable of executing SIMD arithmetic instructions.

[0014] The arithmetic processing unit 1 has a load store queue 2, an access control unit 8, and a data cache 9. The load store queue 2 has a reduced address generation unit 3, a payload 4, and a coincidence determination unit 5. Note that FIG. 1 shows a part of the elements used for memory access. Actually, the arithmetic processing unit 1 may have a scheduler such as an instruction cache, an instruction decoder, a reservation station not shown, a register file, an arithmetic unit including an arithmetic unit capable of executing SIMD arithmetic instructions, and the like.

[0015] An arithmetic processing unit 1 having a scheduler such as a reservation station may execute instructions in an order different from the instruction order decoded by the instruction decoder (that is, the instruction order described in the program). For this reason, in order to guarantee the commit in the in-order of load instructions and store instructions, a load store queue 2 for detecting an address collision is provided. The address collision will be described with reference to FIG. 2. Load instructions and store instructions include a single address or a plurality of addresses.

[0016] The reduced address generation unit 3 generates a reduced address CAD by reducing multiple addresses AD (AD0-AD7) when a memory access instruction MA, such as a load instruction or store instruction, contains multiple addresses AD. For example, the reduced address generation unit 3 reduces multiple addresses included in a vector load instruction or vector store instruction based on a vector load instruction or vector store instruction issued by the scheduler.

[0017] For example, vector load and vector store instructions include consecutive address vector load and consecutive address vector store instructions where addresses are consecutive in ascending or descending order, and stride vector load and stride vector store instructions where addresses are equally spaced. Additionally, there is a gather instruction as a vector load instruction, which allows for specifying any multiple addresses. There is also a scatter instruction as a vector store instruction, which allows for specifying any multiple addresses.

[0018] Figure 1 shows an example where eight addresses AD0-AD7 are reduced, but the reduced address generation unit 3 can reduce two or more addresses AD, and can also output a single address AD as the reduced address CAD. For example, if the reduced address generation unit 3 receives a single address AD in response to a memory access instruction MA, it may output a single address AD as the reduced address CAD. In this case, the path for transferring address AD to payload 4 may be omitted.

[0019] Payload 4 contains multiple entries ENT that hold memory access instructions MA. Payload 4 is an example of a queue. For example, entry ENT holds an execution flag, an instruction code indicating a load or store instruction, an address, and data as a memory access instruction MA. The data held in entry ENT is either store data included in the memory access instruction MA or load data read from data cache 9. In Figure 1, for simplicity, only the address area of ​​each entry ENT is shown. An example of Payload 4 is shown in Figure 2.

[0020] Payload 4 outputs the address (AD or CAD) held in each entry ENT to the match determination unit 5. Payload 4 also outputs the memory access instruction MA held in entry ENT, as instructed by the access control unit 8, to the data cache 9. Payload 4 holds the memory access instruction MA transferred from the scheduler and register file (not shown) and the reduced address CAD output from the reduced address generation unit 3.

[0021] By storing the reduced address CAD generated by the reduced address generation unit 3 in the payload 4, the number of memory access instructions MA that can be stored in the payload 4 can be increased compared to the case where multiple addresses AD before reduction are stored in the payload 4. This increases the number of memory access instructions MA that can be controlled by the access control unit 8, thereby improving the processing performance of the arithmetic processing unit 1. Furthermore, if the processing performance of the arithmetic processing unit 1 does not change, it becomes possible to reduce the number of entries ENT in the payload 4, thereby reducing the circuit size of the arithmetic processing unit 1.

[0022] The match determination unit 5 has a plurality of match determination circuits 6, each corresponding to an entry ENT in the payload 4. Each match determination circuit 6 compares the address (AD or CAD) from the payload 4 with the reduced address CAD generated by the reduced address generation unit 3, and outputs a collision signal COL if an address collision is detected. The match determination unit 5 is an example of a collision determination unit that determines a collision between the reduced address CAD and the address held in the payload 4.

[0023] The access control unit 8 controls the processing of the memory access instruction MA held in the payload 4. For example, the access control unit 8 controls access to the data cache 9 based on the memory access instruction MA held in the payload 4. The access control unit 8 also controls the commit process of the memory access instruction MA held in the payload 4 based on the collision signal COL output from the match determination unit 5.

[0024] Based on the receipt of a read request corresponding to a load instruction, data cache 9 reads the data DT to be read from the data array within data cache 9 and outputs it to the register file. Based on the receipt of a write request corresponding to a store instruction, data cache 9 updates the data held in the data array with the data to be written. If data cache 9 does not hold the data to be accessed in the data array (cache miss), it reads the data from a lower cache or memory such as main memory.

[0025] In Figure 1, an example is shown where the load-store queue 2 operates in common for both load and store instructions. However, for example, the load-store queue 2 may operate separately for load and store instructions. In this case, the payload 4 has multiple entries ENT where load instructions are stored and multiple entries ENT where store instructions are stored.

[0026] Then, when the reduced address generation unit 3 receives multiple addresses AD included in a load instruction, it compares the generated reduced address CAD with the multiple addresses held in the entry ENT for the store instruction to determine if there is a collision.

[0027] Figure 2 shows an example of the state changes of Payload 4 in Figure 1. In Figure 2, an example is shown where two store instructions ST (ST1, ST2) and two load instructions LD (LD3, LD4) are stored in entries ENT1, ENT2, ENT3, and ENT4 of Payload 4, respectively. For example, Payload 4 functions as a ring buffer, and the entry ENT numbers indicate the order in which the instructions are written in the program.

[0028] An execution flag of "0" indicates that the instruction has not been executed. An execution flag of "1" indicates that the instruction has been executed. The "0x" preceding the numbers in the address and data fields indicates that the numbers are in hexadecimal. The code n / a in the address and data fields indicates that the address or data has not been determined. The shaded entry ENT indicates that the state has changed. For example, control of payload 4 is performed by the access control unit 8 in Figure 1.

[0029] In Figure 2, for simplicity, an example is shown where a scalar store instruction ST and a scalar load instruction LD containing a single address are stored in payload 4. However, a vector store instruction ST and a vector load instruction LD containing multiple addresses may also be stored in payload 4. When a vector store instruction ST and a vector load instruction LD are stored in payload 4, the reduced address CAD is stored in entry ENT. Also, when a vector store instruction ST is stored in payload 4, multiple data corresponding to multiple addresses are stored.

[0030] In state 1, the store instruction ST1 and load instruction LD4 are executed, but the store instruction ST2 and load instruction LD3 are not executed. Since the address of the store instruction ST2 is not determined, the data "0x456" obtained by the subsequent load instruction LD4 may be incorrect.

[0031] Next, in state 2, the load instruction LD3 is executed. The address included in the load instruction LD3 is output as a reduced address CAD from the reduced address generation unit 62. The match determination unit 5 compares the address of the load instruction LD3 with the addresses of all instructions stored in the payload 4, regardless of the type of instruction.

[0032] The access control unit 8 refers to the comparison result from the match determination unit 5, comparing the address of the load instruction LD3 with the addresses of the store instructions ST1 and ST2 that precede the load instruction LD3 and are stored in the payload 4. The access control unit 8 then detects a collision between the address of the load instruction LD3 and the address of the store instruction ST1. Therefore, the access control unit 8 decides to forward the data to be read by the load instruction LD3 from entry ENT1 rather than reading it from the data cache 9, and stores the data "0x123" held in entry ENT1 into entry ENT3.

[0033] Next, in state 3, the address of the store instruction ST2 is stored in entry ENT2 by the reduced address generation unit 3, and then the store instruction ST2 is executed. The address "0x100" and data "0x789" of the store instruction ST2 are then stored in entry ENT2. The address included in the store instruction ST2 is output from the reduced address generation unit 62 as a reduced address CAD.

[0034] The match determination unit 5 compares the address of the store instruction ST2 with the addresses of all instructions stored in the payload 4, regardless of the type of instruction. The access control unit 8 refers to the comparison result from the match determination unit 5, comparing the address of the store instruction ST2 with the addresses of the load instructions LD3 and LD4, which are stored in the payload 4 and follow the store instruction ST2. The access control unit 8 then detects a collision between the address of the store instruction ST2 and the address of the load instruction LD3.

[0035] In state 4, the access control unit 8 cancels the execution of the load instructions LD3 and LD4 that follow the store instruction ST2, and ejects them from entries ENT3 and ENT4. This cancels the data "0x123" of the load instruction LD3 that was mistakenly forwarded from entry ENT1 in state 2. The canceled load instructions LD3 and LD4 are then reissued.

[0036] In this embodiment, the matching determination unit 5 compares the reduced address CAD generated by the reduced address generation unit 3 with the address held in the payload 4. This reduces the number of matching determination circuits 6 compared to when multiple addresses before reduction are used for comparison. As a result, the circuit size of the matching determination unit 5 can be reduced compared to when multiple addresses before reduction are used for comparison.

[0037] Furthermore, since the reduced address CAD is stored in payload 4, the utilization efficiency of entry ENT can be improved compared to the case where multiple addresses before reduction are stored in payload 4, and the number of memory access instructions MA that can be stored in payload 4 can be increased. As a result, the number of memory access instructions MA that can be controlled by the access control unit 8 can be increased, and the processing performance of the arithmetic processing unit 1 can be improved.

[0038] Furthermore, if it is not necessary to improve the utilization efficiency of entry ENT, the number of entry ENT can be reduced. This further reduces the number of matching determination circuits 6, and thus further reduces the circuit size of the matching determination unit 5.

[0039] Figure 3 shows an example of how the reduced address generation unit 3 in Figure 1 generates reduced addresses. Figure 3 shows an example where the memory access instruction MA1 is a gather or scatter instruction containing eight addresses AD0-AD7. For simplicity, Figure 3 shows an example where each address AD0-AD7 is 8 bits, but the number of bits for each address AD0-AD7 is not limited to 8 bits. The addresses AD0-AD7 described in Figure 3 and later are also not limited to 8 bits.

[0040] In generation method 1, the reduced address generation unit 3 sets the bit value of the reduced address CAD to "0" if all bit values ​​are "0" at each bit position in addresses AD0-AD7, and sets the bit value of the reduced address CAD to "1" if all bit values ​​are "1". In addition, if there is a mix of "0" and "1" bit values ​​at each bit position in addresses AD0-AD7, the reduced address generation unit 3 sets the bit value of the reduced address CAD to an undefined value "X". In generation method 2, in addition to the rules of generation method 1, the reduced address generation unit 3 sets the bits lower than the bit position that indicates an undefined value "X" in the reduced address CAD to an undefined value "X".

[0041] In this way, the reduced address generation unit 3 can generate a reduced address CAD represented by three-valued logic of "0", "1", and "X" using generation method 1 or generation method 2. If the memory access instruction MA1 includes a single address AD, the reduced address generation unit 3 will use the single address AD as the reduced address CAD.

[0042] This allows the reduced address CAD generated by the reduced address generation unit 3 to be stored in the payload 4, regardless of whether the memory access instruction MA contains a single address AD or multiple addresses AD. Therefore, compared to cases where the storage method of the payload 4 differs depending on whether it is a single address AD or a reduced address CAD, the control for storing addresses AD and CAD in the payload 4 can be simplified.

[0043] However, since the arithmetic processing unit 1 handles binary numbers, it cannot use the undefined value "X". Therefore, in practice, as explained in Figure 8, the reduced address generation unit 3 converts the reduced address CAD, which is expressed in three-valued logic, into a format that can be expressed in binary. For example, the reduced address generation unit 3 may set the undefined value "X" to the value "00", the value "0" to the value "01", and the value "1" to the value "10" in the reduced address CAD.

[0044] Figure 4 shows an example of the address range indicated by the reduced address CAD in Figure 3. The eight addresses AD0-AD7 included in the memory access instruction MA1 exemplified in Figure 4 are the same as the addresses AD0-AD7 shown in Figure 3. Also, the reduced address MA1.CAD exemplified in Figure 4 is the same as the reduced address MA1.CAD shown in generation method 2 in Figure 3. When the reduced address CAD is generated by generation method 2 in Figure 3, the match determination unit 5 determines that the address AD in the range from "10100000" to "10111111" shown in Figure 4 conflicts with the reduced address MA1.CAD.

[0045] When the reduced address CAD is generated by generation method 1 in Figure 3, for example, address AD "10110001" where the second least significant bit of address MA1.AD0 is "0" is determined not to be in conflict with the reduced address MA1.CAD. Therefore, generation method 1 can reduce the number of addresses AD included in the reduced address CAD compared to generation method 2, thereby improving the accuracy of collision detection.

[0046] Figure 5 shows an example of the address determination operation by each match determination circuit 6 of the match determination unit 5 in Figure 1. As shown in Figure 1, the match determination circuit 6 compares each bit of the reduced address CAD generated by the reduced address generation unit 3 with each bit of the address held in one of the entries ENT of the payload 4. Here, the address held in one of the entries ENT of the payload 4 is either a single address AD or a reduced address CAD.

[0047] For example, the match detection circuit 6 outputs "0" to the AND circuit if the bit values ​​being compared are "0" and "1" or "1" and "0". The match detection circuit 6 outputs "1" to the AND circuit if the bit values ​​being compared are both "0", both are "1", or at least one of the bit values ​​being compared is an undefined value "X".

[0048] The AND circuit sets the collision signal COL to "1" to indicate an address collision if all the bit values ​​of the comparison result are "1" (all match). The AND circuit sets the collision signal COL to "0" to indicate no address collision if any of the bit values ​​of the comparison result are "0" (mismatch). The access control unit 8 in Figure 1 determines whether or not to collide between the reduced address CAD generated by the reduced address generation unit 3 and the address held in the payload 4, based on the logical value of the collision signal COL output from each match determination circuit 6. Then, based on the determination result, the access control unit 8 decides whether or not to commit the memory access instruction MA and controls the processing of the memory access instruction MA held in the queue.

[0049] Figure 6 shows an example of another arithmetic processing unit. The arithmetic processing unit 1A shown in Figure 6 does not have the reduced address generation unit 3 of Figure 1, and instead of the match determination unit 5 and access control unit 8 of Figure 1, it has a match determination unit 5A and an access control unit 8A.

[0050] If the arithmetic processing unit 1A does not have a reduced address generation unit 3, the match determination unit 5A directly receives multiple addresses AD0-AD7 included in the vector load instruction LD or the vector store instruction ST. The match determination unit 5A then compares the received addresses AD0-AD7 with the addresses AD held in each entry ENT of the payload 4. For this reason, the match determination unit 5A has a number of match determination circuits 6 corresponding to the product of the number of addresses AD0-AD7 and the number of entries ENT.

[0051] The access control unit 8A receives collision signals COL output from all match determination circuits 6 and controls the commit process of the memory access instruction MA held in the payload 4 based on the received collision signals COL. As shown in Figure 6, the circuit size of the match determination unit 5A and access control unit 8A of the arithmetic processing unit 1A, which does not have a reduced address generation unit 3, is larger than the circuit size of the match determination unit 5 and access control unit 8 in Figure 1.

[0052] For example, the circuit size of the reduced address generation unit 3 in Figure 1 is approximately equivalent to two matching determination circuits 6 for each address AD. Therefore, the reduction in the circuit size of the matching determination unit 5 and the access control unit 8 in Figure 1 is sufficiently larger than the increase in the circuit size of the reduced address generation unit 3.

[0053] In this embodiment, the matching determination unit 5 compares the reduced address CAD generated by the reduced address generation unit 3 with the address held in the payload 4. Therefore, compared to the case where multiple addresses AD0-AD7 before reduction are used for comparison, the number of matching determination circuits 6 can be reduced, and the circuit size of the matching determination unit 5 can be reduced.

[0054] Since the reduced address CAD is stored in payload 4, the utilization efficiency of entry ENT can be improved compared to storing multiple addresses before reduction in payload 4, and the number of memory access instructions MA that can be stored in payload 4 can be increased. This increases the number of memory access instructions MA that can be controlled by the access control unit 8, and thus improves the processing performance of the arithmetic processing unit 1.

[0055] The reduced address generation unit 3 converts a single address AD into a reduced address CAD, allowing the reduced address CAD generated by the reduced address generation unit 3 to be stored in the payload 4, regardless of whether the address AD included in the memory access instruction MA is single or multiple. Therefore, the control for storing the address AD and CAD in the payload 4 can be easily facilitated.

[0056] Figure 7 shows an example of an arithmetic processing unit in another embodiment. Detailed explanations of elements similar to those in Figures 1 to 6 are omitted. The arithmetic processing unit 100 shown in Figure 7 is a processor, such as a CPU capable of executing SIMD arithmetic instructions, similar to the arithmetic processing unit 1 in Figure 1.

[0057] The arithmetic processing unit 100 includes an instruction cache 10, a decoder 20, a scheduler 30 such as a reservation station, a register file 40, a plurality of load-store (LDST) units 50, and a plurality of arithmetic units 90.

[0058] The instruction cache 10 holds instructions transferred from memory such as main memory and outputs the held instructions to the decoder 20. For example, the instruction cache 10 may be a primary instruction cache. The instructions held in the instruction cache 10 are arithmetic instructions and memory access instructions.

[0059] For example, arithmetic instructions include integer arithmetic instructions, fixed-point arithmetic instructions, and floating-point arithmetic instructions. For example, memory access instructions include load instructions and store instructions. In addition, at least one of the integer arithmetic instructions, fixed-point arithmetic instructions, and floating-point arithmetic instructions may include SIMD arithmetic instructions. Furthermore, similar to the arithmetic processing unit 1 in Figure 1, the load instructions include a scalar load instruction containing a single address, as well as a vector load instruction LD which includes a continuous address load instruction LD and a gather instruction. The store instructions include a scalar store instruction containing a single address, as well as a vector store instruction ST which includes a continuous address store instruction ST and a scatter instruction.

[0060] The decoder 20 decodes the instruction received in order from the instruction cache 10 and outputs the decoded instruction to the scheduler 30. The arithmetic processing unit 100 may have an instruction buffer between the instruction cache 10 and the decoder 20 for storing multiple instructions transferred from the instruction cache 10.

[0061] The logical register numbers included in the instructions decoded by the decoder 20 may be converted, for example, by a rename unit to physical register numbers that identify the physical registers in the register file 40. The logical register numbers are the register numbers described in the program. By incorporating a rename unit, the arithmetic processing unit 100 can include more physical registers in the register file 40 than the number of registers that can be described in the program. As a result, the frequency of register contention can be reduced compared to when a rename unit is not provided, and the execution efficiency of instructions can be improved.

[0062] The scheduler 30 has an arithmetic queue containing multiple entries for holding arithmetic instructions output from the decoder 20, and a memory access queue containing multiple entries for holding memory access instructions output from the decoder 20. The scheduler 30 issues the arithmetic instructions held in the arithmetic queue to one of the arithmetic units 90 out of order in the order in which they can be executed. The scheduler 30 also outputs the instructions held in the memory access queue to one of the load / store units 50 out of order in the order in which they can be executed.

[0063] Each of the multiple load-store units 50 executes load and store instructions. Each of the multiple load-store units 50 has multiple address calculators 52. The multiple load-store units 50 also have a load-store queue 60, an access control unit 70, and an L1 (Level 1) data cache 80 common to the multiple load-store units 50. The load-store queue 60 has a reduced address generation unit 62 corresponding to each of the multiple load-store units 50, a payload 64 common to the multiple load-store units 50, and a match determination unit 66. The match determination unit 66 has multiple match determination circuits 67.

[0064] Each of the multiple address calculators 52 calculates the address to be accessed by a memory access instruction by performing addition processing, etc., of data transferred from the register file 40. Each of the multiple address calculators 52 outputs the calculated address to the corresponding reduced address generation unit 62 and payload 64. In the case of a load instruction, it also outputs the address AD to the L1 data cache 80. By providing multiple address calculators 52 in each load / store unit 50, multiple addresses included in a vector load instruction or vector store instruction can be calculated in parallel.

[0065] The reduced address generation unit 62 generates a reduced address CAD by reducing multiple addresses AD included in a load instruction or store instruction, similar to the reduced address generation unit 3 in Figure 1. An example of how to generate a reduced address CAD is shown in Figure 8. The payload 64, similar to the payload 4 in Figure 1, includes multiple entries ENT (not shown) that hold memory access instructions. Payload 64 is an example of a queue. An example of payload 64 is shown in Figure 8.

[0066] The match determination unit 66, similar to the match determination unit 5 in Figure 1, has multiple match determination circuits 67 at the entry of the payload 64. Each match determination circuit 67 compares the address from the payload 64 with the reduced address CAD generated by the reduced address generation unit 62 and outputs a collision signal COL according to the comparison result. The match determination unit 66 is an example of a collision determination unit that determines a collision between the reduced address CAD and the address held in the payload 4. The match determination circuit 67 is an example of a collision determination circuit.

[0067] The access control unit 70, similar to the access control unit 8 in Figure 1, controls the processing of memory access instructions held in the payload 64 based on the collision signal COL, and controls access to the L1 data cache 80. The L1 data cache 80 has the same configuration and function as the data cache 9 in Figure 1.

[0068] Each arithmetic unit 90 executes arithmetic instructions. For example, each arithmetic unit 90 has a fixed-point arithmetic unit, a floating-point arithmetic unit, and a logical arithmetic unit.

[0069] Figure 8 shows an example of the payload 64 in Figure 7 and an example of the method for generating a reduced address by the reduced address generation unit 62. The payload 64 includes multiple entries ENT (ENT1-ENT6, etc.) that hold a memory access instruction MA. For example, each entry ENT holds an execution flag, an instruction type (load instruction LD or store instruction ST), a key address KEY, data, a mask vector MSK, and the original address. The original address is the address before reduction, calculated by each address calculator 52. In this embodiment, the reduced address CAD is represented as the key address KEY and the mask vector MSK.

[0070] The reduced address generation unit 62 generates the reduced address CAD using ternary logic represented by "0", "1", and an undefined value "X", similar to the reduced address generation unit 3 in Figure 1. However, the reduced address generation unit 62 represents the reduced address CAD as a key address KEY and a mask vector MSK in order to determine address collisions using binary numbers handled by the arithmetic processing unit 100.

[0071] By converting the contracted address CAD, which is represented by three-valued logic, into a format that can be represented in binary, the matching unit 66 in the arithmetic processing unit 100, which handles binary numbers, can determine a collision of contracted address CAD containing the undefined value "X". In other words, collisions of contracted address CAD containing the undefined value "X" can be determined without changing the architecture of the arithmetic processing unit 100.

[0072] The reduced address generation unit 62 selects one of the multiple addresses AD included in the memory access instruction MA as the key address KEY. The reduced address generation unit 62 also calculates the exclusive OR (XOR) of the bit values ​​at each bit position of the multiple addresses AD included in the memory access instruction MA and uses this as the mask vector MSK. Figure 8 shows an example of calculating the mask vector MSK from the eight addresses AD0-AD7 included in the memory access instruction MA1. The reduced address CAD (KEY, MSK) generated by the reduced address generation unit 62 is used for determination by the matching determination unit 66 and is stored in the payload 64 along with the information of the memory access instruction MA.

[0073] Figure 9 shows an example of the match determination circuit 67 in Figure 7. The match determination circuit 67 includes a negative exclusive OR circuit XNOR, OR1 and OR2 circuits, and AND circuit. OR1 is an example of a first OR circuit, OR2 is an example of a second OR circuit, and AND is an example of a logical conjunction circuit.

[0074] The XNOR circuit calculates the negative exclusive OR bitwise between the key address KEY held in one of the entries ENT of the payload 64 and the key address KEY generated by the reduced address generation unit 62. The OR1 circuit calculates the logical OR bitwise between the mask vector MSK held in one of the entries ENT of the payload 64 and the mask vector MSK generated by the reduced address generation unit 62.

[0075] The OR2 circuit calculates the bitwise OR of the output of the ENOR circuit and the output of the OR1 circuit. The AND circuit calculates the bitwise AND of all bits of the output of the OR2 circuit and outputs the result as the collision signal COL.

[0076] When the match detection circuit 67 receives the key address KEY and mask vector MSK, as exemplified in the parentheses in Figure 9, from the payload 64 and the reduced address generation unit 62, respectively, it outputs a collision signal COL (="1") indicating an address collision. In this way, the match detection circuit 67 can also detect address collisions when the reduced address CAD is represented by the key address KEY and mask vector MSK. In other words, the match detection circuit 67 can detect collisions of reduced addresses represented by ternary logic.

[0077] As described above, this embodiment also provides the same effects as the embodiments described above. For example, since the match determination unit 66 compares the reduced address CAD with the address held in the payload 64, the number of match determination circuits 67 can be reduced compared to the case where multiple addresses AD before reduction are used for comparison, thereby reducing the circuit size of the match determination unit 66. In addition, by storing the reduced address CAD in the payload 64, more memory access instructions MA can be stored in the payload 64 compared to the case where multiple addresses AD before reduction are stored in the payload 64, thereby improving the processing performance of the arithmetic processing unit 100.

[0078] Furthermore, in this embodiment, by converting the reduced address CAD, which is represented in three-valued logic, into a format that can be represented in binary, the matching unit 66 in the arithmetic processing unit 100 that handles binary numbers can determine a collision of reduced address CAD containing an undefined value "X". In other words, a collision of reduced address CAD containing an undefined value "X" can be determined without changing the architecture of the arithmetic processing unit 100. The matching circuit 67 can also determine an address collision when the reduced address CAD is represented by a key address KEY and a mask vector MSK.

[0079] Figure 10 shows an example of the main components of an arithmetic processing unit in another embodiment. Detailed explanations of elements similar to those in the embodiments described above are omitted. The arithmetic processing unit 100A shown in Figure 10 has a load / store queue 60A, an access control unit 70A, and an L1 data cache 80. The load / store queue 60A has a reduced address generation unit 62A, a payload 64, and a match determination unit 66A. The match determination unit 66A is an example of a collision determination unit.

[0080] The reduced address generation unit 62A groups multiple addresses AD (AD0-AD7) included in the memory access instruction MA (load instruction or store instruction), and generates reduced addresses CAD0 and CAD1 for each of the grouped address groups. The reduced addresses CAD0 and CAD1 are output to the match determination unit 66A and stored in the payload 64.

[0081] By generating reduced addresses CAD0 and CAD1 for each address group, the range of address AD indicated by each reduced address CAD0 and CAD1 can be narrowed compared to generating a single reduced address CAD without grouping address AD. This reduces the number of address ADs included in each reduced address CAD0 and CAD1, thereby improving collision detection accuracy.

[0082] The match determination unit 66A has multiple match determination circuits 67, each corresponding to an entry ENT of the payload 64, for each of the reduced addresses CAD0 and CAD1. Each match determination circuit 67 has the same configuration and function as the match determination circuit 67 in Figure 9. The match determination circuit 67 in Figure 10 compares the address held by the corresponding entry ENT of the payload 64 with the corresponding reduced address CAD0 or AD1, similar to the match determination circuit 6 in Figure 1. The match determination circuit 67 then outputs a collision signal COL to the access control unit 70A according to the comparison result.

[0083] The access control unit 70A controls the processing of memory access instructions held in the payload 64 based on multiple collision signals COL for each of the reduced addresses CAD0 and CAD1, and controls access to the L1 data cache 80.

[0084] As described above, this embodiment also provides the same effects as the embodiments described above. For example, the match determination unit 66A compares the reduced address CAD with the address held in the payload 64. Therefore, compared to the case where multiple addresses AD before reduction are used for comparison, the number of match determination circuits 67 can be reduced, and the circuit size of the match determination unit 66A can be reduced. In addition, the reduced address generation unit 62A stores the generated multiple reduced addresses CAD0 and CAD1 in the payload 64. Therefore, compared to the case where multiple addresses AD before reduction are stored in the payload 64, the number of memory access instructions that can be stored in the payload 64 can be increased. This improves the processing performance of the arithmetic processing unit 100A.

[0085] Furthermore, in this embodiment, the reduced address generation unit 62A generates multiple reduced addresses CAD0 and CAD1. This makes it possible to narrow the range of addresses AD represented by each of the reduced addresses CAD0 and CAD1 compared to the case where only one reduced address CAD is generated. Therefore, the number of addresses AD included in each reduced address CAD0 and CAD1 can be reduced, and the collision detection accuracy can be improved. As a result, for example, the frequency in which a load instruction LD, which does not actually have a collision with an address AD, is determined to be in collision with a preceding store instruction ST and canceled can be reduced, and a decrease in the processing performance of the arithmetic processing unit 100A can be suppressed.

[0086] Figure 11 shows an example of the main components of an arithmetic processing unit in another embodiment. Detailed explanations of elements similar to those in the embodiments described above are omitted. The arithmetic processing unit 100B shown in Figure 11 is similar in configuration to the arithmetic processing unit 100A in Figure 10, except that it has a load-store queue 60B instead of the load-store queue 60A in Figure 10.

[0087] The load-store queue 60B adds a reduced address generation unit 62 to the load-store queue 60A in Figure 10. The reduced address generation unit 62 has the same configuration and function as the reduced address generation unit 62 in Figure 8. That is, the reduced address generation unit 62 reduces multiple addresses AD (AD0-AD7) included in a memory access instruction MA (load instruction or store instruction) to generate a reduced address CAD. The reduced address generation unit 62 in Figure 11 is an example of a first reduced address generation unit, and the reduced address CAD generated by the reduced address generation unit 62 is an example of a first reduced address. The reduced address generation unit 62A is an example of a second reduced address generation unit, and the reduced addresses CAD0 and CAD1 generated by the reduced address generation unit 62A are examples of second reduced addresses.

[0088] The reduced address CAD generated by the reduced address generation unit 62 is stored in the payload 64. Therefore, in this embodiment, the number of reduced address CADs stored in the payload 64 can be reduced from the number of reduced address CAD0 and CAD1 stored in the payload 64 in Figure 10. As a result, the number of addresses AD stored in the payload 64 increases relatively, which allows for an increase in the number of memory access instructions stored in the payload 64 and improves the processing performance of the arithmetic processing unit 100B.

[0089] As described above, the same effects as in the above-described embodiment can be obtained in this embodiment as well. Furthermore, in this embodiment, the reduced address CAD is stored in the payload 64, and the reduced addresses CAD0 and CAD1 are output to the match determination unit 66A. This improves the collision determination accuracy by the match determination unit 66A, while increasing the number of addresses AD stored in the payload 64 compared to the case where the reduced addresses CAD0 and CAD1 are stored in the payload 64. As a result, the processing performance of the arithmetic processing unit 100B can be improved.

[0090] In the above example, the reduced address CAD generated by the reduced address generation unit 62 was described as being a single reduced address. However, the reduced address generation unit 62A may generate multiple reduced addresses for each of several groups, which may be divided in a different number or in a different way than the reduced address generated by the unit. Also, although the reduced address generation unit 62A is described in two examples, there may be three or more reduced addresses generated.

[0091] Figure 12 shows an example of the main components of an arithmetic processing unit in another embodiment. Detailed explanations of elements similar to those in the embodiments described above are omitted. The arithmetic processing unit 100C shown in Figure 12 adds a reduced address generation unit 62C and a match determination circuit 67C to the arithmetic processing unit 100 in Figure 7, the arithmetic processing unit 100A in Figure 10, or the arithmetic processing unit 100B in Figure 11. In Figure 12, one match determination circuit 67C is shown, but in reality, a match determination circuit 67C is provided for each entry ENT (not shown) included in the payload 64. A match determination unit is provided, which includes multiple match determination circuits 67 and multiple match determination circuits 67C. The match determination circuit 67C is an example of a collision determination circuit.

[0092] The reduced address generation unit 62C generates a reduced address CAD2 that indicates the range of multiple addresses AD included in the memory access instruction. The reduced address CAD2 generated by the reduced address generation unit 62C is an example of a fourth reduced address. For example, the reduced address generation unit 62C generates the starting address AH (=A0) and the offset OFSA, which is the distance from the starting address AH to the final address AE, as the reduced address CAD2. The reduced address generation unit 62C stores the generated reduced address CAD2 in the payload 64.

[0093] For example, the entry ENT of the payload 64 (not shown) stores information indicating the memory access instruction MA and a reduced address CAD2 that includes the starting address BH and offset OFSB generated by the previous reduced address generation unit 62C. That is, each entry ENT of the payload 64 stores either the reduced address CAD2 or the reduced address CAD generated by the reduced address generation unit 62 shown in Figure 7. If the memory access instruction MA includes a single address AD, according to the reduction rules, the single address AD is set as the starting address AH (or BH), and the offset OFSA (or OFSB) is set to "0".

[0094] The match determination circuit 67C includes adders ADDa and ADDb, comparators CMPa and CMPb, an OR circuit, and an inverting circuit NOT. Adder ADDa combines the starting address AH output from the reduced address generation unit 62C with the offset OFSA. of The final address AE is calculated by adding the values. The adder ADDb is the payload. 64 The starting address BH and offset are output from the corresponding entry ENT. OFSB and The final address BE is calculated by adding the values.

[0095] Comparator CMPa compares the final address BE with the starting address AH to determine their relative order. For example, comparator CMPa outputs "1" if the final address BE is less than the starting address AH, and outputs "0" if the final address BE is greater than or equal to the starting address AH. Comparator CMPb compares the starting address BH with the final address AE to determine their relative order. For example, comparator CMPb outputs "1" if the final address AE is less than the starting address BH, and outputs "0" if the final address AE is greater than or equal to the starting address BH.

[0096] The OR circuit outputs the logical OR of the outputs of comparators CMPa and CMPb to the NOT inverter circuit. The NOT inverts the logical value output from the OR circuit and outputs it as the collision signal COL. Therefore, the logic of the collision signal COL is given by equation (1). COL="not((AE <BH)or(BE<AH))‥ (1)

[0097] The reduced address generation unit 62C may also generate the starting address AH and the final address AE as the reduced address CAD2. In this case, the number of bits in the reduced address CAD2 increases, but the match detection circuit 67C does not need to have adders ADDa and ADDb. By generating a reduced address CAD2 that indicates the range of multiple addresses AD included in the memory access instruction, the collision detection accuracy can be improved compared to the reduced address CAD generated using ternary logic.

[0098] Figure 13 shows an example of the operation of the match determination circuit 67C in Figure 12. Note that the match determination unit in this embodiment includes the match determination circuit 67 in Figure 9 and the match determination circuit 67C in Figure 12. As shown in Figure 13, the collision signal COL is set to "0" if the range of the reduced address CAD2 indicated by the starting address AH and offset OFSA does not overlap with the range of the reduced address CAD2 indicated by the starting address BH and offset OFSB. The collision signal COL is set to "1" if the range of the reduced address CAD2 indicated by the starting address AH and offset OFSA overlaps with the range of the reduced address CAD2 indicated by the starting address BH and offset OFSB.

[0099] In the arithmetic processing unit 100C shown in Figure 12, a reduced address CAD, represented in ternary logic, and a reduced address CAD2, which indicates the range of address AD, are generated from multiple addresses AD included in the memory access instruction MA. For example, the reduced address generation unit 62 in Figure 7 generates the reduced address CAD by reducing the bits of multiple addresses AD. Alternatively, the reduced address CAD may be generated by the reduced address generation unit 62A in Figure 10 or Figure 11. The reduced address CAD generated by the reduced address generation units 62 and 62A is an example of a third reduced address. Furthermore, the reduced address generation unit 62C in Figure 12 generates a reduced address CAD2, which indicates the range of multiple addresses AD.

[0100] Here, multiple addresses AD that do not change in ascending or descending order are difficult to convert to a reduced address CAD2 as they are. For this reason, the reduced address generation unit 62C, like the reduced address generation unit 62, first generates a reduced address CAD represented by three-valued logic of "0", "1", and "X". Next, the reduced address generation unit 62C generates the minimum value of address AD by assuming that the undefined value "X" of the generated reduced address CAD is "0", and generates the maximum value of address AD by assuming that the undefined value "X" of the generated reduced address CAD is "1". Then, the reduced address generation unit 62C generates the starting address AH and the offset OFSA The reduced address CAD2 is generated, which includes the specified value. The reduced address generation unit 62C may also generate the minimum and maximum values ​​of address AD by replacing the undefined value "X" in the reduced address CAD generated by the reduced address generation unit 62 with "0" and "1".

[0101] The load-store queue, including the reduced address generation unit 62 and the reduced address generation unit 62C, stores the reduced address CAD generated by the reduced address generation unit 62 in the payload 64 if the multiple addresses AD do not change in ascending or descending order. The load-store queue also stores the reduced address CAD2 generated by the reduced address generation unit 62C in the payload 64 if the multiple addresses AD change in ascending or descending order.

[0102] The matching unit, including matching circuits 67 and 67C, determines if a reduced address CAD is held in the entry of the payload 64, and determines a collision between the held reduced address CAD and the reduced address CAD generated by the reduced address generation unit 62. The matching unit, including matching circuits 67 and 67C, determines if a reduced address CAD2 is held in the entry of the payload 64, and determines a collision between the held reduced address CAD2 and the reduced address CAD2 generated by the reduced address generation unit 62C.

[0103] Thus, if the addresses AD included in the memory access instruction MA are not in ascending or descending order, the reduced address CAD generated by the reduced address generation unit 62 is used to determine if there is a collision with address AD. If the addresses AD included in the memory access instruction MA are in ascending or descending order, the reduced address CAD2 generated by the reduced address generation unit 62C is used to determine if there is a collision with address AD.

[0104] For example, as memory access instructions MA where addresses AD are not in ascending or descending order, there are gather instructions or scatter instructions. For example, as memory access instructions MA where addresses AD are in ascending or descending order, there are consecutive address load instructions LD such as stride access instructions or consecutive address vector store instructions ST.

[0105] As described above, the same effects as those of the embodiments described can be obtained in this embodiment as well. Furthermore, in this embodiment, when the addresses AD included in the memory access instruction MA are in ascending or descending order, the collision detection accuracy can be improved by using the reduced address CAD2 to determine the collision of addresses AD.

[0106] The features and advantages of the embodiments will become clear from the detailed description above. This is intended to be so as not to deviate from the spirit and scope of the claims, that the features and advantages of the embodiments described above are included. Furthermore, any improvement and modification should be readily conceivable to a person with ordinary skill in the art. Therefore, there is no intention to limit the scope of inventive embodiments to those described above, and it is also possible to rely on appropriate improvements and equivalents that fall within the scope disclosed in the embodiments. [Explanation of Symbols]

[0107] 1. 1A Arithmetic Processing Unit 2, 2A Load Store Queue 3. Reduced Address Generation Unit 4 Payloads 5, 5A Match judgment section 8, 8A Access Control Unit 9. Data Cache 10 instruction cache 20 Decoders 30 Scheduler 40 Register File 50 Load Store Units 52 Address Calculator 60, 60A, 60B Load Store Queue 62, 62A, 62C Reduced Address Generation Unit 64 payloads 66, 66A Match judgment section 67, 67C Match judgment circuit 70, 70A Access Control Unit 80 L1 Data Cache 90 arithmetic units 100, 100A, 100B, 100C Arithmetic Processing Units AD (AD0-AD7) Addresses AE final address AH starting address BE final address BH starting address CAD, CAD0, CAD1, CAD2 abbreviated addresses COL collision signal DT Data ENT entry ICD instruction code KEY Key Address LD load instruction MA memory access instruction MSK Mask Vector OFSA, OFSB offset ST Store Instruction STD Store Data

Claims

1. A queue that holds memory access instructions containing at least one address, When a memory access instruction includes multiple addresses, including discontinuous addresses, a reduced address generation unit generates a reduced address by reducing the bits of the multiple addresses, A collision determination unit that determines a collision between the reduced address and the address held in the queue, Based on the determination result by the collision determination unit, an access control unit controls the processing of memory access instructions held in the queue, A processing unit having a arithmetic processing unit.

2. The reduced address generation unit stores the generated reduced addresses in the queue. The arithmetic processing device according to claim 1.

3. The reduced address generation unit generates the reduced address by reducing multiple addresses included in a memory access instruction and a single address included in a memory access instruction according to reduction rules. The arithmetic processing device according to claim 1 or claim 2.

4. The reduced address generation unit generates the reduced address for each of the multiple address groups obtained by grouping the multiple addresses included in the memory access instruction, The collision detection unit determines whether there is a collision between the reduced addresses of the plurality of address groups and the addresses held in the queue. The arithmetic processing apparatus according to any one of claims 1 to 3.

5. The reduced address generation unit, A first reduced address generation unit reduces the bits of the multiple addresses for each of the multiple groups, which are divided into a different number or a different grouping method than the aforementioned multiple address groups. It includes a second reduced address generation unit that reduces the bits of multiple addresses for each of the multiple address groups, The first reduced address generated by the first reduced address generation unit is stored in the queue. The second reduced address generated by the second reduced address generation unit is output to the collision determination unit. The arithmetic processing device according to claim 4.

6. The reduced address generation unit generates reduced addresses that indicate a range of multiple addresses included in a memory access instruction, The collision determination unit determines a collision between an address included in the range indicated by the reduced address and an address held in the queue. The arithmetic processing apparatus according to any one of claims 1 to 3.

7. The reduced address generation unit, A third reduced address is generated by reducing the bits of the aforementioned multiple addresses, and a fourth reduced address is generated that indicates a range of the multiple addresses. The generated third reduced address and the fourth reduced address, or both, are kept in the queue. The collision determination unit, If a third reduced address is held in the queue, a collision is determined between the third reduced address held in the queue and the third reduced address generated by the reduced address generation unit. If a fourth reduced address is held in the queue, a collision between the fourth reduced address held in the queue and the fourth reduced address generated by the reduced address generation unit is determined. The arithmetic processing device according to claim 6.

8. The reduced address generation unit generates reduced addresses that are represented by three-valued logic, where each bit position of the plurality of addresses has a bit value that is either all "0", all "1", or undefined. The arithmetic processing device according to any one of claims 2 to 7.

9. The reduced address generation unit generates a reduced address by making the bits lower than the bit position indicating indeterminate indeterminate. The arithmetic processing apparatus according to claim 8.

10. The reduced address generation unit generates a reduced address consisting of a key address that indicates one of the multiple addresses and a mask vector represented by the exclusive OR of the bit values ​​at each bit position of the multiple addresses. The arithmetic processing unit according to claim 8 or claim 9.

11. The collision detection unit has a plurality of collision detection circuits that each determine whether a reduced address is in conflict with a plurality of addresses held in the queue. Each of the above-mentioned collision detection circuits is A negative exclusive OR circuit that calculates the negative exclusive OR of the bits of the key address contained in the reduced address and the reduced address held in the queue, A first OR circuit calculates the logical OR of the bits of the mask vector contained in the reduced address and the reduced address held in the queue, A second OR circuit calculates the bitwise OR of the output of the negative exclusive OR circuit and the output of the first OR circuit, The circuit comprises a logic AND circuit that calculates the logical AND of all bits of the output of the second logic OR circuit, If the output of the aforementioned AND circuit is "1", an address collision is detected. The arithmetic processing device according to claim 10.

12. A method for performing arithmetic operations on an arithmetic processing unit having a queue that holds memory access instructions including at least one address, The reduced address generation unit of the arithmetic processing unit generates a reduced address by reducing the bits of the multiple addresses when a memory access instruction includes multiple addresses that are discontinuous. The collision detection unit of the aforementioned processing unit determines whether there is a collision between the reduced address and the address held in the queue. The access control unit of the arithmetic processing unit controls the processing of memory access instructions held in the queue based on the determination result by the collision determination unit. Calculation processing method.

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