Reducing interference within the display panel while input detection is being performed.

Abstract

To reduce the adverse effect of an interference caused by a detecting device in a display device.SOLUTION: A processing system for an input device comprises sensor circuitry. The sensor circuitry is configured to operate a plurality of sensor electrodes for input sensing during a first sensing frame. During a first period of the first sensing frame, the sensor circuitry is configured to drive a first portion of the plurality of sensor electrodes with a sensing signal, drive a second portion of the plurality of sensor electrodes with a guarding signal, and drive a third portion of the plurality of sensor electrodes with a reference signal. The guarding signal and the sensing signal have at least one characteristic in common selected from the group consisting of amplitude, phase and frequency. The third portion of the plurality of sensor electrodes overlaps a first gate line of a display panel selected for updating during the first period.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to reducing the effects of interference caused by a sensing device in a display device.

Background Art

[0002] Input devices with proximity sensor devices may be used in various electronic systems. A proximity sensor device includes a sensing area defined on a surface, in which the proximity sensor device detects the presence, position, force, and / or movement of one or more input objects. A proximity sensor device may be used to provide an interface to an electronic system. For example, a proximity sensor device is used as an input device for a larger computing system, such as a touchpad incorporated into or provided around a notebook computer, a desktop computer, an automotive multimedia system, or an Internet of Things (IoT) device. A proximity sensor device is also often used in a smaller computing system, such as a touch screen incorporated into a mobile phone.

Summary of the Invention

[0003] In one example, a processing system for an input device includes a sensor circuit. The sensor circuit is configured to activate a plurality of sensor electrodes for input detection during a first detection frame. The sensor circuit is configured to drive a first subset of the plurality of sensor electrodes with a detection signal, a second subset of the plurality of sensor electrodes with a guard signal, and a third subset of the plurality of sensor electrodes with a reference signal during a first period of the first detection frame. The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. The third subset of the plurality of sensor electrodes overlaps a first gate line of a display panel selected for updating during the first period.

[0004] In one example, the input device comprises a plurality of sensor electrodes and a processing system. The processing system is coupled to the plurality of sensor electrodes and is configured to activate the plurality of sensor electrodes for input detection during a first detection frame. The processing system is configured to drive a first subset of the plurality of sensor electrodes with a detection signal, a second subset of the plurality of sensor electrodes with a guard signal, and a third subset of the plurality of sensor electrodes with a reference signal during a first period of the first detection frame. The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. The third subset of sensor electrodes among the plurality of sensor electrodes overlaps a first gate line of a display panel selected for updating during the first period.

[0005] In one example, the method includes driving a first subset of sensor electrodes among a plurality of sensor electrodes with a detection signal for a first period of a first detection frame, and driving a second subset of sensor electrodes among the plurality of sensor electrodes with a guard signal for the same first period. The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. The method is further configured to drive a third subset of sensor electrodes among the plurality of sensor electrodes with a reference signal for the same first period. The third subset of sensor electrodes among the plurality of sensor electrodes overlaps a first gate line of a display panel selected for updating during the first period. [Brief explanation of the drawing]

[0006] To enable a detailed understanding of the features of this disclosure, a more specific description of this disclosure, which is briefly summarized above, may be given with reference to embodiments. Some of these embodiments are illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments, and this disclosure allows for other equally valid embodiments, and should not be considered to limit the scope of the invention.

[0007] [Figure 1] Figure 1 is a schematic block diagram of an input device according to one or more embodiments.

[0008] [Figure 2] Figure 2 is a schematic block diagram of an input device and a display device according to one or more embodiments.

[0009] [Figure 3] Figure 3 is a schematic side view of an input device according to one or more embodiments.

[0010] [Figure 4] Figure 4 is a schematic side view of a portion of an input device according to one or more embodiments.

[0011] [Figure 5] Figure 5 is a flowchart of a method for performing capacity detection according to one or more embodiments.

[0012] [Figure 6] Figure 6 is a timing diagram of a capacitive frame according to one or more embodiments.

[0013] [Figure 7] Figure 7 is a schematic side view of a part of an input device according to one or more embodiments.

[0014] [Figure 8A] Figure 8A is a timing diagram of a capacitive frame according to one or more embodiments. [Figure 8B] Figure 8B is a timing diagram of a capacitive frame according to one or more embodiments. [Figure 9A1] Figure 9A1 is a timing diagram of a capacitive frame according to one or more embodiments. [Figure 9A2] Figure 9A2 is a timing diagram of a capacitive frame according to one or more embodiments. [Figure 9B1] Figure 9B1 is a timing diagram of a capacitive frame according to one or more embodiments. [Figure 9B2] Figure 9B2 is a timing diagram of a capacitive frame according to one or more embodiments.

[0015] [Figure 10] Figure 10 is a timing diagram for performing display updates and input detection according to one or more embodiments.

[0016] For ease of understanding, wherever possible, the same reference numerals are used to designate the same elements common to the drawings. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without particular recitation. The drawings referred to herein are not to be understood as being drawn to scale unless otherwise noted. Also, for purposes of clarity of presentation and description, the drawings are often simplified by omitting details or components. The drawings and the discussion are for purposes of explaining the principles discussed below, and like reference numerals indicate like elements.

Best Mode for Carrying Out the Invention

[0017] The following detailed description is, in essence, merely exemplary and is not intended to limit the disclosure or the application and uses of the disclosure. Further, there is no intention to be bound by any explicit or implicit theory presented in the foregoing background, summary, or the following detailed description.

[0018] In many input devices, sensor electrodes are provided in proximity to a display device. In such input devices, the display electrodes of the display device capacitively couple with the sensor electrodes. Accordingly, a detection signal applied to the sensor electrodes can adversely affect the update of the display of the display device. Interference coupling occurs from the driven sensor electrodes to adjacent display electrodes driven for display update, generating display distortion in the display of the display device. However, by spatially separating the driven sensor electrodes from the display electrodes driven for display update, the interference exerted on the driven display electrodes is mitigated, reducing display distortion.

[0019] Figure 1 illustrates an input device 100 configured to reduce display distortion in a display device. The input device 100 may be configured to supply input to an electronic system (not shown). Some non-exclusive examples of electronic systems include, among many others, desktop computers, laptop computers, netbooks, tablets, terminals, kiosks, mobile phones, automotive multimedia centers, and Internet of Things (IoT) devices.

[0020] The input device 100 comprises a processing system 110 and a plurality of sensor electrodes 105. The processing system 110 activates the sensor electrodes 105 to detect one or more input objects 140 within the detection area of ​​the input device 100. Examples of input objects 140 include fingers and styluses, as illustrated in Figure 1.

[0021] The detection area of ​​the input device 100 includes any space above, around, inside, and / or near the input device 100 in which the input device 100 can detect user input (for example, user input provided by one or more input objects 140).

[0022] The sensor electrodes 105 are connected to the processing system 110 via wiring 150. The exemplary pattern of sensor electrodes 105 illustrated in Figure 1 comprises an array of sensor electrodes 105 arranged in multiple rows and columns. In one example, the sensor electrodes 105 are arranged in rows 170-181. It is expected that the sensor electrodes 105 may be arranged in other patterns, such as an array with poles, a repeating pattern, a non-repeating pattern, a non-uniform array, or other suitable arrangement. The sensor electrodes 105 may have the shape of a circle, rectangle, rhombus, star, square, non-convex, convex, non-concave, concave, or other suitable geometric shape.

[0023] The sensor electrode 105 is provided on a common layer. For example, the sensor electrode 105 may be provided on the first side of the common substrate. In other embodiments, the sensor electrode 105 may be provided on two or more layers. For example, a portion of the sensor electrode 105 may be provided on the first layer, and another portion of the sensor electrode may be provided on the second layer. The first and second layers may be provided on different sides of the common substrate, or on different substrates.

[0024] The sensor electrode 105 is composed of a conductive material such as a metal mesh or indium tin oxide (ITO). Furthermore, the sensor electrodes 105 are ohmically insulated from each other. That is, one or more insulators separate the sensor electrodes and prevent them from electrically short-circuiting each other.

[0025] The processing system 110 comprises a sensor circuit section 104 and a detection module 106. The processing system 110 is configured to activate the sensor electrode 105 to detect one or more input objects 140 in the detection area of ​​the input device 100. The processing system 110 is entirely or partially located on one or more integrated circuit (IC) chips. For example, the processing system 110 may comprise a single IC chip. Alternatively, the processing system 110 may comprise multiple IC chips.

[0026] The sensor circuit unit 104 is coupled to the sensor electrode 105 via wiring 150 and is configured to drive the sensor electrode 105 with a detection signal to detect one or more input objects 140 in the detection area of ​​the input device 100.

[0027] The sensor circuit section 104 includes digital and / or analog circuit sections. For example, the sensor circuit section 104 includes a transmitter (or driver) circuit section configured to apply a detection signal to the sensor electrode 105, and a receiver circuit section for receiving a result signal from the sensor electrode 105. The transmitter circuit section may include one or more amplifiers and / or one or more modulators for applying the detection signal to the sensor electrode 105. The receiver circuit section may include an analog front end (AFE) comprising an integrating circuit section, a filtering circuit section, and / or a demodulation circuit section configured to receive and / or process the result signal from the sensor electrode 105.

[0028] The sensor circuit 104 drives one or more first sensor electrodes of the sensor electrodes 105 with a transformer capacitance detection signal, receives the result signal with one or more second sensor electrodes of the sensor electrodes 105, and activates the sensor electrodes 105 for transformer capacitance detection. By activating the sensor electrodes 105 for transformer capacitance detection, a change in the capacitive coupling between one or more sensor electrodes driven by the transformer capacitance detection signal and one or more sensor electrodes acting as receiver electrodes is detected. The capacitive coupling decreases as an input object (e.g., input object 140) coupled to system ground approaches the sensor electrodes. Driving the sensor electrodes 105 with the transformer capacitance detection signal includes modulating the sensor electrodes 105 with respect to a reference voltage, for example, system ground.

[0029] The transformer capacitance detection signal is a periodic or aperiodic signal that varies between two or more voltages. Furthermore, the transformer capacitance detection signal has a frequency between 100 kHz and 1 MHz. In other embodiments, other frequencies may be used. The transformer capacitance detection signal has a peak-to-peak amplitude in the range of about 1 V to about 10 V. However, in other embodiments, the transformer capacitance detection signal may have a peak-to-peak amplitude greater than about 10 V. In addition, the transformer capacitance detection signal may have a rectangular waveform, a sinusoidal waveform, a triangular waveform, a trapezoidal waveform, or a sawtooth waveform, among many others.

[0030] Activating the sensor electrodes 105 to receive a result signal comprises holding one or more sensor electrodes 105 at a substantially constant voltage, or modulating one or more sensor electrodes 105 with respect to a transformer capacitance detection signal. For example, activating one or more sensor electrodes 105 to receive a result signal by modulating one or more sensor electrodes 105 with respect to a transformer capacitance detection signal involves modulating one or more sensor electrodes 105 with a signal having a different amplitude, phase, waveform, and / or frequency from the transmitter signal. The result signal includes effects corresponding to one or more transformer capacitance detection signals and / or interference from the environment, such as one or more sources of other electromagnetic signals.

[0031] The sensor circuit 104 drives one or more of the first sensor electrodes 105 with an absolute capacitance detection signal and activates the sensor electrode 105 for absolute capacitance detection by receiving a result signal with the driven sensor electrode. By activating the sensor electrode 105 for absolute capacitance detection, a change in the capacitive coupling between the sensor electrode driven by the absolute capacitance detection signal and the input object (e.g., input object 140) is detected. The capacitive coupling of the sensor electrode 105 driven by the absolute capacitance detection signal is changed when the input object (e.g., input object 140) coupled to system ground approaches the sensor electrode.

[0032] The absolute capacitance detection signal is a periodic or aperiodic signal that varies between two or more voltages. Furthermore, the absolute capacitance detection signal has a frequency between 100 kHz and 1 MHz. In other embodiments, other frequencies may be used. In addition, the absolute capacitance detection signal may have a rectangular waveform, sinusoidal waveform, triangular waveform, trapezoidal waveform, or sawtooth waveform, among many others. The absolute capacitance detection signal has a peak-to-peak amplitude in the range of about 1 V to about 10 V. However, in other embodiments, the absolute capacitance detection signal may have a peak-to-peak amplitude greater than about 10 V. In various embodiments, driving the sensor electrode 105 with the absolute capacitance detection signal involves modulating the sensor electrode 105. The resulting signal received while performing absolute capacitance detection includes the effects corresponding to one or more absolute capacitance detection signals and / or interference from the environment, e.g., one or more sources of other electromagnetic signals. The absolute capacitance detection signal may be the same as or different from the transformer capacitance detection signal used in transformer capacitance detection.

[0033] The sensor circuit 104 activates a first subset of sensor electrodes 105 for absolute capacitance detection during a first period. This first subset of sensor electrodes 105 corresponds to one or more sensor electrodes 105. In one embodiment, this first subset of sensor electrodes includes fewer sensor electrodes 105 than all of them. In such an embodiment, this first subset of sensor electrodes 105 corresponds to a first subset of sensor electrodes 105. As illustrated in Figure 1, the sensor electrodes 105 are arranged in multiple rows 170-181. Each of the rows 170-181 includes one or more sensor electrodes 105. Furthermore, each of the rows 170-181 includes the same number of sensor electrodes 105. In other embodiments, one or more rows of rows 170-181 have a different number of sensor electrodes 105 than the other one or more of the sensor electrodes 105. A portion of the first sensor electrodes 105 corresponds to one or more rows from rows 170 to 181. Furthermore, a portion of the first sensor electrodes 105 may correspond to two or more rows from rows 170 to 181. In another embodiment, the sensor circuit 104 activates a portion of the first sensor electrodes 105 to detect transformer capacitance.

[0034] The sensor circuit unit 104 may simultaneously activate two or more sensor electrodes 105 for absolute capacitance detection. For example, the sensor circuit unit 104 simultaneously activates each of the first part of the sensor electrodes 105 for absolute capacitance detection. The sensor circuit unit 104 may simultaneously activate each of the sensor electrodes 105 in a common row (e.g., rows 170-181) for absolute capacitance detection. Furthermore, the sensor circuit unit 104 may simultaneously activate each of the sensor electrodes 105 in two or more rows (e.g., two or more of rows 170-181) for absolute capacitance detection. In another embodiment, the sensor circuit unit 104 activates two or more sensor electrodes 105 for transformer capacitance detection. For example, the sensor circuit unit 104 simultaneously drives one or more first sensor electrodes of the sensor electrodes 105 with a transmitter signal and simultaneously receives result signals from one or more second sensor electrodes of the sensor electrodes 105. The sensor electrode 105 driven by the transmitter signal and the sensor electrode 105 acting as a receiver electrode may be part of a common row among rows 170-181, or they may be part of different rows.

[0035] The sensor circuit 104 drives a second subset of sensor electrodes of the sensor electrode 105 with a guard signal during a first period. The second subset of sensor electrodes of the sensor electrode 105 corresponds to one or more sensor electrodes 105 that are not included in the first subset of sensor electrodes of the sensor electrode 105 and / or are not driven for absolute capacitance detection (or are not driven for transformer capacitance detection). The second subset of sensor electrodes may include fewer sensor electrodes 105 than all of them. In such embodiments, the second subset of sensor electrodes corresponds to a second subset of sensor electrodes 105. In one embodiment, the second subset of sensor electrodes of the sensor electrode 105 corresponds to two or more sensor electrodes 105 that are not included in the first subset of sensor electrodes of the sensor electrode 105. The second subset of sensor electrodes of the sensor electrode 105 corresponds to one or more rows of rows 170-181 that are not included in the first subset of sensor electrodes of the sensor electrode 105. In one embodiment, the second portion of the sensor electrodes 105 corresponds to two or more rows 170-181 that are not included in the first portion of the sensor electrodes 105. The second portion of the sensor electrodes 105 corresponds to more sensor electrodes than the first portion of the sensor electrodes 105. Alternatively, the second portion of the sensor electrodes 105 corresponds to fewer sensor electrodes 105 than the first portion of the sensor electrodes 105. In one embodiment, the first portion of the sensor electrodes and the second portion of the sensor electrodes 105 correspond to the same number of sensor electrodes.

[0036] The sensor circuit unit 104 simultaneously drives the second portion of the sensor electrodes 105 with a guard signal. For example, the sensor circuit unit 104 simultaneously drives one or more rows (e.g., rows 170-181) of the sensor electrodes 105 that correspond to the second portion of the sensor electrodes with a guard signal. Simultaneously driving one or more rows (e.g., rows 170-181) of the sensor electrodes 105 with a guard signal includes driving each sensor electrode 105 in one or more rows (e.g., rows 170-181) of the sensor electrodes 105 with a guard signal.

[0037] A sensor electrode driven by a guard signal is sometimes referred to as a guarded sensor electrode. By driving the sensor electrode with a guard signal, the voltage difference between the guarded sensor electrode and the sensor electrode driven by the absolute capacitance detection signal can be mitigated. Therefore, by applying the absolute capacitance detection signal to one or more second sensor electrodes while applying the guard signal to one or more first sensor electrodes, the change in capacitance between the guarded sensor electrode and the sensor electrode driven by the absolute capacitance detection signal becomes smaller or disappears.

[0038] In one embodiment, the guard signal shares at least one characteristic selected from the group consisting of amplitude, phase, and frequency with the absolute capacitance detection signal. In other words, the guard signal and the absolute detection signal may have a common amplitude, a common phase, a common frequency, or a combination thereof. In some embodiments, the amplitude of the guard signal is either smaller or larger than the amplitude of the absolute capacitance detection signal. In embodiments where the amplitude of the guard signal is smaller than the amplitude of the absolute capacitance detection signal, partial guarding occurs between the sensor electrode driven by the guard signal and the sensor electrode driven by the absolute capacitance detection signal so as to reduce capacitive coupling between the sensor electrodes at least partially. In embodiments where the amplitude of the guard signal is larger than the amplitude of the absolute capacitance detection signal, excessive guarding occurs between the sensor electrode driven by the guard signal and the sensor electrode driven by the absolute capacitance detection signal.

[0039] The guard signal and the absolute capacitance detection signal may have a common waveform. Furthermore, in one embodiment, the guard signal may be identical to the absolute capacitance detection signal.

[0040] The sensor circuit 104 drives a third subset of sensor electrodes 105 with a reference signal. This third subset of sensor electrodes 105 is a subset of sensor electrodes 105 that is not included in the first subset of sensor electrodes 105 and the second subset of sensor electrodes 105. Furthermore, this third subset of sensor electrodes may include not all of the sensor electrodes 105. In such embodiments, this third subset of sensor electrodes corresponds to a third subset of sensor electrodes 105. The sensor circuit 104 drives one or more rows (e.g., rows 170-181) of sensor electrodes 105 with a reference signal. This one or more rows of rows 170-181 of sensor electrodes 105 that are driven by the reference signal include rows 170-181 that are not activated for absolute capacitance detection and are not driven by a guard signal. Driving one or more rows (e.g., rows 170-181) of the sensor electrodes 105 with a reference signal includes sequentially driving each sensor electrode 105 of one or more rows (e.g., rows 170-181) with the reference signal. The reference signal is a constant voltage signal. For example, the reference signal is a direct current (DC) signal. In one embodiment, the reference signal is the ground signal of the input device 100.

[0041] In one or more embodiments, the sensor circuit 104 electrically floats a portion of the third sensor electrodes of the sensor electrode 105. The sensor circuit 104 electrically floats one or more of the sensor electrodes 105. The electrically floating sensor electrodes are not actively driven by the sensor circuit 104. For example, the sensor circuit 104 may be disconnected from the one or more sensor electrodes 105 in order to electrically float them. Furthermore, the sensor circuit 104 may maintain the one or more sensor electrodes in a high-impedance state in order to electrically float them.

[0042] The first, second, and third portions of the sensor electrode 105 may contain the same or different numbers of sensor electrodes 105. For example, the third portion of the sensor electrode may contain more sensor electrodes than the first portion and / or the second portion of the sensor electrode 105.

[0043] As described above, the sensor circuit 104 receives a result signal from the sensor electrode 105 driven by an absolute capacitance detection signal. The sensor circuit 104 integrates, filters, and / or demodulates the result signal. The detection module 106 receives the result signal from the sensor circuit 104 and processes the result signal to detect changes in the capacitive coupling of the sensor electrode 105. The detection module 106 uses the changes in the capacitive coupling of the sensor electrode 105 to detect the position information of one or more input objects (e.g., input object 140).

[0044] In one or more embodiments, a measured value of the change in the capacitive coupling detected from the result signal received from the sensor electrode 105 may be used by the detection module 106 to form a capacitive image. The result signal used to detect the change in the capacitive coupling is received between capacitive frames. A capacitive frame may also be called a detection frame or a capacitive detection frame. A capacitive frame may correspond to one or more capacitive images. Furthermore, during each capacitive frame, each of the sensor electrodes 105 is activated for capacitive detection. For example, during one or more capacitive frames, the sensor electrode 105 is activated for absolute capacitive detection. Furthermore, during one or more capacitive frames, the sensor electrode 105 is activated for transformer capacitive detection. In one or more capacitive frames, the sensor electrode 105 is activated for absolute capacitive detection and transformer capacitive detection. Multiple capacitive images may be acquired over multiple periods, and the differences between the images may be used to obtain information about the input object 140 in the detection area of ​​the input device 100. For example, a series of capacitive images acquired over a series of multiple periods can be used to track the movement of one or more input objects entering, leaving, and being in the detection area.

[0045] As used herein, “location information” broadly encompasses absolute position, relative position, velocity, acceleration, and other types of spatial information. Exemplary “zero-dimensional” location information includes near / far or contact / non-contact information. Exemplary “one-dimensional” location information includes position along an axis. Exemplary “two-dimensional” location information includes motion in a plane. Exemplary “three-dimensional” information includes instantaneous or average velocity in space. Further examples include other representations of spatial information. Additionally, historical data of one or more types of location information, for example, historical data tracking position, motion, or instantaneous velocity over time, may be detected and / or stored.

[0046] In some embodiments, the input device 100 is a touchscreen interface that overlaps at least a portion of the display of the display device. For example, as illustrated in Figure 2, the input device 100 is shown overlapping the display of the display device 200. The display device 200 may include a display panel 210 that is communicatively coupled to a display driver 208 and a gate selection circuit 230. The display panel 210 may include display electrodes that are driven to update subpixels 226 of the display panel 210. In particular, the display electrodes may include data lines 222, gate lines 224 and / or emission control lines 223. In one embodiment, the display panel 210 is an organic light-emitting diode (OLED) display. In such an embodiment, the display panel 210 includes data lines 222, gate lines 224 and / or emission control lines 223. In other embodiments, the display panel 210 is a light-emitting device (LED). In this embodiment, the display panel 210 includes data lines 222 and gate lines 224, but does not include emission control lines 223.

[0047] The data line 222 may be coupled to the display driver 208, and the gate line 224 may be coupled to the gate selection circuit unit 230. Furthermore, the emission control line 223 may be coupled to the emission control circuit unit 240. Each of the subpixels 226 may be coupled to one of the gate lines 224 and one of the data lines 222. Furthermore, in one or more embodiments, each of the subpixels 226 is coupled to the emission control line 223.

[0048] The gate selection circuit 230 may be configured to apply gate selection and gate deselection signals to the gate line 224 to select (activate) and deselect (deactivate) the corresponding subpixel for updating. The gate selection signal may be a voltage gate high signal (Vgh), and the gate deselection signal may be a voltage gate low signal (Vgl). Driving the gate line 224 with the gate selection signal turns on one or more transistors of the subpixel 226 coupled to the driven gate line, selecting (e.g., turning on) the corresponding subpixel 226 for display updating. Driving the gate line 224 with the gate deselection signal turns off one or more transistors of the subpixel 226 coupled to the driven gate line, deselecting (e.g., turning off) the corresponding subpixel 226 for display updating. The gate selection and deselection signals may be voltage signals. The voltage level of the gate selection signal may be higher than the voltage level of the gate deselection signal. For example, the gate selection signal has a voltage level equal to or greater than the turn-on voltage of one or more transistors of the subpixel 226. Furthermore, the gate deselection signal has a voltage level lower than the turn-on voltage of one or more transistors in subpixel 226. In one embodiment, the gate selection signal has a voltage level of approximately 15V and the gate deselection signal has a voltage level of approximately -5V. In other embodiments, the gate selection signal has a voltage level higher or lower than 15V and / or the gate deselection signal has a voltage level higher or lower than -5V.

[0049] The gate selection circuit 230 may include one or more shift registers and one or more drivers. Furthermore, the gate selection circuit 230 may be communicatively coupled to the display driver 208 and receive control signals from the display driver 208 to control the selection and deselection of the gate line 224.

[0050] The emission control lines 223 are driven by the emission control circuit unit 240 to control the brightness of the subpixels 226. The emission control circuit unit 240 may include one or more shift registers and one or more drivers. The emission control circuit unit 240 applies emission control signals to the emission control lines 223. The emission control signals control the duty cycle of the subpixels 226 coupled to each of the emission control lines 223, thereby controlling the brightness of the subpixels 226.

[0051] The display driver 208 includes a display driver circuit configured to update the display of the display device 200 by driving a data line 222 with a subpixel data signal to update a selected subpixel 226. For example, the display driver 208 may apply a display update signal to the data line 222 during a corresponding display update period, which is part of the display frame. Furthermore, the display driver 208 transmits control signals to the gate selection circuit 230 and / or emission control circuit 240 to control the selection and deselection of the gate line 224 and the brightness of the subpixel 226.

[0052] The display driver 208 is configured to update the subpixels 226 during a display frame to update the image displayed on the display panel 210. Display frames are updated or refreshed approximately every 16ms, generating a display frame rate of approximately 60Hz. In other embodiments, other display frame rates may be used. For example, the display frame rate may be 90Hz, 120Hz, 140Hz, or higher.

[0053] During a display frame, each gate line 224 is selected sequentially and driven, for example, by a gate selection signal. For example, gate lines 224 may be selected sequentially during each display frame by sequentially driving the gate line 224 with gate selection signals and gate deselection signals in a common order. In one embodiment, gate lines 224 are selected sequentially from the first gate line 224 to the last gate line 224. The first gate line is close to the first side (end) of the display panel 210, and the last gate line is close to the second side (end) of the display panel 210, where the first end is opposite to the second end.

[0054] The display driver 208, the sensor circuit unit 104, and the detection module 106 may be part of a single processing system (for example, processing system 211). Alternatively, the display driver 208 may be part of a first processing system, and the sensor circuit unit 104 and the detection module 106 may be part of a second separate processing system. Furthermore, the display driver 208, the sensor circuit unit 104, and the detection module 106 may be part of a common IC chip. Alternatively, one or more of the display driver 208, the sensor circuit unit 104, and the detection module 106 may be provided on a first IC chip, and one or more other of the display driver 208, the sensor circuit unit 104, and the detection module 106 may be provided on a second IC chip.

[0055] In various embodiments, the sensor circuit 104 is configured to drive sensor electrodes for capacitance detection during capacitance frames at a certain capacitance frame rate. In one embodiment, each sensor electrode 105 is operated for absolute capacitance detection during each capacitance frame. Furthermore, each capacitance frame may comprise multiple periods during which different sensor electrodes 105 are operated for absolute capacitance detection.

[0056] The "capacitance frame rate" (the rate at which consecutive capacitance images are acquired) may be the same as or different from the "display frame rate" (the rate at which the display image is updated, including refreshing the screen to redisplay the same image). The capacity frame rate may be an integer multiple of the display frame rate, a fractional multiple of the display frame rate, a rational fraction of the display frame rate (e.g., 1 / 2, 2 / 3, 1 / 1, 3 / 2, 2 / 1, etc.), or any appropriate fraction or multiple of the display frame rate. In one or more embodiments, the display frame rate may vary while the capacity frame rate remains constant. In other embodiments, the display frame rate may remain constant even if the capacity frame rate is increased or decreased. Alternatively, the capacity frame rate may be asynchronous with the display frame rate, and the capacity frame rate may be an unreasonable fraction of the display frame rate to minimize interference "beat frequencies" between display updates and input detection.

[0057] Capacitance detection (or input detection) and display updates may occur during periods of at least partial overlap. For example, the sensor circuit 104 is configured to activate the sensor electrode 105 for capacitance detection while the display driver 208 activates the gate line 224 and data line 222 (and emission control line) to update the image displayed on the display panel 210. For example, the update of the display panel 210 and the activation of the sensor electrode 105 for capacitance detection may be asynchronous. Furthermore, the update of the display panel 210 and the activation of the sensor electrode 105 for capacitance detection may or may not be synchronized.

[0058] The updating of the display panel 210 and the operation of the sensor electrode 105 for capacitance detection may occur during periods that do not overlap. For example, the updating of the display panel 210 may occur during the display update period, and the operation of the sensor electrode 105 for capacitance detection may occur during the blank update period. The blank update period may be a blanking period that lies between the last line of a display frame and the first line of a subsequent display frame (e.g., during a vertical blanking period). Each display line corresponds to one or more gate lines 224 and subpixels 226 coupled to the gate lines 224. Furthermore, the blank update period may lie between display line update periods corresponding to two consecutive display lines in a display frame, and have at least the same temporal length as the display line update periods. In such embodiments, the blank update period may be called a long horizontal blanking period or a long h-blanking period, where the blanking period lies between two display line update periods in a display frame, and has at least the same length as the display line update periods.

[0059] Figure 3 shows a partial side view of an input device 100 and a display device 200 according to one or more embodiments. In the embodiment of Figure 3, the display panel 210 is an OLED display panel. However, in other embodiments, other types of displays (e.g., LCD or similar) may be used.

[0060] As illustrated, the display panel 210 comprises a substrate 328, subpixels 226, an organic material layer 330, a cathode electrode 340, a display layer 350, and a sealing layer 360. The cathode electrode 340 may be a sheet of resistive material configured to overlap the subpixels 226. The cathode electrode 340 is coupled to a display driver 208 and driven by the display driver 208 to supply a low-impedance reference voltage. In embodiments where the display panel 210 is an LCD panel, the cathode electrode 340 is replaced by a common voltage (Vcom) electrode layer. Furthermore, the cathode electrode 340 (or Vcom electrode layer) may be referred to as a reference electrode layer.

[0061] The substrate 328 may be a flexible substrate. Alternatively, the substrate 328 may be a rigid substrate. The display layer 350 may, in particular, include one or more polarizers and color filter glass. As shown, the sensor electrode 105 is provided on the sealing layer 360. In embodiments including a lens, the sensor electrode 105 may be provided on the lens instead of the sealing layer 360. The lens may be provided above the sealing layer 360, or in place of the sealing layer 360.

[0062] The wiring 150 is provided in the layer between the sensor electrode 105 and the display panel 210. Alternatively, the wiring 150 is provided in the layer of the display panel 210 between the substrate 328 and the sealing layer 360. In another embodiment, the wiring 150 is provided in the same layer as the sensor electrode 105.

[0063] As discussed above, since the sensor electrode 105 is located above the display panel 210, the display electrodes of the display panel 210 capacitively couple with the sensor electrode 105, which can introduce interference to the display panel 210 when capacitance detection is performed. By spatially isolating the sensor electrode 105, which is driven for capacitance detection (e.g., driven by an absolute capacitance detection signal or a transformer capacitance detection signal), from the gate line 224 selected for display updates, interference introduced to the display panel 210 during display updates can be mitigated, thereby reducing display distortion of the display panel 210.

[0064] Figure 4 is a simplified illustration of the sensor electrode 105 and a portion of the display panel 210. The sensor electrode 105 is virtually depicted so that the gate line 224 is visible. For the purpose of simplification, the data line 222, subpixel 226, and emission control line 223 are omitted. Furthermore, Figure 4 shows 36 gate lines (for example, gate lines 2241-224) 36Although the above is illustrated, other embodiments may include more than 36 gate lines. For example, the number of gate lines 224 may be in the thousands. Furthermore, as illustrated in the embodiment of Figure 4, each sensor electrode 105 overlaps with 3 gate lines. However, in other embodiments, each sensor electrode 105 may overlap with a different number of gate lines.

[0065] Figure 5 is a flowchart illustrating a method 500 for reducing display distortion due to interference introduced during capacitance detection, according to one or more embodiments. Method 500 will be described with reference to Figures 2, 4, 5, and 6. In operation 510, the sensor circuit 104 drives a first portion of the sensor electrodes of the sensor electrode 105 with a detection signal during a first period. The detection signal may be an absolute capacitance detection signal. Furthermore, the sensor circuit 104 acquires a corresponding result signal from each driven sensor electrode. For example, the sensor circuit 104 drives each sensor electrode of row 175 with an absolute capacitance detection signal during the first period and acquires a corresponding result signal from each driven sensor electrode. The first period corresponds to a first portion of the first capacitance frame. Furthermore, the first period corresponds to a first portion of the first display frame. Figure 6 illustrates a portion of the capacitance frame 600 (e.g., the first capacitance frame). The capacitance frame 600 overlaps at least a portion of the display frame. As illustrated, the capacitance frame 600 includes at least three periods during which capacitance detection is performed. For example, the capacitance frame 600 includes at least a first period, a second period, and a third period. In various embodiments, the capacitance frame 600 includes an additional period so that each of the sensor electrodes 105 is activated for absolute capacitance detection before the completion of the capacitance frame. The additional period may be before the first period, after the third period, and / or between the first, second, and third periods.

[0066] In operation 520, each sensor electrode of the second subset of sensor electrodes is driven by a guard signal during the first period. For example, the sensor circuit 104 drives each sensor electrode of row 173 with a guard signal during the first period. Alternatively, the sensor electrodes of row 173 are driven by a reference signal during the first period.

[0067] In operation 530, a third portion of the sensor electrodes of the sensor electrode 105 is driven by a reference signal (e.g., a DC signal) for the duration of the first period. A second portion of the sensor electrodes of the sensor electrode 105 is located between the first portion and the third portion of the sensor electrodes of the sensor electrode 105. Operation 530 includes driving each sensor electrode of the third row of the sensor electrode with a reference signal for the duration of the first period. For example, in one embodiment, the sensor electrodes of row 170 are driven by a reference signal by the sensor circuit 104 for the duration of the first period. The sensor electrodes of row 170 (e.g., the third portion of the sensor electrodes) overlap with a gate line 2241 selected for display updates during the first period. During the first period, a subpixel 226 coupled to the gate line 2241 is selected and driven by the corresponding data line 222 for display updates during the first period. During the first period, the sensor electrode 105 of row 170 is driven with a reference signal, thereby reducing interference coupled to the display panel 210 while the gate line 2241 is selected and the corresponding subpixel 226 is driven for display updating.

[0068] During the first period, driving the sensor electrode 105 of row 175 (e.g., a first portion of the sensor electrode 105) with an absolute capacitance detection signal, driving the sensor electrode 105 of row 173 (e.g., a second portion of the sensor electrode 105) with a guard signal, and driving the sensor electrode 105 of row 170 (e.g., a third portion of the sensor electrode 105) with a reference signal overlap with each other, at least in part. In other embodiments, during the first period, driving the sensor electrode 105 of row 175 (e.g., a first portion of the sensor electrode 105) with an absolute capacitance detection signal, driving the sensor electrode 105 of row 173 (e.g., a second portion of the sensor electrode 105) with a guard signal, and driving the sensor electrode 105 of row 170 (e.g., a third portion of the sensor electrode 105) with a reference signal occur simultaneously with each other.

[0069] In addition, the sensor circuit 104 drives the sensor electrodes of rows 174 and 176 with a guard signal during the first period. Rows 174 and 176 are adjacent to row 175 (for example, a first portion of the sensor electrodes of sensor electrode 105). For example, row 174 is located on the first side of row 175, and row 176 is located on the second side of row 175. Furthermore, during the first period, the sensor electrodes of rows 171-173 and 177-181 are driven with a guard signal or a reference signal.

[0070] As described above, Figure 6 illustrates a capacitance frame 600 that includes at least three periods (a first period, a second period, and a third period). However, in other embodiments, the capacitance frame 600 may include more than three periods. For example, additional periods may be after the third period, before the first period, between the first and second periods, and / or between the second and third periods. During each period, sensor electrodes 105 of one or more rows of rows 170-181 (e.g., one or more partial sensor electrodes) are driven by a detection signal (e.g., an absolute capacitance detection signal or a transformer capacitance detection signal), sensor electrodes 105 of one or more rows of rows 170-181 are driven by a guard signal or a reference signal, sensor electrodes 105 of one or more rows of rows 170-181 are driven by a reference signal, and sensor electrodes 105 of one or more rows of rows 170-181 are driven by a guard signal. Furthermore, during each of these periods (for example, the first period, the second period, and the third period), the sensor electrodes 105 of rows 170 to 181 adjacent to the sensor electrode 105 of the row driven by the detection signal are driven by a guard signal.

[0071] As illustrated in Figure 6, during the first period, the sensor electrode 105 in row 170 is driven by a reference signal, the sensor electrode 105 in row 175 is driven by a detection signal, and the sensor electrodes 105 in rows 174 and 176 are driven by guard signals. Furthermore, the sensor electrodes 105 in rows 171-173 and rows 177-181 are driven by either guard signals or reference signals. Alternatively, the sensor electrodes 105 in rows 171-173 and rows 177-181 are electrically floating so that the sensor electrodes 105 are not actively driven.

[0072] The display electrodes of the display panel 210 (e.g., data lines 222, gate lines 224) are driven to update the display panel 210. As disclosed above, the capacitive frame 600 overlaps at least a portion of the display frame. In one embodiment, the length of the capacitive frame 600 is the same as the length of the display frame. Alternatively, the length of the capacitive frame 600 is shorter than the length of the display frame. For example, the capacitive frame 600 starts during the display frame and completes before the end of the display frame.

[0073] During the first period, gate line 2241 is driven by a gate selection signal for updating the display panel 210. Furthermore, referring to Figure 4, the sensor electrode 105 of row 170 overlaps with (e.g., is positioned above) the gate line 2241. When the voltage of the detection signal or guard signal applied to the sensor electrode 105 changes, interference is introduced to the display electrodes (e.g., gate line 224, data line 222 and / or subpixel 226). For example, the sensor electrode 105 driven by the detection signal or guard signal may adversely affect the voltage of the selected subpixel 226 driven by the display update voltage via the data line 222. Thus, one or more subpixels 226 may be driven to an incorrect voltage, resulting in color and / or brightness distortion (e.g., display distortion) within the display panel 210. However, by driving the sensor electrode 105 of row 170 with a reference signal, the interference introduced to the display panel 210 can be reduced, thereby mitigating display distortion. For example, by driving (or holding) a sensor electrode 105 located above the gate line 224 selected for updating and the corresponding subpixel 226 with a reference signal, interference introduced to the display panel 210 is mitigated, and display distortion is beneficially reduced.

[0074] Referring further to Figure 6, during the second period of the capacitance frame 600, the sensor electrode 105 in row 176 (for example, a fourth portion of the sensor electrode 105) is driven by a detection signal for absolute capacitance detection. Furthermore, the sensor electrodes 105 in rows 175 and 177 are driven by a guard signal during the second period. The sensor electrode 105 in row 173 is driven by a reference signal. The sensor electrodes 105 in rows 170-172, 174, and / or 178-181 are driven by either a guard signal or a reference signal.

[0075] The second period follows the first period. Furthermore, during the second period, gate line 2247 is selected for display updates. The sensor electrode 105 of line 173 is positioned above (e.g., overlapping) gate line 2247, and by driving the sensor electrode 105 of line 173 with a reference signal, interference introduced to the display panel 210 during updates is mitigated, and display distortion is beneficially reduced.

[0076] During the third period of the capacitance frame 600, the sensor electrode 105 of row 173 (for example, a second portion of the sensor electrode 105) is driven by a detection signal for absolute capacitance detection. Furthermore, the sensor electrodes 105 of rows 172 and 174 are driven by a guard signal during the second period. The sensor electrode 105 of row 175 is driven by a reference signal. The sensor electrodes 105 of rows 170-171 and / or rows 176-181 are driven by a guard signal or a reference signal.

[0077] The third period follows the second period. Furthermore, during the third period, gate line 224 16 This is selected for display update. The sensor electrode 105 of row 175 is connected to gate line 224 16 By positioning it above (for example, overlapping) and driving the sensor electrode 105 of row 175 with a reference signal, interference introduced to the display panel 210 during updates is mitigated, and display distortion is beneficially reduced.

[0078] As described above, the capacity frame 600 overlaps at least partially with the first display frame. During the first display frame, the gate lines 224 may be selected according to a first order. For example, during the first display frame, the gate lines 224 may be selected from the first gate line of gate line 224 (e.g., gate line 2241) to the last gate line of gate line 224 (e.g., gate line 2241). 36 ) are selected consecutively. However, in other embodiments, other orders may be used. For example, gate line 224 36The gate line 224 is selected first, and gate line 2241 is selected last. In other embodiments, the gate line 224 selected first may be any gate line, as long as each gate line 224 is selected during the display frame. The order in which the gate lines 224 are selected may be predetermined. For example, the order in which the gate lines 224 are selected may be determined during the design and / or manufacture of the display panel 210. Furthermore, the order in which the gate lines 224 are selected may be stored, for example, in the display driver 208.

[0079] The order in which the sensor electrodes 105 in rows 170-181 are driven by the detection signal (activated for capacitance detection) may differ from the order in which the gate lines 224 are selected for display updates. For example, the order in which the sensor electrodes 105 in rows 170-181 are driven by the detection signal may be determined such that, at any given time, the sensor electrodes 105 driven by the detection signal are not above (e.g., not overlapping) the gate lines 224 selected for display updates. In one embodiment, the order in which the sensor electrodes 105 are selected is non-sequential. For example, the order in which the gate lines 224 are selected is sequential for the first and second sides of the input device (e.g., input device 100), but the order in which rows 170-181 of the sensor electrodes 105 are driven by the detection signal is non-sequential for the first and second sides of the input device.

[0080] The order in which rows 170-181 of the sensor electrode 105 are driven may be determined based on the order in which the gate lines 224 are driven. For example, the order in which rows 170-181 of the sensor electrode 105 are driven may be determined such that the rows of the sensor electrode 105 driven by the detection signal do not overlap with the gate lines 224 selected for display updates.

[0081] Each of rows 170-181 of the sensor electrode 105 that were not driven by a detection signal during the first, second, and third periods may be driven during the other periods such that each of rows 170-181 is driven during one of the other periods of the capacitive frame 600. Furthermore, during each period of the capacitive frame 600, the sensor electrode 105 that overlaps with the gate line 224 selected to update the display panel 210 may be driven by a reference signal.

[0082] Figure 7 illustrates rows 770-777 and gate line 224. Rows 770-777 are configured similarly to rows 170-181 in Figure 2. For example, each of rows 770-777 has one or more sensor electrodes 105, similar to those in rows 170-181 in Figure 2. Each of rows 770-777 may be a part of the sensor electrode 105.

[0083] As illustrated in Figure 7, rows 770 to 777 overlap with gate line 224. For example, row 770 overlaps with gate line 224a, row 771 overlaps with gate line 224b, row 772 overlaps with gate line 224c, and so on.

[0084] Figures 8A-8B illustrate an exemplary capacitance frame 800 having eight periods. In other embodiments, the capacitance frame 800 may include more or fewer than eight periods. The number of periods in the capacitance frame 800 may correspond to the number of rows of sensor electrodes 105. Figures 8A-8B will be described below in relation to Figures 2 and 7.

[0085] During each period of the capacitive frame 800 (for example, periods 1 to 8), the sensor electrodes of the first row of rows 770 to 777 are driven by a detection signal, and the sensor electrodes of one or more rows adjacent to the first row are driven by a guard signal. Furthermore, during each period of the capacitive frame 800, the sensor electrodes of one or more second rows of rows 770 to 777 are driven by a guard signal or a reference signal, and the sensor electrodes of one or more third rows of rows 770 to 777 are driven by a reference signal. The sensor electrodes of the one or more third rows 770 to 777 overlap the gate lines 224 selected for display updates. The sensor electrodes of rows 770 to 777 driven by the detection signal, guard signal, and reference signal may differ from period to period. Furthermore, for at least two consecutive periods, the corresponding rows 770 to 777 driven by the detection signal are non-sequential. For example, as will be explained in more detail below, during the sixth period, the sensor electrode of row 777 is driven by the detection signal, and during the seventh period, the sensor electrode of row 770 is driven by the detection signal. Furthermore, for at least two consecutive periods, the corresponding rows 770-777 are driven by the reference signal consecutively. For example, from the first period to the eighth period, rows 770-777 are driven sequentially by the reference signal.

[0086] During the first period of the capacitive frame (e.g., detection frame) 800, the sensor circuit unit 104 drives the sensor electrode 105 of row 770 with a reference signal and drives the sensor electrodes 105 of rows 774 to 777 with a guard signal or a reference signal. Furthermore, during the first period of the capacitive frame 800, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 771 and 773 with a guard signal and drives the sensor electrode 105 of row 772 with a detection signal. In addition, during the first period of the capacitive frame 800 and during the first display frame, gate lines 224a are selected for updating the display panel 210. The gate lines 224a are selected sequentially for updating the display panel 210 during the first period of the capacitive frame 800.

[0087] During the second period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 771 with a reference signal and drives the sensor electrodes 105 of rows 770 and 775-777 with a guard signal or a reference signal. Furthermore, during the second period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrodes 105 of rows 772 and 774 with a guard signal and drives the sensor electrode 105 of row 773 with a detection signal. In addition, during the second period of the capacitive frame 800 and the first display frame, gate lines 224b are selected for updating the display panel 210. Gate lines 224b are sequentially selected to update the display panel 210 during the second period of the capacitive frame 800.

[0088] During the third period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 772 with a reference signal and drives the sensor electrodes 105 of rows 770-771 and 776-777 with a guard signal or a reference signal. Furthermore, during the third period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrodes 105 of rows 773 and 775 with a guard signal and drives the sensor electrode 105 of row 774 with a detection signal. In addition, during the third period of the capacitive frame 800 and during the first display frame, gate lines 224c are selected for updating the display panel 210. The gate lines 224c are sequentially selected for updating the display panel 210 during the third period of the capacitive frame 800.

[0089] During the fourth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 773 with a reference signal and drives the sensor electrodes 105 of rows 770-773 and 777 with a guard signal or a reference signal. Furthermore, during the fourth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrodes 105 of rows 774 and 776 with a guard signal and drives the sensor electrode 105 of row 775 with a detection signal. In addition, during the fourth period of the capacitive frame 800 and during the first display frame, gate line 224d is selected for updating the display panel 210. Gate line 224d is selected sequentially for updating the display panel 210 during the fourth period of the capacitive frame 800.

[0090] During the fifth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 774 with a reference signal and drives the sensor electrodes 105 of rows 770 to 773 with a guard signal or a reference signal. Furthermore, during the fifth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrodes 105 of rows 775 and 777 with a guard signal and drives the sensor electrode 105 of row 776 with a detection signal. In addition, during the fifth period of the capacitive frame 800 and during the first display frame, gate lines 224e are selected for updating the display panel 210. The gate lines 224e are sequentially selected for updating the display panel 210 during the fifth period of the capacitive frame 800.

[0091] During the sixth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 775 with a reference signal and drives the sensor electrodes 105 of rows 770 to 774 with a guard signal or a reference signal. Furthermore, during the sixth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 776 with a guard signal and drives the sensor electrode 105 of row 777 with a detection signal. In addition, during the sixth period of the capacitive frame 800 and during the first display frame, gate line 224f is selected for updating the display panel 210. Gate line 224f is selected sequentially for updating the display panel 210 during the sixth period of the capacitive frame 800.

[0092] During the seventh period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 776 with a reference signal and drives the sensor electrodes 105 of rows 772-775 and 777 with a guard signal or a reference signal. Furthermore, during the seventh period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 771 with a guard signal and drives the sensor electrode 105 of row 770 with a detection signal. In addition, during the seventh period of the capacitive frame 800 and during the first display frame, gate lines 224g are selected for updating the display panel 210. The gate lines 224g are sequentially selected for updating the display panel 210 during the seventh period of the capacitive frame 800.

[0093] During the eighth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrode 105 of row 777 with a reference signal and drives the sensor electrodes 105 of rows 773-776 with a guard signal or a reference signal. Furthermore, during the eighth period of the capacitive frame 800, the sensor circuit 104 drives the sensor electrodes 105 of rows 770 and 772 with a guard signal and drives the sensor electrode 105 of row 771 with a detection signal. In addition, during the eighth period of the capacitive frame 800 and during the first display frame, gate line 224h is selected for updating the display panel 210. Gate line 224h is selected sequentially for updating the display panel 210 during the eighth period of the capacitive frame 800.

[0094] In the embodiments of Figures 8A and 8B, the capacitive frame rate and the display frame rate are the same. Therefore, between the capacitive frame 800 and the corresponding display frame, all of the sensor electrodes 105 are activated for input detection (e.g., driven by a detection signal), and the display panel 210 is updated. In other embodiments, the capacitive frame rate may be higher than the display frame rate. For example, as described in relation to Figures 9A1, 9A2, 9B1, and 9B2, at least a portion of each of the capacitive frames 910 and 920 may be in a common display frame. The embodiments of Figures 9A1, 9A2, 9B1, and 9B2 are described in relation to Figures 2 and 7.

[0095] As described in relation to the capacitive frame 800 in Figures 8A and 8B, during each period of the capacitive frame 910 or 920 (e.g., period 1 to period 8), the sensor electrodes of the first row of rows 770 to 777 are driven by a detection signal, and the sensor electrodes 105 of one or more rows adjacent to the first row are driven by a guard signal. Furthermore, during each period of the capacitive frame 910 or 920, the sensor electrodes of one or more second rows of rows 770 to 777 are driven by a guard signal or a reference signal, and the sensor electrodes of one or more third rows of rows 770 to 777 are driven by a reference signal. The sensor electrodes of the one or more third rows 770 to 777 overlap with gate lines 224 selected for display updates.

[0096] As described above in relation to Figures 8A and 8B, the sensor electrodes of rows 770-777, driven by the detection signal and guard signal, differ from period to period. Furthermore, for at least two consecutive periods, the corresponding rows 770-777 driven by the detection signal are non-sequential. For example, as will be described in more detail below, row 777 is driven by the detection signal during the sixth period, and row 770 is driven by the detection signal during the seventh period. Capacitance frames 910 and / or 920 differ from capacitive frame 800 in that the sensor electrodes of the same row are driven by the reference signal for at least two consecutive periods of capacitive frames 910 and 920. For example, during the first and second periods of capacitive frame 910, the sensor electrode of row 771 is driven by the reference signal. Furthermore, during two other consecutive periods, the sensor electrodes of consecutive rows are driven by the reference signal. For example, during the second period of the capacitance frame 910, the sensor electrode in row 771 is driven by a reference signal, and during the third period of the capacitance frame 910, the sensor electrode in row 772 is driven by a reference signal.

[0097] During the first period of the capacitive frame (e.g., detection frame) 910, the sensor circuit unit 104 drives the sensor electrode 105 of row 771 with a reference signal and drives the sensor electrodes 105 of rows 770 and 775-777 with a guard signal or reference signal. Furthermore, during the first period of the capacitive frame 910, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 772 and 774 with a guard signal and drives the sensor electrode 105 of row 773 with a detection signal. In addition, during the first period of the capacitive frame 910 and during the first display frame, one or more of the first gate lines of the gate lines 224b are sequentially selected for updating the display panel 210.

[0098] During the second period of the capacitive frame 910, the sensor circuit unit 104 drives the sensor electrode 105 of row 771 with a reference signal and drives the sensor electrodes 105 of rows 770, 772 and 776-777 with a guard signal or a reference signal. Furthermore, during the second period of the capacitive frame 910, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 773 and 775 with a guard signal and drives the sensor electrode 105 of row 774 with a detection signal. In addition, during the second period of the capacitive frame 910 and during the first display frame, one or more second gate lines of the gate lines 224b are sequentially selected for updating the display panel 210.

[0099] During the third period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 772 with a reference electrode and drives the sensor electrodes 105 of rows 770-771, 773, and 777 with a guard signal or a reference signal. Furthermore, during the third period of the capacitive frame 910, the sensor electrodes 105 of rows 774 and 776 are driven with a guard signal and the sensor electrode 105 of row 775 is driven with a detection signal. In addition, during the third period of the capacitive frame 910 and during the first display frame, one or more of the first gate lines of the gate lines 224c are sequentially selected for updating the display panel 210.

[0100] During the fourth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 772 with a reference signal and drives the sensor electrodes 105 of rows 770-771 and 773-774 with a guard signal or a reference signal. Furthermore, during the fourth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrodes 105 of rows 775 and 777 with a guard signal and drives the sensor electrode 105 of row 776 with a detection signal. In addition, during the fourth period of the capacitive frame 910 and during the first display frame, one or more second gate lines of the gate lines 224c are sequentially selected for updating the display panel 210.

[0101] During the fifth period of the capacitive frame 910, the sensor circuit unit 104 drives the sensor electrode 105 of row 773 with a reference signal and drives the sensor electrodes 105 of rows 770-772 and 774-775 with a guard signal or a reference signal. Furthermore, during the fifth period of the capacitive frame 910, the sensor circuit unit 104 drives the sensor electrode 105 of row 776 with a guard signal and drives the sensor electrode 105 of row 777 with a detection signal. In addition, during the fifth period of the capacitive frame 910 and during the first display frame, one or more of the first gate lines of the gate lines 224d are sequentially selected for updating the display panel 210.

[0102] During the sixth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 773 with a reference signal and drives the sensor electrodes 105 of rows 772 and 774-777 with a guard signal or a reference signal. Furthermore, during the sixth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 771 with a guard signal and drives the sensor electrode 105 of row 770 with a detection signal. In addition, during the sixth period of the capacitive frame 910 and during the first display frame, one or more second gate lines of the gate lines 224d are sequentially selected for updating the display panel 210.

[0103] During the seventh period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 774 with a reference signal and drives the sensor electrodes 105 of rows 773 and 775-777 with a guard signal or a reference signal. Furthermore, during the seventh period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrodes 105 of rows 770 and 772 with a guard signal and drives the sensor electrode 105 of row 771 with a detection signal. In addition, during the seventh period of the capacitive frame 910 and during the first display frame, one or more of the first gate lines of gate line 224e are sequentially selected for updating the display panel 210.

[0104] During the eighth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrode 105 of row 774 with a reference signal and drives the sensor electrodes 105 of rows 770 and 775-777 with a guard signal or a reference signal. Furthermore, during the eighth period of the capacitive frame 910, the sensor circuit 104 drives the sensor electrodes 105 of rows 771 and 773 with a guard signal and drives the sensor electrode 105 of row 772 with a detection signal. In addition, during the eighth period of the capacitive frame 910 and during the first display frame, one or more second gate lines of the gate lines 224e are sequentially selected for updating the display panel 210.

[0105] Capacity frame (e.g., detection frame) 920 begins after the completion of capacity frame 910. Furthermore, at least a portion of capacity frame 920 overlaps with the same display frame over which capacity frame 910 overlaps. As will be described in more detail below, periods 1 through 6 of capacity frame 920 overlap with the first display frame (e.g., are in the first display frame), and periods 7 and 8 of capacity frame 920 overlap with the second display frame (e.g., are in the second display frame). The second display frame follows the first display frame.

[0106] During the first period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 775 with a reference signal and drives the sensor electrodes 105 of rows 770 to 774 with a guard signal or a reference signal. Furthermore, during the first period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 776 with a guard signal and drives the sensor electrode 105 of row 777 with a detection signal. In addition, during the first period of the capacitance frame 920 and during the first display frame, one or more of the first gate lines of the gate lines 224f are sequentially selected for updating the display panel 210.

[0107] During the second period of the capacitive frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 775 with a reference signal and drives the sensor electrodes 105 of rows 772-774 and 776-777 with a guard signal or a reference signal. Furthermore, during the second period of the capacitive frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 771 with a guard signal and drives the sensor electrode 105 of row 770 with a detection signal. In addition, during the second period of the capacitive frame 920 and during the first display frame, one or more second gate lines of the gate lines 224f are sequentially selected for updating the display panel 210.

[0108] During the third period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 776 with a reference signal and drives the sensor electrodes 105 of rows 773-775 and 777 with a guard signal or a reference signal. Furthermore, during the third period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 770 and 772 with a guard signal and drives the sensor electrode 105 of row 771 with a detection signal. In addition, during the third period of the capacitance frame 920 and during the second display frame, one or more of the first gate lines of the gate lines 224g are sequentially selected for updating the display panel 210.

[0109] During the fourth period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 776 with a reference signal and drives the sensor electrodes 105 of rows 770, 774-775, and 777 with a guard signal or a reference signal. Furthermore, during the fourth period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 771 and 773 with a guard signal and drives the sensor electrode 105 of row 772 with a detection signal. In addition, during the fourth period of the capacitance frame 920 and during the first display frame, one or more second gate lines of the gate lines 224g are sequentially selected for updating the display panel 210.

[0110] During the fifth period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrode 105 of row 777 with a reference signal and drives the sensor electrodes 105 of rows 770-772 and 775-776 with a guard signal or a reference signal. Furthermore, during the fifth period of the capacitance frame 920, the sensor circuit unit 104 drives the sensor electrodes 105 of rows 772 and 774 with a guard signal and drives the sensor electrode 105 of row 773 with a detection signal. In addition, during the fifth period of the capacitance frame 920 and during the first display frame, one or more of the first gate lines of the gate lines 224h are sequentially selected for updating the display panel 210.

[0111] During the sixth period of the capacitive frame 920, the sensor circuit 104 drives the sensor electrode 105 of row 777 with a reference signal and drives the sensor electrodes 105 of rows 770-772 and 776 with a guard signal or a reference signal. Furthermore, during the sixth period of the capacitive frame 920, the sensor circuit 104 drives the sensor electrodes 105 of rows 773 and 775 with a guard signal and drives the sensor electrode 105 of row 774 with a detection signal. In addition, during the sixth period of the capacitive frame 920 and during the first display frame, one or more second gate lines of the gate lines 224h are sequentially selected for updating the display panel 210.

[0112] During the seventh period of the capacitance frame 920, the sensor circuit 104 drives the sensor electrode 105 of row 770 with a reference signal and drives the sensor electrodes 105 of rows 771-773 and 777 with a guard signal or a reference signal. Furthermore, during the seventh period of the capacitance frame 920, the sensor circuit 104 drives the sensor electrodes 105 of rows 774 and 776 with a guard signal and drives the sensor electrode 105 of row 775 with a detection signal. In addition, during the seventh period of the capacitance frame 920 and during the second display frame, one or more of the first gate lines of gate line 224a are sequentially selected for updating the display panel 210. The second display frame follows the first display frame.

[0113] During the eighth period of the capacitance frame 920, the sensor circuit 104 drives the sensor electrode 105 of row 770 with a reference signal and drives the sensor electrodes 105 of rows 771 to 774 with a guard signal or a reference signal. Furthermore, during the eighth period of the capacitance frame 920, the sensor circuit 104 drives the sensor electrodes 105 of rows 775 and 777 with a guard signal and drives the sensor electrode 105 of row 776 with a detection signal. In addition, during the eighth period of the capacitance frame 920 and during the second display frame, one or more second gate lines of gate line 224a are sequentially selected for updating the display panel 210.

[0114] In the embodiments shown in Figures 9A1, 9A2, 9B1, and 9B2, the order in which rows 770-777 are driven by the detection signal differs between capacitive frames 910 and 920. Furthermore, the order in which rows 770-777 are driven by the reference signal and / or guard signal also differs between capacitive frames 910 and 920. As illustrated in Figures 9A1, 9A2, 9B1, and 9B2, the order in which rows 770-777 are driven is non-sequential.

[0115] During each period of capacitive frames 800, 910, and 920, one row (e.g., 770-777) of sensor electrodes 105 is driven by a reference signal. In other embodiments, during one or more periods of capacitive frames 800, 910, and 920, two or more rows (e.g., 770-777) of sensor electrodes 105 are driven by a reference signal. These two or more rows of sensor electrodes 105 are driven sequentially by a reference signal during a common period of the capacitive frames (e.g., capacitive frames 800, 910, and 920). Such embodiments may be used during periods of capacitive frames in which gate lines 224 where sensor electrodes 105 of two different rows overlap are selected for updating the display panel 210. For example, during periods in which one or more gate lines among gate lines 224a and 224b are selected for updating the display panel 210, the sensor electrodes 105 of rows 770 and 771 are driven by a reference signal. Furthermore, in the embodiments of Figures 9A1, 9A2, 9B1, and 9B2, two capacitive frames are in a common display frame (e.g., overlapping), but in other embodiments, more than two capacitive frames may be in a common display frame. The more capacitive frames there are in a single display frame, the greater the capacitive frame rate relative to the display frame. Additionally, rows 770-777 may be driven in a different order than those shown in Figures 8 and 9, as long as the row driven by the reference signal overlaps with the gate line 224 selected for updating.

[0116] Capacity frames 910 and 920 may be used as the corresponding capacity frame type and may be repeated while the display panel 210 is being updated. For example, each of capacity frames 910 and 920 may appear multiple times while the display panel 210 is being updated.

[0117] Figure 10 is an exemplary timing diagram illustrating an embodiment in which the capacitive frame rate (e.g., detection frame rate or capacitive detection frame rate) is higher than the display frame rate. For example, capacitive frames 910 and 920 are in display frame 1020. Furthermore, Figure 10 illustrates multiple capacitive frames 920. As illustrated, one capacitive frame 920 is in display frames 1020 and 1022. In such an example, we could say that the capacitive frame 920 spans display frames 1020 and 1022. Between each of display frames 1020 and 1022, gate lines (e.g., gate line 224 in Figure 2) are driven in the order of gate line 1 to gate line N, where N is greater than 1.

[0118] A display control signal 1010 is used to initiate the updating of the display frame. The display control signal 1010 may also be a vertical synchronization (or Vsync) signal. Additionally, referring to Figure 2, the display control signal 1010 is used by the display driver 208 to initiate the updating of the display panel 210. The display frame is initiated (e.g., started) based on the Vsync signal. For example, depending on the rising or falling edge of the display control signal 1010, the control signal is sent from the display driver 208 to the gate selection circuit 230 to initiate the selection of the gate line 224. Furthermore, the display driver 208 initiates the application of a display update signal to the data line 222 based on the rising or falling edge of the display control signal 1010. The display control signal 1010 is sent from the display driver 208 to the sensor circuit 104 to initiate (e.g., start) input detection (e.g., driving a detection signal) using the sensor electrode 105 during the capacitive frame. A delay 1030 is inserted between the rising or falling edge of the display control signal 1010 and the start of the capacitive frame 910. The delay 1030 is used to align the timing of the capacitance frames 910 and 920 with the selection of the gate lines 224 of the display frames 1020 and 1022. Furthermore, during the delay 1030, the sensor circuit 104 can prepare to drive the sensor electrode 105 with the detection signal. Delaying the start of the capacitance frame 910 by the delay 1030 beneficially improves the timing of driving the sensor electrode 105 between the capacitance frames 910 and 920 by referencing the timing of selecting the gate lines (e.g., gate lines 224 in Figure 2) for display updates, thereby mitigating display distortion. Furthermore, in one or more embodiments, delaying the start of the capacitance frame 910 by the delay 1030 causes the capacitance frame 920 to overlap with multiple display frames (e.g., display frames 1020 and 1022), further mitigating interference caused by driving the sensor electrode 105 for capacitance detection.

[0119] In the embodiment shown in Figure 10, the capacity frame 920 spans multiple display frames (e.g., display frames 1020 and 1022), but in other embodiments, both capacity frames 910 and 920 may begin and end within a single display frame (e.g., display frame 1020). Furthermore, the capacity frame 920 may overlap with portions of display frames 1020 and 1022 that are not shown in Figure 10.

[0120] Thus, the embodiments and examples described herein are presented to best illustrate embodiments of the Art and their specific applications, enabling those skilled in the art to manufacture and use the disclosed products. However, those skilled in the art will recognize that the foregoing descriptions and examples are provided for illustrative purposes only. The descriptions provided are not intended to be exhaustive, nor are they intended to limit the disclosure to the disclosed form.

[0121] In the aforementioned regard, the technical scope of this disclosure is determined by the subsequent claims.

Claims

1. A processing system for an input device, During the first detection frame, the sensor circuit section is configured to activate multiple sensor electrodes for absolute capacitance detection. Equipped with, The sensor circuit unit, during the first period in which the absolute capacity detection and the display panel update are performed simultaneously, A first portion of the plurality of sensor electrodes is driven by a detection signal to obtain a result signal from the first portion of sensor electrodes, the absolute capacitance detection is based on the result signal, and the first portion of sensor electrodes overlap with one or more gate lines of the display panel that are not selected for the display update during the first period. A second portion of the aforementioned plurality of sensor electrodes is driven by a guard signal. A third portion of the aforementioned plurality of sensor electrodes is driven by a reference signal. It is configured in such a way, The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. Some of the third of the plurality of sensor electrodes overlap one or more gate lines of the display panel selected for the display update during the first period. Processing system.

2. The second portion of the sensor electrode is located between the first portion of the sensor electrode and the third portion of the sensor electrode. The processing system according to claim 1.

3. The sensor circuit section operates during the second period of the first detection frame. The first part of the sensor electrodes and the third part of the sensor electrodes are driven by the guard signal. The second set of sensor electrodes are driven by the reference signal, A fourth portion of the aforementioned plurality of sensor electrodes is driven by the detection signal. It is configured in such a way, The second portion of the sensor electrodes overlaps with the second gate line of the display panel selected for updating during the second period. The second period follows the first period. The processing system according to claim 1.

4. The sensor circuit unit operates during the third period of the first detection frame. The first part of the sensor electrodes is driven by the reference signal, The second part of the sensor electrodes is driven by the detection signal, The third portion of the sensor electrodes and the fourth portion of the sensor electrodes are driven by the guard signal. It is further configured in this way, The first portion of the sensor electrodes overlaps with the third gate line of the display panel selected for updating during the third period. The third period follows the second period. The processing system according to claim 3.

5. The plurality of sensor electrodes are operated in a first sequence for absolute capacitance detection during the first detection frame. The aforementioned plurality of sensor electrodes are operated in a second sequence for absolute capacitance detection during the second detection frame. The first order is different from the second order. The processing system according to claim 1.

6. A processing system for an input device, During the first detection frame, the sensor circuit section is configured to activate multiple sensor electrodes for input detection. Equipped with, The sensor circuit unit operates during the first period of the first detection frame. A first portion of the multiple sensor electrodes is driven by a detection signal. A second portion of the aforementioned plurality of sensor electrodes is driven by a guard signal. A third portion of the aforementioned plurality of sensor electrodes is driven by a reference signal. It is configured in such a way, The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. Some of the third of the plurality of sensor electrodes overlap the first gate line of the display panel selected for updating during the first period. The plurality of sensor electrodes are operated in a first sequence for input detection during the first detection frame. The aforementioned plurality of sensor electrodes are operated in a second sequence for input detection during the second detection frame. The first order is different from the second order, The first detection frame is in the first display frame, The second detection frame is present in the first display frame and the second display frame. Between the first display frame and the second display frame, the display panel is updated. Processing system.

7. A processing system for an input device, During the first detection frame, the sensor circuit section is configured to activate multiple sensor electrodes for input detection. Equipped with, The sensor circuit unit operates during the first period of the first detection frame. A first portion of the multiple sensor electrodes is driven by a detection signal. A second portion of the aforementioned plurality of sensor electrodes is driven by a guard signal. A third portion of the aforementioned plurality of sensor electrodes is driven by a reference signal. It is configured in such a way, The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. Some of the third of the plurality of sensor electrodes overlap the first gate line of the display panel selected for updating during the first period. The plurality of sensor electrodes are operated in a first sequence for input detection during the first detection frame. The aforementioned plurality of sensor electrodes are operated in a second sequence for input detection during the second detection frame. The first order is different from the second order, The first detection frame is in the first display frame, The second detection frame is in the first display frame, The third detection frame is present in the first display frame and the second display frame. Between the first display frame and the second display frame, the display panel is updated. Processing system.

8. The sensor circuit is further configured to start driving the first detection frame based on a display update signal that instructs the start of a display frame. The start of the first detection frame is delayed from the start of the display frame. The processing system according to claim 1.

9. Multiple sensor electrodes, A processing system coupled to the plurality of sensor electrodes and configured to operate the plurality of sensor electrodes for absolute capacitance detection during the first detection frame, Equipped with, The processing system operates during the first period in which the absolute capacity detection and the display panel update of the first detection frame are performed simultaneously. A first portion of the plurality of sensor electrodes is driven by a detection signal to obtain a result signal from the first portion of sensor electrodes, the absolute capacitance detection is based on the result signal, and the first portion of sensor electrodes overlap with one or more gate lines of the display panel that are not selected for the display update during the first period. A second portion of the aforementioned plurality of sensor electrodes is driven by a guard signal. A third portion of the aforementioned plurality of sensor electrodes is driven by a reference signal. It is configured in such a way, The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. Some of the third of the plurality of sensor electrodes overlap one or more gate lines of the display panel selected for the display update during the first period. Input device.

10. During a first period in the first detection frame in which absolute capacitance detection and display panel display updating are performed simultaneously, a first portion of the sensor electrodes among a plurality of sensor electrodes is driven by a detection signal to obtain a result signal from the first portion of sensor electrodes, the absolute capacitance detection is based on the result signal, and the first portion of sensor electrodes overlap with one or more gate lines of the display panel that are not selected for the display updating during the first period. During the first period, a second portion of the multiple sensor electrodes is driven by a guard signal, During the first period, a third portion of the sensor electrodes among the plurality of sensor electrodes are driven by a reference signal, Includes, The guard signal and the detection signal share at least one characteristic selected from the group consisting of amplitude, phase, and frequency. Some of the third of the plurality of sensor electrodes overlap one or more gate lines of the display panel selected for the display update during the first period. method.

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