Nitride semiconductor equipment

Abstract

To provide a nitride semiconductor device capable of reducing an operating resistance value.SOLUTION: A nitride semiconductor device 10 includes: a substrate 12; a drift layer 14 with a first conductivity type; a first base layer 16 formed over the drift layer 14; a second base layer 18 with a second conductivity type formed above the first base layer 16; an electron transport layer 28 formed above the second base layer 18 and in portion along an inner surface of a gate opening 24; and an electronic supply layer 30 formed above the electron transport layer 28 covering the gate opening 24.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This disclosure relates to nitride semiconductor devices. [Background technology]

[0002] Nitride semiconductors such as GaN (gallium nitride) are wide-bandgap semiconductors with a large bandgap, a high dielectric breakdown field, and a higher electron saturation drift rate compared to GaAs (gallium arsenide) semiconductors or Si (silicon) semiconductors. For these reasons, research and development of power transistors using nitride semiconductors, which are advantageous for high power output and high breakdown voltage, is being conducted.

[0003] For example, Patent Document 1 discloses a semiconductor device formed on a GaN-based laminate. The semiconductor device described in Patent Document 1 is a vertical field-effect transistor (FET) comprising a regrowth layer positioned to cover an opening provided in the GaN-based laminate, and a gate electrode positioned on the regrowth layer along the regrowth layer. A channel is formed by two-dimensional electron gas (2DEG) generated in the regrowth layer, realizing an FET with high mobility and low on-resistance. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2011-82397 [Overview of the project] [Problems that the invention aims to solve]

[0005] However, in the field-effect transistor described in Patent Document 1, the current flows only directly below the opening and does not diffuse laterally. This leads to the problem that the resistance value of the field-effect transistor becomes large when it is in operation.

[0006] Therefore, this disclosure provides a nitride semiconductor device that can reduce the resistance value during operation. [Means for solving the problem]

[0007] To solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure comprises: a substrate having a first main surface and a second main surface opposite to the first main surface; a first electron transport layer having a first conductivity type provided above the first main surface; a first electron supply layer provided above the first electron transport layer; a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron supply layer; a second electron transport layer provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of a first opening that penetrates the first electron supply layer and the first nitride semiconductor layer and reaches the first electron transport layer; and a second electron supply layer provided above the second electron transport layer and covering the first opening.

[0008] Furthermore, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface; a first electron transport layer having a first conductivity type provided above the first main surface; a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron transport layer; a second electron transport layer provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of a first opening that penetrates the first electron supply layer and the first nitride semiconductor layer and reaches the first electron transport layer; and an electron supply layer provided above the second electron transport layer and covering the first opening. The first electron transport layer includes a third nitride semiconductor layer having the first conductivity type and a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer and having a higher impurity concentration than the third nitride semiconductor layer. [Effects of the Invention]

[0009] According to the nitride semiconductor device of the present disclosure, the resistance value during operation can be reduced.

Brief Description of the Drawings

[0010] [Figure 1] FIG. 1 is a plan view showing a planar layout of a nitride semiconductor device according to Embodiment 1. [Figure 2] FIG. 2 is a cross-sectional view of a nitride semiconductor device according to Embodiment 1. [Figure 3A] FIG. 3A is a cross-sectional view showing a nitride semiconductor stacking process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 3B] FIG. 3B is a cross-sectional view showing a resist patterning process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 3C] FIG. 3C is a cross-sectional view showing a gate opening formation process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 3D] FIG. 3D is a cross-sectional view showing a nitride semiconductor regrowth process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 3E] FIG. 3E is a cross-sectional view showing a gate electrode formation process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 3F] FIG. 3F is a cross-sectional view showing a source opening formation process in the manufacturing method of the nitride semiconductor device according to Embodiment 1. [Figure 4] FIG. 4 is a cross-sectional view of a nitride semiconductor device according to Modification 1. [Figure 5A] FIG. 5A is a cross-sectional view showing a resist patterning process for a mask during ion implantation in the manufacturing method of the nitride semiconductor device according to Modification 1. [Figure 5B] FIG. 5B is a cross-sectional view showing an ion implantation process in the manufacturing method of the nitride semiconductor device according to Modification 1. [Figure 6] FIG. 6 is a cross-sectional view of a nitride semiconductor device according to Modification 2. [Figure 7]Figure 7 is a cross-sectional view of the nitride semiconductor device according to Embodiment 2. [Figure 8] Figure 8 is a cross-sectional view of the nitride semiconductor device according to Embodiment 3. [Modes for carrying out the invention]

[0011] (Summary of this disclosure) To solve the above problems, a nitride semiconductor device according to one aspect of the present disclosure includes a substrate having a first main surface and a second main surface opposite to the first main surface, a first electron transport layer having a first conductivity type provided above the first main surface, a first electron supply layer provided above the first electron transport layer, a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron supply layer, and a first electron transport layer penetrating the first electron supply layer and the first nitride semiconductor layer. The device comprises a first opening that reaches the layer, a second electron transport layer provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of the first opening, a second electron supply layer provided above the second electron transport layer and covering the first opening, a gate electrode provided above the second electron supply layer and covering the first opening, a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, and a drain electrode provided on the second main surface side of the substrate.

[0012] As a result, the two-dimensional electron gas generated in the first electron transport layer forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel within the first electron transport layer. In other words, the path for the current flowing within the first electron transport layer can be widened, making it easier for the source-drain current to flow. Therefore, according to this embodiment, a nitride semiconductor device is provided that can reduce the resistance value during operation.

[0013] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include a high-resistance layer made of a nitride semiconductor, which has a higher resistance value than the first nitride semiconductor layer, provided between the first nitride semiconductor layer and the second electron transport layer along the inner surface of the first aperture.

[0014] As a result, a high-resistance layer is provided between the first nitride semiconductor layer and the second electron transport layer, so that the leakage current from the source electrode to the gate electrode via the first nitride semiconductor layer and the second electron transport layer is suppressed by the high-resistance layer. For example, the high-resistance layer functions as an insulating layer, substantially blocking the path of the leakage current and sufficiently reducing the leakage current.

[0015] Furthermore, for example, the high-resistance layer may contain iron.

[0016] This allows for increased resistance in the high-resistance layer by incorporating iron into the nitride semiconductor, thereby further reducing leakage current. Furthermore, the high-resistance layer can be easily formed in a desired region and shape by methods such as ion implantation. For example, ion implantation allows for easy amorphous formation of the nitride semiconductor in the region where iron ions are implanted, thereby increasing the resistance of that region. Ion implantation also allows for precise adjustment of the resistance value and shape of the high-resistance layer, thereby improving the reliability of the leakage current suppression effect.

[0017] Furthermore, for example, the high-resistance layer may be provided along the inner surface of the first opening, between the first electron supply layer and the second electron transport layer.

[0018] This allows not only the first nitride semiconductor layer but also the portion of the first electron supply layer exposed into the first opening to be covered by the high-resistance layer. Therefore, the edges of the first nitride semiconductor layer can be reliably covered by the high-resistance layer, further enhancing the reliability of the leakage current suppression effect.

[0019] Furthermore, for example, the first opening may include a bottom portion and a side wall portion, and the high-resistance layer may be provided extending from the side wall portion to a part of the bottom portion.

[0020] As a result, since it is provided from the side wall portion to a part of the bottom portion of the inner surface of the first opening, it is possible to suppress the concentration of the electric field at the boundary between the side wall portion and the bottom portion. By suppressing electric field concentration, the breakdown voltage of the nitride semiconductor device can be increased.

[0021] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure may further include a second nitride semiconductor layer having the second conductivity type, provided between the gate electrode and the second electron transport layer.

[0022] As a result, the carrier concentration directly beneath the gate electrode can be reduced by the second nitride semiconductor layer, and the threshold voltage of the nitride semiconductor device can be shifted to the positive side. Therefore, the nitride semiconductor device according to this embodiment can be operated as a normally-off type FET.

[0023] Furthermore, for example, when the substrate is viewed in plan view, the end of the gate electrode may be located closer to the source electrode than the end of the first opening.

[0024] This makes it possible to improve the controllability of channels formed in the regrowth layer.

[0025] Furthermore, for example, a nitride semiconductor device according to one aspect of the present disclosure further includes a second opening located at a position away from the gate electrode, penetrating the second electron transport layer and reaching the first nitride semiconductor layer, and at least a portion of the source electrode may be provided within the second opening.

[0026] This allows a depletion layer to form near the interface between the second nitride semiconductor layer and the first nitride semiconductor layer by the voltage applied between the source electrode and the drain electrode. The formation of the depletion layer suppresses the generation of leakage current between the source and drain. Therefore, the breakdown voltage of the nitride semiconductor device can be increased.

[0027] Furthermore, for example, the first electron transport layer may include a third nitride semiconductor layer of the first conductivity type and an undoped fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first electron supply layer.

[0028] As a result, the two-dimensional electron gas generated in the fourth nitride semiconductor layer forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel within the fourth nitride semiconductor layer. In other words, the path for the current flowing through the first electron transport layer can be widened, making it easier for the source-drain current to flow. Therefore, according to this embodiment, a nitride semiconductor device is provided that can reduce the resistance value during operation. Furthermore, since the fourth nitride semiconductor layer is an undoped nitride semiconductor layer and contains few impurities, its mobility can be increased.

[0029] Furthermore, for example, a nitride semiconductor device according to another aspect of the present disclosure comprises a substrate having a first main surface and a second main surface opposite to the first main surface; a first electron transport layer having a first conductivity type provided above the first main surface; a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first electron transport layer; a first opening penetrating the first nitride semiconductor layer and reaching the first electron transport layer; a second electron transport layer provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of the first opening; an electron supply layer provided above the second electron transport layer and covering the first opening; a gate electrode provided above the electron supply layer and covering the first opening; a source electrode connected to the first nitride semiconductor layer and the second electron transport layer; and a drain electrode provided on the second main surface side of the substrate. The first electron transport layer includes a third nitride semiconductor layer of the first conductivity type and a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer, having a higher impurity concentration than the third nitride semiconductor layer.

[0030] As a result, the two-dimensional electron gas generated in the fourth nitride semiconductor layer, which has a high impurity concentration, forms a channel, and the source-drain current flowing through the opening diffuses laterally along the channel within the fourth nitride semiconductor layer. In other words, the path for the current flowing through the first electron transport layer can be widened, making it easier for the source-drain current to flow. Furthermore, since the fourth nitride semiconductor layer has a high impurity concentration and low resistance, it can further promote current diffusion. Therefore, according to this embodiment, a nitride semiconductor device is provided that can further reduce the resistance value during operation.

[0031] The embodiments will be described in detail below with reference to the drawings.

[0032] The embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangement and connection configurations of components, steps, and the order of steps shown in the following embodiments are examples only and are not intended to limit this disclosure. Furthermore, any components in the following embodiments that are not described in an independent claim will be described as optional components.

[0033] Furthermore, each figure is a schematic diagram and not necessarily a strictly accurate representation. Therefore, for example, the scale may not necessarily match in each figure. Also, in each figure, substantially identical components are given the same reference numerals, and redundant explanations are omitted or simplified.

[0034] Furthermore, in this specification, terms indicating relationships between elements, such as parallel or coincident, terms indicating the shape of elements, such as rectangle or trapezoid, and numerical ranges do not represent only strict meanings, but also include substantially equivalent ranges, such as differences of a few percent.

[0035] Furthermore, in this specification, the terms "upper" and "lower" do not refer to the upward (vertically upward) and downward (vertically downward) directions in absolute spatial perception, but rather are used as terms defined by the relative positional relationship based on the stacking order in a stacked configuration. Moreover, the terms "upper" and "lower" apply not only when two components are spaced apart and another component exists between them, but also when two components are placed in close proximity and touching each other.

[0036] (Embodiment 1) [composition] First, the configuration of the nitride semiconductor device according to Embodiment 1 will be explained using Figures 1 and 2.

[0037] Figure 1 is a plan view showing the planar layout of the nitride semiconductor device 10 according to this embodiment. Figure 2 is a cross-sectional view of the nitride semiconductor device 10 according to this embodiment.

[0038] Here, Figure 1(a) is a plan view of the nitride semiconductor device 10 as seen from above. Figure 1(b) shows a magnified view of one unit cell 11 of the nitride semiconductor device 10. Figure 2 shows a cross-section of the nitride semiconductor device 10 according to this embodiment along the line II-II in Figure 1.

[0039] As shown in Figure 1(a), the nitride semiconductor device 10 comprises a plurality of unit cells 11. The plurality of unit cells 11 are arranged in a two-dimensional configuration. Each of the plurality of unit cells 11 has the same configuration as the others. The plan view shape of one unit cell 11 is a hexagon. In a plan view, the plurality of unit cells 11 are arranged such that the center of each unit cell 11 is located at the vertices of a tethered regular hexagon.

[0040] Each unit cell 11 is centered around a single source electrode 36. Figure 2 shows a cross-section along the II-II line passing through the centers of two adjacent unit cells 11.

[0041] As shown in Figure 2, the nitride semiconductor device 10 comprises a substrate 12, a drift layer 14, a first underlayer 16, a second underlayer 18, a third underlayer 20, a fourth underlayer 22, a gate opening 24, an electron transport layer 28, an electron supply layer 30, a gate electrode 32, a source opening 34, a source electrode 36, and a drain electrode 38. Furthermore, as shown in Figure 1(a), the nitride semiconductor device 10 comprises a gate electrode pad 40 and a source electrode pad 42. In Figure 1(a), the outline of the source electrode pad 42 is schematically represented by a dashed line.

[0042] The nitride semiconductor device 10 is a device having a stacked structure of semiconductor layers mainly composed of nitride semiconductors such as GaN and AlGaN. Specifically, the nitride semiconductor device 10 has a heterostructure of an AlGaN film and a GaN film.

[0043] In a heterostructure of AlGaN and GaN films, spontaneous polarization or piezoelectric polarization on the c-plane, represented by the (0001) plane, generates a high concentration of two-dimensional electron gas (2DEG) at the heterointerface. Therefore, even in an undoped state, 1 × 10¹⁶ electrons are present at the interface. 13 cm -2 It has the characteristic of being able to obtain the above sheet carrier concentrations.

[0044] The nitride semiconductor device 10 has multiple heterostructures. Specifically, the laminated structure of the drift layer 14 and the first base layer 16, and the laminated structure of the electron transport layer 28 and the electron supply layer 30 each form a heterostructure. Within the drift layer 14, a two-dimensional electron gas 46 is generated near the interface between the drift layer 14 and the first base layer 16. Within the electron transport layer 28, a two-dimensional electron gas 44 is generated near the interface between the electron transport layer 28 and the electron supply layer 30. The nitride semiconductor device 10 according to this embodiment is a field-effect transistor (FET) that utilizes the two-dimensional electron gas 44 generated within the electron transport layer 28 as a channel. Specifically, the nitride semiconductor device 10 is a so-called vertical FET. In Figure 2, the two-dimensional electron gases 44 and 46 are schematically shown by dashed lines.

[0045] The substrate 12 is made of a nitride semiconductor and, as shown in Figure 2, has a first main surface 12a and a second main surface 12b facing away from each other. The first main surface 12a is the main surface on which the drift layer 14 is formed. Specifically, the first main surface 12a substantially coincides with the c-plane. The second main surface 12b is the main surface on the opposite side of the first main surface 12a and is the main surface on which the drain electrode 38 is formed. The planar shape of the substrate 12 is, for example, rectangular, but is not limited to this.

[0046] The substrate 12 has, for example, a thickness of 300 μm and a carrier concentration of 1 × 10⁻¹⁶ 18 cm -3 This is a substrate made of n-type GaN. Note that n-type and p-type refer to the conductivity type of the semiconductor. In this embodiment, n-type is an example of a first conductivity type of nitride semiconductor. p-type is an example of a second conductivity type with a different polarity from the first conductivity type.

[0047] Note that the substrate 12 does not have to be a nitride semiconductor substrate. For example, the substrate 12 may be a silicon (Si) substrate, a silicon carbide (SiC) substrate, a zinc oxide (ZnO) substrate, or the like.

[0048] The drift layer 14 is an example of a first electron traveling layer having a first conductivity type provided above the first main surface 12a of the substrate 12. The drift layer 14 is composed of a nitride semiconductor of the first conductivity type. The drift layer 14 has, for example, a thickness of 8 μm and a carrier concentration of 1×10 16 cm -3 and is a film made of n-type GaN. The drift layer 14 is provided in contact with the first main surface 12a of the substrate 12.

[0049] The first underlayer 16 is an example of a first electron supply layer provided above the drift layer 14. The first underlayer 16 is composed of a nitride semiconductor. The first underlayer 16 is, for example, a film made of undoped Al 0.2 Ga 0.8 N with a thickness of 50 nm. The first underlayer 16 forms an AlGaN / GaN heterointerface with the drift layer 14. Thereby, a two-dimensional electron gas 46 is generated in the drift layer 14.

[0050] The second underlayer 18 is an example of a first nitride semiconductor layer having a second conductivity type different from the first conductivity type provided above the first underlayer 16. The second underlayer 18 has, for example, a thickness of 400 nm and a carrier concentration of 1×10 17 cm -3 and is a film made of p-type GaN. The second underlayer 18 is provided in contact with the upper surface of the first underlayer 16.

[0051] The second underlayer 18 suppresses leakage current between the source electrode 36 and the drain electrode 38. For example, when a reverse voltage is applied to the pn junction formed by the second underlayer 18 and the drift layer 14, specifically when the drain electrode 38 becomes at a higher potential than the source electrode 36, a depletion layer extends in the drift layer 14. This makes it possible to increase the breakdown voltage of the nitride semiconductor device 10.

[0052] The third underlayer 20 is located on the second underlayer 18. The third underlayer 20 is formed of an insulating or semi-insulating nitride semiconductor. For example, the third underlayer 20 is a film made of undoped GaN with a thickness of 200 nm. The third underlayer 20 is provided in contact with the second underlayer 18.

[0053] Here, "undoped" means that the GaN is not doped with a dopant such as silicon (Si) or magnesium (Mg) that changes the polarity of the GaN to n-type or p-type. In this embodiment, the third base layer 20 is doped with carbon. Specifically, the carbon concentration of the third base layer 20 is higher than that of the second base layer 18.

[0054] Furthermore, the third underlayer 20 may contain silicon (Si) or oxygen (O) that is mixed in during film formation. In this case, the carbon concentration of the third underlayer 20 may be, for example, 3 × 10⁻⁶. 17 cm -3 That's all, but 1 × 10 18 cm -3 The above is also acceptable. The silicon concentration or oxygen concentration of the third sublayer 20 is, for example, 5 × 10 16 cm -3 The following is 2 × 10 16 cm -3 The following is also acceptable.

[0055] Here, assuming that the nitride semiconductor device 10 does not have a third underlayer 20, the source electrode 36 and the drain electrode 38 have a stacked structure consisting of an n-type electron supply layer 30 and an electron transport layer 28 / a p-type second underlayer 18 / an n-type first underlayer 16 and an n-type drift layer 14. This stacked structure is a parasitic bipolar transistor consisting of a parasitic npn structure.

[0056] When the nitride semiconductor device 10 is in the off state, if current flows through the second underlayer 18, this parasitic bipolar transistor may turn on, potentially reducing the breakdown voltage of the nitride semiconductor device 10. In this case, malfunction of the nitride semiconductor device 10 is likely to occur.

[0057] The third underlayer 20 suppresses the formation of this parasitic NPN structure. Therefore, malfunctions of the nitride semiconductor device 10 caused by the formation of the parasitic NPN structure can be reduced. However, if the current flowing through the second underlayer 18 is sufficiently suppressed, the nitride semiconductor device 10 does not need to have the third underlayer 20.

[0058] The fourth sublayer 22 is placed on the third sublayer 20. The fourth sublayer 22 is made of, for example, Al with a thickness of 20 nm. 0.2 Ga 0.8 It is a membrane made of N. The fourth underlayer 22 is provided in contact with the third underlayer 20.

[0059] The fourth underlayer 22 suppresses the diffusion of p-type impurities such as Mg from the second underlayer 18. If Mg diffuses into the channels in the electron transport layer 28, the carrier concentration of the two-dimensional electron gas 44 may decrease, potentially increasing the on-resistance. The degree of Mg diffusion also varies depending on the growth conditions of epitaxial growth. Therefore, if Mg diffusion is suppressed, the nitride semiconductor device 10 does not need to have the fourth underlayer 22.

[0060] Furthermore, the fourth underlayer 22 may have the function of supplying electrons to the channel formed at the interface between the electron transport layer 28 and the electron supply layer 30. The fourth underlayer 22 has a larger band gap than, for example, the electron supply layer 30.

[0061] The gate opening 24 is an example of a first opening that penetrates the first sublayer 16 and reaches the drift layer 14. Specifically, the gate opening 24 penetrates the fourth sublayer 22, the third sublayer 20, the second sublayer 18, and the first sublayer 16 in that order, starting from the upper surface of the fourth sublayer 22, and reaching the drift layer 14. The bottom 24a of the gate opening 24 is the upper surface of the drift layer 14. In this embodiment, as shown in Figure 2, the bottom 24a of the gate opening 24 is located below the interface between the drift layer 14 and the first sublayer 16.

[0062] In this embodiment, the gate opening 24 is formed such that its opening area increases as it moves away from the substrate 12. Specifically, the side wall portion 24b of the gate opening 24 is inclined at an angle. For example, the cross-sectional shape of the gate opening 24 is an inverted trapezoid, more specifically, an inverted isosceles trapezoid. In Figure 1(b), the outline of the upper end of the gate opening 24 is shown by a dashed line. The outline of the bottom portion 24a of the gate opening 24 is slightly smaller than the outline shown in Figure 1(b).

[0063] The electron traveling layer 28 is an example of a second electron traveling layer provided in the upper portion of the second base layer 18 and in the portion along the inner surface of the gate opening 24. The electron traveling layer 28 is a first regrowth layer formed by regrowth of a nitride semiconductor after the gate opening 24 has been formed. Specifically, the electron traveling layer 28 is formed with a substantially uniform thickness along the upper surface of the fourth base layer 22 and the side walls 24b and bottom 24a of the gate opening 24. The electron traveling layer 28 is, for example, a film made of undoped GaN with a thickness of 100 nm.

[0064] The electron traveling layer 28 is in contact with the drift layer 14 at the bottom 24a of the gate opening 24. The electron traveling layer 28 is in contact with the sides of the first sublayer 16, the second sublayer 18, the third sublayer 20, and the fourth sublayer 22 at the side wall 24b of the gate opening 24. Furthermore, the electron traveling layer 28 is in contact with the upper surface of the fourth sublayer 22.

[0065] The electron transport layer 28 has channels. Specifically, a two-dimensional electron gas 44 is generated near the interface between the electron transport layer 28 and the electron supply layer 30. The two-dimensional electron gas 44 functions as channels in the electron transport layer 28. The electron transport layer 28 is undoped, but it may be made n-type by Si doping or the like.

[0066] Furthermore, although not shown in the figures, in this embodiment, an AlN film with a thickness of approximately 1 nm is provided as a second regrowth layer between the electron transport layer 28 and the electron supply layer 30. The AlN film can suppress alloy scattering and improve the mobility of the channel. Note that the AlN film is not required, and the electron transport layer 28 and the electron supply layer 30 may be in direct contact.

[0067] The electron supply layer 30 is an example of a second electron supply layer provided above the second substrate layer 18 and along the inner surface of the gate opening 24. The electron supply layer 30 is a third regrowth layer formed by regrowth of a nitride semiconductor after the gate opening 24 has been formed. The electron transport layer 28 and the electron supply layer 30 are provided in this order from the substrate 12 side. The electron supply layer 30 is formed with a shape along the upper surface of the electron transport layer 28 and has a substantially uniform thickness. The electron supply layer 30 is, for example, an undoped aluminum alloy with a thickness of 50 nm. 0.2 Ga 0.8 It is a membrane made of N.

[0068] The electron supply layer 30 forms an AlGaN / GaN heterointerface with the electron transport layer 28, for example, by sandwiching an AlN film with a thickness of 1 nm between them. This generates a two-dimensional electron gas 44 within the electron transport layer 28.

[0069] The electron supply layer 30 supplies electrons to the channels (i.e., the two-dimensional electron gas 44) formed in the electron transport layer 28. As mentioned above, in this embodiment, the fourth underlayer 22 also has an electron supply function. Both the electron supply layer 30 and the fourth underlayer 22 are formed from AlGaN, but the Al composition ratio is not particularly limited. For example, the Al composition ratio of the electron supply layer 30 may be 20%, and the Al composition ratio of the fourth underlayer 22 may be 25%.

[0070] The gate electrode 32 is provided above the electron supply layer 30 and covering the gate opening 24. In this embodiment, the gate electrode 32 is shaped to conform to the upper surface of the electron supply layer 30 and is formed with a substantially uniform thickness in contact with the upper surface of the electron supply layer 30.

[0071] The gate electrode 32 is formed using a conductive material such as a metal. For example, the gate electrode 32 is formed using palladium (Pd). The material for the gate electrode 32 can be a material that is Schottky-connected to an n-type semiconductor, such as nickel (Ni)-based materials, tungsten silicide (WSi), or gold (Au).

[0072] The gate electrode 32 is formed spaced apart in a plan view so as not to come into contact with the source electrode 36. Specifically, as shown in Figure 1(b), the gate electrode 32 is provided so as to surround the source electrode 36 in a plan view. More specifically, the gate electrode 32 is formed as a single plate with multiple openings corresponding to the hexagonal source electrode 36.

[0073] In this embodiment, in a plan view, the end of the gate electrode 32 is located closer to the source electrode 36 than the end of the gate opening 24. Specifically, in a plan view, the gate opening 24 is provided inside the gate electrode 32. In other words, in a plan view, the gate electrode 32 completely covers the gate opening 24.

[0074] The source opening 34 is an example of a second opening that penetrates the electron transport layer 28 and reaches the second underlayer 18, at a position away from the gate electrode 32. Specifically, the source opening 34 penetrates the electron supply layer 30, the electron transport layer 28, the fourth underlayer 22, and the third underlayer 20 in that order, reaching the second underlayer 18. In this embodiment, as shown in Figure 2, the bottom 34a of the source opening 34 is the upper surface of the second underlayer 18. The bottom 34a is located below the interface between the second underlayer 18 and the third underlayer 20. In a plan view, the source opening 34 is located at a position away from the gate opening 24.

[0075] As shown in Figure 2, the source opening 34 is formed with a substantially constant opening area. Specifically, the side wall portion 34b of the source opening 34 is substantially parallel to the thickness direction of the substrate 12. For example, the cross-sectional shape of the source opening 34 is rectangular. Alternatively, the cross-sectional shape of the source opening 34 may be an inverted trapezoid, similar to the gate opening 24.

[0076] In this embodiment, the opening shape of the source opening 34, that is, the shape in plan view, is a regular hexagon, as shown in Figure 1(b). The distance between the source opening 34 and the gate electrode 32, which is provided so as to surround the outer circumference of the source opening 34, is approximately constant. The side wall portion 34b of the source opening 34 has a {1-100} plane. Here, the {1-100} plane is a general term for the (1-100) plane and planes equivalent to the (1-100) plane.

[0077] The source electrode 36 is provided in the source opening 34. Specifically, the source electrode 36 is provided so as to fill the inside of the source opening 34.

[0078] The source electrode 36 is connected to the second substrate 18. Specifically, the source electrode 36 is connected to the end faces of the electron supply layer 30, the electron traveling layer 28, the fourth substrate 22, and the third substrate 20. The source electrode 36 is ohmic connected to the electron traveling layer 28 and the electron supply layer 30.

[0079] The source electrode 36 is formed using a conductive material such as a metal. As the material for the source electrode 36, for example, a material that is ohmic connected to the n-type semiconductor layer, such as Ti / Al, can be used.

[0080] Since the source electrode 36 is connected to the third underlayer 20, the potential of the third underlayer 20 can be fixed. This stabilizes the operation of the nitride semiconductor device 10.

[0081] Furthermore, Al is Schottky-connected to the second underlying layer 18, which is made of a p-type nitride semiconductor. For this reason, a metal material with a high work function, such as Pd or Ni, which has low contact resistance to the p-type nitride semiconductor, may be provided in the lower part of the source electrode 36. This makes it possible to further stabilize the potential of the second underlying layer 18.

[0082] The drain electrode 38 is provided on the second main surface 12b side of the substrate 12. Specifically, the drain electrode 38 is provided in contact with the second main surface 12b. The drain electrode 38 is formed using a conductive material such as metal. As for the material of the drain electrode 38, similar to the material of the source electrode 36, a material that is ohmic connected to the n-type semiconductor layer, such as Ti / Al, can be used.

[0083] The gate electrode pad 40 is electrically connected to the gate electrode 32. The gate electrode pad 40 is provided, for example, above the gate electrode 32. In this embodiment, since the gate electrode 32 is formed as a single plate, as shown in Figure 1(a), the gate electrode pad 40 is provided only in a portion of the plan view of the nitride semiconductor device 10. A power supply for controlling the gate electrode 32 is connected to the gate electrode pad 40.

[0084] The source electrode pad 42 is electrically connected to each of the multiple source electrodes 36. The source electrode pad 42 is located above the source electrodes 36. In this embodiment, each of the multiple source electrodes 36 is formed in the shape of a hexagonal island. Therefore, the source electrode pad 42 is provided in a plan view of the nitride semiconductor device 10, covering most of the area except for the gate electrode pad 40, so as to cover each of the multiple source electrodes 36.

[0085] As described above, in the nitride semiconductor device 10 according to this embodiment, the interface between the electron transport layer 28 and the electron supply layer 30 becomes an AlGaN / GaN heterointerface. As a result, a two-dimensional electron gas 44 is generated in the electron transport layer 28, and a channel is formed. Since the two-dimensional electron gas 44 has a high carrier concentration, the mobility of the channel is increased, and the resistance value during operation (on-resistance) is reduced.

[0086] In the nitride semiconductor device 10, the two-dimensional electron gas 46 is formed within the drift layer 14 so as to extend laterally (specifically, in a direction parallel to the first main surface 12a of the substrate 12) from the vicinity of the bottom 24a of the gate opening 24. As a result, electrons moving through the two-dimensional electron gas 44 in the electron transport layer 28 tend to spread laterally through the two-dimensional electron gas 46 near the bottom 24a. Therefore, within the drift layer 14, not only the portion located directly below the bottom 24a but also the portion located outside of that portion (outside the bottom 24a in a plan view) can be used as a current flow path. As a result, the source-drain current tends to diffuse more easily over a wider area within the drift layer 14. Thus, the resistance value of the nitride semiconductor device 10 during operation can be reduced.

[0087] [Manufacturing method] Next, the method for manufacturing the nitride semiconductor device 10 according to this embodiment will be described using Figures 3A to 3F. Figures 3A to 3F are cross-sectional views showing each step of the manufacturing method for the nitride semiconductor device 10 according to this embodiment.

[0088] The following describes the case in which each nitride semiconductor layer constituting the nitride semiconductor device 10 is deposited by metal-organic vapor phase epitaxy (MOVPE). However, the method for depositing the nitride semiconductor layers is not limited to this; for example, molecular beam epitaxy (MBE) may also be used.

[0089] Furthermore, n-type nitride semiconductors are formed by adding, for example, silicon (Si). P-type nitride semiconductors are formed by adding magnesium (Mg). Note that n-type and p-type impurities are not limited to these.

[0090] First, a substrate 12 made of n-type GaN with a first main surface 12a being the (0001) plane, i.e., the c plane, is prepared. As shown in Figure 3A, an n-type GaN film 13 with Si added as an n-type impurity and an undoped Al film are placed on the first main surface 12a of the substrate 12. 0.2 Ga 0.8 An undoped AlGaN film 15 made of N, a p-type GaN film 17 with Mg added as a p-type impurity, an undoped GaN film 19, and an undoped Al 0.2 Ga 0.8 An undoped AlGaN film 21 made of N is deposited in this order. The n-type GaN film 13, undoped AlGaN film 15, p-type GaN film 17, undoped GaN film 19, and undoped AlGaN film 21 are each patterned into predetermined shapes to become the drift layer 14, the first underlayer 16, the second underlayer 18, the third underlayer 20, and the fourth underlayer 22 shown in Figure 2.

[0091] The thickness and carrier concentration of each layer are, for example, as follows: The n-type GaN film 13 has a thickness of 8 μm and a carrier concentration of 1 × 10⁻⁶ 16 cm -3 The undoped AlGaN film 15 has a thickness of 20 nm. The p-type GaN film 17 has a thickness of 400 nm and a carrier concentration of 1 × 10⁻¹⁶. 17 cm -3The undoped GaN film 19 has a thickness of 200 nm. The undoped AlGaN film 21 has a thickness of 20 nm. Note that these values ​​are just examples.

[0092] Next, as shown in Figure 3B, a resist is applied to the undoped AlGaN film 21, and the applied resist is patterned by photolithography to form a resist mask 90. ​​The resist mask 90 is a mask for forming the gate opening 24 and has an opening 91 corresponding to the planar shape of the gate opening 24.

[0093] Next, as shown in Figure 3C, a gate opening 24 is formed by dry etching. The gate opening 24 penetrates the undoped AlGaN film 21, the undoped GaN film 19, the p-type GaN film 17, and the undoped AlGaN film 15, exposing the n-type GaN film 13. At this time, the bottom 24a of the gate opening 24 is parallel to the first main surface 12a of the substrate 12. The side wall portion 24b of the gate opening 24 is inclined with respect to the bottom 24a at a predetermined inclination angle. The inclination angle is, for example, in the range of 20° to 80°. This allows a regrowth layer to be formed on the side wall portion 24b with a uniform thickness, thereby suppressing channel narrowing and preventing both a decrease in carrier concentration and an increase in on-resistance.

[0094] Next, after removing the resist mask 90, as shown in Figure 3D, an undoped GaN film 27, an undoped AlN film (not shown), and an undoped AlGaN film 29 are deposited in this order along the shape of the gate opening 24 using the MOVPE method. The undoped GaN film 27 and the undoped AlGaN film 29 are patterned into predetermined shapes to become the electron transport layer 28 and the electron supply layer 30, respectively.

[0095] The thickness of each layer is approximately uniform. For example, the undoped GaN film 27 has a thickness of 100 nm. The undoped AlN film has a thickness of 1 nm. The undoped AlGaN film 29 has a thickness of 50 nm. Note that these values ​​are just examples.

[0096] Next, a gate metal film made of Pd is deposited to cover the gate opening 24 by a vapor deposition method or sputtering method. As shown in Figure 3E, the gate electrode 32 is formed by patterning the deposited gate metal film.

[0097] Furthermore, as shown in Figure 3F, a source opening 34 is formed at a position away from the gate electrode 32, penetrating the undoped AlGaN film 29, undoped AlN film (not shown), undoped GaN film 27, undoped AlGaN film 21, and undoped GaN film 19, and reaching the p-type GaN film 17. The source opening 34 is formed by photolithography and dry etching, similar to the gate opening 24. The undoped AlGaN film 29, undoped GaN film 27, undoped AlGaN film 21, undoped GaN film 19, and p-type GaN film 17 are patterned to form the electron supply layer 30, electron transport layer 28, fourth underlayer 22, third underlayer 20, and second underlayer 18.

[0098] Next, a source metal film made of Ti and Au is deposited by vapor deposition or sputtering to fill the source opening 34, and then patterned to form the source electrode 36. Furthermore, a drain metal film made of Ti and Al is deposited on the second main surface 12b of the substrate 12 by vapor deposition or sputtering, and then patterned as necessary to form the drain electrode 38.

[0099] Through the above process, the nitride semiconductor device 10 shown in Figure 2 is formed.

[0100] After forming the gate electrode 32 and source electrode 36, an insulating film is deposited, and contact holes are formed in the deposited insulating film to expose a portion of each of the multiple source electrodes 36 and a portion of the gate electrode 32. Subsequently, a metal film is deposited and patterned to form the gate electrode pad 40 and source electrode pad 42.

[0101] [Differentiation] Here, a modified example of the nitride semiconductor device 10 according to this embodiment will be described.

[0102] [Example 1] Figure 4 is a cross-sectional view of the nitride semiconductor device 110 according to Modification 1. As shown in Figure 4, the nitride semiconductor device 110 differs from the nitride semiconductor device 10 shown in Figure 2 in that it newly includes a high-resistance layer 126. In the following, the differences from the embodiment will be explained in detail, and the explanation of the common points will be omitted or simplified.

[0103] The high-resistance layer 126 is provided between the second base layer 18 and the electron traveling layer 28 at the gate opening 24. In this modified example, the high-resistance layer 126 is also provided between the first base layer 16 and the electron traveling layer 28. Specifically, the high-resistance layer 126 is provided from the side wall portion 24b of the gate opening 24 to a part of the bottom portion 24a. More specifically, the high-resistance layer 126 is provided so as to cover the entire side wall portion 24b from the upper end of the gate opening 24, i.e., a part of the upper surface of the fourth base layer 22 to a part of the bottom portion 24a. In other words, the high-resistance layer 126 is provided between each of the first base layer 16, the second base layer 18, the third base layer 20, and the fourth base layer 22 and the electron traveling layer 28.

[0104] For example, as shown in Figure 4, the upper surface of the upper end of the high-resistance layer 126 is flush with the upper surface of the fourth sublayer 22. Also, the upper surface of the lower end of the high-resistance layer 126 is flush with the portion of the upper surface of the drift layer 14 that forms the bottom 24a. The high-resistance layer 126 is formed to be embedded in the surface and end portions of the fourth sublayer 22, the end portion of the third sublayer 20, the end portion of the second sublayer 18, the end portion of the first sublayer 16, and the surface portion of the drift layer 14.

[0105] The high-resistance layer 126 has a higher resistance value than the second underlayer 18. In this modified example, the high-resistance layer 126 has a higher resistance value than the third underlayer 20.

[0106] The high-resistance layer 126 is made of a nitride semiconductor. In this modified example, the high-resistance layer 126 contains iron (Fe). The high-resistance layer 126 is made of, for example, iron-doped and high-resistance GaN. The thickness of the high-resistance layer 126 is, for example, 50 nm.

[0107] Here, the method for manufacturing the nitride semiconductor device 110 according to this modified example will be explained using Figures 5A and 5B. Figures 5A and 5B are cross-sectional views showing the method for manufacturing the nitride semiconductor device 110 according to this modified example.

[0108] The manufacturing method for the nitride semiconductor device 110 according to this modified example is the same as that for the nitride semiconductor device 10 according to Embodiment 1 up to the formation of the gate opening 24. After forming the gate opening 24 shown in Figure 3C, the resist mask 90 is removed. Then, a resist is applied again on the undoped AlGaN film 21 and inside the gate opening 24. As shown in Figure 5A, the applied resist is patterned by photolithography to form a resist mask 192.

[0109] The resist mask 192 is a mask for forming the high-resistance layer 126. The resist mask 192 has an opening 193 that is larger than the side wall portion 24b of the gate opening 24. The opening 193 is provided from the upper end of the side wall portion 24b to a part of the upper surface and part of the bottom 24a of the undoped AlGaN film 21, and in a plan view, exposes at least the entire side wall portion 24b.

[0110] Next, a high-resistance layer 126 is formed by ion implantation of iron ions into the portion exposed at the opening 193 of the resist mask 192, as shown in Figure 5B. The high-resistance layer 126 is a layer in which iron is doped into the portion exposed at the opening 193 of each of the undoped AlGaN film 21, undoped GaN film 19, p-type GaN film 17, undoped AlGaN film 15, and n-type GaN film 13. The portion of the n-type GaN film 13 excluding the high-resistance layer 126 becomes the drift layer 14.

[0111] The implantation conditions for ion implantation are, for example, an acceleration energy of 40 keV and a dose of 1 × 10⁻¹⁶. 14 cm -2 This results in the formation of a high-resistance layer 126 with a thickness of approximately 50 nm. The region where iron ions are implanted, i.e., the high-resistance layer 126, becomes highly resistant because its crystal structure is destroyed and it enters an amorphous state.

[0112] In this case, instead of iron ions, ions of metals with a large atomic number, such as titanium ions, chromium ions, copper ions, or nickel ions, may be used. This suppresses the recrystallization of the high-resistance layer 126 due to heat treatment in subsequent processes, and increases the resistance value of the high-resistance layer 126.

[0113] The process after forming the high-resistance layer 126 is the same as that for the nitride semiconductor device 10 according to Embodiment 1. Specifically, after forming the high-resistance layer 126, as shown in Figure 3D, an undoped GaN film 27, an undoped AlN film (not shown), and an undoped AlGaN film 29 are sequentially formed by regrowth. Since the high-resistance layer 126 is formed of a nitride semiconductor, the film quality of the undoped GaN film 27, undoped AlN film (not shown), and undoped AlGaN film 29 is improved by regrowth.

[0114] As described above, in this modified example, a high-resistance layer 126 is provided between the electron transport layer 28 and the second underlayer 18, so that leakage current from the source electrode 36 through the second underlayer 18 and the electron transport layer 28 to the gate electrode 32 can be suppressed. Thus, according to this modified example, a nitride semiconductor device 110 with suppressed leakage current is realized.

[0115] The resist mask 192 may be formed such that the opening 193 exposes only the p-type GaN film 17 at the side wall portion 24b. In other words, the plan view shape of the opening 193 may coincide with the boundary between the p-type GaN film 17 and the undoped GaN film 19, and the boundary between the p-type GaN film 17 and the undoped AlGaN film 15. Alternatively, the resist mask 192 may be formed such that the opening 193 exposes the entire p-type GaN film 17 and the entire undoped AlGaN film 15 at the side wall portion 24b. By exposing the entire p-type GaN film 17 at the side wall portion 24b, the high-resistivity layer 126 can be formed to reliably cover the portion of the p-type GaN film 17 exposed at the side wall portion 24b.

[0116] [Differentiation 2] Figure 6 is a cross-sectional view of the nitride semiconductor device 210 according to the second modified example. As shown in Figure 6, the nitride semiconductor device 210 differs from the nitride semiconductor device 10 shown in Figure 2 in that it includes a threshold control layer 248. In the following, the differences from Embodiment 1 will be explained in detail, and the explanation of the common points will be omitted or simplified.

[0117] The threshold control layer 248 is an example of a second nitride semiconductor layer of a second conductivity type, provided between the gate electrode 32 and the electron transport layer 28. The threshold control layer 248 is provided on the electron supply layer 30 and is in contact with the electron supply layer 30 and the gate electrode 32.

[0118] In this modified example, when the substrate 12 is viewed from above, the edge of the threshold control layer 248 is located closer to the source electrode 36 than the edge of the gate electrode 32. The threshold control layer 248 and the source electrode 36 are spaced apart and not in contact.

[0119] The threshold control layer 248 has, for example, a thickness of 100 nm and a carrier concentration of 1 × 10⁻⁶. 17 cm -3 p-type Al 0.2 Ga 0.8This is a nitride semiconductor layer made of N. The threshold control layer 248 is formed by depositing and patterning it using the MOVPE method, following the deposition of the undoped AlGaN film 29 that forms the electron supply layer 30.

[0120] According to this modified example, the threshold control layer 248 raises the potential at the conduction band edge of the channel portion. Therefore, the threshold voltage of the nitride semiconductor device 210 can be increased. Consequently, the nitride semiconductor device 210 can be realized as a normally-off type FET.

[0121] The threshold control layer 248 may be formed using an insulating material. In other words, the threshold control layer 248 may be an insulating layer.

[0122] (Embodiment 2) Next, Embodiment 2 will be described. Embodiment 2 differs from Embodiment 1 in that the first electron transport layer has a two-layer structure. In the following, the differences from Embodiment 1 will be explained in detail, and the explanation of the common points will be omitted or simplified.

[0123] Figure 7 is a cross-sectional view of the nitride semiconductor device 310 according to this embodiment. As shown in Figure 7, the nitride semiconductor device 310 differs from the nitride semiconductor device 10 shown in Figure 2 in that it has an electron transport layer 314 instead of a drift layer 14.

[0124] The electron transport layer 314 is an example of a first electron transport layer. The electron transport layer 314 includes a drift layer 314a and an undoped nitride semiconductor layer 314b.

[0125] The drift layer 314a is an example of a third nitride semiconductor layer of the first conductivity type, and is substantially the same as the drift layer 14 according to Embodiment 1. In this embodiment, the only difference is that the gate opening 24 does not reach the drift layer 314a. For this reason, the upper surface of the drift layer 314a is flat.

[0126] The undoped nitride semiconductor layer 314b is an example of an undoped fourth nitride semiconductor layer located between the drift layer 314a and the first underlayment layer 16. Specifically, the undoped nitride semiconductor layer 314b is a film made of undoped GaN. The film thickness of the undoped nitride semiconductor layer 314b is, for example, 200 nm, but is not limited to this.

[0127] The undoped nitride semiconductor layer 314b is in contact with the first underlying layer 16, forming an AlGaN / GaN heterointerface between it and the first underlying layer 16. This generates a two-dimensional electron gas 46 within the undoped nitride semiconductor layer 314b.

[0128] The drift layer 314a and the undoped nitride semiconductor layer 314b are formed, for example, by the following method. Specifically, in the manufacturing process shown in Figure 3A, after forming the n-type GaN film 13, the undoped GaN film is formed before forming the undoped AlGaN film 15. Then, in the manufacturing process shown in Figure 3C, a gate opening 24 is formed so as to expose the undoped GaN film. Therefore, in this embodiment, the bottom 24a of the gate opening 24 becomes the upper surface of the undoped nitride semiconductor layer 314b.

[0129] According to this embodiment, electrons spread laterally due to the two-dimensional electron gas 46 formed within the undoped nitride semiconductor layer 314b. Therefore, similar to Embodiment 1, the source-drain current is more easily diffused over a wide area within the drift layer 314a. Furthermore, since the undoped nitride semiconductor layer 314b has fewer impurities, electron mobility can be increased. Thus, faster operation of the nitride semiconductor device 310 is achieved.

[0130] (Embodiment 3) Next, Embodiment 3 will be described. Embodiment 3 differs from Embodiment 1 in that the first electron transport layer has a two-layer structure and does not have a first electron supply layer. In the following, the differences from Embodiment 1 will be explained in detail, and the explanation of the common points will be omitted or simplified.

[0131] Figure 8 is a cross-sectional view of the nitride semiconductor device 410 according to this embodiment. As shown in Figure 8, the nitride semiconductor device 410 differs from the nitride semiconductor device 10 shown in Figure 2 in that it has an electron transport layer 414 instead of a drift layer 14. Also, the nitride semiconductor device 410 does not have a first underlayer 16.

[0132] The electron transport layer 414 is an example of a first electron transport layer. The electron transport layer 414 includes a low-concentration layer 414a and a high-concentration layer 414b.

[0133] The low-concentration layer 414a is an example of a third nitride semiconductor layer of the first conductivity type, and is substantially the same as the drift layer 14 according to Embodiment 1. In this embodiment, the only difference is that the gate opening 24 does not reach the low-concentration layer 414a. For this reason, the upper surface of the low-concentration layer 414a is flat.

[0134] The high-concentration layer 414b is located between the low-concentration layer 414a and the second underlying layer 18, and is an example of a fourth nitride semiconductor layer with a higher impurity concentration than the low-concentration layer 414a. Specifically, the high-concentration layer 414b is a film made of n-type GaN with a higher concentration of n-type impurities than the low-concentration layer 414a. The carrier concentration of the high-concentration layer 414b is, for example, 1 × 10⁻⁶ 18 cm -3 The above is the most accurate description, but it is not limited to this. The thickness of the high-concentration layer 414b is smaller than the thickness of the low-concentration layer 414a, for example, less than 1 μm, but it is not limited to this. By making the thickness of the low-concentration layer 414a thicker than the high-concentration layer 414b, the breakdown voltage of the nitride semiconductor device can be increased.

[0135] The high-concentration layer 414b is in contact with the second underlying layer 18. In this embodiment, the difference in band gaps between the low-concentration layer 414a, the high-concentration layer 414b, and the second underlying layer 18 is small, and no heterointerface is formed. Therefore, the two-dimensional electron gas 46 shown in Figure 2 and other figures is not generated.

[0136] Although a two-dimensional electron gas 46 is not generated, the high-concentration layer 414b has a high concentration of n-type impurities, resulting in low resistance. Therefore, electrons spread laterally within the high-concentration layer 414b. Consequently, similar to Embodiment 1, the source-drain current is easily diffused over a wide area within the high-concentration layer 414b and the low-concentration layer 414a.

[0137] The low-concentration layer 414a and the high-concentration layer 414b are formed, for example, by the following method. Specifically, in the manufacturing process shown in Figure 3A, after forming the n-type GaN film 13, and before forming the undoped AlGaN film 15, an n-type GaN film with a higher impurity concentration than the n-type GaN film 13 is formed. Then, in the manufacturing process shown in Figure 3C, a gate opening 24 is formed so as to expose the n-type GaN film with the higher impurity concentration. Therefore, in this embodiment, the bottom 24a of the gate opening 24 becomes the upper surface of the high-concentration layer 414b.

[0138] According to this embodiment, since the resistance of the high-concentration layer 414b is low, electrons spread easily in the lateral direction. Therefore, similar to Embodiment 1, the source-drain current is easily diffused over a wide area within the electron transport layer 414. Thus, the resistance value during operation can be further reduced.

[0139] (Other embodiments) Although nitride semiconductor devices according to one or more embodiments have been described above based on embodiments, this disclosure is not limited to these embodiments. Without departing from the spirit of this disclosure, various modifications to these embodiments that a person skilled in the art could conceive, as well as configurations constructed by combining components from different embodiments, are also included within the scope of this disclosure.

[0140] For example, in the embodiments described above, we have shown examples where the first conductivity type is n type and the second conductivity type is p type, but we are not limited to this. The first conductivity type may be p type and the second conductivity type may be n type.

[0141] Furthermore, for example, the high-resistance layer 126 may be provided only between the electron-traveling layer 28 and the second base layer 18. For example, the high-resistance layer 126 may be provided only on a part of the side wall portion 24b of the gate opening 24, and may not cover the end faces of the first base layer 16, the third base layer 20, and the fourth base layer 22.

[0142] Furthermore, for example, in a plan view, the end of the gate electrode 32 may coincide with the end of the gate opening 24. Alternatively, in a plan view, the gate electrode 32 may be located inside the gate opening 24.

[0143] Furthermore, although the above embodiment provides a source opening 34 that reaches the second base layer 18, it is not limited to this. For example, the source opening 34 may be an opening that reaches the electron traveling layer 28, and the source electrode 36 may be connected to the electron traveling layer 28 but not to the second base layer 18.

[0144] Furthermore, for example, the drift layer 14, which is an example of the first electron transport layer, may have the same composition as the electron transport layer 28, which is an example of the second electron transport layer. Alternatively, the carbon concentration of the drift layer 14 may be higher than the carbon concentration of the electron transport layer 28. For example, the carbon concentration of the drift layer 14 may be 10 18 cm -3 The order is such that the carbon concentration of the electron transport layer 28 is 10 16 cm -3 It may also be made to order. By increasing the carbon concentration of the drift layer 14, the breakdown voltage of the nitride semiconductor device 10 can be increased.

[0145] Furthermore, the carbon concentration within the drift layer 14 does not have to be uniform. For example, the carbon concentration may be low in the surface portion of the drift layer 14, i.e., near the interface with the first underlying layer 16. This promotes the generation of the two-dimensional electron gas 46 and increases the channel mobility, thereby facilitating the diffusion of the current.

[0146] Furthermore, the planar layout of a nitride semiconductor device is not limited to the example shown in Figure 1. For example, the source electrode 36 may have a planar shape that is a rectangle extending in one direction. Multiple source electrodes 36 may be arranged in the short-side direction. In this case, the short-side direction corresponds to the direction along the II-II line.

[0147] Furthermore, each of the above embodiments may be modified, replaced, added, or omitted in various ways within the scope of the claims or equivalent thereof. [Industrial applicability]

[0148] This disclosure can be used as a nitride semiconductor device with low resistance, and can be used, for example, as a power transistor used in power supply circuits for consumer electronics such as televisions. [Explanation of Symbols]

[0149] 10, 110, 210, 310, 410 Nitride semiconductor equipment 11 unit cells 12 circuit boards 12a First main surface 12b Second main surface 13 n-type GaN film 14, 314a Drift layer 15, 21, 29 Undoped AlGaN film 16. The first sublayer 17 p-type GaN film 18. Second sublayer 19, 27 Undoped GaN film 20 Third sublayer 22. The fourth sublayer 24 Gate opening 24a, 34a bottom 24b, 34b side wall part 28, 314, 414 electron transport layers 30 Electron supply layer 32 gates 34 Source opening 36 Source electrodes 38 Drain electrode 40 gate electrode pads 42 Source electrode pads 44, 46 Two-dimensional electron gas 90, 192 Resist Masks 91, 193 aperture 126 High resistance layer 248 Threshold Control Layer 314b Undoped nitride semiconductor layer 414a Low concentration layer 414b High concentration layer

Claims

1. A substrate having a first main surface and a second main surface opposite to the first main surface, A first electron transport layer having a first conductivity type is provided above the first main surface, A first electron supply layer provided above the first electron transport layer, A first nitride semiconductor layer having a second conductivity type different from the first conductivity type is provided above the first electron supply layer, A second electron transport layer is provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of the first opening that penetrates the first electron supply layer and the first nitride semiconductor layer and reaches the first electron transport layer, The present invention comprises a second electron supply layer provided above the second electron transport layer and covering the first opening, The first electron transport layer is The third nitride semiconductor layer of the first conductivity type, The third nitride semiconductor layer and the first electron supply layer are located between them and an undoped fourth nitride semiconductor layer. Nitride semiconductor equipment.

2. Furthermore, along the inner surface of the first opening, a high-resistance layer made of nitride semiconductor material is provided between the first nitride semiconductor layer and the second electron transport layer, with a higher resistance than the first nitride semiconductor layer. The nitride semiconductor device according to claim 1.

3. The aforementioned high-resistance layer contains iron The nitride semiconductor device according to claim 2.

4. The high-resistance layer is provided along the inner surface of the first opening, between the first electron supply layer and the second electron transport layer. The nitride semiconductor device according to claim 2 or 3.

5. A gate electrode is provided above the second electron supply layer and covering the first opening, The system comprises a second nitride semiconductor layer having the second conductivity type, provided between the gate electrode and the second electron supply layer. A nitride semiconductor device according to any one of claims 1 to 4.

6. The system comprises a source electrode connected to the first nitride semiconductor layer and the second electron transport layer, When the substrate is viewed in plan view, the end of the gate electrode is located closer to the source electrode than the end of the first opening. The nitride semiconductor device according to claim 5.

7. Furthermore, at a position away from the gate electrode, a second opening is provided that penetrates the second electron transport layer and reaches the first nitride semiconductor layer. At least a portion of the source electrode is provided within the second opening. The nitride semiconductor device according to claim 6.

8. A substrate having a first main surface and a second main surface opposite to the first main surface, A first electron transport layer having a first conductivity type is provided above the first main surface, A first nitride semiconductor layer having a second conductivity type different from the first conductivity type is provided above the first electron transport layer, A second electron transport layer is provided in the upper portion of the first nitride semiconductor layer and in the portion along the inner surface of the first opening that penetrates the first nitride semiconductor layer and reaches the first electron transport layer, An electron supply layer is provided above the second electron transport layer and covering the first opening, Equipped with, The first electron transport layer is The third nitride semiconductor layer of the first conductivity type, The present invention includes a fourth nitride semiconductor layer located between the third nitride semiconductor layer and the first nitride semiconductor layer, the fourth nitride semiconductor layer having a higher impurity concentration than the third nitride semiconductor layer. Nitride semiconductor equipment.

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