Circuit and method for ensuring the stability of the I / O interface during partial reconfiguration of a reprogrammable integrated circuit device.

Abstract

A circuit (300) for sending data within an integrated circuit device is described. The circuit (300) includes an input / output port (307) and an interface circuit (301) coupled to the input / output port and configured to receive data. The interface circuit includes a selection circuit (310) that enables selection of data and a predetermined value (Constant 2). The circuit includes a control circuit (311) coupled to control the selection circuit (310). The control circuit is responsive to a control signal (311 out) to hold the input / output port at the predetermined value (Constant 2) during partial reconfiguration of the integrated circuit device. A method of configuring a circuit for sending data within an integrated circuit device is also described (FIG. 12).

Description

Technical Field

[0001] Technical Field The present invention generally relates to integrated circuit devices, and more particularly to circuits and methods for ensuring the stability of an IO interface during partial reconfiguration of a reprogrammable integrated circuit device.

Background Art

[0002] Background A programmable logic device is an integrated circuit device that enables a user of the integrated circuit to program a device using a circuit design selected by the user. A programmable logic device is reconfigurable as desired and often undergoes partial reconfiguration (PR). Partial reconfiguration can be beneficial, but it can also have drawbacks or lead to adverse events. In most systems that use partial reconfiguration, the external input / output (I / O) interfaces are fixed and cannot be reconfigured. However, the programmable logic connected to these interfaces can depend on multiple partial reconfigurations as part of normal system operation.

Summary of the Invention

Problems to be Solved by the Invention

[0003] Therefore, there is a need for an IO circuit that provides predictable and acceptable performance during partial reconfiguration.

Means for Solving the Problems

[0004] Summary This document describes a circuit for providing stable values ​​to external input / output interfaces, etc., during partial reconfiguration within an integrated circuit device. The input / output circuit comprises input / output ports and interface circuits coupled to the input / output ports and configured to receive data. The interface circuit includes a selection circuit that enables the selection of data and predetermined values. The input / output circuit further comprises a control circuit coupled to control the selection circuit. The control circuit, in response to a control signal, maintains the input / output ports at predetermined values ​​during partial reconfiguration of the integrated circuit device.

[0005] A method for providing stable values ​​to external input / output interfaces, etc., during partial reconfiguration within an integrated circuit device is also described. This method includes the step of coupling interface circuits to input / output ports. The input / output ports are configured to receive data. The interface circuits include selection circuits that enable the selection of data and predetermined values. This method includes the steps of configuring a control circuit to control the selection circuit and holding the input / output ports at predetermined values ​​during partial reconfiguration of the integrated circuit device in response to control signals from the control circuit.

[0006] Brief explanation of the drawing [Brief explanation of the drawing]

[0007] [Figure 1] This is a block diagram of an integrated circuit having I / O circuits. [Figure 2] This is a block diagram of the I / O circuit of an integrated circuit device. [Figure 3] This is a block diagram of an asynchronous I / O circuit for an integrated circuit device. [Figure 4] This is a block diagram of a synchronous I / O circuit for an integrated circuit device. [Figure 5] Figure 4 is a time chart showing the operation of the synchronous I / O circuit. [Figure 6] This is a block diagram of other I / O circuits in an integrated circuit device. [Figure 7] This is a partial block diagram of an integrated circuit device relating to the I / O pads of the integrated circuit device. [Figure 8] A block diagram showing the implementation configuration of I / O circuits coupled to memory elements. [Figure 9] A block diagram showing the implementation configuration of an input / output circuit coupled to a memory element during hold operation. [Figure 10] This is another block diagram of a programmable logic device. [Figure 11] Figure 10 is a block diagram of the configurable logic elements of a programmable logic device. [Figure 12] This is a flowchart showing how to implement I / O circuits within an integrated circuit device. [Modes for carrying out the invention]

[0008] Detailed explanation Circuits and methods for implementing an I / O interface enable holding values ​​at a specific voltage at the output of an integrated circuit during a PR (partial reconfiguration) event. According to one implementation, the output value can be synchronously switched to a programmable constant value during the duration of a PR event using an existing clock for the output path. That is, when a hold signal is enabled, the I / O interface enables synchronous switching to a predefined constant value. The tristate control value for the tristate buffer of the I / O interface can also be switched to a programmable constant value during the duration of a PR event using an existing clock for the tristate path. Thus, I / O programming can be maintained during PR events and selected on a unit I / O-pair basis. According to other implementations, asynchronous operation can be employed where a constant value is switched when a hold signal is enabled. As will be described in more detail below, the circuit and method provide stable I / O during partial reconfiguration of the integrated circuit device by holding values ​​at a fixed value in the I / O interface.

[0009] This specification includes claims defining features of one or more implementations of the present invention that are considered novel, but the description will be easier to understand when viewed in conjunction with the drawings. While various circuits and methods are disclosed, it should be understood that these circuits and methods are merely illustrative examples of progressive arrangements and can be implemented in various forms. Accordingly, the specific structural and functional details disclosed in this specification should not be construed as limitations, but merely as the basis for the claims and as representative grounds for teaching those skilled in the art the adoption of various progressive arrangements in any practical, appropriate detailed structure. Furthermore, the terms and phrases used herein are not intended to be limiting, but rather to provide an easily understandable description of the circuits and methods.

[0010] First, referring to Figure 1, a block diagram of an integrated circuit device 100 having an I / O circuit is shown. Specifically, input / output ports 102 are coupled to a control circuit 104. The control circuit 104 controls a programmable resource 106 having configurable logic elements 109 such as input / output blocks (IOBs) and blocks of random access memory (BRAMs), and other programmable resources. Configuration data can be provided to a configuration memory 108 by a configuration controller 110. The configuration data enables the operation of the programmable resource 106. Memory 113 may be coupled to the control circuit 104 and the programmable resource 106. A transmit / receive circuit 114, comprising a transmitter and a receiver, is coupled to the control circuit 104, the programmable resource 106, and memory 113, and can receive signals in the integrated circuit via I / O ports 116, 117. Other I / O ports, such as I / O port 118 coupled to the control circuit 104 as shown, may be coupled to the circuitry of the integrated circuit device. The clock network 120 is coupled to various elements of the circuit in Figure 1. The circuit in Figure 1 is illustrative, and other circuits may be used to implement I / O circuits of other circuits that require data values ​​to be retained during partial reconstruction.

[0011] Next, referring to Figure 2, a block diagram of the IO circuit 200 of the integrated circuit device is shown. The control circuit 202 is coupled to the input / output port 204. The control circuit 202 receives a clock signal at the clock input 206 and generates a hold signal to be supplied to the control input 208 and data (HOLD DATA) to be supplied to the first data input 210. As will be described in more detail below, HOLD DATA is the voltage at which the output data (OUTPUT) of the IO port 204 is held. In addition to receiving the hold signal and hold data, data generated at output 214 as output data (Output) during normal operation (i.e., operation outside of partial reconfiguration) is supplied to the IO circuit at the second data input 212. The IO port 204 may also receive a clock signal at the second clock input 216.

[0012] Although input / output ports are shown, it should be understood that input / output port 204 may be an input-only circuit or an output-only circuit. The circuit in Figure 2 may be implemented, for example, in the IO block of Figure 1, or in the input / output logic (IOL) of Figure 10. As will be described in more detail below, the output data generated by output 214 may be used to hold the voltage of a node in another circuit, such as a memory circuit. Other circuits may be, for example, part of an integrated circuit having input / output circuit 200, or a circuit separate from the integrated circuit having input / output circuit 200. As with Figures 3 to 6, which will be described in more detail below, while Figure 2 illustrates holding a value at a fixed value as an output of an input / output port during partial reconfiguration, it should be understood that the circuit and method may be used to hold an input / output port intended to operate as an input port at a predetermined value. For example, in the implementation of Figure 2, input data may be coupled to port 214 (i.e., the input / output port may operate as an input), input data may be generated at 212 (i.e., input 212 may function as an output), or 212 may generate a fixed value. In other words, the control circuit 202 can control the input / output port 204 so that the node that sends the received data acts as an input port whose value is held fixed (i.e., input 212 acts as the output of input / output port 204).

[0013] Next, referring to Figure 3, a block diagram of the asynchronous I / O circuit 300 for the integrated circuit device is shown. According to the implementation in Figure 3, the interface circuit 301 is a circuit coupled to the input / output port and includes a first register 302. The first register 302 is shown as a flip-flop in this example and is configured to receive a tristate signal (TRISTATE) at input 303 and a clock signal (CLK) at the clock input. The output of register 302 is coupled to a selection circuit 304. The output of the selection circuit 304 is a selected tristate control signal (IO_T_VAL) that controls the tristate buffer 306. The output of the tristate buffer is coupled to an I / O pad 307. The control terminal of the selection circuit 304 is used to select either the tristate control signal generated by register 302 or a constant value (CONSTANT1) which is a predetermined voltage. As will be described in more detail below, the constant value may be selected during partial reconfiguration operation.

[0014] Data is also sent to the IO pad 307 via register 308, which has an input 309 for receiving data (DATA) generated at the IO port during normal operation of the integrated circuit (e.g., operation other than partial reconfiguration). The clock input also receives a clock signal. A selection circuit 310, shown as a multiplexer in example, allows selection of data or a constant value (CONSTANT2) generated by register 308, which is provided as the IO_OUT_VAL signal to the data input of the tristate buffer 306. This constant value may be selected by the selection circuit 310 and provided as the IO_OUT_VAL signal to the data input of the tristate buffer 306 in order to allow the value at the IO pad 307 to be held at a predetermined voltage (i.e., logic "0" or logic "1") during partial reconfiguration, etc.

[0015] The selection circuits 304 and 310 are controlled by control signals generated by the control circuit 311 and applied to the control terminals of the selection circuits. More specifically, the output of the logic circuit 312 of the control circuit 311, here shown by way of example as an AND gate 312, is configured to receive a hold signal (HOLD) and a complete signal (COMPLETE). The HOLD signal can be used as a request for partial reconfiguration. The COMPLETE signal can be used to indicate that the status of the initial configuration has been completed after partial reconfiguration can be performed. During operation, the hold signal and the complete signal are used to generate an output. This output will select the tri-state and data signals used to supply data to the IO pads 307 during normal operation, such as during partial reconfiguration, or to supply a fixed predetermined value to the IO pads.

[0016] Next, referring to FIG. 4, a block diagram of a synchronous IO circuit 400 for an integrated circuit device is shown. According to the implementation of FIG. 4, the control circuit 401 also includes a logic circuit 402, shown by way of example as an AND gate, and registers 404 and 406. The registers 404, 406 are mounted in series on the output of the logic circuit 402 so that the selection of the signals generated by the selection circuits 304 and 310 is reliably synchronized with the tri-state and data inputs to the registers 302 and 308. As shown in the timing diagram of FIG. 5, a constant synchronization signal (CONSTANT_SYNC) generated at the output of the control circuit 401 enables the synchronization of the tri-state control and the data values (IO_OUT_VAL and IO_T_VAL) during partial reconfiguration.

[0017] Next, referring to FIG. 6, a block diagram of another IO circuit 600 of the integrated circuit device is shown. The IO circuit 600 includes an interface circuit 601 controlled by a control circuit 602. The logic circuit 603 of the control circuit 602 is shown here as an AND gate as an example and is configured to receive a hold signal (Hold) and a completion signal (Complete). The output of the logic circuit 603 is a partial reconfiguration hold signal (PR_Hold) coupled to an inverter 604 configured to generate an inverted partial reconfiguration hold signal (PR_Hold_B) and a delayed partial reconfiguration hold signal (PR_Hold_Delayed) generated by a delay element 606. The partial reconfiguration hold signal includes PR_Hold, PR_Hold_B, and PR_Hold_Delayed and is used to control a plurality of selection circuits shown as a multiplexer as an example.

[0018] The first selection circuit 608 is configured to receive a termination value (Termination) and a partial reconfiguration value (PR_constant) (i.e., the value held by the output during partial reconfiguration). The output is generated in response to the PR_Hold_Delayed signal applied to the selection input of the selection circuit 608. The output of the first selection circuit 608 and the delayed output generated via the delay element 610 are coupled to another selection circuit 612. The data input to the IO port 614 is generated in response to the PR_Hold signal applied to the control terminal of the selection circuit 612. When the termination value is selected by the selection circuit 608, the impedance of the IO port 614 can be controlled to enable receiving input data (DATA) at the IO port. When the PR_Constant is selected by the selection circuit 608, the output of the IO port 614 can be held at a predetermined value, such as during partial reconfiguration.

[0019] An additional circuit element is provided in the IO circuit 600 to enable the IO port 614. The selection circuit 616 is coupled to receive an enable signal (Data_EN) for normal operation and a partial reconstruction enable signal (PR_Constant). The output and the delayed output generated by the delay element 618 are supplied to the input of the selection circuit 620. The selection circuit 620 generates an enable signal (Enable) for the IO port 614 in response to the PR_Hold_B signal supplied to the control terminal of the selection circuit 620. The enable signal enables the IO port 614 to generate an output based on the Data or the output of the selection circuit 612 supplied to the input / output circuit 614. In other words, the data generated at the output of the IO port may include data generated during the normal operation of the IO circuit 614, or predetermined fixed values ​​used to hold the values ​​at the output of the IO circuit for external circuitry (e.g., memory) during partial reconstruction. The termination value, PR_constant value, and Data_En value can be stored in registers having outputs coupled to the selection circuits 608 and 616.

[0020] Delay elements may be included to ensure the presence of make-before-break connections. More specifically, delay element 606 is used to generate a delayed PR Hold signal so that the outputs of selectors 608 and 616 are not selected until selectors 612 and 620 are selected. Delay element 618 may be used to delay the data enable value (i.e., Data_En) so that the termination value is prepared before the data transmitted during normal operation (DATA) becomes unusable. Thus, delay element 618 ensures that the output is always either a logical 0 or 1. Furthermore, if the output value is to be released from hold during the PR hold period, it is beneficial to delay the termination value generated at the output of selector 608, for example, by using delay element 610. Note that the operation of selectors 612 and 620 is opposite: when entering PR Hold mode, the delayed output of multiplexer 608 is used, and when exiting PR Hold mode, the delayed output of multiplexer 616 is used. As explained with reference to Figure 2, the input / output ports 307 and 614 in Figures 3, 4, and 6 can also function as input ports, and the values ​​in the input ports are held at fixed values.

[0021] Next, referring to Figure 7, a block diagram of a portion of an integrated circuit device relating to the operation of the I / O pads of the integrated circuit device is shown. The portion of the integrated circuit in Figure 7 comprises a fabric 702, a physical interface (PHY) 704, a physical I / O (PIO) 706, and a contact element 708. The fabric 702 may include programmable resources of a programmable logic device, as described with reference to Figures 10 and 11. The contact element 708 is, for example, a contact pad of the integrated circuit device, or other connecting element used to electrically connect one circuit to another. Circuits and methods for maintaining voltage values ​​in the contact element 708 may be implemented, for example, in the PIO 706 and controlled by circuits in the fabric 702 and PHY 704. According to other implementations, the I / O interface is located between the fabric and the PHY and may require further multiplexers and constant program values. The I / O circuits may be used with different I / O interface types. For example, I / O may be connected via a physical interface (PHY) to a hard double data-rate memory controller (DDRMC) that does not require connection to the fabric, or to the fabric of a programmable logic device via a PHY, or to the fabric via a PHY (Component), or to the fabric, for example, via a PHY feedthrough.

[0022] Referring now to Figure 8, the block diagram shows the implementation of the I / O circuitry coupled to the memory element. The first circuit 802 is an integrated circuit, such as a programmable logic device, and is coupled to a second circuit, which is a memory circuit, such as a double data rate 4 (DDR4) memory. The reconfigurable logic module 806, which has memory interface logic, generates logical values ​​(i.e., logic "1" or "0") at multiple outputs. These outputs are shown here, for example, as tristate buffers configured to receive both data and tristate control signals. The multiple output pads of the first circuit 802 and the corresponding input pads of the second circuit 804 include a clock enable (CKE) output pad 810 coupled to the corresponding clock enable input pad 812, a chip select (CS_n) pad 814 coupled to the corresponding chip select pad 816, an active open row (ACT_n) pad 818 coupled to the corresponding active open row pad 820, a column address select (CAS_n) pad 822 coupled to the corresponding column address select pad 824, a row address select (RAS_n) pad 826 coupled to the corresponding row address select pad 828, and a write enable (WE_n) pad 830 coupled to the corresponding write enable pad 832.

[0023] In some implementations, the above circuit and method can be used to retain values ​​in a memory device in self-refresh mode. As shown in Figure 8, the interface controller first applies self-refresh entry commands (CS_n, RAS_n, CAS_n, and CKE held low when WE_n and ACT_n are high) to buffer 808. As shown in Figure 9, the interface controller retains values ​​enforced by the activation of a partial reconfiguration hold signal (PR_HOLD) generated by the reconfiguration logic module 806 to keep the memory self-refresh while the interface controller is reconfigured. That is, the values ​​in output pads 808, 810, 814, 822, 826 and 830 are retained at specific values ​​during partial reconfiguration to maintain self-refresh mode. It should be understood that circuits 802 and 804 can be implemented on a single IC die, on separate IC dies of a single device (e.g., a multi-chip module or a board with direct-connect IC dies), on separate dies on a printed circuit board (PCB) (e.g., direct-connect dies), or in separate IC packages.

[0024] The circuit and method improve performance by eliminating the need to implement isolation logic between the I / O interface and the programmable logic (which may require the use of programmable logic that could be better utilized elsewhere) and by enabling an isolation control signal when a PR is about to occur. The circuit and method also prevent the implementation of the I / O interface within a reconfigurable module if the interface had to be shut down, reprogrammed, and recalibrated before the reconfigurable module could be made available again. Such implementations are undesirable because they can, for example, add extra time to the partial reconfiguration process or lead to the loss of data stored in external memory.

[0025] Next, referring to Figure 10, other block diagrams of programmable logic devices with I / O circuits are shown. While devices with programmable resources can be implemented as any type of integrated circuit device, such as an ASIC (application-specific integrated circuit), other devices have dedicated programmable logic devices (PLDs). One type of PLD is a CPLD (Complex Programmable Logic Device). A CPLD contains two or more "functional blocks" connected to each other by an interconnect switch matrix and connected to input / output (I / O) resources. Each functional block of a CPLD contains a two-level AND / OR structure similar to those used in PLA (Programmable Logic Array) or PAL (Programmable Array Logic) devices. Another type of PLD is an FPGA (field programmable gate array). In a typical FPGA, configurable logic blocks (CLBs) are coupled to programmable input / output blocks (IOBs). CLBs and IOBs are interconnected by a hierarchy of programmable transmit resources. CLBs, IOBs, and programmable transmit resources are typically customized by loading a configuration bitstream from off-chip memory into the FPGA's configuration memory cells. For both of these types of programmable logic devices, the functionality of the device is controlled by the configuration data bits of the configuration bitstream provided to the device for that purpose (or configuration data bits transmitted during partial reconfiguration). The configuration data bits can be stored in volatile memory (e.g., static memory cells in FPGAs and some CPLDs), non-volatile memory (flash memory in some CPLDs), or any other type of memory cell.

[0026] The device in Figure 10 features an FPGA architecture 1000 with numerous different programmable tiles. These programmable tiles include multi-gigabit transceivers (MGTs) 1001, CLBs 1002, random access memory blocks (BRAMs) 1003, input / output blocks (IOBs) 1004, configuration and clock logic (CONFIG / CLOCKS) 1005, digital signal processing blocks (DSPs) 1006, dedicated input / output blocks (I / O) 1007 (e.g., configuration ports and clock ports), and other programmable logic 1008 such as a digital clock manager, analog-to-digital converter, and system monitoring logic. Some FPGAs also include dedicated processing blocks (PROCs) 1010, which may be used, for example, to implement software applications.

[0027] In some FPGAs, each programmable tile includes a programmable interconnect element (INT) 1011 that has standardized connections to the corresponding interconnect elements in each of the adjacent tiles. Therefore, together, the programmable interconnect elements realize a programmable interconnect structure for the illustrated FPGA. The programmable interconnect element 1011 also includes connections to programmable logic elements within the same tile, as shown in the example included at the top of Figure 10.

[0028] For example, CLB1002 may include a configurable logic element (CLE) that can be programmed to implement a single programmable interconnect element 1011 in addition to user logic. BRAM1003 may include one or more programmable interconnect elements in addition to BRAM logic elements (BRL)1013. BRAM includes a dedicated memory separate from the distributed RAM of the configurable logic block. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the illustrated implementation, the BRAM tile is the same height as five CLBs, but other numbers may also be used. DSP tile 1006 may include a suitable number of programmable interconnect elements in addition to DSP logic elements (DSPL)1014. IOB1004 may include, for example, one programmable interconnect element 1011 in addition to two input / output logic elements (IOL)1015. The circuit and method may be implemented using IOL1015. The connection locations of a device are controlled by configuration data bits in a configuration bitstream provided to the device for that purpose. Programmable interconnects, in response to the bits in the configuration bitstream, enable connections, including interconnect lines, used to couple various signals to circuits implemented in programmable logic, other circuits such as BRAMs, or processors.

[0029] In the illustrated implementation, the column region near the center of the die is used for configuration, clock, and other control logic. The config / clock distribution region 1009 extending from this column is used to distribute clock and configuration signals throughout the FPGA. Some FPGAs utilizing the architecture illustrated in Figure 10 include additional logic blocks that disrupt the regular column structure that makes up the majority of the FPGA. These additional logic blocks may be programmable blocks and / or dedicated logic. For example, the processor block PROC1010 shown in Figure 10 consists of a sequence of CLBs and BRAMs.

[0030] It should be noted that Figure 10 is intended only to illustrate a representative example of an FPGA architecture. The number of logic blocks in a column, the relative width of the column, the number and order of the columns, the types of logic blocks in a column, the relative size of the logic blocks, and the interconnect / logic implementation included at the top of Figure 10 are merely illustrative. For example, in a real FPGA, there are typically more than one adjacent column to the CLBs, wherever the CLBs are, to facilitate the efficient implementation of user logic. While the implementation in Figure 10 relates to an integrated circuit with programmable resources, it should be understood that the above circuit and method can be implemented in any type of device with a combination of programmable resources and hard blocks.

[0031] Next, referring to Figure 11, a block diagram of the configuration logic elements that can be implemented in Figure 10 is shown. Specifically, Figure 11 shows a simplified configuration logic element of the configuration logic block 1002 in Figure 10, which is an example of programmable logic. In the implementation configuration of Figure 11, slice M1101 includes four reference tables (LUTMs) 1101A to 1101D. Each reference table is driven by six LUT data input terminals A1 to A6, B1 to B6, C1 to C6, and D1 to D6, which provide two LUT output signals O5 and O6. The O6 output terminals from LUTs 1101A to 1101D drive slice output terminals A to D, respectively. The LUT data input signals are supplied via an input multiplexer by an FPGA interconnect structure that can be implemented by the programmable interconnect element 1111. The LUT output signals are also supplied to the interconnect structure. Slice M further includes output selection multiplexers 1111A-1111D that drive output terminals AMUX-DMUX, multiplexers 1112A-1112D that drive data input terminals of memory elements 1102A-1102D, combinational multiplexers 1116, 1118 and 1119, bounce multiplexer circuits 1122 and 1123, a circuit represented by inverter 1105 and multiplexer 1106 (together providing optional inversion to the input clock path), and carry logic having multiplexers 1114A-1114D, 1115A-1115D, 1120, 1121 and exclusive OR gates 1113A-1113D. All of these elements are connected as shown in Figure 11. Although the selection input for the multiplexer shown in Figure 11 is not shown, the selection input is controlled by the configuration memory cell. That is, the configuration bits of the configuration bitstream stored in the configuration memory cell are coupled to the selection input of the multiplexer in order to select the correct input to the multiplexer. These configuration memory cells are known and are omitted from Figure 11, as with other selection diagrams in this specification, for clarity.

[0032] In the illustrated implementation, each memory element 1102A to 1102D can be programmed to function as a synchronous or asynchronous flip-flop or latch. The selection between synchronous and asynchronous functionality is made by the synchronous / asynchronous (Syns / Asynch) selection circuit 1103 for all four memory elements in the slice. If a memory element is programmed to provide a set function via the S / R (set / reset) input signal, the REV input terminal provides a reset function. If a memory element is programmed to provide a reset function via the S / R (set / reset) input signal, the REV input terminal provides a set function. Memory elements 1102A to 1102D are clocked by a clock signal CK, which may be provided, for example, by a global clock network or interconnect structure. Such programmable memory elements are well known in the field of FPGA design. Each memory element 1102A to 1102D provides registered output signals AQ to DQ to the interconnect structure. Since each LUT1101A~1101D provides two output signals, O5 and O6, the LUTs can be configured to function as two 5-input LUTs with five shared input signals (IN1~IN5), or as a single 6-input LUT with input signals IN1~IN6.

[0033] In the implementation shown in Figure 11, each LUT 1101A-1101D can function in any of several modes. In table reference mode, each LUT has six data input signals IN1-IN6 supplied by the FPGA interconnect structure via input multiplexers. One of 64 data values ​​is programmatically selected from the configuration memory cell based on the values ​​of signals IN1-IN6. In RAM mode, each LUT functions as either a single 64-bit RAM or two 32-bit RAMs sharing an address. RAM write data is supplied to the 64-bit RAM via input terminal DI1 (via multiplexers 1117A-1117C for LUTs 1101A-1101C) or to the two 32-bit RAMs via input terminals DL1 and DL2. RAM write operations within the LUT RAMs are controlled by a clock signal CK from multiplexer 1106 and a write enable signal WEN from multiplexer 1107, which may selectively pass either the clock enable signal CE or the write enable signal WE. In shift register mode, each LUT functions as two 16-bit shift registers, or with two 16-bit shift registers connected in series to create a single 32-bit shift register. Shift-in signals are provided via one or both of the input terminals DI1 and DI2. 16-bit and 32-bit shift-out signals can be provided via the LUT output terminals. A 32-bit shift-out signal can also be provided more directly via the LUT output terminal MC31. The 32-bit shift-out signal MC31 for LUT 1101A can also be provided via the general interconnect structure for shift register chaining, through the output selection multiplexer 1111D and the CLE output terminal DMUX. Therefore, the above circuits and methods can be implemented in devices such as those shown in Figures 10 and 11, or in any other suitable device.

[0034] Referring next to Figure 12, the flowchart illustrates how to implement I / O circuits within an integrated circuit device. In block 1202, an interface circuit is coupled to an input / output port. The input / output port is configured to receive data. The interface circuit includes a selection circuit that allows selection of data and predetermined values. The input / output port may be, for example, the input / output ports in Figures 2, 3, 4, and 6. In block 1204, a control circuit is configured to control the selection circuit of the interface circuit. The control circuit may be, for example, the control circuit in Figures 2, 3, 4, and 6. In block 1206, the input / output port is held to a predetermined value, such as logic 0 or logic 1, in response to a control signal from the control circuit during partial reconfiguration of the integrated circuit device.

[0035] In one implementation, the step of configuring an interface circuit includes configuring a multiplexer having a first input for receiving data and a second input for receiving a predetermined value. The method includes configuring a register having a data input for receiving data and a data output for generating data in response to a clock signal. The method may further include connecting a tristate buffer between the output of a selection circuit and an input / output port, and configuring a second register for receiving a buffer control signal. The buffer control signal is used to control the tristate buffer. A second selection circuit may also be implemented, having a first input configured to receive the buffer control signal via the second register, and a second input configured to receive a second predetermined value. The step of configuring the second selection circuit includes configuring a multiplexer having a first input for receiving the buffer control signal via the second register, and a second input for receiving a second predetermined value. The output of the control circuit is coupled to the control terminal of the second selection circuit. The method may further include configuring registers for receiving data and a clock signal, and configuring a synchronization circuit for receiving a clock signal and generating a synchronization control signal coupled to the selection circuit. The step of configuring the synchronous circuit may include configuring multiple registers in series to receive control signals at the data input and a clock signal. The synchronous control signals are generated at the outputs of the multiple registers. As shown and explained in Figures 8 and 9, the memory may be coupled to input / output ports. The values ​​at the input / output ports are held at predetermined values ​​during partial reconstruction.

[0036] The method shown in Figure 12 can be implemented using the circuits described in Figures 1 to 11, or other suitable circuits. While specific elements of the method have been described, it should be understood that additional elements of the method or additional details related to those elements can be implemented in accordance with the disclosures in Figures 1 to 6.

[0037] In one example, a circuit for sending data within an integrated circuit device comprises input / output ports, an interface circuit coupled to the input / output ports and configured to receive data, and a control circuit. The interface circuit includes a selection circuit that allows selection of data or a predetermined value. The control circuit is coupled to control the selection circuit. The control circuit holds the input / output ports at a predetermined value during partial reconfiguration of the integrated circuit device.

[0038] In one example, the selection circuit comprises a multiplexer having a first input configured to receive data and a second input configured to receive a predetermined value. In another example, the circuit further comprises a register having a data input configured to receive data and a data output configured to generate data in response to a clock signal. The data is coupled to the first input of the selection circuit. In yet another example, the circuit further comprises a tristate buffer coupled between the output of the selection circuit and an input / output port. In yet another example, the circuit further comprises a second register having an input for receiving a buffer control signal. The buffer control signal is used to control the tristate buffer. In yet another example, the circuit further comprises a second selection circuit having a first input configured to receive a buffer control signal via the second register and a second input configured to receive a second predetermined value. In yet another example, the second selection circuit comprises a multiplexer having a first input configured to receive a buffer control signal via the second register and a second input configured to receive a second predetermined value. The output of the control circuit is coupled to the control terminal of the second selection circuit. In one example, the circuit further comprises registers configured to receive data and clock signals. The circuit further comprises a synchronization circuit configured to receive a clock signal and generate a synchronization control signal coupled to a selection circuit. In one example, the synchronization circuit comprises a plurality of registers coupled in series to receive a synchronization control signal at a data input and a clock signal. The synchronization control signal is generated at the outputs of the plurality of registers.

[0039] In one example, a method for configuring a circuit for sending data within an integrated circuit device includes the step of coupling an interface circuit to input / output ports. The input / output ports are configured to receive data. The interface circuit includes a selection circuit that allows selection of data and predetermined values. The method includes the steps of configuring a control circuit to control the selection circuit and holding the input / output ports at predetermined values ​​during partial reconfiguration of the integrated circuit device.

[0040] In one example, the step of configuring an interface circuit includes the step of configuring a multiplexer having a first input for receiving data and a second input for receiving a predetermined value. In one example, the method further includes the step of configuring a register having a data input for receiving data and a data output for generating data in response to a clock signal. In one example, the method further includes the step of coupling a tristate buffer between the output of a selection circuit and an input / output port. In one example, the method includes the step of configuring a register for receiving data and a clock signal, and the step of configuring a synchronization circuit that receives a clock signal and generates a synchronization control signal coupled to the selection circuit. In one example, the method further includes the step of coupling memory to an input / output port. The values ​​at the input / output port are held at predetermined values ​​during partial reconfiguration.

[0041] Therefore, it can be understood that a novel circuit and method for implementing an I / O interface within an integrated circuit has been described. It should be understood that the existence of numerous alternative and equivalent configurations incorporated into the disclosed invention will be apparent to those skilled in the art. Consequently, the invention should not be limited to the aforementioned implementation forms, but should be limited only to the following claims.

Claims

1. A circuit for sending data within an integrated circuit device including a programmable resource having a logic element that can be configured using configuration data, An input / output port configured so that it cannot be reconfigured by the aforementioned programmable resource, The system includes an interface circuit that is coupled to the input / output port and configured to receive data, The interface circuit includes a selection circuit that enables the selection of the data or a predetermined value. The circuit comprises a control circuit coupled to control the selection circuit, The impedance of the input / output port is controlled to be able to receive the data or predetermined value selected by the selection circuit. The aforementioned control circuit is The system is configured to receive a first signal indicating that the initial configuration of the programmable resource is complete and a second signal indicating a request for partial reconfiguration of the programmable resource, and to generate a control signal based on the first and second signals indicating that the initial configuration is complete and that the request exists, and output it to the selection circuit. After the completion of the initial configuration, the input / output ports are held at the predetermined values ​​during the partial reconstruction. A circuit that enables the supply of the data from the selection circuit to the input / output port after the completion of the partial reconstruction.

2. The circuit according to claim 1, wherein the control circuit is configured to synchronize the tristate signal received by the interface circuit with the data supplied from the selection circuit during the partial reconstruction.

3. The selection circuit includes a multiplexer, The aforementioned multiplexer is A first input configured to receive the aforementioned data, The circuit according to claim 1, further comprising a second input configured to receive the predetermined value.

4. With additional registers, The aforementioned register is A data input configured to receive the aforementioned data, It has a data output configured to generate the data in response to a clock signal, The circuit according to claim 1, wherein the aforementioned data is coupled to the first input of the selection circuit.

5. The circuit according to claim 1, further comprising a tristate buffer coupled between the output of the selection circuit and the input / output port.

6. It further comprises a second register having an input for receiving a buffer control signal, The circuit according to claim 5, wherein the buffer control signal is used to control the tristate buffer.

7. Further equipped with a second selection circuit, The second selection circuit is, A first input configured to receive the buffer control signal via the second register, The circuit according to claim 6, further comprising a second input configured to receive a second predetermined value.

8. The second selection circuit includes a multiplexer, The aforementioned multiplexer is A first input configured to receive the buffer control signal via the second register, It has a second input configured to receive the second predetermined value, The circuit according to claim 7, wherein the output of the control circuit is coupled to the control terminal of the second selection circuit.

9. The system further comprises registers configured to receive the aforementioned data and clock signals, The circuit according to claim 1, further comprising a synchronization circuit configured to receive the clock signal and generate a synchronization control signal coupled to the selection circuit.

10. The synchronization circuit includes a plurality of registers connected in series to receive the synchronization control signal and the clock signal at the data input, The circuit according to claim 9, wherein the synchronization control signal is generated at the output of the plurality of registers.

11. A method for configuring a circuit for sending data within an integrated circuit device including a programmable resource having a logic element that can be configured using configuration data, The step includes coupling the interface circuit to the input / output ports, The input / output port cannot be reconfigured by the programmable resource and is configured to receive data. The interface circuit includes a selection circuit that enables the selection of the data and a predetermined value. The impedance of the input / output port is controlled to be able to receive the data or predetermined value selected by the selection circuit. The process includes the step of configuring a control circuit to control the selection circuit, wherein the control circuit receives a first signal indicating that the initial configuration of the programmable resource is complete and a second signal indicating a request for partial reconfiguration of the programmable resource, and is configured to generate a control signal based on the first and second signals indicating that the initial configuration is complete and that the request exists, and output it to the selection circuit, and further, After the completion of the initial configuration, the control circuit holds the input / output ports at predetermined values ​​during partial reconfiguration of the integrated circuit device, A method comprising the step of enabling the output of the data from the selection circuit to the input / output port by the control circuit after the completion of the partial reconstruction.

12. The method according to claim 11, further comprising the step of configuring the control circuit to synchronize the tristate signal received by the interface circuit with the data supplied from the selection circuit during the partial reconstruction.

13. The method according to claim 11, wherein the step of configuring an interface circuit includes the step of configuring a multiplexer having a first input for receiving the data and a second input for receiving the predetermined value.

14. The method according to claim 11, further comprising the step of configuring a register having a data input for receiving the aforementioned data and a data output for generating the aforementioned data in response to a clock signal.

15. The method according to claim 11, further comprising the step of coupling a tristate buffer between the output of the selection circuit and the input / output port.

16. The steps include configuring a register to receive the aforementioned data and clock signal, The method according to claim 11, further comprising the step of receiving the clock signal and configuring a synchronization circuit for generating a synchronization control signal coupled to the selection circuit.

17. The step further includes coupling the memory to the input / output port, The method according to claim 11, wherein the value in the input / output port is maintained at the predetermined value during the partial reconstruction.

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