Real-time clock module

Abstract

To provide a real-time clock module capable of preventing unnecessary storage of event data in each application in a time stamp.SOLUTION: A real-time clock module includes a timer circuit for performing timing to generate time data, a selection circuit for selecting at least one of a plurality of kinds of event data as object event data to be a storage object depending on an occurrence of an event, and selecting data corresponding to at least a portion of time digits of the time data as object time data to be a storage object, and a memory circuit for storing the object time data and the object event data.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a real-time clock module.

Background Art

[0002] Patent Document 1 discloses an event recorder including a timekeeping unit that generates time data consisting of multiple digits, a memory that records the time data, a recording digit setting means that selects a part of the digits of the time data having multiple digits, an event detection circuit that detects the occurrence of an event, and a control circuit that records, in the memory, the time data having only the digits selected by the recording digit setting means and the occurrence of the event when the event occurs. According to this event recorder, the amount of time data recorded in the memory can be reduced, and the capacity of the memory can be saved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the event recorder described in Patent Document 1, although it is possible to select the digits of the time data stored in the memory when an event occurs, the types of event data stored simultaneously are fixed, and unnecessary event data may be stored in the memory depending on the application.

Means for Solving the Problems

[0005] One aspect of the real-time clock module according to the present invention is a timekeeping circuit that generates time data by performing timekeeping, A selection circuit that, in response to the occurrence of an event, selects at least one of several types of event data as the target event data to be stored, and also selects data corresponding to at least a portion of the time digits of the time data as the target time data to be stored. The system includes a memory circuit for storing the aforementioned target time data and the aforementioned target event data. [Brief explanation of the drawing]

[0006] [Figure 1] A diagram showing an example configuration of a system including a real-time clock module of the first embodiment. [Figure 2] Functional block diagram of the real-time clock module of the first embodiment. [Figure 3] A diagram showing an example of a processor configuration. [Figure 4] A figure showing an example of captured data in the first embodiment. [Figure 5] A timing chart diagram showing an example of timestamp processing using a selection circuit. [Figure 6] A diagram showing an example configuration of a system including a real-time clock module according to the second embodiment. [Figure 7] Functional block diagram of the real-time clock module of the second embodiment. [Figure 8] A figure showing an example of captured data in the second embodiment. [Modes for carrying out the invention]

[0007] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. There are none. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0008] 1. First Embodiment Figure 1 shows an example configuration of a system including a real-time clock module according to the first embodiment.

[0009] As shown in Figure 1, the real-time clock module 1 of the first embodiment is connected to the main power supply 4, the backup power supply 5, and the host device 6.

[0010] The real-time clock module 1 is supplied with power voltage VDD from the main power supply 4 and power voltage VBAT from the backup power supply 5. The real-time clock module 1 operates with power voltage VDD when power voltage VDD is supplied from the main power supply 4, and operates with power voltage VBAT when the supply of power voltage VDD from the main power supply 4 is cut off. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power voltage VDD from the main power supply 4 is cut off.

[0011] The host device 6 operates by receiving the power supply voltage VDD from the main power supply 4. In this embodiment, the host device 6 and the real-time clock module 1 are configured with the host device 6 as the master and the real-time clock module 1 as the slave. 2 Communication is conducted via the C bus. 2 C stands for Inter-Integrated Circuit. The host device 6 is implemented by, for example, an MCU or MPU. MCU stands for Micro Controller Unit, and MPU stands for Micro Processor Unit.

[0012] Figure 2 is a functional block diagram of the real-time clock module 1 of the first embodiment. As shown in Figure 2, the real-time clock module 1 comprises an oscillator 2 and a real-time clock circuit 3.

[0013] The real-time clock module 1 is supplied with the power supply voltage VDD from the main power supply 4 via the terminal P1 of the real-time clock circuit 3, and the power supply voltage VBAT is supplied from the backup power supply 5 via the terminal P2 of the real-time clock circuit 3.

[0014] The oscillator 2 may be a tuning fork type crystal oscillator, an AT-cut crystal oscillator, a SC-cut crystal oscillator, etc., or may be a piezoelectric oscillator other than a SAW resonator or a crystal oscillator. SAW is the abbreviation of Surface Acoustic Wave. Also, the oscillator 2 may be a MEMS oscillator made of a silicon semiconductor. MEMS is the abbreviation of Micro Electro Mechanical Systems. The oscillator 2 may be excited by the piezoelectric effect or driven by the Coulomb force.

[0015] The real-time clock circuit 3 includes an oscillation circuit 10, a frequency division circuit 20, a timing circuit 30, an event trigger circuit 40, a selection circuit 50, a memory circuit 60, a register group 70, an interface circuit 80, a temperature sensor 90, an oscillation monitoring circuit 100, a power supply voltage monitoring circuit 110, a power supply voltage selection circuit 120, a power supply circuit 130, and an interrupt generation circuit 140. However, the real-time clock circuit 3 may have a configuration in which some of these elements are omitted or changed, or other elements are added. In this embodiment, the real-time clock circuit 3 is a one-chip integrated circuit, but may be composed of a multi-chip integrated circuit, or at least a part thereof may be composed of discrete components.

[0016] The power supply voltage monitoring circuit 110 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is equal to or higher than a predetermined voltage value VT1, and outputs a determination signal VDET. In this embodiment, when the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is equal to or higher than the voltage value VT1, it outputs a determination signal VDET of a high level, and when it determines that the power supply voltage VDD is less than the voltage value VT1, it outputs a determination signal VDET of a low level.

[0017] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VDD, determines whether the power supply voltage VDD is less than or equal to a predetermined voltage value VT2, and outputs a first power supply voltage drop signal VDDLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is less than or equal to the voltage value VT2, it outputs a high-level first power supply voltage drop signal VDDLOW, and if it determines that the power supply voltage VDD is greater than the voltage value VT2, it outputs a low-level first power supply voltage drop signal VDDLOW. Note that the voltage value VT2 may be the same as or different from the voltage value VT1.

[0018] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VBAT, determines whether the power supply voltage VBAT is less than or equal to a predetermined voltage value VT3, and outputs a second power supply voltage drop signal VBATLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VBAT is less than or equal to the voltage value VT3, it outputs a high-level second power supply voltage drop signal VBATLOW, and if it determines that the power supply voltage VBAT is greater than the voltage value VT3, it outputs a low-level second power supply voltage drop signal VBATLOW.

[0019] Furthermore, the power supply voltage monitoring circuit 110 monitors the power supply voltage VOUT output from the power supply voltage selection circuit 120, determines whether the power supply voltage VOUT is less than or equal to a predetermined voltage value VT4, and outputs a third power supply voltage drop signal VTMPLOW. In this embodiment, if the power supply voltage monitoring circuit 110 determines that the power supply voltage VOUT is less than or equal to the voltage value VT4, it outputs a high-level third power supply voltage drop signal VTMPLOW, and if it determines that the power supply voltage VOUT is greater than the voltage value VT4, it outputs a low-level third power supply voltage drop signal VTMPLOW.

[0020] In this way, the power supply voltage monitoring circuit 110 monitors the power supply voltages VDD, VBAT, and VOUT, and generates power supply voltage monitoring data, namely the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW, respectively.

[0021] The power supply voltage selection circuit 120 selects either the power supply voltage VDD or the power supply voltage VBAT based on the determination signal VDET and outputs it as the power supply voltage VOUT. Specifically, the power supply voltage selection circuit 120 selects the power supply voltage VDD when the determination signal VDET is at a high level, that is, when the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is greater than or equal to the voltage value VT1. Conversely, the power supply voltage selection circuit 120 selects the power supply voltage VBAT when the determination signal VDET is at a low level, that is, when the power supply voltage monitoring circuit 110 determines that the power supply voltage VDD is less than the voltage value VT1.

[0022] Therefore, when the power supply voltage VDD is supplied from the main power supply 4 to the real-time clock module 1, the power supply voltage VOUT is the power supply voltage VDD and is a predetermined voltage value greater than or equal to VT1. When the supply of power supply voltage VDD from the main power supply 4 to the real-time clock module 1 is cut off, the power supply voltage VOUT immediately switches to the power supply voltage VBAT and becomes a predetermined voltage value less than or equal to VT1. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power supply voltage VDD from the main power supply 4 is cut off. In contrast, the host device 6 that controls the operation of the real-time clock module 1 operates when power supply voltage VDD is supplied from the main power supply 4, and stops operating when the supply of power supply voltage VDD from the main power supply 4 is cut off.

[0023] The power supply circuit 130 generates stabilized power supply voltages VOSC and VLOGIC with constant voltage values ​​based on the power supply voltage VOUT. The power supply circuit 130 is implemented, for example, by a regulator.

[0024] The power supply voltage VOSC is supplied to the oscillation circuit 10. The power supply voltage VLOGIC is supplied to the frequency divider circuit 20, the timing circuit 30, the event trigger circuit 40, the selection circuit 50, the memory circuit 60, the register group 70, the interface circuit 80, the temperature sensor 90, the oscillation monitoring circuit 100, the power supply voltage monitoring circuit 110, and the interrupt generation circuit 140.

[0025] The temperature sensor 90 outputs a temperature signal VTMP whose magnitude changes according to the temperature. The temperature signal VTMP may be a digital signal or an analog signal.

[0026] The oscillation circuit 10 generates a first clock signal CK1 by causing the resonator 2 to oscillate. Specifically, the oscillation circuit 10 is electrically connected to both ends of the resonator 2 via terminals P3 and P4 of the real-time clock circuit 3, and oscillates the resonator 2 by amplifying the output signal of the resonator 2 and feeding it back, thereby outputting the first clock signal CK1. The oscillation circuit 10 also incorporates a temperature compensation circuit that controls the frequency of the first clock signal CK1 to remain constant regardless of temperature by changing the frequency of the first clock signal CK1 according to the temperature signal VTMP output from the temperature sensor 90. In this embodiment, the frequency of the first clock signal CK1 is 32.768 kHz. However, the frequency of the first clock signal CK1 is not particularly limited. In this embodiment, when the power supply voltage VOUT is greater than the voltage value VT4, that is, when the third power supply voltage drop signal VTMPLOW is at a low level, the temperature compensation circuit operates normally. On the other hand, if the power supply voltage VOUT is less than or equal to the voltage value VT4, that is, if the third power supply voltage drop signal VTMPLOW is at a high level, the normal operation of the temperature compensation circuit cannot be guaranteed, and therefore the temperature compensation circuit will stop operating.

[0027] The oscillation monitoring circuit 100 monitors the first clock signal CK1, determines whether the oscillation circuit 10 has stopped oscillating, and outputs an oscillation stop signal FST. In this embodiment, the oscillation monitoring circuit 100 determines that the oscillation circuit 10 has stopped oscillating if the logic level of the first clock signal CK1 does not invert for a predetermined time, and outputs a high-level oscillation stop signal FST. Also, the oscillation monitoring circuit 100 determines that the oscillation circuit 10 has not stopped oscillating if the logic level of the first clock signal CK1 inverts within a predetermined time, and outputs a low-level oscillation stop signal FST. In this way, the oscillation monitoring circuit 100 monitors the first clock signal CK1 and generates the oscillation stop signal FST, which is oscillation monitoring data.

[0028] The frequency divider circuit 20 divides the first clock signal CK1 to generate a second clock signal CK2 having a desired frequency. In this embodiment, the division ratio of the frequency divider circuit 20 is 32, and the frequency of the second clock signal CK2 is 1.024 kHz. However, the division ratio of the frequency divider circuit 20 and the frequency of the second clock signal CK2 are not particularly limited.

[0029] The timing circuit 30 performs timing based on the second clock signal CK2 and generates time data TM. In this embodiment, the time data TM has time digits of 1 / 1024 seconds, seconds, minutes, hours, days, months, and years. Specifically, the time data TM consists of binary subsecond data representing time in units of 1 / 1024 seconds as 0 to 1023, BCD format second data representing time in units of seconds as 0 to 59, BCD format minute data representing time in units of minutes as 0 to 59, BCD format hour data representing time in units of hours as 0 to 23, BCD format day data representing time in units of days as 1 to 31, BCD format month data representing time in units of months as 1 to 12, and BCD format year data representing time in units of years as 0 to 9999. BCD stands for Binary Coded Decimal.

[0030] The event trigger circuit 40 receives the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3, which are input from the host device 6 via terminals P7, P8, and P9 of the real-time clock circuit 3, respectively. The rigger circuit 40 receives the event command detection signal WRCom output from the interface circuit 80. The event trigger circuit 40 also receives the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW output from the power supply voltage monitoring circuit 110. The event trigger circuit 40 also receives the oscillation stop signal FST output from the oscillation monitoring circuit 100. The event trigger circuit 40 outputs a high-pulse event trigger signal TRG when at least one rising edge occurs in the event command detection signal WRCom, the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, the third power supply voltage drop signal VTMPLOW, and the oscillation stop signal FST. The event trigger circuit 40 also outputs a high-pulse event trigger signal TRG when at least one of the specified edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3 occurs. The edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3, which generate the event trigger signal TRG, may be specified as rising edges, falling edges, or both edges, respectively, by the event control registers included in the register group 70.

[0031] The selection circuit 50, in response to the occurrence of an event, selects at least one of several types of event data as the target event data to be stored, and also selects data corresponding to at least some of the time digits of the time data TM generated by the timing circuit 30 as the target time data to be stored. In other words, the selection circuit 50 selects the target event data and target time data in response to the event trigger signal TRG output from the event trigger circuit 40.

[0032] The multiple types of event data may include the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, and the third power supply voltage drop signal VTMPLOW, which are power supply voltage monitoring data generated by the power supply voltage monitoring circuit 110. Furthermore, the multiple types of event data may also include the oscillation stop signal FST, which is oscillation monitoring data generated by the oscillation monitoring circuit 100.

[0033] Furthermore, events are generated by external input signals input from outside the real-time clock module 1, and multiple types of event data may include data corresponding to said external input signals. In this embodiment, said external input signals are a first event signal EVIN1, a second event signal EVIN2, a third event signal EVIN3, and an event generation command that generates an event, and the data corresponding to said external input signals are the first event signal EVIN1, the second event signal EVIN2, the third event signal EVIN3, and an event command detection signal WRCom.

[0034] The selection circuit 50 then causes the memory circuit 60 to store the captured data CPDT, which includes the target time data and the target event data. In other words, the selection circuit 50 performs a timestamp process in response to the event trigger signal TRG, associating the target time data with the target event data and storing it in the memory circuit 60.

[0035] In this embodiment, the selection circuit 50 includes a processor 51 and a non-volatile memory 52. ​​The non-volatile memory 52 stores an instruction set 521 that specifies target time data and target event data. The processor 51, in synchronization with the first clock signal CK1, selects the target time data and target event data based on the instruction set 521 and stores them in the memory circuit 60. That is, the instruction set 521 consists of a plurality of instruction codes necessary for the selection circuit 50 to perform timestamp processing.

[0036] In order to reduce power consumption, the processor 51 may wake from sleep mode when an event trigger signal TRG is generated, perform control processing and timestamp processing for the power supply circuit 130, and then return to sleep mode once these processes are completed.

[0037] Figure 3 shows an example configuration of the processor 51. As shown in Figure 3, the processor 51 includes a fetch circuit 511, a decode circuit 512, a logic operation circuit 513, a data buffer 514, and a capture circuit 515.

[0038] The fetch circuit 511 fetches each instruction code included in the instruction set 521 in sequence, synchronized with the first clock signal CK1.

[0039] The decode circuit 512, synchronized with the first clock signal CK1, sequentially decodes each instruction code fetched by the fetch circuit 511 and outputs a control signal corresponding to the decoding result.

[0040] The logic operation circuit 513 performs a logic operation selected from multiple types of logic operations according to the control signal output from the decoding circuit 512 on one or two input data selected from multiple input data. The multiple input data include subsecond data, second data, minute data, hour data, day data, month data, and year data included in the time data TM, and the first power supply voltage drop signal VDDLOW, second power supply voltage drop signal VBATLOW, third power supply voltage drop signal VTMPLOW, oscillation stop signal FST, first event signal EVIN1, second event signal EVIN2, third event signal EVIN3, and event command detection signal WRCom included in multiple types of event data. The multiple types of logic operations include, for example, through operation, NOT operation, AND operation, OR operation, XOR operation, bit shift operation, addition, subtraction, etc.

[0041] The data buffer 514 holds the data output from the logic circuit 513 in synchronization with the first clock signal CK1.

[0042] The capture circuit 515, in accordance with the control signal output from the decode circuit 512 and synchronized with the first clock signal CK1, writes the data held in the data buffer 514 to the current address of the memory circuit 60 and increments the address. The data buffer 514 holds, for example, each 8-bit data that constitutes the captured data CPDT in order, and the capture circuit 515 writes each of these data to the memory circuit 60.

[0043] In this embodiment, the processor 51, in accordance with the instruction set 521, can cause the memory circuit 60 to store the captured data CPDT, which includes the selected target time data and target event data, when an event trigger signal TRG is generated. That is, each data that constitutes the captured data CPDT can be arbitrarily selected by the instruction set 521.

[0044] Furthermore, according to the instruction set 521, the processor 51 can also perform timestamp processing only when an event trigger signal TRG occurs, and the cause of the event trigger signal TRG is one or more signals selected from the first power supply voltage drop signal VDDLOW, the second power supply voltage drop signal VBATLOW, the third power supply voltage drop signal VTMPLOW, the oscillation stop signal FST, the first event signal EVIN1, the second event signal EVIN2, the third event signal EVIN3, and the event command detection signal WRCom. In other words, the signal that triggers timestamp processing can be arbitrarily selected by the instruction set 521. For example, the instruction set 521 can be used to perform timestamp processing If only the first event signal EVIN1 is selected as the triggering signal, the processor 51 can determine whether the cause of the event trigger signal TRG is the first event signal EVIN1, based on the logic level of the first event signal EVIN1, when the event trigger signal TRG occurs, and then decide whether or not to perform timestamp processing based on the determination result.

[0045] Returning to the explanation of Figure 2, the memory circuit 60 stores the capture data CPDT, which includes the target time data and target event data selected by the selection circuit 50. In this embodiment, the memory circuit 60 is a volatile memory such as SRAM and functions as an N-stage FIFO capable of storing N capture data CPDTs. That is, the memory circuit 60 can simultaneously store N capture data CPDTs for N occurrences of events. SRAM stands for Static Random Access Memory, and FIFO stands for First In First Out.

[0046] When the processor 51 finishes timestamp processing based on the event trigger signal TRG, it outputs a timestamp completion signal TSEND to the interrupt generation circuit 140.

[0047] The interrupt generation circuit 140 generates an interrupt signal INT based on the timestamp end signal TSEND and outputs the interrupt signal INT to the host device 6 via terminal P10 of the real-time clock circuit 3. Upon receiving the interrupt signal INT, the host device 6 performs predetermined interrupt processing. For example, the host device 6 sends a command to the real-time clock module 1 requesting the reading of timestamp data and receives the captured data CPDT stored in the memory circuit 60 from the real-time clock module 1.

[0048] Furthermore, in order to reduce the overall power consumption of the system, the host device 6 enters a sleep state when not performing any processing. When it receives an interrupt signal INT while in the sleep state, it wakes up from the sleep state, reads the timestamp data, and then returns to the sleep state once the necessary processing is complete.

[0049] The register group 70 includes various registers. For example, the register group 70 includes an event control register, a flag register, a command trigger register, etc. The event control register holds, for example, 2 bits of data for specifying whether the edges of the first event signal EVIN1, the second event signal EVIN2, and the third event signal EVIN3 that generate the event trigger signal TRG are rising edges, falling edges, or both. The flag register holds a first power supply voltage drop flag, which is set to 1 when the rising edge of the first power supply voltage drop signal VDDLOW occurs; a second power supply voltage drop flag, which is set to 1 when the rising edge of the second power supply voltage drop signal VBATLOW occurs; a third power supply voltage drop flag, which is set to 1 when the rising edge of the third power supply voltage drop signal VTMPLOW occurs; and an oscillation stop flag, which is set to 1 when the rising edge of the oscillation stop signal FST occurs. The command trigger register is a register for generating an event command detection signal WRCom in response to an event generation command.

[0050] The interface circuit 80 is a communication interface circuit between the real-time clock module 1 and the host device 6. In communication via the interface circuit 80, the host device 6 is the master and the real-time clock module 1 is the slave. That is, the interface circuit 80 functions as a slave interface to the host device 6. In this embodiment, the interface circuit 80 is I 2 This is a C-bus compatible interface circuit, and it is connected via terminal P5 of the real-time clock circuit 3. The real-time clock circuit 3 communicates with the host device 6 based on the input serial clock signal SCL and the serial data signal SDA that is input / output via terminal P6 of the real-time clock circuit 3. However, the interface circuit 80 may be another serial bus compatible interface circuit such as SPI, or a parallel bus compatible interface circuit. SPI stands for Serial Peripheral Interface.

[0051] The interface circuit 80 receives commands from the host device 6 via terminals P5 and P6, and performs various processes according to the received commands.

[0052] Specifically, when the interface circuit 80 receives a command from the host device 6 requesting time setting, it updates the time data TM generated by the timing circuit 30 with the time data included in the command.

[0053] Furthermore, when the interface circuit 80 receives a command from the host device 6 requesting time reading, it acquires the time data TM generated by the timing circuit 30 and transmits it to the host device 6.

[0054] Furthermore, when the interface circuit 80 receives a command from the host device 6 requesting the reading of timestamp data, it reads the captured data CPDT from the memory circuit 60 and sends it to the host device 6.

[0055] Furthermore, when the interface circuit 80 receives a command from the host device 6 requesting the writing or reading of data to or from various registers included in the register group 70, it performs the writing or reading of data to or from the target register. For example, when the interface circuit 80 receives an event occurrence command, which is a command requesting the writing of arbitrary data to a command trigger register, it generates an event command detection signal WRCom.

[0056] Furthermore, when the interface circuit 80 receives a command from the host device 6 requesting to write or read data to or from the non-volatile memory 52, it performs the writing or reading of data to or from the non-volatile memory 52. ​​For example, in the pre-shipment inspection process of the real-time clock module 1, the inspection device, which functions as the host device 6, sends a command requesting to write the instruction set 521 to the non-volatile memory 52, and the interface circuit 80 receives the command and writes the instruction set 521 to the non-volatile memory 52.

[0057] Figure 4 shows an example of capture data CPDT stored in the memory circuit 60. In the example in Figure 4, the capture data CPDT is 64 bits of data and is stored, for example, at addresses 0x0 to 0x07 of the memory circuit 60.

[0058] Specifically, at address 0x0 of the memory circuit 60, bits 7-2 store the lower 6 bits of the 10-bit subsecond data included in the time data TM, bit 1 stores data corresponding to the logic level of the third event signal EVIN3, and bit 0 stores data corresponding to the logic level of the second event signal EVIN2.

[0059] Furthermore, at address 0x1 of the memory circuit 60, bits 7 to 4 store the lower 4 bits of the 7-bit second data included in the time data TM, and bits 3 to 0 store the upper 4 bits of the 10-bit subsecond data.

[0060] Furthermore, at address 0x2 of the memory circuit 60, bits 7 to 3 contain time data TM. The 5 bits of minute data contained within are stored, and bits 2 through 0 store the upper 3 bits of the 7 bits of second data.

[0061] Furthermore, at address 0x3 of the memory circuit 60, bits 7-2 store the 6-bit time data included in the time data TM, and bits 1-0 store the upper 2 bits of the 7-bit minute data.

[0062] Furthermore, at address 0x4 of the memory circuit 60, bits 7 to 6 store the lower two bits of the five-bit month data included in the time data TM, and bits 5 to 0 store the six-bit day data included in the time data TM.

[0063] Furthermore, at address 0x5 of the memory circuit 60, bits 7 to 3 store the lower 5 bits of the 8-bit year data included in the time data TM, and bits 2 to 0 store the upper 3 bits of the 5-bit month data.

[0064] Furthermore, at address 0x6 of the memory circuit 60, bit 7 stores data corresponding to the logic level of the second power supply voltage drop signal VBATLOW, bit 6 stores data corresponding to the logic level of the third power supply voltage drop signal VTMPLOW, bit 5 stores data corresponding to the logic level of the first power supply voltage drop signal VDDLOW, bit 4 stores data corresponding to the logic level of the oscillation stop signal FST, bit 3 stores data corresponding to the logic level of the first event signal EVIN1, and bits 2 to 0 store the upper 3 bits of the 8-bit year data.

[0065] Furthermore, address 0x7 of the memory circuit 60 stores data indicating the trigger for the timestamp processing. Specifically, if the third event signal EVIN3 is the trigger, bit 7 is set to 1; if the second event signal EVIN2 is the trigger, bit 6 is set to 1; if the first event signal EVIN1 is the trigger, bit 5 is set to 1; if the second power supply voltage drop signal VBATLOW is the trigger, bit 4 is set to 1; if the third power supply voltage drop signal VTMPLOW is the trigger, bit 3 is set to 1; if the first power supply voltage drop signal VDDLOW is the trigger, bit 2 is set to 1; if the oscillation stop signal FST is the trigger, bit 1 is set to 1; and if the event command detection signal WRCom is the trigger, bit 0 is set to 1.

[0066] In the example shown in Figure 4, the sub-second data, second data, minute data, hour data, day data, month data, and year data are the target time data, while all other data are the target event data.

[0067] In the example shown in Figure 4, the captured data CPDT, which is the subject of the timestamp, is 64 bits of data. For the selection circuit 50 to write the captured data CPDT to the memory circuit 60 all at once, it is necessary to allocate 64 bits of data to one address in the memory circuit 60, which increases the size of both the memory circuit 60 and the selection circuit 50. Therefore, in this embodiment, 8 bits of data are allocated to one address in the memory circuit 60, and the selection circuit 50 is configured to acquire 8 bits of data and write it to the memory circuit 60 eight times, thereby reducing the size of both the memory circuit 60 and the selection circuit 50. However, on the other hand, the selection circuit 50 requires at least 8 cycles to acquire the data necessary for the captured data CPDT. Consequently, if a time update timing occurs during the period when the time data TM is being acquired by the selection circuit 50, the target time data included in the captured data CPDT will be partially pre-update data and partially post-update data, resulting in an incorrect input to the memory circuit 60. There is a possibility that the time data will be stored.

[0068] Therefore, in this embodiment, the selection circuit 50 performs timestamp processing to acquire the target time data and store it in the memory circuit 60 after the event occurs, that is, after the event trigger signal TRG is generated and the next time update timing has arrived. Figure 5 is a timing chart diagram showing an example of timestamp processing by the selection circuit 50. In Figure 5, the captured data CPDT is assumed to be 64 bits of data.

[0069] In the example shown in Figure 5, the event trigger signal TRG changes from a low level to a high level in synchronization with the rising edge of the first clock signal CK1 at time t1, and changes from a high level to a low level in synchronization with the rising edge of the first clock signal CK1 at time t2. In other words, the event trigger signal TRG, which triggers the timestamp processing, is generated between times t1 and t2.

[0070] The time data TM is updated by the change in subsecond data SSB from n to n+1, synchronized with the rising edge of the first clock signal CK1 at time t3. In other words, time t3 corresponds to the next time update timing after the event trigger signal TRG occurs.

[0071] After the time update timing arrives at time t3, the selection circuit 50 first acquires the first 8-bit data D0 of the captured data CPDT into the data buffer 514, synchronized with the rising edge of the first clock signal CK1 at time t4.

[0072] Next, the selection circuit 50 sets the write signal wr to a high level, sets the memory address maddr to 0x0, and sets the memory data mdata to the 8-bit data D0 held by the data buffer 514, synchronized with the rising edge of the first clock signal CK1 at time t5. The write signal wr, memory address maddr, and memory data mdata are supplied from the capture circuit 515 to the memory circuit 60. The selection circuit 50 also acquires the second 8-bit data D1 of the captured data CPDT into the data buffer 514, synchronized with the rising edge of the first clock signal CK1 at time t5.

[0073] Next, synchronized with the rising edge of the first clock signal CK1 at time t6, 8-bit data D0 is written to address 0x0 of the memory circuit 60. Also, synchronized with the rising edge of the first clock signal CK1 at time t6, the selection circuit 50 sets the memory address maddr to 0x1 and sets the memory data mdata to 8-bit data D1 held by the data buffer 514. Furthermore, synchronized with the rising edge of the first clock signal CK1 at time t6, the selection circuit 50 acquires the third 8-bit data D2 of the captured data CPDT into the data buffer 514.

[0074] Next, synchronized with the rising edge of the first clock signal CK1 at time t7, 8-bit data D1 is written to address 0x1 of the memory circuit 60. Also, synchronized with the rising edge of the first clock signal CK1 at time t7, the selection circuit 50 sets the memory address maddr to 0x2 and sets the memory data mdata to 8-bit data D2 held by the data buffer 514. Furthermore, synchronized with the rising edge of the first clock signal CK1 at time t7, the selection circuit 50 acquires the fourth 8-bit data D3 of the captured data CPDT into the data buffer 514.

[0075] Next, synchronized with the rising edge of the first clock signal CK1 at time t8, 8-bit data D2 is written to address 0x2 of the memory circuit 60. Also, selection circuit 5 0 sets the memory address maddr to 0x3 and the memory data mdata to the 8-bit data D3 held by the data buffer 514, synchronized with the rising edge of the first clock signal CK1 at time t8. Furthermore, the selection circuit 50 acquires the fifth 8-bit data D4 of the captured data CPDT into the data buffer 514, synchronized with the rising edge of the first clock signal CK1 at time t8.

[0076] Next, synchronized with the rising edge of the first clock signal CK1 at time t9, 8-bit data D3 is written to address 0x3 of the memory circuit 60. Also, synchronized with the rising edge of the first clock signal CK1 at time t9, the selection circuit 50 sets the memory address maddr to 0x4 and sets the memory data mdata to 8-bit data D4 held by the data buffer 514. Furthermore, synchronized with the rising edge of the first clock signal CK1 at time t9, the selection circuit 50 acquires the sixth 8-bit data D5 of the captured data CPDT into the data buffer 514.

[0077] Next, synchronized with the rising edge of the first clock signal CK1 at time t10, 8-bit data D4 is written to address 0x4 of the memory circuit 60. Also, synchronized with the rising edge of the first clock signal CK1 at time t10, the selection circuit 50 sets the memory address maddr to 0x5 and sets the memory data mdata to 8-bit data D5 held by the data buffer 514. Furthermore, synchronized with the rising edge of the first clock signal CK1 at time t10, the selection circuit 50 acquires the seventh 8-bit data D6 of the captured data CPDT into the data buffer 514.

[0078] Next, synchronized with the rising edge of the first clock signal CK1 at time t11, the 8-bit data D5 is written to address 0x5 of the memory circuit 60. Also, synchronized with the rising edge of the first clock signal CK1 at time t11, the selection circuit 50 sets the memory address maddr to 0x6 and sets the memory data mdata to the 8-bit data D6 held by the data buffer 514. Furthermore, synchronized with the rising edge of the first clock signal CK1 at time t11, the selection circuit 50 acquires the 8th 8-bit data D7 of the captured data CPDT into the data buffer 514.

[0079] Next, in synchronization with the rising edge of the first clock signal CK1 at time t12, 8-bit data D6 is written to address 0x6 of the memory circuit 60. Also, in synchronization with the rising edge of the first clock signal CK1 at time t12, the selection circuit 50 sets the memory address maddr to 0x7 and sets the memory data mdata to the 8-bit data D7 held by the data buffer 514.

[0080] Next, in synchronization with the rising edge of the first clock signal CK1 at time t13, 8-bit data D7 is written to address 0x7 of the memory circuit 60. Also, the selection circuit 50 sets the write signal wr to a low level in synchronization with the rising edge of the first clock signal CK1 at time t13.

[0081] Subsequently, the time data TM is updated by the change in subsecond data SSB from n+1 to n+2, synchronized with the rising edge of the first clock signal CK1 at time t14. That is, at time t4, the next time update timing arrives.

[0082] Thus, in the example shown in Figure 5, the selection circuit 50 acquires each 8-bit data that makes up the capture data CPDT and writes it to the memory circuit 60 between the time t3 (when the next time update timing arrives) and the time t14 (when the next time update timing arrives), after the event trigger signal TRG is generated at times t1 to t2. Therefore, the selection circuit 50 acquires the target time data included in the capture data CPDT. Since the time update timing does not occur during the period in which the data is being acquired, the selection circuit 50 can store the target event data in the memory circuit 60 in association with the correct target time data. Furthermore, since the target event data is not affected by changes in time, it is permissible for the time update timing to occur during the period in which the selection circuit 50 is acquiring the target event data.

[0083] As described above, in the real-time clock module 1 of the first embodiment, the selection circuit 50 selects at least one of several types of event data as target event data to be stored in response to the occurrence of an event, and also selects data corresponding to at least a portion of the time digits of the time data TM as target time data to be stored, and stores the capture data CPDT, which includes the target time data and target event data, in the memory circuit 60. Specifically, in the selection circuit 50, the processor 51 selects the target time data and target event data based on the instruction set 521 stored in the non-volatile memory 52. ​​Therefore, according to the real-time clock module 1 of the first embodiment, it is possible to prevent unnecessary event data for each application from being stored in the memory circuit 60 in the timestamp. Furthermore, because the real-time clock module 1 writes the capture data CPDT to the memory circuit 60, the sleep period of the host device 6, which consumes more power than the real-time clock module 1, can be extended, thereby reducing the power consumption of the entire system.

[0084] Furthermore, in the real-time clock module 1 of the first embodiment, the selection circuit 50 acquires the target time data after an event occurs and after the next time update timing has arrived, and stores it in the memory circuit 60. Therefore, according to the real-time clock module 1 of the first embodiment, since the time update timing does not arrive during the period in which the selection circuit 50 acquires the target time data in response to an event, the risk of incorrect target time data being stored in the memory circuit 60 is reduced.

[0085] Furthermore, according to the real-time clock module 1 of the first embodiment, the selection circuit 50 can, in response to the occurrence of an event, select a first power supply voltage drop signal VDDLOW, a second power supply voltage drop signal VBATLOW, or a third power supply voltage drop signal VTMPLOW, which are power supply voltage monitoring data, as target event data and store it in the memory circuit 60.

[0086] Furthermore, according to the real-time clock module 1 of the first embodiment, the selection circuit 50 can, in response to the occurrence of an event, select a first event signal EVIN1, a second event signal EVIN2, a third event signal EVIN3, or an event command detection signal WRCom, which are data corresponding to the external input signal that generates the event, as target event data and store them in the memory circuit 60.

[0087] 2. Second Embodiment Regarding the real-time clock module 1 of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and descriptions that overlap with those of the first embodiment are omitted or simplified. The main focus of this explanation will be on the differences from the first embodiment.

[0088] Figure 6 shows an example of the system configuration including the real-time clock module 1 of the second embodiment.

[0089] As shown in Figure 6, the real-time clock module 1 of the second embodiment is connected to a main power supply 4, a backup power supply 5, a host device 6, and M sensor devices 7-1 to 7-M, where M is an integer greater than or equal to 1.

[0090] Similar to the first embodiment, the real-time clock module 1 is supplied with a power supply voltage VDD from the main power supply 4 and a power supply voltage VBAT from the backup power supply 5. The real-time clock module 1 operates with the power supply voltage VDD when it is supplied from the main power supply 4, and operates with the power supply voltage VBAT when the supply of power supply voltage VDD from the main power supply 4 is cut off. Therefore, the real-time clock module 1 can continue its timing operation even when the supply of power supply voltage VDD from the main power supply 4 is cut off.

[0091] Similar to the first embodiment, the host device 6 operates with the power supply voltage VDD supplied from the main power supply 4, and the host device 6 and the real-time clock module 1 are configured with the host device 6 as the master and the real-time clock module 1 as the slave.2 Communication is conducted via the C bus.

[0092] Sensor devices 7-1 to 7-M are, for example, temperature sensors, position sensors, inertial sensors, etc. Real-time clock module 1 and sensor devices 7-1 to 7-M are configured with real-time clock module 1 as the master and sensor devices 7-1 to 7-M as slaves. 2 Communication is conducted via the C bus.

[0093] Figure 7 is a functional block diagram of the real-time clock module 1 of the second embodiment. As shown in Figure 7, the real-time clock module 1 of the second embodiment differs from the real-time clock module 1 of the first embodiment in that sensor devices 7-1 to 7-M are connected and the real-time clock circuit 3 includes a sensor interface circuit 150.

[0094] The sensor interface circuit 150 is supplied with a power supply voltage VLOGIC. The sensor interface circuit 150 is a communication interface circuit between the real-time clock module 1 and M sensor devices 7-1 to 7-M located outside the real-time clock module 1. M is an integer greater than or equal to 1. In communication via the sensor interface circuit 150, the real-time clock module 1 is the master, specifically the processor 51 is the master, and the sensor devices 7-1 to 7-M are slaves. That is, the sensor interface circuit 150 functions as a master interface for the sensor devices 7-1 to 7-M. In this embodiment, the sensor interface circuit 150 is I 2This is a C-bus compatible interface circuit that communicates with sensor devices 7-1 to 7-M based on the serial clock signal SCL2 output via terminal P11 of the real-time clock circuit 3 and the serial data signal SDA2 input / output via terminal P12 of the real-time clock circuit 3. However, the sensor interface circuit 150 may be another serial bus compatible interface circuit such as SPI, or a parallel bus compatible interface circuit.

[0095] The sensor interface circuit 150 transmits commands to the sensor devices 7-1 to 7-M via terminals P11 and P12 in accordance with the instructions of the processor 51, and the sensor devices 7-1 to 7-M receive the commands and perform various processes in accordance with the commands.

[0096] In particular, in this embodiment, the sensor interface circuit 150 sends a command to the sensor device 7-i requesting it to transmit the detected data, in response to instructions from the processor 51. The sensor device 7-i receives the command and transmits the detected data to the sensor interface circuit 150. The sensor interface circuit 150 receives the data detected by the sensor device 7-i and transmits the received data to the processor 51. i is an integer between 1 and M.

[0097] In the second embodiment, as in the first embodiment, the selection circuit 50 responds to the occurrence of an event. In other words, in response to the event trigger signal TRG, at least one of several types of event data is selected as the target event data to be stored, and data corresponding to at least some of the time digits of the time data TM generated by the timing circuit 30 is selected as the target time data to be stored.

[0098] Similar to the first embodiment, the multiple types of event data may include a first power supply voltage drop signal VDDLOW, a second power supply voltage drop signal VBATLOW, a third power supply voltage drop signal VTMPLOW, an oscillation stop signal FST, a first event signal EVIN1, a second event signal EVIN2, a third event signal EVIN3, and an event command detection signal WRCom.

[0099] Furthermore, in the second embodiment, the multiple types of event data further include sensor data based on data detected by sensor devices 7-1 to 7-M. For example, any of sensor devices 7-1 to 7-M may be a temperature sensor, and the sensor data may include temperature data. In this case, the temperature compensation circuit included in the oscillation circuit 10 may use data detected by a temperature sensor, which is any of sensor devices 7-1 to 7-M, instead of the temperature signal VTMP output from the temperature sensor 90. Also, for example, any of sensor devices 7-1 to 7-M may be a position information sensor, and the sensor data may include position data. The position information sensor may be, for example, a GPS sensor. GPS stands for Global Positioning System or Global Positioning Satellite. Also, for example, any of sensor devices 7-1 to 7-M may be an inertial sensor, and the sensor data may include inertial data. For example, the inertial sensor may be an acceleration sensor, and the inertial data may be acceleration data. Also, for example, the inertial sensor may be an angular velocity sensor, and the inertial data may be angular velocity data. Furthermore, for example, the inertial sensor may be an IMU, and the inertial data may include acceleration data and angular velocity data. IMU stands for Inertial Measurement Unit.

[0100] The selection circuit 50 then causes the memory circuit 60 to store the captured data CPDT, which includes the target time data and the target event data. In other words, the selection circuit 50 performs a timestamp process in response to the event trigger signal TRG, associating the target time data with the target event data and storing it in the memory circuit 60.

[0101] Figure 8 shows an example of capture data CPDT stored in the memory circuit 60 in the second embodiment. In the example in Figure 8, the capture data CPDT is 64 bits of data and is stored, for example, at addresses 0x0 to 0x07 of the memory circuit 60.

[0102] Specifically, at address 0x0 of the memory circuit 60, bit 7 is stored as 0, and bits 6 to 0 store the 7 bits of seconds data included in the time data TM.

[0103] Furthermore, at address 0x1 of the memory circuit 60, bit 7 is stored as 0, and bits 6 to 0 store the 7 bits of minute data included in the time data TM.

[0104] Furthermore, at address 0x2 of the memory circuit 60, bits 7 and 6 are stored as 0, and bits 5 to 0 store the 6 bits of time data included in the time data TM.

[0105] Furthermore, at address 0x3 of the memory circuit 60, bits 7 and 6 are stored as 0, and bits 5 to 0 store the 6 bits of day data included in the time data TM.

[0106] Furthermore, at address 0x4 of the memory circuit 60, bit 7 stores data corresponding to the logic level of the third event signal EVIN3, bit 6 stores data corresponding to the logic level of the second event signal EVIN2, and bit 5 stores data corresponding to the first event signal EVIN Data corresponding to the logical level of N1 is stored, and bits 4-0 store the 5 bits of month data included in the time data TM.

[0107] Furthermore, at address 0x5 of the memory circuit 60, bits 7 to 3 store the 8-bit year data included in the time data TM.

[0108] Furthermore, at address 0x6 of the memory circuit 60, bits 7 to 0 store the upper 8 bits of the sensor data.

[0109] Furthermore, at address 0x7 of the memory circuit 60, bits 7 to 0 store the lower 8 bits of the sensor data.

[0110] In the example shown in Figure 8, the second data, minute data, hour data, day data, month data, and year data are the target time data, and all other data are the target event data.

[0111] In the example shown in Figure 8, the captured data CPDT, which is the subject of the timestamp, is 64 bits of data. Eight bits of data are assigned to one address in the memory circuit 60, and the selection circuit 50 acquires the eight bits of data and writes it to the memory circuit 60, performing this process eight times. Therefore, if a time update timing occurs during the period when the time data TM is being acquired by the selection circuit 50, the target time data included in the captured data CPDT may consist of some data before the update and some data after the update, potentially resulting in incorrect target time data being stored in the memory circuit 60.

[0112] Therefore, in the second embodiment as in the first embodiment, the selection circuit 50 performs timestamp processing to acquire the target time data and store it in the memory circuit 60 after the event occurs, that is, after the event trigger signal TRG is generated and the next time update timing has arrived. A timing chart showing an example of timestamp processing by the selection circuit 50 may be the same as in Figure 5, so its illustration and explanation are omitted.

[0113] The real-time clock module 1 of the second embodiment described above can achieve the same effects as the real-time clock module 1 of the first embodiment.

[0114] Furthermore, according to the real-time clock module 1 of the second embodiment, the selection circuit 50 can select sensor data such as temperature data, position data, and inertia data as target event data in response to the occurrence of an event, and store them in the memory circuit 60.

[0115] 3. Variant The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0116] For example, in each of the above embodiments, the target time data and target event data selected by the selection circuit 50 were the same regardless of the cause of the event trigger signal TRG, but they may be different for each cause of the event trigger signal TRG.

[0117] Furthermore, for example, in each of the above embodiments, the processor 51 could arbitrarily select target time data and target event data by performing software processing based on the instruction set 521 in the selection circuit 50. However, the selection circuit 50 may be configured as hardware that selects target time data and target event data based on selection data arbitrarily set in a predetermined register included in the non-volatile memory 52 or the register group 70.

[0118] Furthermore, in each of the embodiments described above, the instruction set 521 specifies the target time data and the target event data, but the target event data may be specified without specifying the target time data. That is, the target time data selected by the selection circuit 50 may have a fixed type and cannot be selected by the instruction set 521, while the target event data may be arbitrarily selected by the instruction set 521.

[0119] The embodiments and variations described above are examples only and are not limited thereto. For example, each embodiment and each variation can be combined as appropriate.

[0120] The present invention includes configurations that are substantially identical to those described in the embodiments (for example, configurations with the same function, method, and result, or configurations with the same purpose and effect). Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Furthermore, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0121] The following can be derived from the embodiments and modifications described above.

[0122] One embodiment of a real-time clock module is: A timing circuit that performs timing and generates time data, A selection circuit that, in response to the occurrence of an event, selects at least one of several types of event data as the target event data to be stored, and also selects data corresponding to at least a portion of the time digits of the time data as the target time data to be stored. The system includes a memory circuit for storing the aforementioned target time data and the aforementioned target event data.

[0123] This real-time clock module stores selected event data from multiple types of event data in the memory circuit along with the target time data in response to an event, thus preventing the storage of unnecessary event data for each application in the timestamp.

[0124] In one embodiment of the real-time clock module, The aforementioned selection circuit is A non-volatile memory that stores an instruction set specifying the target event data, The processor may include a processor that selects the target event data based on the instruction set.

[0125] This real-time clock module allows the processor to select target event data based on the instruction set, preventing unnecessary event data from being stored in the memory circuit for each application in the timestamp.

[0126] In one embodiment of the real-time clock module, The selection circuit may acquire the target time data after the event has occurred and the next time update timing has arrived, and store it in the memory circuit.

[0127] With this real-time clock module, the time update timing does not occur during the period when the selection circuit is acquiring target time data in response to an event, thus reducing the risk of incorrect target time data being stored in the memory circuit.

[0128] One embodiment of the real-time clock module is: It includes a power supply voltage monitoring circuit that monitors the power supply voltage and generates power supply voltage monitoring data. The aforementioned multiple types of event data may include the power supply voltage monitoring data.

[0129] This real-time clock module allows you to select power supply voltage monitoring data as the target event data in response to an event and store it in the memory circuit.

[0130] In one embodiment of the real-time clock module, The aforementioned event is generated by an external input signal received from outside the real-time clock module. The aforementioned multiple types of event data may include data corresponding to the external input signals.

[0131] This real-time clock module allows you to select data corresponding to the external input signal that generates an event and store it in the memory circuit as the target event data in response to the occurrence of an event.

[0132] In one embodiment of the real-time clock module, The aforementioned multiple types of event data may include sensor data based on data detected by external sensor devices.

[0133] This real-time clock module allows sensor data to be selected as the target event data and stored in the memory circuit in response to the occurrence of an event.

[0134] In one embodiment of the real-time clock module, The aforementioned sensor device is a temperature sensor, The aforementioned sensor data may include temperature data.

[0135] This real-time clock module allows you to select sensor data, including temperature data, as the target event data in response to an event, and store it in the memory circuit.

[0136] In one embodiment of the real-time clock module, The aforementioned sensor device is a location information sensor, The aforementioned sensor data may include location data.

[0137] This real-time clock module allows you to select sensor data, including location data, as the target event data in response to an event, and store it in the memory circuit.

[0138] In one embodiment of the real-time clock module, The aforementioned sensor device is an inertial sensor, The aforementioned sensor data may include inertial data.

[0139] This real-time clock module allows for the selection of sensor data, including inertial data, as target event data in response to an event, and to store it in the memory circuit.

[0140] One embodiment of the real-time clock module is: The oscillator and, The system comprises an oscillator circuit that generates a clock signal by causing the oscillator to oscillate, The timing circuit may perform the timing based on the clock signal.

[0141] This real-time clock module allows for timekeeping based on a highly accurate clock signal obtained by oscillating an oscillator. [Explanation of Symbols]

[0142] 1…Real-time clock module, 2…Oscillator, 3…Real-time clock circuit, 4…Main power supply, 5…Backup power supply, 6…Host device, 7-1~7-M…Sensor device, 10…Oscillator circuit, 20…Frequency divider circuit, 30…Timer circuit, 40…Event trigger circuit, 50…Selection circuit, 51…Processor, 52…Non-volatile memory, 60…Memory circuit, 70…Register group, 80…Interface circuit, 90…Temperature sensor, 100…Oscillator monitoring circuit, 110…Power supply voltage monitoring circuit, 120…Power supply voltage selection circuit, 130…Power supply circuit, 140…Interrupt generation circuit, 150…Sensor interface circuit, 511…Fetch circuit, 512…Decode circuit, 513…Logic operation circuit, 514…Data buffer, 515…Capture circuit, 521…Instruction set

Claims

1. A timing circuit that performs timing and generates time data, A selection circuit that, in response to the occurrence of an event, selects at least one of several types of event data as the target event data to be stored, and also selects data corresponding to at least a portion of the time digits of the time data as the target time data to be stored. The system includes a memory circuit that stores the target time data and the target event data, The selection circuit is a real-time clock module that, after the event occurs and the next time update timing arrives, acquires the target time data and stores it in the memory circuit.

2. The aforementioned selection circuit is A non-volatile memory that stores an instruction set specifying the target event data, The real-time clock module according to claim 1, comprising a processor that selects the target event data based on the instruction set.

3. It includes a power supply voltage monitoring circuit that monitors the power supply voltage and generates power supply voltage monitoring data. The real-time clock module according to claim 1, wherein the multiple types of event data include the power supply voltage monitoring data.

4. The aforementioned event is generated by an external input signal received from outside the real-time clock module. The real-time clock module according to claim 1, wherein the multiple types of event data include data corresponding to the external input signal.

5. The real-time clock module according to claim 1, wherein the multiple types of event data include sensor data based on data detected by an external sensor device.

6. The aforementioned sensor device is a temperature sensor, The sensor data includes temperature data, as described in claim 5 of the real-time clock model. Jules.

7. The aforementioned sensor device is a location information sensor, The real-time clock module according to claim 5, wherein the sensor data includes position data.

8. The aforementioned sensor device is an inertial sensor, The real-time clock module according to claim 5, wherein the sensor data includes inertial data.

9. The oscillator and, The system comprises an oscillator circuit that generates a clock signal by causing the oscillator to oscillate, The real-time clock module according to any one of claims 1 to 8, wherein the timing circuit performs timing based on the clock signal.

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