Liquid crystal display device

Abstract

To provide a liquid crystal display device capable of accurately measuring the temperature.SOLUTION: A liquid crystal display device 1 includes: an image display portion having a plurality of pixels arranged in a two-dimensional matrix shape; a horizontal shift register that sequentially takes in a plurality of video signals for the number of columns of the plurality of pixels; a latch circuit that outputs, all at once, the plurality of video signals taken in by the horizontal shift register; a signal processing circuit that converts each of the plurality of video signals output from the latch circuit into a plurality of analog signals; a vertical shift register that controls so that the signal processing circuit enables the plurality of analog signals to access the plurality of pixels arranged in a row of any one of the plurality of pixels; and a temperature measuring circuit. The temperature measuring circuit has a temperature sensor and measures the temperature of the liquid crystal display device on the basis of a detection result by the temperature sensor in a period in which power consumption of the liquid crystal display device is a predetermined power level or less.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a liquid crystal display device, and more particularly to a liquid crystal display device suitable for accurately measuring temperature.

Background Art

[0002] In an active matrix liquid crystal display device, when strong light is irradiated and the temperature becomes high, there is a possibility that the semiconductor integrated circuit malfunctions or the liquid crystal deteriorates. Therefore, it is necessary to measure the temperature of the liquid crystal display device using a temperature sensor and adjust the temperature of the liquid crystal display device to an appropriate temperature using a cooling device or the like based on the measurement result.

[0003] Patent Document 1 discloses a liquid crystal display device including a liquid crystal display panel having a structure in which a liquid crystal material is sandwiched between a first substrate and a second substrate, and a second semiconductor element (temperature detection element) for detecting the temperature of the liquid crystal material is formed in the liquid crystal display panel using the manufacturing process of the first semiconductor element for driving the liquid crystal pixels formed on the first substrate. Thereby, this liquid crystal display device can detect the temperature of the liquid crystal material without being affected by the outside air or the like.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, Patent Document 1 does not disclose the relationship between the timing of temperature detection by the temperature detection element and the driving timing of the liquid crystal display device. In other words, in Patent Document 1, since the temperature detection element detects temperature independently of the driving timing of the liquid crystal display device, it is affected by noise caused by power supply fluctuations and signal changes that occur when the liquid crystal display device is driven, and as a result, it is not possible to detect the temperature accurately.

[0006] This disclosure has been made in view of the above points, and aims to provide a liquid crystal display device suitable for measuring temperature with high accuracy. [Means for solving the problem]

[0007] A liquid crystal display device according to one aspect of the present disclosure comprises: an image display unit having a plurality of pixels arranged in a two-dimensional matrix; a horizontal shift register that sequentially captures a plurality of video signals equal to the number of rows of the plurality of pixels; a latch circuit that simultaneously outputs the plurality of video signals captured by the horizontal shift register; a signal processing circuit that converts each of the plurality of video signals output from the latch circuit into a plurality of analog signals; a vertical shift register that controls the signal processing circuit to allow access of the plurality of analog signals to a plurality of pixels arranged in any row of the plurality of pixels; and a temperature measurement circuit, wherein the temperature measurement circuit has a temperature sensor and measures the temperature of the liquid crystal display device based on the detection result by the temperature sensor during a period in which the power consumption of the liquid crystal display device is below a predetermined power. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a liquid crystal display device capable of accurately measuring temperature. [Brief explanation of the drawing]

[0009] [Figure 1] This figure shows an example configuration of a liquid crystal display device according to Embodiment 1. [Figure 2] This figure shows in more detail the horizontal driver and analog switch section provided in the liquid crystal display device shown in Figure 1. [Figure 3] This figure shows a specific example of the pixel configuration provided in the liquid crystal display device shown in Figure 1. [Figure 4] Figure 1 is a timing chart illustrating the pixel driving method of the liquid crystal display device shown. [Figure 5] This diagram illustrates the voltage levels from black to white for both positive and negative polarity video signals written to pixels. [Figure 6] Figure 1 is a timing chart showing the operation of the liquid crystal display device. [Figure 7] Figure 6 is a timing chart showing a magnified portion of the operation of the liquid crystal display device. [Figure 8] This is a block diagram illustrating the method for calculating the power consumption of the liquid crystal display device 1. [Figure 9] This is a timing chart of power consumption estimated by simulation of the operation of the liquid crystal display device 1. [Modes for carrying out the invention]

[0010] <Embodiment 1> Figure 1 shows an example configuration of an active-matrix liquid crystal display device 1 according to Embodiment 1. As shown in Figure 1, the liquid crystal display device 1 includes an image display unit 11, a timing generator 13, a polarity switching control circuit 14, a vertical shift register 15, a horizontal driver 16, an analog switch unit (signal processing circuit) 17, and a temperature measurement circuit 20. The horizontal driver 16, together with the analog switch unit 17, constitutes a data line driving circuit and includes a shift register circuit (horizontal shift register) 161, a 1-line latch circuit 162, a comparator unit 163, and a grayscale counter 164. Figure 1 also shows a lamp signal generator 40 connected to the liquid crystal display device 1 during normal operation.

[0011] Figure 2 is a diagram showing in more detail the horizontal driver 16 and analog switch section 17 provided in the liquid crystal display device 1. The comparator section 163 comprises m comparators 163_1 to 163_m corresponding to m rows of pixels 12 (where m is an integer of 2 or more). The analog switch section 17 comprises m sets of switch elements SW1+, SW1- to SWm+, SWm- corresponding to m rows of pixels 12.

[0012] The pixel arrangement area of ​​the image display unit 11 is wired with row scan lines G1 to Gn, which extend horizontally (X-axis direction) in n rows (n is an integer of 2 or more), and sets of data lines D1+, D1- to Dm+, Dm-, which extend vertically (Y-axis direction). In addition, gate control signal lines S+, S- and gate control signal line B are wired to the pixel arrangement area of ​​the image display unit 11.

[0013] The image display unit 11 has a plurality of pixels 12 arranged in a regular pattern of n rows × m columns. These plurality of pixels 12 are arranged in a two-dimensional matrix at a total of n × m intersections where n rows of row scan lines G1 to Gn extending in the horizontal direction (X-axis direction) intersect with m sets of data lines D1+, D1- to Dm+, Dm- extending in the vertical direction (Y-axis direction).

[0014] A row scan line Gj (where j is any integer from 1 to n), which is any row scan line G1 to Gn of the n rows, is commonly connected to each of the m pixels 12 located in the j-th row. Similarly, data lines Di+, Di- (where i is any integer from 1 to m), which are any pair of data lines D1+, D1- to Dm+, Dm-, are commonly connected to each of the n pixels 12 located in the i-th column. Furthermore, gate control signal lines S+, S-, and gate control signal line B are all commonly connected to all pixels 12. However, gate control signal lines S+, S-, and gate control signal line B may each be provided individually for each row.

[0015] Based on the timing signal generated by the timing generator 13, the polarity switching control circuit 14 outputs a gate control signal for the positive polarity (hereinafter referred to as the gate control signal S+) to the gate control signal line S+, outputs a gate control signal for the negative polarity (hereinafter referred to as the gate control signal S−) to the gate control signal line S−, and further outputs a gate control signal (hereinafter referred to as the gate control signal B) to the gate control signal line B.

[0016] The vertical shift register 15 outputs the scanning pulses of n rows to the row scanning lines G1 to Gn in order one by one from the first row to the nth row at the period of one horizontal scanning period (the pulse period of the horizontal synchronization signal HST; the access period to the m pixels 12 for one row).

[0017] The temperature measurement circuit 20 is a circuit that measures the temperature of the liquid crystal display device 1, and has, for example, a temperature sensor 201 and an arithmetic circuit 202. The temperature sensor 201 is, for example, a PN junction diode through which a constant current flows from the anode to the cathode always during the operation of the liquid crystal display device 1 or only during the period in which the temperature is measured. Note that the temperature sensor 201 is not limited to one PN junction diode, and may be constituted by a plurality of PN junction diodes scattered in the liquid crystal display device 1.

[0018] (Specific configuration example of pixel 12) FIG. 3 is a diagram showing a specific configuration example of the pixel 12. Hereinafter, a specific configuration example of the pixel 12 provided in the j-th row and the i-th column among the n×m pixels 12 will be described as a representative.

[0019] As shown in FIG. 3, the pixel 12 has N-channel MOS transistors (hereinafter simply referred to as transistors) Tr1, Tr2, Tr5, Tr6 and P-channel MOS transistors (hereinafter simply referred to as transistors) Tr3, Tr4, Tr7, Tr8.

[0020] The transistor Tr1 and the holding capacitor Cs1 constitute a sample-and-hold circuit that samples and holds the positive polarity video signal supplied via the data line Di+. Specifically, the source of transistor Tr1 is connected to one of the data line pairs, data line Di+, the drain is connected to the gate of transistor Tr3, and the gate is connected to the row scan line Gj. The holding capacitor Cs1 is located between the gate of transistor Tr3 and the ground voltage terminal Vss.

[0021] Transistor Tr2 and holding capacitor Cs2 constitute a sample-and-hold circuit that samples and holds the negative polarity video signal supplied via the data line Di-. Specifically, the source of transistor Tr2 is connected to the other data line Di- of the data line pair, the drain is connected to the gate of transistor Tr4, and the gate is connected to the row scan line Gj. Holding capacitor Cs2 is provided between the gate of transistor Tr3 and the ground voltage terminal Vss. Holding capacitors Cs1 and Cs2 are provided independently of each other and hold the positive and negative polarity video signals in parallel, respectively.

[0022] Transistors Tr3 and Tr7 constitute a source follower buffer (impedance conversion buffer) that outputs the voltage held in the holding capacitance Cs1. Specifically, in the source follower transistor Tr3, the drain is connected to the ground voltage line Vss and the source is connected to node Na. In transistor Tr7, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Na, and the gate is connected to the gate control signal line B.

[0023] Transistors Tr4 and Tr8 constitute a source follower buffer that outputs a voltage held in the holding capacitance Cs2. Specifically, in the source follower transistor Tr4, the drain is connected to the ground voltage line Vss and the source is connected to node Nb. In transistor Tr8, which is used as a bias-controllable constant current load, the source is connected to the power supply voltage line Vdd, the drain is connected to node Nb and the gate is connected to the gate control signal line B.

[0024] Transistors Tr5 and Tr6 constitute a polarity switching switch. Specifically, in transistor Tr5, the source is connected to node Na, the drain is connected to the pixel drive electrode PE, and the gate is connected to one of the gate control signal lines, S+. In transistor Tr6, the source is connected to node Nb, the drain is connected to the pixel drive electrode PE, and the gate is connected to the other gate control signal line, S-.

[0025] The liquid crystal display element (LC) is composed of a pixel driving electrode (reflective electrode) PE having light-reflecting properties, a common electrode CE positioned opposite and spaced apart from the pixel driving electrode PE and having light-transmitting properties, and liquid crystal LCM filling and encapsulating the space between them. A common voltage Vcom is applied to the common electrode CE.

[0026] The data line pairs Di+ and Di- are supplied with video signals of opposite polarity, sampled by the analog switch unit 17. When a scan pulse output from the vertical shift register 15 is supplied to the row scan line Gj, transistors Tr1 and Tr2 turn on simultaneously. As a result, the voltages of the positive and negative video signals are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0027] Furthermore, the input resistances of the positive and negative source follower buffers are virtually infinite. Therefore, the charge accumulated in the holding capacitors Cs1 and Cs2 is retained without leakage until one vertical scan period (the pulse period of the vertical synchronization signal VST; the access period for all pixels 12 from the first to the nth row) has elapsed and a new video signal is written.

[0028] Transistors Tr5 and Tr6, which constitute the polarity switching switch, switch on and off according to the gate control signals S+ and S-, thereby alternately selecting and outputting to the pixel drive electrode PE the output voltage of the positive-side source follower buffer (voltage of the positive polarity video signal) and the output voltage of the negative-side source follower buffer (voltage of the negative polarity video signal). As a result, the pixel drive electrode PE is supplied with a video signal voltage that periodically reverses polarity. In this way, each pixel 12 has a polarity reversal function, so the liquid crystal display device 1 can rapidly switch the polarity of the video signal voltage supplied to the pixel drive electrode PE at each pixel 12, enabling AC driving at high frequencies regardless of the vertical scanning frequency.

[0029] (Explanation of the AC driving method for pixel 12) Figure 4 is a timing chart illustrating the AC driving method of the pixels 12 by the liquid crystal display device 1. Below, as a representative example, the AC driving method for the pixel 12 located in the jth row and ith column of an n-row × m-column pixel 12 will be described.

[0030] In Figure 4, VST represents the vertical synchronization signal which serves as the reference for vertical scanning of the video signal. B represents the gate control signals supplied to the gates of transistors Tr7 and Tr8, which are used as constant current loads for the two types of source follower buffers. S+ represents the gate control signal supplied to the gate of transistor Tr5 on the positive side of the polarity switching switch. S- represents the gate control signal supplied to the gate of transistor Tr6 on the negative side of the polarity switching switch. VPE represents the voltage applied to the pixel drive electrode PE. Vcom represents the voltage applied to the common electrode CE. VLC represents the AC voltage applied to the liquid crystal LCM.

[0031] Figure 5 is a diagram illustrating the voltage levels from black to white for both the positive and negative polarity video signals written to pixel 12. In the example in Figure 5, the positive polarity video signal represents the black level when the voltage level is minimum and the white level when the voltage level is maximum. Conversely, the negative polarity video signal represents the white level when the voltage level is minimum and the black level when the voltage level is maximum. However, the positive polarity video signal may be configured to represent the white level when the voltage level is minimum and the black level when the voltage level is maximum, and the negative polarity video signal may be configured to represent the black level when the voltage level is minimum and the white level when the voltage level is maximum. The dashed lines in the figure indicate the inversion centers of the positive and negative polarity video signals.

[0032] In pixel 12, transistors Tr1 and Tr2 are temporarily turned on when a scan pulse is supplied to the row scan line Gj (not shown in Figure 4). When transistors Tr1 and Tr2 are turned on, the positive and negative polarity video signal voltages are stored and held in the holding capacitors Cs1 and Cs2, respectively.

[0033] As shown in Figure 4, the positive-side transistor Tr5 is turned on during the period when the gate control signal S+ is at the H level. At this time, by setting the gate control signal B to the L level, transistor Tr7 is turned on, and the positive-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the positive-polarity video signal. Also, by setting the gate control signal B to the L level, transistor Tr8 is turned on, and the negative-polarity source follower buffer also becomes active. However, since the negative-polarity transistor Tr6 is off, the pixel drive electrode PE is not charged to the voltage level of the negative-polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S+ is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the positive-polarity drive voltage is maintained in the liquid crystal capacitance.

[0034] On the other hand, during the period when the gate control signal S- is at the H level, the negative-side transistor Tr6 is turned on. At this time, by setting the gate control signal B to the L level, the negative-side transistor Tr8 is turned on, and the negative-side source follower buffer becomes active. As a result, the pixel drive electrode PE is charged to the voltage level of the negative polarity video signal. Furthermore, by setting the gate control signal B to the L level, the transistor Tr7 is turned on, and the positive-side source follower buffer also becomes active. However, since the positive-side transistor Tr5 is off, the pixel drive electrode PE is not charged to the voltage level of the positive polarity video signal. When the pixel drive electrode PE is fully charged, the gate control signal B is switched from the L level to the H level, and the gate control signal S- is switched from the H level to the L level. As a result, the pixel drive electrode PE becomes floating, and the negative polarity drive voltage is maintained in the liquid crystal capacitance.

[0035] By alternately repeating the operations of the positive and negative electrodes described above, a drive voltage VPE, which is converted into AC using the voltages of the positive and negative video signals, is applied to the pixel drive electrode PE.

[0036] Furthermore, since the charge held in the retention capacitors Cs1 and Cs2 is not directly transferred to the pixel drive electrode PE, but rather transferred via a source follower buffer, even when the positive and negative polarity video signal voltages are repeatedly charged and discharged at the pixel drive electrode PE, pixel driving can be achieved without neutralizing the charge and without attenuation of the voltage level.

[0037] Furthermore, as shown in Figure 4, the polarity of the voltage Vcom applied to the common electrode CE is switched to the opposite polarity to the applied voltage VPE in synchronization with the polarity switching of the voltage VPE applied to the pixel drive electrode PE. Note that the voltage Vcom applied to the common electrode CE is set to an inverted reference voltage (dotted-dotted line in Vcom in the figure) that is approximately equal to the inverted reference voltage of the voltage VPE applied to the pixel drive electrode PE (dotted-dotted line in VPE in the figure).

[0038] Here, the effective AC voltage VLC applied to the liquid crystal LCM is the difference voltage between the voltage VPE applied to the pixel drive electrode PE and the voltage Vcom applied to the common electrode CE. Therefore, an AC voltage VLC without a DC component is applied to the liquid crystal LCM. In this way, by switching the voltage Vcom applied to the common electrode CE in opposite phase to the voltage VPE applied to the pixel drive electrode PE, the amplitude of the voltage to be applied to the pixel drive electrode PE can be reduced, thereby reducing the breakdown voltage and power consumption of the transistors constituting the pixel circuit.

[0039] Even if the current flowing steadily through the source follower buffer per pixel is a minute current of 1 μA, the total current flowing steadily through all pixels of the liquid crystal display can become a significant amount. For example, a 2-megapixel full HD liquid crystal display can consume up to 2 A of current. Therefore, in pixel 12, transistors Tr7 and Tr8, which are used as constant current loads, are not kept on all the time, but are only turned on for a limited period of time while the positive and negative transistors Tr5 and Tr6, respectively, are on. This allows the operation of one source follower buffer to be stopped when the other source follower buffer is operating, thereby suppressing the increase in current consumption.

[0040] The AC drive frequency of a liquid crystal display element (LC) can be freely adjusted by adjusting the inversion control period of the pixel itself, regardless of the vertical scanning frequency. For example, suppose the vertical scanning frequency is 60Hz, which is commonly used in television video signals, and the number of vertical periodic scan lines n for full HD is 1125 lines. Also, assume that polarity switching at each pixel is performed at a period of about 15 line periods. In other words, the number of lines r per polarity switching period at each pixel is 30 lines. In this case, the AC drive frequency of the liquid crystal becomes 60Hz × 1125 / (15 × 2) = 2.25Hz. In other words, the liquid crystal display device 1 can dramatically increase the AC drive frequency of the liquid crystal. This makes it possible to significantly improve the reliability, stability, and display quality of the image displayed on the liquid crystal screen, which were problems when the AC drive frequency of the liquid crystal was low.

[0041] (Operation of the liquid crystal display device 1) Next, in addition to Figures 1 and 2, Figures 6 and 7 will be used to explain the operation of the liquid crystal display device 1. Figure 6 is a timing chart showing the operation of the liquid crystal display device 1. Figure 7 is a timing chart showing a magnified portion of the operation of the liquid crystal display device 1 shown in Figure 6.

[0042] As shown in Figures 6 and 7, when a pulse signal of the horizontal synchronization signal HST is supplied, the shift register circuit 161 sequentially captures m columns of s (where s is an integer of 2 or more) bit width video signals in synchronization with the clock signal HCK. The 1-line latch circuit 162 simultaneously outputs the m columns of video signals captured by the shift register circuit 161 at the moment the trigger signal REG_S becomes temporarily active.

[0043] The grayscale counter 164 counts the number of rising edges of the clock signal CNT_CK and outputs a grayscale signal Cout with a grayscale level corresponding to the count value. Here, the grayscale counter 164 outputs the minimum level grayscale signal Cout at the start of one horizontal scanning period (when the horizontal synchronization signal HST is rising), increases the grayscale level of the grayscale signal Cout as the count value increases, and outputs the maximum level grayscale signal Cout at the end of one horizontal scanning period (just before the next rising edge of the horizontal synchronization signal HST). The count value of the grayscale counter 164 is initialized to "0", for example, when the reset signal CNT_R becomes active in response to the rising edge of the horizontal synchronization signal HST.

[0044] The m-column comparators 163_1 to 163_m provided in the comparator unit 163 operate in synchronization with the clock signal CMP_CK. When the gradation signal Cout output from the gradation counter 164 matches each of the m-column video signals (line data) simultaneously output from the 1-line latch circuit 162, the matching signals P1 to Pm are activated (for example, to an L level).

[0045] Of the m sets of switch elements SW1+, SW1-~SWm+, and SWm- provided in the analog switch section 17, the positive polarity switch elements SW1+~SWm+ are provided between the data lines D1+~Dm+ and the common wiring Dcom+, respectively. The negative polarity switch elements SW1-~SWm- are provided between the data lines D1-~Dm- and the common wiring Dcom-, respectively. The m sets of switch elements SW1+, SW1-~SWm+, and SWm- are switched on and off by the matching signals P1~Pm from comparators 163_1~163_m, respectively.

[0046] The common wiring Dcom+ is supplied with the reference lamp voltage Ref_R+, which is a positive-polarity lamp signal output from the lamp signal generator 40 located outside the liquid crystal display device 1. The common wiring Dcom- is supplied with the reference lamp voltage Ref_R-, which is a negative-polarity lamp signal output from the lamp signal generator 40 located outside the liquid crystal display device 1.

[0047] The reference ramp voltage Ref_R+ is a sweep signal in which the image level changes from a black level to a white level from the start to the end of each horizontal scan period. The reference ramp voltage Ref_R- is a sweep signal in which the image level changes from a white level to a black level from the start to the end of each horizontal scan period. Therefore, the reference ramp voltage Ref_R+ with respect to the common voltage Vcom and the reference ramp voltage Ref_R- with respect to the common voltage Vcom are inverse relationships with each other.

[0048] The switch elements SW1+, SW1-~SWm+, and SWm- are all turned on simultaneously at the start of the horizontal scanning period when the start signal SW_Start becomes active (e.g., at a high level). Subsequently, the switch elements SW1+, SW1-~SWm+, and SWm- are switched from on to off when the matching signals P1~Pm output from comparators 163_1~163_m become active (e.g., at a low level). At the end of the horizontal scanning period, the start signal SW_Start becomes inactive (e.g., at a low level).

[0049] In the examples in Figures 6 and 7, the waveform SPk represents the timing of switching the on and off of the switch elements SWq+ and SWq- (where q is an integer from 1 to m), which are provided in correspondence with the pixel sequence on which the video signal of grayscale level k is written. Referring to Figures 6 and 7, the switch elements SWq+ and SWq- are turned on at the rising edge of the start signal SW_Start, and then switched from on to off when the match signal Pq becomes active. Here, the switch elements SWq+ and SWq- sample the reference lamp voltages Ref_R+ and Ref_R- (voltages P and Q in Figures 6 and 7) at the timing of switching from on to off. These sampled voltages P and Q are supplied to the data lines Dq+ and Dq-. In other words, the analog voltages P and Q, which are the DA conversion results of the video signal of grayscale level k, are supplied to the data lines Dq+ and Dq-, respectively.

[0050] At this time, the vertical shift register 15 outputs the scan pulses for n rows to the row scan lines G1 to Gn, one row at a time, from the first row to the nth row. Therefore, for example, the transistors Tr1 and Tr2 provided for each of the m pixels 12 in the j-th row are temporarily turned on when the scan pulse for the j-th row is supplied to the row scan line Gj. As a result, the corresponding positive and negative polarity video signal voltages are stored and held in the retention capacitors Cs1 and Cs2 provided for each of the m pixels 12 in the j-th row, respectively. The AC driving method for each pixel 12 thereafter is as previously described.

[0051] As described above, the switch elements SW1+, SW1-~SWm+, and SWm- are all turned on simultaneously at the start of each horizontal scanning period, but each can be turned off at any time according to the grayscale level of the image to be displayed on the corresponding pixel 12. In other words, the switch elements SW1+, SW1-~SWm+, and SWm- may all be turned off at the same time, or they may be turned off at different times. Furthermore, the order in which they are turned off is not fixed.

[0052] In this way, the liquid crystal display device 1 can improve the linearity of the image by performing a digital-to-analog conversion of the video signal using a lamp signal and then writing it to the pixels 12.

[0053] Here, the temperature measurement circuit 20 acquires the detection result from the temperature sensor 201 at the timing when the operation of the liquid crystal display device 1 per predetermined period becomes smaller than a predetermined operation, and calculates the temperature of the liquid crystal display device 1 using the calculation circuit 202 from the acquired detection result. In other words, the temperature measurement circuit 20 measures the temperature of the liquid crystal display device 1 at the timing when the operation of the liquid crystal display device 1 per predetermined period becomes smaller than a predetermined operation.

[0054] The timing at which the operation of the liquid crystal display device 1 per predetermined period becomes smaller than the predetermined operation is, for example, the timing at which the power consumption of the liquid crystal display device 1 becomes smaller than the predetermined power. The timing at which the power consumption of the liquid crystal display device 1 becomes smaller than the predetermined power is, for example, the period during which access to multiple pixels 12 is temporarily suspended, specifically the vertical blanking period and the horizontal blanking period.

[0055] Referring to Figure 6, the vertical blanking period is the period from when the analog switch unit 17 has finished accessing the pixels 12 for n rows from the 1st row to the nth row, until the analog switch unit 17 starts accessing the pixels 12 for n rows from the 1st row to the nth row again. In other words, the vertical blanking period is the period from when the vertical shift register 15 has finished supplying scan pulses for n rows to the row scan lines G1 to Gn, until the vertical shift register 15 starts supplying scan pulses for n rows to the row scan lines G1 to Gn again. The vertical blanking period is determined, for example, based on the rising edge timing of the vertical synchronization signal VST.

[0056] Referring to Figure 7, the horizontal blanking period is the period from when the analog switch unit 17 has finished accessing m pixels 12 in any j row to when it starts accessing m pixels 12 in the j+1 row, out of the n rows of pixels 12 from row 1 to row n. In other words, the horizontal blanking period is the period from when the supply of scan pulses from the vertical shift register 15 to any row scan line Gj is completed to when the supply of scan pulses from the vertical shift register 15 to row scan line Gj+1 begins. The horizontal blanking period is determined, for example, based on the rising edge timing of the horizontal synchronization signal HST.

[0057] As described above, in the liquid crystal display device 1 according to this embodiment, the temperature measurement circuit 20 measures the temperature of the liquid crystal display device 1 at a time when the power consumption of the liquid crystal display device 1 is low, such as during the vertical blanking period or the horizontal blanking period. As a result, the temperature measurement circuit 20 is less susceptible to noise caused by fluctuations in power supply voltage, such as IR drop, and noise caused by signal changes, and can accurately measure the temperature of the liquid crystal display device 1. Consequently, the liquid crystal display device 1 can adjust its temperature to an appropriate temperature using a cooling device (not shown) or the like, based on the measurement results from the temperature measurement circuit 20, and thus can display high-quality images.

[0058] In this embodiment, the temperature measurement timing by the temperature measurement circuit 20 was described as being at least one of the vertical blanking period and the horizontal blanking period, but it is not limited to this. The temperature measurement timing by the temperature measurement circuit 20 may be any other period during which the power consumption of the liquid crystal display device 1 is less than or equal to a predetermined power.

[0059] Alternatively, the influence of the power consumption of the liquid crystal display device 1 on the temperature sensor 201 may be weighted and calculated using any method, and the measurement timing may be determined based on this. For example, the influence of the power consumption of the liquid crystal display device 1 may be calculated based on the distance between the temperature sensor 201 and each functional block, and the power consumption of each functional block. Below, an example of a method for calculating the influence of the power consumption of the liquid crystal display device 1 will be explained using Figure 8.

[0060] Figure 8 is a block diagram illustrating the method for calculating the impact of power consumption on the liquid crystal display device 1. Figure 8 shows a simplified representation of some of the functional blocks of the liquid crystal display device 1 shown in Figure 1. For the sake of simplicity, the following explanation will use the example of calculating the power consumption of the liquid crystal display device 1 using only the power consumption of each functional block shown in Figure 8.

[0061] As shown in Figure 8, the distances between the temperature sensor 201 and the vertical shift register 15, image display unit 11, analog switch unit 17, 1-line latch circuit 162, and shift register circuit (horizontal shift register) 161 are denoted as L1 to L5. Also, the power consumption of the vertical shift register 15, image display unit 11, analog switch unit 17, 1-line latch circuit 162, and shift register circuit 161 at time t are denoted as W1 to W5. In this case, the influence Wa of the power consumption of the liquid crystal display device 1 at time t can be expressed, for example, as shown in equation (1) below.

[0062] Wa=(W1 / L1)+(W2 / L2)+(W3 / L3)+(W4 / L4)+(W5 / L5) ···(1)

[0063] As shown in equation (1), the influence of power consumption Wa is calculated by weighting the power consumption of each of the multiple functional blocks by the reciprocal of the distance between the temperature sensor 201 and each of the multiple functional blocks, and then summing them up. This is a simplified evaluation based on the fact that the noise of each functional block is proportional to the power of each functional block W1 to W5, and the electromagnetic effect of that noise is proportional to the reciprocal of the distance L1 to L5.

[0064] In the example shown in Figure 8, the case where each distance L1 to L5 is the shortest distance between the temperature sensor 201 and each functional block was explained, but this is not the only case. Each distance L1 to L5 may be the distance between the temperature sensor 201 and the central part of each functional block, or it may be the distance between the temperature sensor 201 and a predetermined area (e.g., a high power consumption area) of each functional block.

[0065] Furthermore, the power consumption impact Wa is not limited to the sum of the power consumption of each of the multiple functional blocks, weighted by the reciprocal of the distance between the temperature sensor 201 and each of the multiple functional blocks. For example, the power consumption impact Wa may be the sum of the power consumption of each of the multiple functional blocks, weighted by the reciprocal of the square of the distance between the temperature sensor 201 and each of the multiple functional blocks.

[0066] The temperature measurement circuit 20 may measure the temperature during any period in which the influence of power consumption Wa is below a predetermined value. Alternatively, the temperature measurement circuit 20 may measure the temperature during a period in which the influence of power consumption Wa is below a predetermined value, as estimated from the simulation results of the operation of the liquid crystal display device 1, more preferably during the period in which the influence of power consumption Wa is lowest (see Figure 9).

[0067] This disclosure is not limited to the embodiments described above, and may be modified as appropriate without departing from its spirit.

[0068] Furthermore, this disclosure can be realized by having a CPU (Central Processing Unit) execute a computer program to perform some or all of the control processing in the liquid crystal display device 1.

[0069] The program described above includes, when loaded into a computer, a set of instructions (or software code) for causing the computer to perform one or more of the functions described in the embodiments. The program may be stored in a non-temporary computer-readable medium or a physical storage medium. Examples, but not limited to, include RAM (Random-Access Memory), ROM (Read-Only Memory), flash memory, SSD (Solid-State Drive), or other memory technologies, CD-ROM, DVD (Digital Versatile Disc), Blu-ray® disc, or other optical disc storage, magnetic cassette, magnetic tape, magnetic disk storage, or other magnetic storage devices. The program may be transmitted over a temporary computer-readable medium or a communication medium. Examples, but not limited to, include temporary computer-readable medium or a communication medium that includes electrically, optically, acoustically, or otherwise propagating signals.

[0070] Furthermore, some or all of the above embodiments may also be described as follows, but are not limited to the following.

[0071] (Note 1) An image display unit having multiple pixels arranged in a two-dimensional matrix, A horizontal shift register that sequentially captures multiple video signals corresponding to the number of rows of the aforementioned multiple pixels, A latch circuit that simultaneously outputs the multiple video signals captured by the horizontal shift register, A signal processing circuit that converts each of the multiple video signals output from the latch circuit into multiple analog signals, A vertical shift register that controls the signal processing circuit to enable access to multiple analog signals to multiple pixels located in any row of the multiple pixels, A temperature measuring circuit having a temperature sensor, A method for measuring the temperature of a liquid crystal display device, comprising: Using the temperature measurement circuit, the temperature of the liquid crystal display device is measured based on the detection result by the temperature sensor during a period in which the power consumption of the liquid crystal display device is below a predetermined power. A method for measuring the temperature of a liquid crystal display device.

[0072] (Note 2) An image display unit having multiple pixels arranged in a two-dimensional matrix, A horizontal shift register that sequentially captures multiple video signals corresponding to the number of rows of the aforementioned multiple pixels, A latch circuit that simultaneously outputs the multiple video signals captured by the horizontal shift register, A signal processing circuit that converts each of the multiple video signals output from the latch circuit into multiple analog signals, A vertical shift register that controls the signal processing circuit to enable access to multiple analog signals to multiple pixels located in any row of the multiple pixels, A temperature measurement program for a liquid crystal display device, comprising: A temperature measurement program that causes a computer to perform a process of measuring the temperature of the liquid crystal display device based on the detection results from a temperature sensor during a period in which the power consumption of the liquid crystal display device is below a predetermined power. [Explanation of Symbols]

[0073] 1 LCD display device 11 Image display section 12 pixels 13 Timing Generator 14 Polarity switching control circuit 15 Vertical Shift Register 16 Horizontal Driver 17 Analog switch section 20 Temperature measurement circuit 40 Lamp signal generator 161 Shift Register Circuit 162 1-line latch circuit 163 Comparator section 163_1~163_m Comparator 164-level grayscale counter 201 Temperature Sensor 202 Arithmetic circuit B Gate control signal line CE Common Electrode Cs1,Cs2 retention capacity D1+, D1- ~ Dm+, Dm- data lines Dcom+, Dcom- Common wiring G1~Gn row scanning line LC liquid crystal display element LCM LCD Na,Nb nodes PE pixel driving electrode (reflector electrode) S+, S- gate control signal lines SW1+, SW1- ~ SWm+, SWm- Switch elements Tr1~Tr8 Transistors

Claims

1. An image display unit having multiple pixels arranged in a two-dimensional matrix, A horizontal shift register that sequentially captures multiple video signals corresponding to the number of rows of the aforementioned multiple pixels, A latch circuit that simultaneously outputs the multiple video signals captured by the horizontal shift register, A signal processing circuit that converts each of the multiple video signals output from the latch circuit into multiple analog signals, A vertical shift register that controls the signal processing circuit to enable access to multiple analog signals to multiple pixels located in any row of the multiple pixels, A temperature measuring circuit having a temperature sensor, A liquid crystal display device equipped with, The temperature measurement circuit calculates the influence of the liquid crystal display device's power consumption by weighting the power consumption of each of the multiple functional blocks, including at least the image display unit, the horizontal shift register, the latch circuit, the signal processing circuit, and the vertical shift register, by the reciprocal of the distance between the temperature sensor and each of the multiple functional blocks, and then summing them up. Based on this influence and the detection results by the temperature sensor during the period in which the power consumption of the liquid crystal display device is below a predetermined power, the temperature of the liquid crystal display device is measured. LCD display device.

2. The temperature measurement circuit measures the temperature of the liquid crystal display device based on the detection result by the temperature sensor during a horizontal blanking period, which is the period from when access to a plurality of pixels located in a first row, which is any row of the plurality of pixels, is completed until access to a plurality of pixels located in a second row, which is accessed after the plurality of pixels located in the first row, begins. The liquid crystal display device according to claim 1.

3. The temperature measurement circuit measures the temperature of the liquid crystal display device based on the detection results from the temperature sensor during a vertical blanking period, which is the period from when access to all of the plurality of pixels is completed until access to all of the plurality of pixels is started again. The liquid crystal display device according to claim 1.

4. The temperature measurement circuit measures the temperature of the liquid crystal display based on the detection result from the temperature sensor during the period in which the influence of the liquid crystal display's power consumption is lowest, which is estimated from the simulation results of the operation of the liquid crystal display. A liquid crystal display device according to any one of claims 1 to 3.

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