III-V compound semiconductor single crystal substrate and method for manufacturing the same

Abstract

This group III-V compound semiconductor single crystal substrate has a circular main surface, is an indium phosphide single crystal substrate, and has a ripple pattern visible on the main surface by being subjected to the following process. The ripple pattern is a pattern corresponding to a part of ripples concentrically spread from a wave source, and the wave source is not positioned on the main surface.　Process: The main surface is horizontally disposed at a position 10 mm downward in the depth direction from a liquid level of a 25ºC mixed solution composed of 10 g of chromium(VI) oxide, 10 mL of a hydrofluoric acid solution having a concentration of 50 mass%, and 400 mL of pure water, and light of a reflection-type incandescent bulb of 500 W is radiated toward the main surface for 1-2 hours from a position that is spaced 20 cm upward from the liquid level.

Description

Technical Field

[0001] The present disclosure relates to a group III-V compound semiconductor single crystal substrate and a method for manufacturing the same.

Background Art

[0002] JP-A-2012-236770 (Patent Document 1) and WO 2004 / 106597 (Patent Document 2) disclose group III-V compound semiconductor single crystal substrates such as indium phosphide single crystal substrates. JP-A-2019-043788 (Patent Document 3) discloses a method for growing a compound semiconductor single crystal serving as a raw material for a compound semiconductor single crystal substrate or the like by using a so-called VB method such as a vertical Bridgman method. Generally, the above-mentioned group III-V compound semiconductor single crystal substrates are manufactured by cutting out a group III-V compound semiconductor single crystal such as an indium phosphide single crystal or a gallium arsenide single crystal into a disk shape (hereinafter, the above-mentioned cutting is also referred to as "slicing").

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0004] The group III-V compound semiconductor single crystal substrate according to the present disclosure is a group III-V compound semiconductor single crystal substrate having a circular main surface, the group III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, the indium phosphide single crystal substrate has a wavy pattern visually recognized on the main surface by performing the following treatment, the wavy pattern is a pattern corresponding to a part of waves spreading concentrically from a wave source, and the wave source is not located on the main surface. Treatment: Horizontally place the main surface at a position 10 mm below the liquid surface in the depth direction of a 25°C mixed solution composed of 10 g of chromium(VI) oxide, 10 mL of a hydrofluoric acid solution with a concentration of 50% by mass, and 400 mL of pure water, and irradiate the main surface with light from a 500 W reflective incandescent bulb for 1 hour or more and 2 hours or less from a position 20 cm above the liquid surface.

[0005] The III-V compound semiconductor single crystal substrate according to the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate, the gallium arsenide single crystal substrate has a wavy pattern visually recognizable on the main surface by performing the following treatment, the wavy pattern is a pattern corresponding to a part of the waves spreading concentrically from a wave source, and the wave source is not located on the main surface. Treatment: Horizontally place the main surface at a position 10 mm below the liquid surface in the depth direction of a 25°C mixed solution composed of 10 g of chromium(VI) oxide, 10 mL of a hydrofluoric acid solution with a concentration of 50% by mass, and 400 mL of pure water, and irradiate the main surface with light from a 500 W reflective incandescent bulb for 5 minutes or more and 20 minutes or less from a position 20 cm above the liquid surface.

[0006] The method for manufacturing a III-V compound semiconductor single crystal substrate according to the present disclosure is a method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, including a step of obtaining a III-V compound semiconductor single crystal by bringing a seed crystal into contact with a raw material melt and growing a crystal solid on the raw material melt side of the seed crystal, and a step of obtaining a III-V compound semiconductor single crystal substrate having a circular main surface by cutting out the III-V compound semiconductor single crystal. The crystal growth apparatus includes at least a cylindrical crucible and a heating element for heating the crucible. The crucible houses the seed crystal at its bottom and houses the raw material melt above the seed crystal in the crucible. The interface between the crystal solid and the raw material melt has an intersection angle of less than 90° with respect to the axis of the crucible.

Brief Description of the Drawings

[0007]

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[0008] [Issues this disclosure aims to address] In processes for obtaining compound semiconductor single crystal substrates by slicing, as disclosed in Patent Documents 1 and 2, there were cases where a more stringent yield was required. Specifically, when slicing a compound semiconductor single crystal, so-called cracking defects, such as cracks or chips in the substrate, could occur, and there was a need to reduce the probability of such cracking defects (hereinafter also referred to as the "cracking defect rate"). In such cases, the III-V compound semiconductor single crystal substrates disclosed in Patent Documents 1 and 2 had room for improvement from the standpoint of reducing the cracking defect rate.

[0009] In view of the above circumstances, this disclosure aims to provide a III-V compound semiconductor single crystal substrate with a reduced cracking defect rate, and a method for manufacturing the same.

[0010] [Effects of this disclosure] According to this disclosure, it is possible to provide a III-V compound semiconductor single crystal substrate with a reduced cracking defect rate, and a method for manufacturing the same.

[0011] [Summary of the Embodiment] First, an overview of the embodiments of this disclosure will be described. The inventors have diligently studied and completed this disclosure in order to solve the above problems. Specifically, using a so-called VB method such as the vertical boat method, the inventors adopted the following method for growing a III-V compound semiconductor single crystal, which will be the raw material for a III-V compound semiconductor single crystal substrate, in a crucible of a crystal growth apparatus. That is, the interface between the crystal solid to be grown on the raw material molten side of the seed crystal and the raw material molten is not made horizontal as in the conventional method, but is made to have an intersection angle of less than 90° with respect to the axis of the crucible. It was found that when this method is used, the rate of crack defects when obtaining the III-V compound semiconductor single crystal substrate by slicing is reduced. Furthermore, it was found that the wave source of the wave pattern obtained by performing a predetermined etching treatment on the main surface of the III-V compound semiconductor single crystal substrate obtained using the above method is not located on the main surface, unlike in the conventional method, and thus the inventors arrived at this disclosure.

[0012] Next, embodiments of this disclosure will be listed and described. [1] A III-V compound semiconductor single crystal substrate according to one aspect of the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, wherein the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, and the indium phosphide single crystal substrate has a wave-like pattern visible on the main surface by subjecting it to the following treatment, wherein the wave-like pattern corresponds to a part of a wave spreading concentrically from a wave source, and the wave source is not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Light from a 500 W reflective incandescent light bulb is then shone onto the main surface from a position 20 cm above the surface for 1 to 2 hours.

[0013] Indium phosphide single crystal substrates, which are III-V compound semiconductor single crystal substrates possessing these characteristics, can reduce the rate of crack defects during slicing.

[0014] [2] The diameter of the indium phosphide single crystal substrate is preferably 50 mm or more and 155 mm or less. This makes it possible to reduce the rate of crack defects during slicing for indium phosphide single crystal substrates having a diameter of 50 mm or more and 155 mm or less.

[0015] [3] The dislocation density of the main surface is 0 cm -2 More than 2000cm -2 The following is preferable. This makes it possible to provide an indium phosphide single crystal substrate in which the dislocation density is further reduced across the entire main surface.

[0016] [4] The asymmetry of the dislocations present on the main surface is 1.8 or greater, and the asymmetry divides the main surface into a first region and a second region by a virtual first line that intersects perpendicularly with a virtual straight line extending from the wave source toward the center of the main surface and passes through the center of the main surface, and in each of the first region and the second region, there are two or more points at a pitch of 5 mm or more in the direction away from the center of the main surface on the virtual second line that passes through the center of the main surface and intersects perpendicularly with the first line, with a pitch of 5 mm or more. 2 A measurement point is set in a square having an area of ​​1 cm, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated from the measurement result to 1 cm 2 Preferably, the value is converted to a value per unit area, and the absolute value of the number obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the second region from the average value of the converted values ​​obtained from all measurement points in the first region is then calculated by dividing the absolute value of the number obtained by dividing the absolute value by the average value of the converted values ​​obtained from all measurement points in both the first and second regions. This makes it possible to further reduce the rate of crack defects during slicing.

[0017] [5] A III-V compound semiconductor single crystal substrate according to one aspect of the present disclosure is a III-V compound semiconductor single crystal substrate having a circular main surface, wherein the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate, and the gallium arsenide single crystal substrate has a wave-like pattern visible on the main surface by subjecting it to the following treatment, wherein the wave-like pattern corresponds to a part of a wave spreading concentrically from a wave source, and the wave source is not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Light from a 500 W reflective incandescent light bulb is then shone onto the main surface from a position 20 cm above the surface for 5 to 20 minutes.

[0018] Gallium arsenide single crystal substrates, which are III-V compound semiconductor single crystal substrates possessing these characteristics, can reduce the rate of crack defects during slicing.

[0019] [6] The diameter of the gallium arsenide single crystal substrate is preferably 75 mm or more and 205 mm or less. This makes it possible to reduce the rate of crack defects during slicing for gallium arsenide single crystal substrates having a diameter of 75 mm or more and 205 mm or less.

[0020] [7] The dislocation density of the main surface is 0 cm -2 More than 50cm -2 The following is preferable. This makes it possible to provide a gallium arsenide single crystal substrate in which the dislocation density is further reduced across the entire main surface.

[0021] [8] The degree of asymmetry of the dislocations existing on the main surface is 2.0 or more. The degree of asymmetry intersects perpendicularly with a virtual straight line extending from the wave source toward the center of the main surface on the main surface, and is divided into a first region and a second region by a virtual first straight line passing through the center of the main surface. In each of the first region and the second region, on a virtual second straight line passing through the center of the main surface and intersecting perpendicularly with the first straight line, two or more square measurement points having an area of 1 mm with a pitch of 5 mm or more in the direction away from the center of the main surface are set, and the number of dislocations is measured at the measurement points, and the number of dislocations is converted into a converted value per unit area of 1 cm 2 from the measurement results. The absolute value of the numerical value obtained by subtracting the average value of the converted values obtained from all the measurement points in the second region from the average value of the converted values obtained from all the measurement points in the first region is preferably calculated by dividing by the average value of the converted values obtained from all the measurement points in the first region and the second region. Thereby, the crack defect rate during slicing can be further reduced. 2

[0022] [9] The main surface preferably has an off-angle of 0° or more and 15° or less from the {100} plane. Thereby, the main surface can be made a surface excellent in electrical characteristics and optical characteristics. Thus, in a III-V compound semiconductor single crystal substrate having a surface excellent in electrical characteristics and optical characteristics as the main surface, the crack defect rate during slicing can be reduced.

[0023]

[10] The average value of the residual strain, which is the absolute value of the difference between the strain in the direction along the diameter of the main surface and the strain in the direction along the tangent, is preferably 3.5×10 -5 or less. Thereby, the crack defect rate during slicing can be more sufficiently reduced.

[0024]

[11] The residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangent, does not have a distribution that is n times symmetric with respect to the origin in polar coordinates, with the center of the main surface as the origin and a hypothetical line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate, and it is preferable that n is an integer of 2 or more. This makes it possible to more sufficiently reduce the crack defect rate during slicing.

[0025]

[12] The conductivity type of the III-V compound semiconductor single crystal substrate is preferably electron-withdrawing. This makes it possible to reduce the rate of crack defects during slicing in III-V compound semiconductor single crystal substrates whose conductivity type is electron-withdrawing (hereinafter also referred to as "n-type").

[0026]

[13] The III-V compound semiconductor single crystal substrate preferably contains tin or sulfur as an impurity atom when it is an indium phosphide single crystal substrate, and preferably contains silicon as an impurity atom when it is a gallium arsenide single crystal substrate. This makes it possible to reduce the rate of crack defects during slicing in both the indium phosphide single crystal substrate containing tin or sulfur as an impurity atom and the gallium arsenide single crystal substrate containing silicon as an impurity atom.

[0027]

[14] The atomic concentration of the above impurity atoms is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following is preferable. This makes it possible to provide a III-V compound semiconductor single crystal substrate containing impurity atoms that have an n-type conductivity at an appropriate concentration.

[0028]

[15] Preferably, the impurity atoms exhibit a uniform concentration distribution in the III-V compound semiconductor single crystal substrate, moving from the wave source toward the center of the main surface. This makes it possible to further reduce the rate of crack defects during slicing in a III-V compound semiconductor single crystal substrate having an n-type conductivity.

[0029]

[16] A method for manufacturing a III-V compound semiconductor single crystal substrate according to one aspect of the present disclosure is a method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, comprising the steps of: obtaining a III-V compound semiconductor single crystal by bringing a seed crystal into contact with a raw material melt and growing a crystalline solid on the raw material melt side of the seed crystal; and obtaining a III-V compound semiconductor single crystal substrate having a circular main surface by cutting the III-V compound semiconductor single crystal, wherein the crystal growth apparatus comprises at least a cylindrical crucible and a heating element for heating the crucible, the crucible having the seed crystal at its bottom and the raw material melt above the seed crystal in the crucible, and the interface between the crystalline solid and the raw material melt having an intersection angle of less than 90° with respect to the axis of the crucible. A method for manufacturing a III-V compound semiconductor single crystal substrate having these features can be used to obtain a III-V compound semiconductor single crystal substrate with a reduced rate of crack defects during slicing.

[0030] [Details of the embodiment] The following describes in more detail one embodiment of the present disclosure (hereinafter also referred to as "this embodiment"), but the present disclosure is not limited thereto. The following description may involve reference to the drawings, where the same or corresponding elements are denoted by the same reference numerals in this specification and the drawings, and the same description will not be repeated. Furthermore, the scale of the drawings has been adjusted as appropriate to facilitate understanding of each component, and the scale of the components shown in the drawings does not necessarily match the scale of the actual components.

[0031] In this specification, the notation "A~B" means an upper and lower limit of a range (i.e., greater than or equal to A and less than or equal to B). If no unit is specified for A, but a unit is specified only for B, the units of A and B are the same. Furthermore, when compounds are represented by chemical formulas in this specification, unless otherwise specified, all conventionally known atomic ratios are included and should not necessarily be limited to those within the stoichiometric range.

[0032] In this specification, the “main surface” of a III-V compound semiconductor single crystal substrate means both of the two circular surfaces of the substrate. In a III-V compound semiconductor single crystal substrate, if at least one of these two surfaces satisfies the claims of this disclosure, it falls within the scope of the present invention. Furthermore, when the diameter of a III-V compound semiconductor single crystal substrate is stated as “50 mm”, it means that the diameter is approximately 50 mm (about 50 to 50.8 mm) or 2 inches. When the diameter is stated as “75 mm”, it means that the diameter is approximately 75 mm (about 75 to 76.5 mm) or 3 inches. When the diameter is stated as “100 mm”, it means that the diameter is approximately 100 mm (about 95 to 105 mm) or 4 inches. When the diameter is stated as “150 mm”, it means that the diameter is approximately 150 mm (about 145 to 155 mm) or 6 inches. When the diameter is stated as "200mm" above, it means that the diameter is approximately 200mm (about 195-205mm), or it means 8 inches. This diameter can be measured using conventionally known outer diameter measuring instruments such as calipers.

[0033] The above-mentioned III-V compound semiconductor single crystal substrate has a "circular" main surface, as described later. In this specification, the term "circular" used to describe the shape of the main surface includes not only a geometric circle, but also a shape in which the main surface does not form a geometric circle due to the formation of at least one of a notch, orientation flat (hereinafter also referred to as "OF"), or index flat (hereinafter also referred to as "IF"). In other words, "a shape in which the main surface does not form a geometric circle" means a shape in which, among line segments extending from any point on the outer circumference of the main surface to the center of the main surface, the length of the line segment extending from any point on the notch, OF, and IF to the center of the main surface is shorter. In other words, in this specification, the shape of the main surface is considered to be "circular" based on the shape before the formation of the notch, OF, and IF. For this reason, the position and size (length) of the center of the main surface and the diameter of the substrate are determined based on the circular shape before the formation of the notch, OF, and IF, etc. Furthermore, the term "shape in which the main surface does not form a geometric circle" includes shapes in which the lengths of all line segments extending from any point on the outer circumference of the main surface to the center of the main surface are not necessarily the same, due to the shape of the III-V compound semiconductor single crystal before it was cut as a III-V compound semiconductor single crystal substrate. In this case, the center of the main surface refers to the position of the centroid, and the diameter of the substrate refers to the length of the longest line segment extending from any point on the outer circumference of the substrate to the center of the main surface.

[0034] In the crystallographic descriptions herein, individual orientations are indicated by [], collective orientations by <>, individual planes by (), and collective planes by {}. Furthermore, while negative crystallographic exponents are usually indicated by placing a "-" (bar) above the number, in this specification, a negative sign will be placed before the number.

[0035] [III-V compound semiconductor single crystal substrate] <First Embodiment: Indium Phosphate Single Crystal Substrate (InP Substrate)> In this embodiment, for example, the III-V compound semiconductor single crystal substrate according to the first embodiment has a circular main surface. In particular, the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate (hereinafter also referred to as "InP substrate"). The InP substrate has a wave-like pattern visible on the main surface by subjecting it to the following treatment. The wave-like pattern corresponds to a part of a wave that spreads concentrically from a wave source. Furthermore, the wave source is not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Light from a 500 W reflective incandescent light bulb is then shone onto the main surface from a position 20 cm above the surface for 1 to 2 hours.

[0036] InP substrates, which are III-V compound semiconductor single crystal substrates possessing these characteristics, can reduce the rate of crack defects during slicing because the wave source of the aforementioned wave pattern is not located on the main surface.

[0037] The diameter of the InP substrate described above is preferably 50 mm or more and 155 mm or less. This reduces the rate of crack defects during slicing for InP substrates having a diameter of 50 mm or more and 155 mm or less. Specifically, an InP substrate with a diameter of 50 mm or more and 155 mm is preferably an InP substrate with a diameter of 50 mm, 75 mm, 100 mm, or 150 mm, in other words, an InP substrate with a diameter of 2 inches, 3 inches, 4 inches, or 6 inches is preferred. As described above, the diameter of the InP substrate can be measured using a conventionally known outer diameter measuring instrument such as a caliper.

[0038] <Second Embodiment: Gallium Arsenide Single Crystal Substrate (GaAs Substrate)> In this embodiment, for example, the III-V compound semiconductor single crystal substrate according to the second embodiment has a circular main surface. In particular, the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate (hereinafter also referred to as "GaAs substrate"). The GaAs substrate has a wave-like pattern visible on the main surface by subjecting it to the following treatment. The wave-like pattern corresponds to a part of a wave that spreads concentrically from a wave source. Furthermore, the wave source is not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Light from a 500 W reflective incandescent light bulb is then shone onto the main surface from a position 20 cm above the surface for 5 to 20 minutes.

[0039] GaAs substrates, which are III-V compound semiconductor single crystal substrates possessing these characteristics, can reduce the rate of crack defects during slicing because the wave source of the aforementioned wave pattern is not located on the main surface.

[0040] The diameter of the GaAs substrate is preferably 75 mm or more and 205 mm or less. This reduces the rate of crack defects during slicing for GaAs substrates with a diameter of 75 mm or more and 205 mm or less. Specifically, a GaAs substrate with a diameter of 75 mm or more and 205 mm or less preferably refers to a GaAs substrate with a diameter of 75 mm, 100 mm, 150 mm, or 200 mm, or in other words, a GaAs substrate with a diameter of 3 inches, 4 inches, 6 inches, or 8 inches. As mentioned above, the diameter of the GaAs substrate can be measured using a conventionally known outer diameter measuring instrument such as a caliper.

[0041] <Main surface> The III-V compound semiconductor single crystal substrate according to this embodiment has a circular main surface as described above. Furthermore, the III-V compound semiconductor single crystal substrate (InP substrate and GaAs substrate) has a wave-like pattern visible on the main surface by subjecting it to the following treatment. Specifically, the wave-like pattern is created by placing the main surface horizontally at a position 10 mm below the liquid surface in the depth direction of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water, and shining light from a 500 W reflective incandescent light bulb from a position 20 cm above the liquid surface toward the main surface, for 1 to 2 hours if the III-V compound semiconductor single crystal substrate is the indium phosphide single crystal substrate, and for gallium arsenide single crystal substrate. more than 5 minutes The ripple pattern is visible on the main surface after irradiation for 20 minutes or less (hereinafter also referred to as "light etching"). In other words, the ripple pattern is a pattern that appears on the main surface only after performing light etching on the main surface.

[0042] (Wave pattern and wave source position of said wave pattern) The III-V compound semiconductor single crystal substrate described above has a wave-like pattern as described above. The wave-like pattern is made visible on the main surface by performing an etching process using light on the main surface as described above. Figure 1 is an explanatory diagram illustrating the wave-like pattern visible on the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment, and the position of the wave source of the wave-like pattern, after performing an etching process using light on the main surface. In this specification, "wave-like pattern" refers to a pattern that can be likened to the wave pattern (so-called ripples) that appears when an object falls onto the surface of water and spreads out in a concentric circle. Furthermore, the "wave source" of the wave-like pattern refers to the starting point or source from which the waves of the wave-like pattern are generated. As shown in Figure 1, the wave-like pattern P that appears on the main surface S of the III-V compound semiconductor single crystal substrate 100 according to this embodiment is a pattern that corresponds to a part of the ripples that spread concentrically from the wave source O, that is, a pattern in which multiple arcs curving in the same direction are connected. Furthermore, as shown in Figure 1, the wave source O of the above wave pattern P is not located on the main surface S.

[0043] The reason why the rate of crack defects during slicing is reduced in the III-V compound semiconductor single crystal substrate 100 having such a wave-like pattern P is presumed to be based on the following factors, although the details are unknown. First, the wave-like pattern P visible on the main surface by the light etching process described above is thought to be a pattern corresponding to the amount of impurity atoms added to the III-V compound semiconductor single crystal substrate 100 as dopants, etc. In other words, the wave-like pattern P can be considered to be a visualized image of the impurity atoms contained in the III-V compound semiconductor single crystal substrate 100.

[0044] Figure 2 is an explanatory diagram illustrating the wave pattern visible on the main surface of a conventional III-V compound semiconductor single crystal substrate after light etching, and the location of the wave source of the wave pattern. As shown in Figure 2, in a conventional III-V compound semiconductor single crystal substrate 101, the wave pattern P visible on the main surface S after light etching is usually a pattern in which the wave source O is located at or near the center of the main surface S, and the wave spreads concentrically from the wave source O. Such a III-V compound semiconductor single crystal substrate 101 is achieved by making the interface between the crystalline solid to be grown on the raw material molten side of the seed crystal and the raw material molten liquid horizontal (or nearly horizontal) during the process of growing the III-V compound semiconductor single crystal, which is the raw material, in a crucible provided in a crystal growth apparatus. In this case, the impurity atoms contained in the III-V compound semiconductor single crystal substrate 101 correspond to the wave pattern P described above, and show a distribution that spreads concentrically from or near the center of the main surface S. At this time, the strain generated in the III-V compound semiconductor single crystal substrate 101 based on the above-mentioned impurity atoms (hereinafter also referred to as "residual strain") exhibits a distribution that is point-symmetric (specifically, four-fold symmetry) around the wave source O when expressed in polar coordinates with the wave source O as the origin (see Figure 4). As a result, it is understood that in conventional III-V compound semiconductor single crystal substrates 101, the stress of the above-mentioned residual strain is difficult to release on the substrate. Therefore, the stress of the above-mentioned residual strain is easily released during slicing processes to obtain the III-V compound semiconductor single crystal substrate 101 from the III-V compound semiconductor single crystal, and it is thought that cracks occur in the substrate at a certain rate.

[0045] On the other hand, as shown in Figure 1, in the III-V compound semiconductor single crystal substrate 100 according to this embodiment, the wave pattern P has a wave source O outside the main surface S. In other words, the wave source O is not located on the main surface S. Therefore, the wave pattern P of the III-V compound semiconductor single crystal substrate according to this embodiment is a pattern corresponding to a part of the waves spreading concentrically from the wave source O, that is, a pattern in which multiple arcs curving in the same direction are connected. Such a III-V compound semiconductor single crystal substrate 100 is achieved in the process of growing the III-V compound semiconductor single crystal that serves as its raw material in a crucible provided in a crystal growth apparatus, for example, as exemplified in the section [Method for manufacturing a III-V compound semiconductor single crystal substrate] described later, by having the interface between the crystal solid to be grown on the raw material molten side of the seed crystal and the raw material molten, not horizontal, but having an intersection angle of less than 90° with respect to the axis of the crucible. In this case, the impurity atoms contained in the III-V compound semiconductor single crystal substrate 100 exhibit a distribution such that multiple arcs curving in the same direction are connected on the main surface S, corresponding to the wave-like pattern P described above. At this time, the residual strain generated in the III-V compound semiconductor single crystal substrate 100 based on the impurity atoms, when expressed in polar coordinates with the center of the main surface S as the origin, does not exhibit a distribution that is n times symmetric (where n is an integer of 2 or more) with respect to the origin, but rather exhibits a distribution that is simply one time symmetric, in particular a distribution that is almost mirror-symmetric (see Figure 3). Thus, it is understood that in the III-V compound semiconductor single crystal substrate 100 according to this embodiment, the stress of the residual strain is easily released on the substrate (for example, the stress is easily released at the intersection of the outer circumference of the main surface and the left and right ends of the arcs). Therefore, the stress of the residual strain does not need to be released during slicing to obtain the III-V compound semiconductor single crystal substrate 100 from the III-V compound semiconductor single crystal, and it is thought that the crack defect rate of the substrate is reduced.

[0046] The details of the etching process using light described above will now be explained. First, a III-V compound semiconductor single crystal substrate is prepared by polishing at least one of its two main surfaces to an arithmetic mean roughness Ra of 0.1 nm to 0.5 nm. Furthermore, with the polished surface facing upwards, the substrate is placed horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium(VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. Next, if the substrate is, for example, an indium phosphide single crystal substrate, the polished surface is etched by irradiating it with light from a 500 W reflective incandescent light bulb (for example, product name: "iLamp (registered trademark)", Iwasaki Electric Co., Ltd.) from a position 20 cm above the liquid surface for 1 to 2 hours. This allows a pattern to be formed on the polished surface. On the other hand, if the substrate is, for example, a gallium arsenide single crystal substrate, the polished surface is etched by irradiating it with light for 5 to 20 minutes from a position 20 cm above the liquid surface. This allows a pattern to be formed on the polished surface. Finally, by visually inspecting the pattern formed on the polished surface, it is possible to identify whether the pattern is a wave pattern, and if so, whether the wave source is located on the main surface.

[0047] The reason why the time for irradiating the main surface with light from a reflective incandescent bulb (hereinafter also referred to as "etching time") differs depending on whether the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate or a gallium arsenide single crystal substrate, and why there is a range for the etching time, is to make the pattern (ripple pattern) formed on the polished surface clearer. Therefore, in this disclosure, regardless of whether the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate or a gallium arsenide single crystal substrate, the etching time can be extended or shortened within the range described above for the purpose of making the pattern formed on the polished surface clearer. Furthermore, fine adjustments such as increasing or decreasing the intensity of the light can also be made. The temperature of the mixed solution (25°C) refers to the temperature at the start of the etching process using light. Therefore, the temperature of the mixed solution may fluctuate during the etching process due to the thermal energy of the light from the reflective incandescent bulb, etc. In addition, in the etching process, it is preferable to agitate the substrate in the mixed solution at predetermined intervals (for example, every minute) in order to make the pattern formed on the polished surface clearer.

[0048] (Residual strain) In the III-V compound semiconductor single crystal substrate according to this embodiment, the average value of residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangential, is 3.5 × 10 -5 The following is preferable: The average value of the above residual strain is 3.5 × 10⁻⁶. -5 As a result, the stress does not need to be released during slicing to obtain the III-V compound semiconductor single crystal substrate, thus reducing the crack defect rate of the substrate. While there is no particular limit to the average value of the residual strain, it is typically 1.0 × 10⁻⁶. -6 The above is the most realistic outcome. In this specification, the stretching strain in the direction along the diameter of the main surface may be represented by "Sr", and the stretching strain in the direction along the tangential of the main surface may be represented by "St".

[0049] In particular, the average value of the residual strain can have more favorable values ​​depending on whether the III-V compound semiconductor single crystal substrate is an InP substrate or a GaAs substrate, the type of impurity atoms contained in the substrate, the size of the substrate's diameter, etc. For example, in the case of an InP substrate with a diameter of 50 mm containing tin as an impurity atom, the average value of the residual strain is 5.9 × 10⁻⁶. -6 It is more preferable that the following conditions are met: In the case of a 50 mm diameter InP substrate containing sulfur as an impurity atom, the average value of the above residual strain is 5.4 × 10 -6 The following is more preferable:

[0050] In the case of an InP substrate with a diameter of 75 mm containing tin as an impurity atom, the average value of the above residual strain is 1.1 × 10⁻⁶. -5 It is more preferable that the following conditions are met: In the case of an InP substrate with a diameter of 75 mm containing sulfur as an impurity atom, the average value of the residual strain is 9.5 × 10 -6 The following is more preferable: In the case of an InP substrate with a diameter of 100 mm containing tin as an impurity atom, the average value of the above residual strain is 2.2 × 10⁻⁶. -5 It is more preferable that the following conditions are met: In the case of an InP substrate with a diameter of 100 mm containing sulfur as an impurity atom, the average value of the above residual strain is 2.0 × 10⁻⁶. -5 The following is more preferable: In the case of an InP substrate with a diameter of 150 mm containing tin as an impurity atom, the average value of the above residual strain is 3.9 × 10⁻⁶ -5 It is more preferable that the following conditions are met, and in the case of an InP substrate with a diameter of 150 mm containing sulfur as an impurity atom, the average value of the above residual strain is 3.4 × 10 -6 The following is more preferable:

[0051] In the case of a GaAs substrate with a diameter of 75 mm containing silicon as an impurity atom, the average value of the above residual strain is 8.2 × 10⁻⁶. -6 It is more preferable that the following conditions are met: In the case of a GaAs substrate with a diameter of 100 mm containing silicon as an impurity atom, the average value of the above residual strain is 1.0 × 10⁻⁶. -5It is more preferable that the following conditions are met, and in the case of a GaAs substrate with a diameter of 150 mm containing silicon as an impurity atom, the average value of the above residual strain is 2.0 × 10 -5 It is more preferable that the following conditions are met, and in the case of a GaAs substrate with a diameter of 200 mm containing silicon as an impurity atom, the average value of the above residual strain is 3.5 × 10⁻⁶. -5 The following is more preferable:

[0052] Regarding the residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangent, it is convenient to represent the residual strain in polar coordinates, with the center of the main surface as the origin and a hypothetical line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate, in order to identify the amount and distribution of the residual strain contained in the III-V compound semiconductor single crystal substrate. This is because the distribution of the residual strain in the III-V compound semiconductor single crystal substrate can be visually understood using the polar coordinates, and thus the ease with which the residual strain is released during slicing to obtain the substrate, i.e., the likelihood of crack defects occurring (the rate of crack defects), can be easily grasped. In this case, the residual strain in the III-V compound semiconductor single crystal substrate according to this embodiment does not have a distribution that is n times symmetric around the origin in the polar coordinates, and it is preferable that n is an integer of 2 or more. Specifically, it is preferable that the residual strain exhibits a distribution that is symmetrical once around the origin in the polar coordinate system. Particularly from the viewpoint of further reducing the crack defect rate of the substrate, it is preferable that the residual strain exhibits a distribution that has symmetry close to mirror image symmetry (hereinafter also referred to as "approximately mirror image symmetry") with a virtual straight line extending from the center of the main surface to the wave source as the central axis. In this specification, "n-fold symmetry" around the origin means symmetry characterized as rotational symmetry around the origin, and specifically means symmetry in which it overlaps with itself when rotated (360 / n)° around the origin. The above n is an integer of 2 or more, and for example, "3-fold symmetry" means n=3 and symmetry in which it overlaps with itself when rotated 120°.

[0053] The residual strain (hereinafter also referred to as "|Sr-St|"), which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangential, can be measured based on the photoelastic method described in Appl. Phys. Lett. 47 (1985) pp. 365-367. First, a III-V compound semiconductor single crystal substrate is prepared by polishing at least one of the two main surfaces to an arithmetic mean roughness Ra of 0.1 nm or more and 0.5 nm or less, similar to the procedure for etching using light described above. Next, the residual strain present across the entire polished surface can be measured by applying the photoelastic method described above. In particular, the residual strain in the photoelastic method can be determined as the absolute value |Sr-St|. In the photoelastic method described above, the residual strain (|Sr-St|) is defined as shown in equation (1) below.

[0054]

number

[0055] In equation (1) above, λ represents the wavelength of light used for measurement, d represents the thickness of the III-V compound semiconductor single crystal substrate used for measurement, n0 represents the refractive index, δ represents the phase difference caused by the birefringence of the sample under measurement, φ represents the principal oscillation azimuthal angle, and p 11 , p 12 , p 44 This represents the photoelastic constant.

[0056] According to the above photoelastic method, the residual strain (|Sr-St|) across the entire main surface of the substrate can be determined by measuring only the phase difference δ and the principal vibration azimuthal angle φ caused by the birefringence of the sample under test.

[0057] Furthermore, based on the residual strain (|Sr-St|) across the entire main surface of the substrate, for example, as shown in Figures 3 and 4, the center of the main surface is taken as the origin, and the wave is directed from the center of the main surface towards the wave source. directionAccordingly, it can be expressed in polar coordinates with a hypothetical line segment as the starting line, which extends to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate.

[0058] Figure 3 is an explanatory diagram showing the residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangent, in a polar coordinate system with the center of the main surface as the origin and a hypothetical line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate. Figure 4 is an explanatory diagram showing the residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangent, in a polar coordinate system with the center of the main surface as the origin and a hypothetical line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate.

[0059] As can be seen from a comparison of Figures 3 and 4, the residual strain on the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment does not have a distribution that is n times symmetric (where n is an integer of 2 or more) in polar coordinates, but rather exhibits a distribution that is one time symmetric around the origin. In particular, according to Figure 3, it can be seen that the residual strain of the III-V compound semiconductor single crystal substrate according to this embodiment exhibits a distribution that is approximately mirror-symmetric with respect to a hypothetical straight line extending from the center of the main surface to the wave source as the central axis. By exhibiting such a distribution that is one time symmetric, particularly approximately mirror-symmetric, around the origin in polar coordinates, it can be seen that the III-V compound semiconductor single crystal substrate according to this embodiment has areas on the substrate where the residual strain stress is easily released. On the other hand, conventional III-V compound semiconductor single crystal substrates exhibit a distribution that is four times symmetric with respect to the origin in polar coordinates, and therefore it can be seen that there are no areas on the substrate where the residual strain stress is easily released.

[0060] In the III-V compound semiconductor single crystal substrate according to this embodiment, when measuring the residual strain, this may be done before determining the dislocation density of the main surface, as described later, or after determining the dislocation density of the main surface. When measuring the residual strain after determining the dislocation density of the main surface, corrosion holes corresponding to dislocations (etch pits) are formed on the main surface. Therefore, both sides of the main surface can be polished for the purpose of removing these corrosion holes and for the purpose of making the main surface a polished surface as described above.

[0061] (Off-angle) The main surface is preferably a surface having an off-angle of 0° to 15° from the {100} plane. When the main surface has an off-angle of 0° to 15° from the {100} plane, the main surface of the III-V compound semiconductor single crystal substrate is a surface having an orientation that is excellent in electrical properties and optical properties. As a result, this embodiment makes it possible to reduce the crack defect rate in a III-V compound semiconductor single crystal substrate having a surface with excellent electrical properties and optical properties as its main surface.

[0062] Such a III-V compound semiconductor single crystal substrate can be obtained by slicing a III-V compound semiconductor single crystal, which is the raw material for the III-V compound semiconductor single crystal substrate, with the {100} plane (just plane) without an off-angle as the main surface. Alternatively, it can be obtained by performing a conventionally known slicing method on the above-mentioned III-V compound semiconductor single crystal so that the main surface is a plane having an off-angle greater than 0° and 15° or less from the {100} plane. When obtaining such a raw material (III-V compound semiconductor single crystal), the growth direction of the III-V compound semiconductor single crystal is <100> It is preferable that the direction is directional. Hereinafter, the "off-angle" has an accuracy error of ±0.5°. For example, if the main surface is a {100}just surface, the main surface may have an off-angle of -0.5 to 0.5° from the {100} surface. Also, for example, if the main surface is a surface with an off-angle of 15° from the {100} surface, the main surface may have an off-angle of 14.5 to 15.5° from the {100} surface.

[0063] The off-angle from the {100} plane on the main surface of a III-V compound semiconductor single crystal can be measured using a conventionally known crystal orientation measuring device (for example, product name (part number): "2991G2", manufactured by Rigaku Corporation).

[0064] (Dislocation density) When the above-mentioned III-V compound semiconductor single crystal substrate is an InP substrate, the dislocation density of the main surface is 0 cm². -2 More than 2000cm -2 Preferably, the following: The dislocation density of the main surface is 0 cm -2 More than 1500cm -2 The following is more preferable. On the other hand, if the III-V compound semiconductor single crystal substrate is a GaAs substrate, the dislocation density of the main surface is 0 cm -2 More than 50cm -2 Preferably, the following: The dislocation density of the main surface is 0 cm -2 More than 30cm -2 The following is more preferable. This makes it possible to provide a III-V compound semiconductor single crystal substrate (InP substrate and GaAs substrate) in which the dislocation density is further reduced across the entire main surface. Thus, this embodiment can reduce the cracking defect rate for a III-V compound semiconductor single crystal substrate in which the dislocation density is reduced across the entire main surface.

[0065] In particular, the dislocation density of the main surface can have more favorable values ​​depending on whether the III-V compound semiconductor single crystal substrate is an InP substrate or a GaAs substrate, the type of impurity atoms contained in the substrate, the size of the substrate's diameter, etc. For example, in the case of an InP substrate with a diameter of 50 mm containing tin as an impurity atom, the dislocation density of the main surface is 1000 cm². -2 The following is more preferable, and in the case of an InP substrate with a diameter of 50 mm containing sulfur as an impurity atom, 200 cm -2 below It is preferable that it be so.

[0066] In the case of an InP substrate with a diameter of 75 mm containing tin as an impurity atom, the dislocation density on the main surface is 2000 cm². -2 It is more preferable that the following conditions are met: if the InP substrate has a diameter of 75 mm and contains sulfur as an impurity atom, the dislocation density of the main surface is 350 cm². -2 The following is more preferable: If the InP substrate has a diameter of 100 mm and contains tin as an impurity atom, the dislocation density of the main surface is 2000 cm². -2 It is more preferable that the following conditions are met: In the case of an InP substrate with a diameter of 100 mm containing sulfur as an impurity atom, the dislocation density of the main surface is 600 cm². -2 The following is more preferable: If the InP substrate has a diameter of 150 mm and contains tin as an impurity atom, the dislocation density of the main surface is 2000 cm². -2 It is more preferable that the following conditions are met: In the case of an InP substrate with a diameter of 150 mm containing sulfur as an impurity atom, the dislocation density of the main surface is 700 cm². -2 The following is more preferable:

[0067] In the case of a GaAs substrate with a diameter of 75 mm containing silicon as an impurity atom, the dislocation density on the main surface is 25 cm². -2 It is more preferable that the following conditions are met: In the case of a GaAs substrate with a diameter of 100 mm containing silicon as an impurity atom, the dislocation density of the main surface is 35 cm². -2 It is more preferable that the following conditions are met: In the case of a GaAs substrate with a diameter of 150 mm containing silicon as an impurity atom, the dislocation density of the main surface is 35 cm². -2 It is more preferable that the following conditions are met: In the case of a GaAs substrate with a diameter of 200 mm containing silicon as an impurity atom, the dislocation density of the main surface is 90 cm². -2 The following is more preferable:

[0068] In this specification, "dislocations" and "dislocation density" on the main surface refer to "etch pits" and "etch pit density (hereinafter also referred to as "EPD")," respectively. "Etch pits" refer to corrosion holes formed on the surface of a III-V compound semiconductor single crystal substrate by treating the surface with chemicals. Specifically, "etch pits" refer to corrosion holes formed on the main surface when the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate and is immersed for 1 to 5 minutes in a chemical solution consisting of hydrogen bromide and phosphoric acid, with a mass ratio of hydrogen bromide to phosphoric acid of 1:2 at 25°C. Furthermore, "etch pits" refer to corrosion holes formed on the main surface when the III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate and is immersed for 45 minutes in molten potassium hydroxide at 600°C. Furthermore, if the main surface of a III-V compound semiconductor single crystal substrate is a polished surface, pretreatment can be performed before immersing the substrate in a chemical solution. For example, the polished surface of an indium phosphide single crystal substrate can be pretreated with inverse aqua regia, and the polished surface of a gallium arsenide single crystal substrate can be pretreated with sulfuric acid and hydrogen peroxide. This makes it possible to more clearly identify the etch pits on the main surface. These etch pits appear as white spots when the main surface of the III-V compound semiconductor single crystal substrate is observed with an optical microscope or the like. Although etch pits are not academically synonymous with dislocations, they can be considered equivalent to dislocations in this technical field.

[0069] The following describes a method for measuring etch pits formed on the main surface of a III-V compound semiconductor single crystal substrate and a method for calculating EPD, with reference to Figure 5, using the case where the III-V compound semiconductor single crystal substrate is a GaAs substrate with a diameter of 150 mm as an example. Figure 5 is an explanatory diagram illustrating 69 measurement points set on the main surface for the purpose of determining the dislocation density of the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment.

[0070] First, the main surface of the III-V compound semiconductor single crystal substrate (GaAs substrate) 100 is immersed in molten potassium hydroxide at 600°C for 45 minutes. Conventional known methods can be used for the immersion. Next, the III-V compound semiconductor single crystal substrate 100 is removed from the molten potassium hydroxide. Subsequently, as shown in Figure 5, 69 measurement points M (where M is 1 mm) are measured within the main surface S of the III-V compound semiconductor single crystal substrate 100. 2 A square with an area of ​​1mm x 1mm is defined. The number of etch pits at these 69 measurement points M is measured at 100x magnification using a known optical microscope (e.g., product name: "ECLIPSE(registered trademark) LV150N", manufactured by Nikon Corporation). Finally, the number of etch pits measured at the 69 measurement points M is measured in 1cm². 2 Convert to a value per unit area. This will give you 1 cm of etch pit. 2 Since 69 numerical values ​​are obtained per unit area, the average of these 69 values ​​can be calculated as the EPD.

[0071] According to the method described above, it is possible to measure the number of etch pits by assigning one measurement point to one field of view (1 mm × 1 mm in size). Furthermore, if the III-V compound semiconductor single crystal substrate 100 is an InP substrate, the method for measuring the etch pits formed on its main surface S and the method for calculating the EPD can be determined in the same manner as the method for measuring etch pits and calculating the EPD for the GaAs substrate described above, except that the main surface is immersed in the above chemical solution of hydrogen bromide:phosphoric acid in a mass ratio of 1:2 at 25°C for 1 to 5 minutes.

[0072] In the substrate shown in Figure 5, the 69 measurement points M are arranged perpendicular to the orientation flat OF provided at the top, with 5, 7, 9, 9, 9, 9, 9, 7, and 5 points from right to left. These measurement points M are spaced 15 mm apart. That is, if the diameter of the III-V compound semiconductor single crystal substrate is 150 mm, it is possible to set 69 measurement points within the plane of the main surface S by setting the spacing I between one measurement point M and the other measurement point M closest to it to 15 mm.

[0073] When the diameter of the III-V compound semiconductor single crystal substrate is 50 mm, 69 measurement points M can be set within the plane of the main surface S by setting the distance I between one measurement point M and the other measurement point M closest to that measurement point M to 5 mm. Similarly, when the diameter of the III-V compound semiconductor single crystal substrate is 75 mm, 69 measurement points M can be set within the plane of the main surface S by setting the distance I between one measurement point M and the other measurement point M closest to that measurement point M to 7.5 mm. When the diameter of the III-V compound semiconductor single crystal substrate is 100 mm, measurement 69 fixed points M can be set within the plane of the main surface S by setting the distance I between one measurement point M and the other measurement point M closest to that measurement point M to 10 mm. If the diameter of the III-V compound semiconductor single crystal substrate is 200 mm, 69 of the above measurement points M can be set within the plane of the main surface S by setting the distance I between one measurement point M and the other measurement point M closest to that measurement point M to 20 mm.

[0074] (Asymmetry of dislocation) When the III-V compound semiconductor single crystal substrate is an InP substrate, the asymmetry of the dislocations on the main surface is preferably 1.8 or higher, and more preferably 2.0 or higher. Furthermore, when the III-V compound semiconductor single crystal substrate is a GaAs substrate, the asymmetry of the dislocations is preferably 2.0 or higher, and more preferably 2.3 or higher. The asymmetry is determined by dividing the main surface into a first region and a second region by a virtual first line that intersects perpendicularly with a virtual straight line extending from the wave source toward the center of the main surface and passes through the center of the main surface, and in each of the first and second regions, at a pitch of 5 mm or more, there are two or more points of 1 mm in the direction away from the center of the main surface on a virtual second line that passes through the center of the main surface and intersects perpendicularly with the first line. 2 A measurement point is set in a square having an area of ​​1 cm, and the number of dislocations is measured at the measurement point, and the number of dislocations is calculated from the measurement result to 1 cm 2 The value is converted to a value per unit area, and the absolute value of the number obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the second region from the average value of the converted values ​​obtained from all measurement points in the first region is then calculated by dividing the absolute value of the number obtained from all measurement points in both the first and second regions by the average value of the converted values ​​obtained from all measurement points in both regions.

[0075] In this specification, "dislocation asymmetry" refers to an index that indicates how much the number of dislocations present in the first and second regions differs when the main surface is divided into a first region and a second region by a hypothetical first straight line that intersects perpendicularly with a hypothetical straight line extending from the wave source toward the center of the main surface and passes through the center of the main surface. The larger the value of "dislocation asymmetry," the greater the reduction in the rate of crack defects during slicing, although the detailed reasons are unknown. The "dislocation asymmetry" of the III-V compound semiconductor single crystal substrate according to this embodiment can be shown to be a larger value than that of conventional III-V compound semiconductor single crystal substrates for the following reasons.

[0076] As described above, when the main surface of the III-V compound semiconductor single crystal substrate according to this embodiment is etched using light, a wave pattern is observed on the main surface in which the wave source is not located on the main surface. On the other hand, when the main surface of a conventional III-V compound semiconductor single crystal substrate is etched using light, a wave pattern is observed on the main surface in which the wave source is located at or near the center of the main surface. In this case, the wave pattern in the conventional III-V compound semiconductor single crystal substrate corresponds to a wave pattern that spreads concentrically from a wave source located at or near the center of the main surface, as described above. Therefore, the number of dislocations in the first region and the second region are the same or similar, and thus the "asymmetry of dislocations" is considered to be small. On the other hand, the wave pattern in the III-V compound semiconductor single crystal substrate according to this embodiment is a pattern in which multiple arcs curving in the same direction are connected, as described above. Therefore, the number of dislocations in the first region and the second region are different, and thus the "asymmetry of dislocations" is considered to be large. Furthermore, the larger the value of "dislocation asymmetry," the more orientations with lower strain appear in the III-V compound semiconductor single crystal. Therefore, it is believed that the rate of crack defects can be further reduced by slicing the single crystal along these orientations to obtain the substrate.

[0077] In the III-V compound semiconductor single crystal substrate according to this embodiment, the dislocation asymmetry can be 1.8 or higher when it is an InP substrate. In contrast, in conventional InP substrates, the asymmetry is usually less than 1.8. When the III-V compound semiconductor single crystal substrate according to this embodiment is a GaAs substrate, the dislocation asymmetry can be 2.0 or higher. In contrast, in conventional GaAs substrates, the asymmetry is usually less than 2.0.

[0078] The method for calculating the "dislocation asymmetry" present on the main surface described above will be explained in detail below with reference to Figure 6. Figure 6 is an explanatory diagram illustrating a method for determining the dislocation asymmetry present on the main surface of a III-V compound semiconductor single crystal substrate according to this embodiment, by utilizing the wave pattern shown in Figure 1 and the 69 measurement points shown in Figure 5.

[0079] First, a wave pattern P is formed on the main surface S of the III-V compound semiconductor single crystal substrate 100 by performing the aforementioned light-based etching process. After identifying the position of the wave source from the wave pattern P, a virtual straight line is drawn on the main surface S extending from the wave source toward the center of the main surface S. Next, the position of a virtual first straight line L1 on the main surface S, which intersects the virtual straight line perpendicularly and passes through the center of the main surface, is identified. Furthermore, the position of the virtual first straight line L1 is recorded on the main surface S by methods such as damaging the outer periphery of the III-V compound semiconductor single crystal substrate 100 or marking the main surface S. After that, the wave pattern is removed from the main surface S by polishing the main surface S.

[0080] Next, 69 measurement points M are set on the main surface S in the same manner as the dislocation density measurement method described above. Furthermore, the main surface S is divided into a first region R1 and a second region R2 based on a virtual first straight line L1 recorded on the main surface S. Subsequently, a virtual second straight line L2 is created that passes through the center of the main surface S and intersects the first straight line L1 perpendicularly, and measurement points M that coincide with this second straight line L2 are selected in the first region R1 and the second region R2, respectively.

[0081] Next, the number of dislocations (etch pits) is measured at selected measurement points M in both the first region R1 and the second region R2, and the number of dislocations is calculated from the measurement results per 1 cm. 2The value is converted to a value per unit area. Furthermore, the average value of the above converted values ​​obtained from all measurement points M selected in the first region R1 is subtracted from the average value of the above converted values ​​obtained from all measurement points M selected in the second region R2. Finally, the absolute value of the number obtained by the above subtraction is divided by the average value of the above converted values ​​obtained from all measurement points M selected in both the first region R1 and the second region R2. The "asymmetry of dislocation" can be determined by the above method.

[0082] Here, in each of the first region R1 and the second region R2, if the virtual second line L2 and the measurement point M do not overlap at two or more points, it may not be possible to calculate the average value of the conversion for determining the "dislocation asymmetry." In such cases, in each of the first region R1 and the second region R2, the measurement point M nearest to the virtual second line L2, and the next nearest measurement point M, are considered as measurement points M that overlap with the second line L2, and by measuring the number of dislocations at these measurement points M, it becomes possible to calculate the average value of the above conversion. Furthermore, if the diameter of the III-V compound semiconductor single crystal substrate 100 is 50 mm, the distance I between one measurement point M and the other measurement point M closest to that measurement point M is 5 mm. Therefore, for the III-V compound semiconductor single crystal substrate 100 for which the "dislocation asymmetry" is to be determined, if the diameter is 50 mm or more, the distance I (pitch) of measurement points M that overlap with the virtual second line L2 will always be 5 mm or more.

[0083] <Conductive type> The III-V compound semiconductor single crystal substrate according to this embodiment can be given electron-withdrawing (n-type) conductivity by adding impurity atoms to the seed crystal used as its raw material. In other words, it is preferable that the conductivity type of the III-V compound semiconductor single crystal substrate is n-type. In particular, if the III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate, it is preferable that it contains tin or sulfur as an impurity atom, and if it is a gallium arsenide single crystal substrate, it is preferable that it contains silicon. This makes it possible to reduce the rate of crack defects during slicing in a III-V compound semiconductor single crystal substrate with n-type conductivity.

[0084] For example, an InP substrate can contain both or either S (sulfur) atoms and Sn (tin) atoms to impart n-type conductivity. A conductive InP substrate containing both or either S (sulfur) atoms and Sn (tin) atoms can, for example, have a resistivity of 1 Ω·cm or less. A GaAs substrate can contain Si (silicon) atoms to impart n-type conductivity.

[0085] The atomic concentration of the above impurity atoms (S, Sn, or Si) is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 19 cm -3 The following is preferable: The atomic concentration of the above impurity atoms is 1 × 10⁻⁶ 18 cm -3 The above 1 x 10 19 cm -3 The following is more preferable. The atomic concentration of the above impurity atoms can be measured using GDMS (glow discharge mass spectrometry).

[0086] It is preferable that the above-mentioned impurity atoms exhibit a concentration distribution that changes uniformly in the direction from the wave source toward the center of the main surface within the III-V compound semiconductor single crystal substrate. Specifically, in a III-V compound semiconductor single crystal substrate 100 having a wave source O outside the main surface S as shown in Figure 1, and having a pattern (wave pattern P) in which multiple arcs curving in the same direction are connected, the above-mentioned impurity atoms can exhibit a concentration distribution that changes uniformly in the direction from the wave source O toward the center of the main surface S. It is more preferable that the above-mentioned impurity atoms exhibit a concentration distribution that increases uniformly in the direction from the wave source O toward the center of the main surface S within the III-V compound semiconductor single crystal substrate 100. In this case, when the strain (residual strain) caused by the impurity atoms generated in the III-V compound semiconductor single crystal substrate 100 is expressed in polar coordinates with the center of the main surface S as the origin, the residual strain does not show a distribution that is n times symmetric (where n is an integer of 2 or more) around the origin, but simply a distribution that is 1 time symmetric (see Figure 3). As a result, the stress of the residual strain is more easily released on the substrate. Therefore, the stress of the residual strain does not need to be released during slicing or other processes, which can reduce the rate of cracking defects in the substrate.

[0087] The concentration distribution of the above-mentioned impurity atoms can be determined specifically by the following method. First, at each position on the main surface where a hypothetical straight line passing through the center of the main surface and extending in the direction from the wave source to the center of the main surface coincides with the outer circumference on the wave source side of the center of the main surface, the center of the main surface, and the outer circumference on the opposite side of the wave source of the center of the main surface, a III-V compound semiconductor single crystal substrate is determined. split Open the device. Typically, a measurement sample having a square surface with sides of 10 mm and a thickness of 300 to 1000 μm is prepared, and the above-described GDMS is performed using the measurement sample. This makes it possible to clarify the concentration distribution of the impurity atoms in the III-V compound semiconductor single crystal substrate in the direction from the wave source toward the center of the main surface.

[0088] [Method for manufacturing III-V compound semiconductor single crystal substrates] The method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment is preferably the following method. That is, the above manufacturing method is a method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, and includes a step (first step) of obtaining a III-V compound semiconductor single crystal by bringing a seed crystal into contact with a raw material melt and growing a crystalline solid on the raw material melt side of the seed crystal, and a step (second step) of cutting the III-V compound semiconductor single crystal to obtain a III-V compound semiconductor single crystal substrate having a circular main surface. The crystal growth apparatus comprises at least a cylindrical crucible and a heating element for heating the crucible. The crucible contains the seed crystal at its bottom and the raw material melt above the seed crystal in the crucible. The interface between the crystalline solid and the raw material melt has an intersection angle of less than 90° with respect to the axis of the crucible.

[0089] The inventors, when growing a III-V compound semiconductor single crystal, which is the raw material for a III-V compound semiconductor single crystal substrate, in a crucible of a crystal growth apparatus using the VB method, have modified the structure of the heating element, for example as described later, so that the interface between the crystal solid to be grown on the raw material molten side of the seed crystal and the raw material molten is not horizontal as in the conventional method, but has an intersection angle of less than 90° with respect to the axis of the crucible. In this case, the inventors have found that the rate of crack defects when obtaining a III-V compound semiconductor single crystal substrate from the crystal-grown III-V compound semiconductor single crystal by slicing is reduced compared to the conventional method.

[0090] In this specification, "cracking defect rate" refers to the percentage of III-V compound semiconductor single crystal substrates that crack during a series of processes for manufacturing III-V compound semiconductor single crystal substrates. Specifically, it refers to the percentage of cracking defects, including chipping, that occur during a series of processes in which a III-V compound semiconductor single crystal is grown, its outer periphery is ground, an OF or notch is formed, and a III-V compound semiconductor single crystal substrate precursor is obtained by slicing it to a desired thickness, and then the outer periphery of the III-V compound semiconductor single crystal substrate precursor is ground, the back surface is etched and the front surface is polished, and then cleaning and drying are performed to obtain a III-V compound semiconductor single crystal substrate. On the other hand, in this specification, "slicing yield" refers to the percentage of good III-V compound semiconductor single crystal substrates that do not exhibit the above-mentioned cracking defects.

[0091] Hereinafter, with reference to Figure 7, an example of a method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment will be explained, employing the so-called VB method, which uses a crucible such as the vertical Bridgeman method or the vertical temperature gradient solidification method, which are included in the vertical boat method. In the method for manufacturing a III-V compound semiconductor single crystal substrate according to this embodiment, the following steps are performed in this order: seed crystal loading, raw material loading, encapsulant placement, crystal growth as the first step, cutting as the second step, and outer edge grinding. When performing the above manufacturing method, for example, a crystal growth apparatus equipped with a crucible 1 and a heating element 2 as shown in Figure 7 can be used. Figure 7 is a schematic diagram illustrating a crystal growth apparatus for growing a III-V compound semiconductor single crystal, which is the raw material for the III-V compound semiconductor single crystal substrate according to this embodiment.

[0092] In the crystal growth apparatus, the crucible 1 is cylindrical and comprises a seed crystal holding section and a crystal growth section connected to the seed crystal holding section. The crystal growth section further includes a conical section and a straight section. The seed crystal holding section is a cylindrical region having a cylindrical cavity that opens on the side connected to the crystal growth section and has a bottom wall formed on the opposite side. The seed crystal holding section can hold a seed crystal 31 in the cavity. The conical section of the crystal growth section has a conical shape and is connected to the seed crystal holding section on its smaller diameter side. The straight section has a hollow cylindrical shape and is connected to the larger diameter side of the conical section. The crystal growth section of the crucible 1 has the function of holding a solid III-V compound semiconductor raw material inside it. Furthermore, the crystal growth section of the crucible 1 has the function of growing a III-V compound semiconductor single crystal as a crystalline solid 32 by solidifying a raw material melt 33, which is a raw material heated to a molten state. Crucible 1 can be made from various materials capable of withstanding the melting temperature of the III-V compound semiconductor raw material. For example, it is convenient to use pyrolysis boron nitride (pBN) as the material for crucible 1. Furthermore, the crystal growth apparatus may be equipped with a crucible holder 4 for holding crucible 1. For example, silicon carbide can be used as the material for the crucible holder 4.

[0093] In the crystal growth apparatus, the heating element 2 is arranged in pairs to surround the outer circumference of the cylindrical crucible 1. Furthermore, each heating element 2 is divided into multiple parts perpendicular to the axis of the crucible, resulting in a multi-stage configuration. This allows the output of the heating element 2 to be controlled independently for each element and each part, making it possible to easily gradually decrease the output of the heating element 2 upward along the axis of the crucible 1. By gradually decreasing the output of the heating element 2 upward along the axis of the crucible 1, the interface between the crystal solid to be grown on the raw material molten side of the seed crystal and the raw material molten can be made to have an intersection angle of less than 90° with respect to the axis of the crucible 1. The manufacturing methods for InP substrates and GaAs substrates as III-V compound semiconductor single crystal substrates will be described in detail below, with reference to Figure 8 for each step of the above manufacturing method. Figure 8 is a flowchart showing an example of a manufacturing method for a III-V compound semiconductor single crystal substrate according to this embodiment.

[0094] <Method for manufacturing InP substrate> (Seed crystal loading step S10) In the method for manufacturing an InP substrate, first, a seed crystal loading step S10 is executed. In the seed crystal loading step S10, a seed crystal 31 (InP seed crystal) is loaded into the cavity of the seed crystal holding part of the crucible 1. As a method for loading the seed crystal 31 into the seed crystal holding part, a conventionally known method can be used. Here, for the seed crystal 31, it is preferable that the cross-sectional area thereof is 15% or more with respect to the cross-sectional area of the straight body part of the crucible 1, and more preferably 50% or more. The average dislocation density of the seed crystal 31 is preferably 5000 cm -2 and more preferably 2000 cm -2 . It is also preferable to add a trace amount of impurity atoms (S, Sn) to the seed crystal 31. Further, the inclination angle from the conical part to the straight body part of the crucible 1 is preferably 40° or less, and more preferably 20° or less.

[0095] (Raw material loading step S20) Next, a raw material loading step S20 is executed. In the raw material loading step S20, a plurality of块状物 made of polycrystalline (InP polycrystalline) of a III-V compound semiconductor raw material are loaded into and stacked in the crucible 1 in the crystal growth part (conical part and straight body part). Further, a predetermined amount of impurity atoms (S, Sn) can be added in this step.

[0096] (Sealing agent placement step S30) Next, a sealing agent placement step S30 is executed. In the sealing agent placement step S30, a conventionally known sealing agent (for example, a solid sealing agent made of B2O3 (boron oxide)) in the VB method is placed on the above块状物.

[0097] (Crystal growth step S40: First step) It should be noted that the text contains some unclear or potentially incorrect expressions like "塊状物" which might need further clarification in the original context for a more accurate translation.Next, the first step, the crystal growth step S40, is executed. Specifically, the first step, the crystal growth step S40, is performed with the aim of obtaining a III-V compound semiconductor single crystal (InP single crystal) by bringing a seed crystal 31 into contact with a raw material melt 33 and growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31. Specifically, a crucible 1 containing the seed crystal 31, a lump of raw material for the III-V compound semiconductor single crystal, and a solid encapsulant is loaded into the crucible holder 4 of the crystal growth apparatus. Then, an electric current is supplied to the heating element 2, and the crucible 1 is heated. As a result, the solid encapsulant melts into a liquid encapsulant 5, and the lump of raw material melts into a raw material melt 33. Subsequently, a portion of the seed crystal 31 also melts and comes into contact with the raw material melt 33 at its interface. Furthermore, by gradually lowering the crucible 1 along its axis downward (towards the seed crystal holding portion) relative to the heating element 2, a temperature gradient is formed in the crucible 1 such that the temperature on the seed crystal 31 side is lower and the temperature on the raw material melt 33 side is higher, causing the raw material melt 33 in contact with the seed crystal 31 to solidify and the crystalline solid 32 to grow on the raw material melt 33 side of the seed crystal 31. The speed at which the crucible 1 is lowered along its axis is preferably 10 mm / hour or less, and more preferably 5 mm / hour or less. 。

[0098] Here, the heating elements 2 are arranged in pairs (one set) at half-circles so as to cover the outer circumference of the crucible 1, as described above. Furthermore, the output of the heating elements 2 is controlled to gradually decrease upward along the axis of the crucible 1. As a result, in the first step, when the crystalline solid 32 is grown on the raw material molten 33 side of the seed crystal 31, the interface 3a between the crystalline solid 32 and the raw material molten 33 is not horizontal, but has an intersection angle of less than 90° with respect to the axis of the crucible 1. For example, it is preferable that the interface 3a has an intersection angle of 10 to 70° with respect to the axis of the crucible 1.

[0099] In the first step, subsequently, the crucible 1 is pulled downward along its axis with respect to the heating element 2, and the non-horizontal interface 3a between the crystalline solid 32 and the raw material melt 33 is raised toward the liquid sealant 5 side to solidify the raw material melt 33, and the crystalline solid 32 can be grown upward along the axis of the crucible 1. The growth of the crystalline solid 32 continues until the solidification of the raw material melt 33 remaining in the crystal growth portion of the crucible 1 is completed. Thereby, a III-V compound semiconductor single crystal (InP single crystal) made of the crystalline solid 32 can be obtained.

[0100] (Cutting process and outer peripheral grinding process S50: Second step) The cutting process is a process of obtaining a III-V compound semiconductor substrate precursor by cutting out a III-V compound semiconductor crystal (InP single crystal) taken out from the crucible 1. Further, the outer peripheral grinding process is a process of obtaining a III-V compound semiconductor substrate (InP substrate) having a circular main surface by grinding the outer periphery of the III-V compound semiconductor substrate precursor. That is, the cutting process and the outer peripheral grinding process S50 (second step) are processes of performing slicing on the above InP single crystal. The cutting process and the outer peripheral grinding process S50 can be respectively executed by using a conventionally known cutting method and outer peripheral grinding method in the method for manufacturing an InP substrate using the VB method.

[0101] <Method for manufacturing a GaAs substrate> (Seed crystal loading process S10) In the method for manufacturing a GaAs substrate, first, the seed crystal loading process S10 is executed. In the seed crystal loading process S10, a seed crystal 31 (GaAs seed crystal) is loaded into the cavity of the seed crystal holding portion of the crucible 1. A conventionally known method can be used as the method for loading the seed crystal 31 into the seed crystal holding portion.

[0102] (Raw material loading process S20) Next, the raw material charging process S20 is performed. In the raw material charging process S20, multiple lumps of polycrystalline (GaAs polycrystalline) III-V compound semiconductor raw materials are charged into the crucible 1 and stacked in the crystal growth section (conical section and straight section). Furthermore, a predetermined amount of impurity atoms (Si) can be added in this process.

[0103] (Sealant placement process S30) Next, the sealant placement step S30 is performed. In the sealant placement step S30, a sealant conventionally known in the VB method (for example, a solid sealant consisting of B2O3 (boron oxide)) is placed on the above-mentioned mass.

[0104] (Crystal growth process S40: 1st process) Next, the first step, the crystal growth step S40, is executed. Specifically, the first step, the crystal growth step S40, is performed with the aim of obtaining a III-V compound semiconductor single crystal (GaAs single crystal) by bringing a seed crystal 31 into contact with a raw material melt 33 and growing a crystalline solid 32 on the raw material melt 33 side of the seed crystal 31. Specifically, a crucible 1 containing the seed crystal 31, a lump of raw material for the III-V compound semiconductor single crystal, and a solid encapsulant is loaded into the crucible holder 4 of the crystal growth apparatus. Then, an electric current is supplied to the heating element 2, and the crucible 1 is heated. As a result, the solid encapsulant melts into a liquid encapsulant 5, and the lump of raw material melts into a raw material melt 33. Subsequently, a portion of the seed crystal 31 also melts and comes into contact with the raw material melt 33 at its interface. Furthermore, by gradually pulling the crucible 1 downward along its axis (towards the seed crystal holding part) relative to the heating element 2, a temperature gradient is formed in the crucible 1 such that the temperature on the seed crystal 31 side is lower and the temperature on the raw material melt 33 side is higher, causing the raw material melt 33 in contact with the seed crystal 31 to solidify and the crystalline solid 32 to grow on the raw material melt 33 side of the seed crystal 31. The speed at which the crucible 1 is pulled downward along its axis is not particularly limited, but can be, for example, 2 to 10 mm / hour.

[0105] As described above, the heating elements 2 are arranged in pairs (one set) at half-circles around the outer circumference of the crucible 1. Furthermore, the output of the heating elements 2 is controlled to gradually decrease upward along the axis of the crucible 1. As a result, in the first step, when the crystalline solid 32 is grown on the raw material molten 33 side of the seed crystal 31, the interface 3a between the crystalline solid 32 and the raw material molten 33 is not horizontal, but has an intersection angle of less than 90° with respect to the axis of the crucible 1. For example, it is preferable that the interface 3a has an intersection angle of 10 to 70° with respect to the axis of the crucible 1.

[0106] In the first step, the crucible 1 is subsequently pulled downward along its axis relative to the heating element 2, raising the non-horizontal interface 3a between the crystalline solid 32 and the raw material molten 33 toward the liquid sealant 5, thereby solidifying the raw material molten 33 and allowing the crystalline solid 32 to grow upward along the axis of the crucible 1. The growth of the crystalline solid 32 continues until the solidification of the raw material molten 33 remaining in the crystal growth section of the crucible 1 is complete. This makes it possible to obtain a III-V compound semiconductor single crystal (GaAs single crystal) consisting of the crystalline solid 32.

[0107] (Cutting process and outer circumference grinding process S50: Second process) The cutting step is a step in which a III-V compound semiconductor substrate precursor is obtained by cutting the III-V compound semiconductor crystal (GaAs single crystal) removed from crucible 1. Furthermore, the outer edge grinding step is a step in which a III-V compound semiconductor substrate (GaAs substrate) having a circular main surface is obtained by grinding the outer edge of the III-V compound semiconductor substrate precursor. In other words, the cutting step and the outer edge grinding step S50 (second step) are steps in which slicing is performed on the above GaAs single crystal. The cutting step and the outer edge grinding step S50 can be performed, respectively, by using conventionally known cutting method and outer edge grinding method in a GaAs substrate manufacturing method using the VB method.

[0108] <Effects and Effects> By performing each of the above steps, a III-V compound semiconductor single crystal substrate having a circular main surface can be manufactured. In the manufacturing method of the III-V compound semiconductor single crystal substrate according to this embodiment, in particular, in the first step, the crystalline solid 32 is grown on the raw material melt 33 side of the seed crystal 31 such that the interface 3a between the crystalline solid 32 and the raw material melt 33 has an intersection angle of less than 90° with respect to the axis of the crucible 1. As a result, the crack defect rate of the III-V compound semiconductor single crystal substrate is reduced when slicing is performed in the second step. Thus, a III-V compound semiconductor single crystal substrate with a reduced crack defect rate can be obtained by the above manufacturing method.

[0109] In the above manufacturing method, the growth direction of the III-V compound semiconductor single crystal (crystalline solid 32) is <100> It is preferable that the orientation is such. Furthermore, the III-V compound semiconductor single crystal substrate according to this embodiment is preferably obtained by cutting out the {100}just plane from a III-V compound semiconductor single crystal as the main surface. Furthermore, the above-mentioned III-V compound semiconductor single crystal substrate having an off-angle greater than 0° and 15° or less from the {100} plane is, <100> It can be obtained by performing gradient slicing using conventionally known methods from a III-V compound semiconductor single crystal with the direction of growth as the growth direction. [Examples]

[0110] The present disclosure will be described in more detail below with reference to examples, but the present disclosure is not limited to these examples. In the examples described later, the VB method is used by using the crystal growth apparatus shown in Figure 7. <100> III-V compound semiconductor single crystals were grown with the direction as the growth direction to obtain InP substrates (Examples 1-8) with a main surface orientation of the (100) just plane and GaAs substrates (Examples 11-17) with a main surface orientation of the (100) plane having an off-angle of 0-15° from the (100) plane. On the other hand, in the comparative examples described later, III-V compound semiconductor crystals (InP substrates and GaAs substrates) were grown using a conventional crystal growth apparatus equipped with a heating element that covers the entire circumference of the side surface of the crucible. In each example and comparative example, 1000 InP substrates or GaAs substrates were manufactured.

[0111] <<First Examination>> [Manufacturing of III-V compound semiconductor single crystal substrates] <Example 1: InP substrate> (Seed crystal charging process S10) A seed crystal 31 made of InP, manufactured by a conventionally known method, was inserted into the cavity of the seed crystal holding section of the crucible 1 provided in the crystal growth apparatus using a conventionally known method. A small amount of tin (Sn) was added to the seed crystal 31 as an impurity element. The cross-sectional area of ​​the seed crystal 31 was set to 50% of the cross-sectional area of ​​the straight section of the crucible 1. Furthermore, the inclination angle from the conical section of the crucible 1 to the straight section was set to 20°.

[0112] (Raw material loading process S20 and sealant placement process S30) Multiple lumps made of polycrystalline InP were placed in the crystal growth section of crucible 1 and stacked. A predetermined amount of tin (Sn) was also added. Furthermore, a solid encapsulant made of B2O3 was placed on top of the raw materials of the lumps. The inner diameter of the crystal growth section of crucible 1 used in this embodiment was 60 mm.

[0113] (Crystal growth process S40: 1st process) By supplying an electric current to the heating element 2 and heating the crucible 1, the solid encapsulant was converted into a liquid encapsulant 5, and the lumpy material in the crucible 1 was converted into a raw material melt 33. Furthermore, a portion of the seed crystal 31 and the lumpy material located at the interface with the seed crystal 31 were also converted into the raw material melt 33 and brought into contact with it. Next, by pulling the crucible 1 downward along its axis (towards the seed crystal holding part) relative to the heating element 2, a crystalline solid 32 was grown on the raw material melt 33 side of the seed crystal 31.

[0114] Here, the heating element 2 is arranged in pairs to surround the outer circumference of the cylindrical crucible 1, as described above. Furthermore, each heating element 2 is divided into multiple parts perpendicular to the axis of the crucible 1, thus forming a multi-stage structure. This configuration gradually reduces the output of the heating element 2 upward along the axis of the crucible 1. As a result, in the first step, the interface 3a between the crystalline solid 32 and the raw material molten 33 has an intersection angle of 30° with respect to the axis of the crucible 1.

[0115] Next, the heating element 2 was pulled downward along the axis of the crucible 1, raising the interface 3a between the crystalline solid 32 and the raw material molten 33 upward along the axis of the crucible 1, and causing the crystalline solid 32 to grow upward along the axis of the crucible 1. This was continued until the solidification of the raw material molten 33 remaining in the crystal growth section of the crucible 1 was completed. In this way, an InP single crystal was produced in the crucible 1. After that, the InP single crystal was removed from the crucible 1 using a conventionally known method.

[0116] (Cutting process and outer circumference grinding process S50: Second process) An InP substrate precursor was obtained by cutting an InP single crystal removed from crucible 1 using a conventionally known cutting method and outer circumference grinding method. Further grinding of the outer circumference of the InP substrate precursor produced an InP substrate having a circular main surface. Thus, an InP substrate with a diameter of 50 mm and a thickness of 350 μm was obtained as Example 1.

[0117] <Example 2: InP substrate> An InP substrate with a diameter of 50 mm and a thickness of 350 μm was obtained by using the same method as in Example 1, except that a seed crystal 31 with a small amount of sulfur (S) added in the seed crystal charging process was prepared. In the crystal growth process (first step) of Example 2, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0118] <Example 3: InP substrate> An InP substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 85 mm. In the crystal growth process (first step) of Example 3, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0119] <Example 4: InP substrate> An InP substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 85 mm. In the crystal growth process (first step) of Example 4, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0120] <Example 5: InP substrate> An InP substrate with a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 110 mm. In the crystal growth process (first step) of Example 5, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0121] <Example 6: InP substrate> An InP substrate with a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 110 mm. In the crystal growth process (first step) of Example 6, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0122] <Example 7: InP substrate> An InP substrate with a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 160 mm. In the crystal growth process (first step) of Example 7, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0123] <Example 8: InP substrate> An InP substrate with a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 160 mm. In the crystal growth process (first step) of Example 8, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0124] <Comparative Example 1: InP substrate> By using a conventional crystal growth apparatus, an InP substrate with a diameter of 50 mm and a thickness of 350 μm was obtained by using the same method as in Example 1, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0125] <Comparative Example 2: InP Substrate> By using a conventional crystal growth apparatus, an InP substrate with a diameter of 50 mm and a thickness of 350 μm was obtained by using the same method as in Example 2, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0126] <Comparative Example 3: InP Substrate> An InP substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Comparative Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 85 mm.

[0127] <Comparative Example 4: InP Substrate> An InP substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Comparative Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 85 mm.

[0128] <Comparative Example 5: InP Substrate> An InP substrate with a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Comparative Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 110 mm.

[0129] <Comparative Example 6: InP Substrate> An InP substrate with a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Comparative Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 110 mm.

[0130] <Comparative Example 7: InP Substrate> An InP substrate with a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Comparative Example 1, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 160 mm.

[0131] <Comparative Example 8: InP Substrate> An InP substrate with a diameter of 150 mm and a thickness of 675 μm was obtained by using the same method as in Comparative Example 2, except that the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus was set to 160 mm.

[0132] <Example 11: GaAs substrate> (Seed crystal charging process S10) A seed crystal 31 made of GaAs, manufactured by a conventionally known method, was inserted into the cavity of the seed crystal holding section of the crucible 1 provided in the crystal growth apparatus using a conventionally known method. A small amount of silicon (Si) was added to the seed crystal 31 as an impurity element.

[0133] (Raw material loading process S20 and sealant placement process S30) Multiple lumps made of polycrystalline GaAs were placed in the crystal growth section of crucible 1 and stacked. A predetermined amount of Si was also added. Furthermore, a solid encapsulant made of B2O3 was placed on top of the raw materials of the lumps. The inner diameter of the crystal growth section of crucible 1 used in this embodiment is 80 mm.

[0134] (Crystal growth process S40: 1st process) By supplying an electric current to the heating element 2 and heating the crucible 1, the solid encapsulant was converted into a liquid encapsulant 5, and the lumpy material in the crucible 1 was converted into a raw material melt 33. Furthermore, a portion of the seed crystal 31 and the lumpy material located at the interface with the seed crystal 31 were also converted into the raw material melt 33 and brought into contact with it. Next, by pulling the crucible 1 downward along its axis (towards the seed crystal holding part) relative to the heating element 2, a crystalline solid 32 was grown on the raw material melt 33 side of the seed crystal 31.

[0135] Here, the heating element 2 is arranged in pairs to surround the outer circumference of the cylindrical crucible 1, as described above. Furthermore, each heating element 2 is divided into multiple parts perpendicular to the axis of the crucible 1, thus forming a multi-stage structure. This configuration gradually reduces the output of the heating element 2 upward along the axis of the crucible 1. As a result, in the first step, the interface 3a between the crystalline solid 32 and the raw material molten 33 has an intersection angle of 30° with respect to the axis of the crucible 1.

[0136] Next, the heating element 2 was pulled downward along the axis of the crucible 1, raising the interface 3a between the crystalline solid 32 and the raw material molten 33 upward along the axis of the crucible 1, and causing the crystalline solid 32 to grow upward along the axis of the crucible 1. This was continued until the solidification of the raw material molten 33 remaining in the crystal growth section of the crucible 1 was completed. In this way, a GaAs single crystal was produced in the crucible 1. After that, the GaAs single crystal was removed from the crucible 1 using a conventionally known method.

[0137] (Cutting process and outer circumference grinding process S50: Second process) Using conventionally known cutting and outer circumference grinding methods, GaAs was extracted from crucible 1. single A GaAs substrate precursor was obtained by cutting a crystal using a known slicing method so that the main surface had a (100)just plane. A GaAs substrate having a circular main surface was then manufactured by grinding the outer periphery of the GaAs substrate precursor. As a result, a GaAs substrate with a diameter of 75 mm and a thickness of 600 μm was obtained as Example 11.

[0138] <Example 12: GaAs substrate> In the cutting and outer circumference grinding process (second step), a GaAs substrate precursor was obtained by cutting the GaAs single crystal removed from the crucible 1 so that the main surface had an off-angle of 10° from the (100) plane. Except for this, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 75 mm and a thickness of 600 μm. In the crystal growth process (first step) of Example 12, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0139] <Example 13: GaAs substrate> Except for setting the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus to 110 mm, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 100 mm and a thickness of 625 μm. In the crystal growth process (first step) of Example 13, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0140] <Example 14: GaAs substrate> Except for setting the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus to 160 mm, and cutting the GaAs single crystal removed from the crucible 1 in the cutting and outer circumference grinding process S50 so that the main surface has an off-angle of 2° from the (100) plane, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm. In the crystal growth process (first step) of Example 14, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0141] <Example 15: GaAs substrate> Except for setting the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus to 160 mm, and cutting the GaAs single crystal removed from the crucible 1 in the cutting and outer circumference grinding process S50 so that the main surface has an off-angle of 6° from the (100) plane, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm. In the crystal growth process (first step) of Example 15, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0142] <Example 16: GaAs substrate> Except for setting the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus to 160 mm, and cutting the GaAs single crystal removed from the crucible 1 in the cutting and outer circumference grinding process S50 so that the main surface has an off-angle of 15° from the (100) plane, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm. In the crystal growth process (first step) of Example 16, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0143] <Example 17: GaAs substrate> Except for setting the inner diameter of the crystal growth section in the crucible 1 of the crystal growth apparatus to 210 mm, and cutting the GaAs single crystal removed from the crucible 1 in the cutting and outer circumference grinding process S50 so that the main surface has an off-angle of 6° from the (100) plane, the same method as in Example 11 was used to obtain a GaAs substrate with a diameter of 200 mm and a thickness of 675 μm. In the crystal growth process (first step) of Example 17, the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 had an intersection angle of 30° with respect to the axis of the crucible 1.

[0144] <Comparative Example 11: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 11, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0145] <Comparative Example 12: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 75 mm and a thickness of 600 μm was obtained by using the same method as in Example 12, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0146] <Comparative Example 13: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 100 mm and a thickness of 625 μm was obtained by using the same method as in Example 13, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0147] <Comparative Example 14: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm was obtained by using the same method as in Example 14, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0148] <Comparative Example 15: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm was obtained by using the same method as in Example 15, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0149] <Comparative Example 16: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 150 mm and a thickness of 760 μm was obtained by using the same method as in Example 16, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0150] <Comparative Example 17: GaAs Substrate> By using a conventional crystal growth apparatus, a GaAs substrate with a diameter of 200 mm and a thickness of 675 μm was obtained by using the same method as in Example 17, except that the interface 3a between the crystal solid 32 grown in the crucible 1 and the raw material melt 33 in the crystal growth process (first step) was made to have a 90° intersection angle with respect to the axis of the crucible 1 (i.e., made horizontal).

[0151] [Evaluation of III-V compound semiconductor single crystals] For the III-V compound semiconductor single crystal substrates of Examples 1 to 8, Examples 11 to 17, Comparative Examples 1 to 8, and Comparative Examples 11 to 17, the average concentration of impurity atoms in the substrate, the dislocation density on the main surface, and the degree of asymmetry of dislocations present on the main surface were determined using the method described above. Furthermore, the average value of residual strain and the morphology of the distribution of residual strain in polar coordinates (whether it is n-fold symmetric, and furthermore, whether it is mirror symmetry (including cases where it is nearly mirror symmetry)) were determined using the method described above, and it was also determined whether the wave source of the wave pattern visible on the main surface is located on the main surface using the method described above. The results are shown in Tables 1 to 4.

[0152] Furthermore, when manufacturing 1000 III-V compound semiconductor single crystal substrates for Examples 1 to 8, Examples 11 to 17, Comparative Examples 1 to 8, and Comparative Examples 11 to 17, the percentage of good III-V compound semiconductor single crystal substrates obtained without cracking, chipping, etc., was determined as the "slicing yield." The results are also shown in Tables 1 to 4. In Tables 1 to 4, a "slicing yield" of 90% or more was evaluated as good, and a yield of less than 90% was evaluated as not good.

[0153] [Table 1]

[0154] [Table 2]

[0155] [Table 3]

[0156] [Table 4]

[0157] [Consideration] According to Tables 1 to 4, in each of the III-V compound semiconductor single crystal substrates in Examples 1 to 8 and Examples 11 to 17, the wave source of the wave pattern formed on the main surface was not located on the main surface, and in that case, the "slicing yield" could be evaluated as good at 90% or more. On the other hand, in each of the III-V compound semiconductor single crystal substrates in Comparative Examples 1 to 8 and Comparative Examples 11 to 17, the wave source of the wave pattern formed on the main surface was located on the main surface, and in that case, the "slicing yield" was less than 90%, and could not be evaluated as good.

[0158] <<Second Examination>> The concentration distribution of impurity atoms (S) on the main surface of the III-V compound semiconductor single crystal substrates (InP substrates) of Examples 4 and 6, and Comparative Examples 4 and 6, was measured using the method described above. The results are shown in Table 5. In Table 5, the impurity atom (S) concentration shown in the "Wave Source Side" column refers to the concentration measured in a sample obtained from a position on the main surface where a hypothetical straight line passing through the center of the main surface and extending from the wave source toward the center of the main surface coincides with the outer circumference on the wave source side of the main surface. The impurity atom (S) concentration shown in the "Center" column refers to the concentration measured in a sample obtained from the center of the main surface, and the impurity atom (S) concentration shown in the "Ripple Spreading Side" column refers to the concentration measured in a sample obtained from a position on the main surface where a hypothetical straight line passing through the center of the main surface and extending from the wave source toward the center of the main surface coincides with the outer circumference on the opposite side of the wave source from the center of the main surface.

[0159] [Table 5]

[0160] [Consideration] According to Table 5, the impurity atoms present in the InP substrates of Examples 4 and 6 increased uniformly along the direction from the wave source towards the center of the main surface, i.e., from the "wave source side" to the "ripple expansion side," resulting in a higher concentration distribution on the "ripple expansion side" than on the "wave source side." On the other hand, the impurity atoms present in the InP substrates of Comparative Examples 4 and 6 showed a distribution with similar concentrations on both the "wave source side" and the "ripple expansion side."

[0161] <<Third Examination>> The concentration distribution of impurity atoms (Si) on the main surface of the III-V compound semiconductor single crystal substrates (GaAs substrates) of Examples 13 and 15, and Comparative Examples 13 and 15, was measured using the method described above. The results are shown in Table 6. In Table 6, the impurity atom (Si) concentration shown in the "Wave Source Side" column refers to the concentration measured in a sample obtained from a position on the main surface where a hypothetical straight line passing through the center of the main surface and extending from the wave source toward the center of the main surface coincides with the outer periphery on the wave source side of the main surface. The impurity atom (Si) concentration shown in the "Center" column refers to the concentration measured in a sample obtained from the center of the main surface, and the impurity atom (Si) concentration shown in the "Wave Spreading Side" column refers to the concentration measured in a sample obtained from a position on the main surface where a hypothetical straight line passing through the center of the main surface and extending from the wave source toward the center of the main surface coincides with the outer periphery on the opposite side of the wave source from the center of the main surface.

[0162] [Table 6]

[0163] [Consideration] According to Table 6, the impurity atoms present in the GaAs substrates of Examples 13 and 15 increased uniformly along the direction from the wave source towards the center of the main surface, i.e., from the "wave source side" to the "ripple expansion side," resulting in a higher concentration distribution on the "ripple expansion side" than on the "wave source side." On the other hand, the impurity atoms present in the GaAs substrates of Comparative Examples 13 and 15 showed a distribution with similar concentrations on both the "wave source side" and the "ripple expansion side."

[0164] As described above, the embodiments and examples of this disclosure have been explained, but it is also intended from the outset that the configurations of each of the embodiments and examples described above may be combined as appropriate.

[0165] The embodiments and examples disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the present invention is indicated by the claims rather than the embodiments and examples described above, and all modifications within the scope of the claims are intended to be included in the meaning of equivalents and within the scope. [Explanation of Symbols]

[0166] O wave source, P wave pattern, S main surface, 100 III-V compound semiconductor single crystal substrate, 101 III-V compound semiconductor single crystal substrate (conventional), I spacing, M measurement point, L1 virtual first line, L2 virtual second line, R1 first region, R2 second region, OF orientation flat, 1 crucible, 2 heating element, 3a interface, 31 seed crystal, 32 crystal solid, 33 raw material melt, 3a interface, 4 crucible holder, 5 liquid encapsulant, S10 seed crystal loading process, S20 raw material loading process, S30 encapsulant placement process, S40 crystal growth process, S50 cutting process and outer circumference grinding process.

Claims

1. A III-V compound semiconductor single crystal substrate having a circular main surface, The aforementioned III-V compound semiconductor single crystal substrate is an indium phosphide single crystal substrate. The indium phosphide single crystal substrate has a wave-like pattern visible on its main surface after being subjected to the following treatment: The aforementioned wave-like pattern corresponds to a part of the wave pattern that spreads concentrically from the wave source. The wave source is a III-V compound semiconductor single crystal substrate not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. The main surface is then irradiated with light from a 500 W reflective incandescent bulb from a position 20 cm above the surface for 1 to 2 hours.

2. The III-V compound semiconductor single crystal substrate according to claim 1, wherein the diameter of the indium phosphide single crystal substrate is 50 mm or more and 155 mm or less.

3. The dislocation density of the main surface is 0 cm -2 More than 2000cm -2 The following is a III-V compound semiconductor single crystal substrate according to claim 1 or claim 2.

4. The degree of asymmetry of the dislocations present on the main surface is 1.8 or greater. The aforementioned asymmetry is, The main surface is divided into a first region and a second region by a hypothetical first straight line that intersects perpendicularly with a hypothetical straight line extending from the wave source toward the center of the main surface and passes through the center of the main surface. In each of the first and second regions, two or more points are placed at a pitch of 5 mm or more in the direction away from the center of the main surface, on a virtual second line that passes through the center of the main surface and intersects the first line perpendicularly, with a distance of 1 mm from the center of the main surface. 2 A measurement point is set in a square having an area of ​​1 cm, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated from the measurement result to 1 cm. 2 Convert to a value per unit area, A III-V compound semiconductor single crystal substrate according to claim 1 or claim 2, wherein the absolute value of a numerical value obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the second region from the average value of the converted values ​​obtained from all measurement points in the first region is calculated by dividing the absolute value of the numerical value obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the first region and all measurement points in the second region.

5. A III-V compound semiconductor single crystal substrate having a circular main surface, The aforementioned III-V compound semiconductor single crystal substrate is a gallium arsenide single crystal substrate. The gallium arsenide single crystal substrate has a wave-like pattern visible on its main surface by the following treatment: The aforementioned wave-like pattern corresponds to a part of the wave pattern that spreads concentrically from the wave source. The wave source is a III-V compound semiconductor single crystal substrate not located on the main surface. Treatment: The main surface is positioned horizontally at a depth of 10 mm below the surface of a 25°C mixture consisting of 10 g of chromium (VI) oxide, 10 mL of a 50% by mass hydrofluoric acid solution, and 400 mL of pure water. The main surface is then illuminated with light from a 500 W reflective incandescent bulb from a position 20 cm above the surface for 5 to 20 minutes.

6. The III-V compound semiconductor single crystal substrate according to claim 5, wherein the diameter of the gallium arsenide single crystal substrate is 75 mm or more and 205 mm or less.

7. The dislocation density of the main surface is 0 cm -2 More than 50cm -2 The following is the III-V compound semiconductor single crystal substrate according to claim 5 or claim 6.

8. The degree of asymmetry of the dislocations present on the main surface is 2.0 or greater. The aforementioned asymmetry is, The main surface is divided into a first region and a second region by a hypothetical first straight line that intersects perpendicularly with a hypothetical straight line extending from the wave source toward the center of the main surface and passes through the center of the main surface. In each of the first and second regions, two or more points are placed at a pitch of 5 mm or more in the direction away from the center of the main surface, on a virtual second line that passes through the center of the main surface and intersects the first line perpendicularly, with a distance of 1 mm from the center of the main surface. 2 A measurement point is set in a square having an area of ​​1 cm, the number of dislocations is measured at the measurement point, and the number of dislocations is calculated from the measurement result to 1 cm. 2 Convert to a value per unit area, A III-V compound semiconductor single crystal substrate according to claim 5 or claim 6, wherein the absolute value of a numerical value obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the second region from the average value of the converted values ​​obtained from all measurement points in the first region is calculated by dividing the absolute value of the numerical value obtained by subtracting the average value of the converted values ​​obtained from all measurement points in the first region and all measurement points in the second region.

9. The main surface is a plane having an off-angle of 0° to 15° from the {100} plane, as described in claim 1 or claim 5, for a III-V compound semiconductor single crystal substrate.

10. The average value of the residual strain, which is the absolute value of the difference between the expansion / contraction strain in the direction along the diameter of the main surface and the expansion / contraction strain in the direction along the tangent line, is 3.5×10 -5 The III-V compound semiconductor single crystal substrate according to claim 1 or claim 5, which is as follows.

11. The residual strain, which is the absolute value of the difference between the stretching strain in the direction along the diameter of the main surface and the stretching strain in the direction along the tangent, does not have a distribution that is n times symmetric around the origin in polar coordinates, where the origin is the center of the main surface and the starting line is a hypothetical line segment extending from the center of the main surface toward the wave source to a point 15 mm away from the outer edge of the III-V compound semiconductor single crystal substrate, and n is an integer of 2 or more, as described in claim 1 or claim 5.

12. The III-V compound semiconductor single crystal substrate according to claim 1 or claim 5, wherein the conductivity type of the III-V compound semiconductor single crystal substrate is electron-withdrawing.

13. The III-V compound semiconductor single crystal substrate according to claim 1 or claim 5, wherein the III-V compound semiconductor single crystal substrate contains tin or sulfur as an impurity atom when it is an indium phosphide single crystal substrate, and contains silicon as an impurity atom when it is a gallium arsenide single crystal substrate.

14. The atomic concentration of the aforementioned impurity atoms is 1 × 10 16 cm -3 The above 1 x 10 19 cm -3 The following is the III-V compound semiconductor single crystal substrate according to claim 13.

15. The III-V compound semiconductor single crystal substrate according to claim 13, wherein the impurity atoms exhibit a uniform concentration distribution in the III-V compound semiconductor single crystal substrate that changes uniformly in the direction from the wave source toward the center of the main surface.

16. A method for manufacturing a III-V compound semiconductor single crystal substrate using a crystal growth apparatus, A step of obtaining a group III-V compound semiconductor single crystal by bringing a seed crystal into contact with a raw material melt and growing a crystalline solid on the raw material melt side of the seed crystal, The process includes the step of obtaining a III-V compound semiconductor single crystal substrate having a circular main surface by cutting out the aforementioned III-V compound semiconductor single crystal, The crystal growth apparatus comprises at least a cylindrical crucible and a heating element for heating the crucible. The crucible has the seed crystal contained at its bottom, and the raw material molten liquid contained above the seed crystal within the crucible. A method for manufacturing a group III-V compound semiconductor single crystal substrate, wherein the interface between the crystalline solid and the raw material melt has an intersection angle of less than 90° with respect to the axis of the crucible.

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