Compound semiconductor single crystal substrate and method for manufacturing compound semiconductor single crystal

A compound semiconductor single crystal substrate with controlled growth methods and asymmetric heating in a crucible enhances the yield of epitaxial substrates, addressing the low yield issue in existing technologies.

WO2026110286A1PCT designated stage Publication Date: 2026-05-28SUMITOMO ELECTRIC INDUSTRIES LTD
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Patent Information

Authority / Receiving Office
WO · WO
Patent Type
Applications
Current Assignee / Owner
SUMITOMO ELECTRIC INDUSTRIES LTD
Filing Date
2024-11-21
Publication Date
2026-05-28

AI Technical Summary

Technical Problem

Existing methods for manufacturing compound semiconductor single crystals result in low yield of epitaxial substrates, particularly when using materials like gallium arsenide, indium phosphide, gallium nitride, silicon carbide, and gallium phosphide.

Method used

The development of a compound semiconductor single crystal substrate with specific cleavage patterns and controlled growth methods, including the use of a crucible with asymmetric heating and rotation, to enhance the yield of epitaxial substrates.

Benefits of technology

The proposed method and substrate design significantly improve the yield of epitaxial substrates by ensuring precise control over crystal growth, even with challenging materials, and allow for larger diameter substrates.

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Abstract

Provided is a compound semiconductor single crystal substrate, wherein: a first striped pattern is observed on at least one of a first cleavage plane and a second cleavage plane and a second striped pattern is observed on at least one of a third cleavage plane and a fourth cleavage plane; the first striped pattern is formed by a plurality of first lines; the second striped pattern is formed by a plurality of second lines; and at least one of a first distance and a second distance is 0.5 mm or less. The first distance is the distance in a first direction between arbitrary two points that overlap any one of the plurality of first lines, have a distance longer than 5 mm from an outer peripheral surface in a second direction, and have a mutual distance of 5 mm in the second direction, and the second distance is the distance in the first direction between arbitrary two points that overlap any one of the plurality of second lines, have a distance longer than 5 mm from the outer peripheral surface in the second direction, and have a mutual distance of 5 mm in a third direction.
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Citation Information

Patent Citations

  • Production of compound semiconductor single crystal

    JP1992074788A

  • Method for growing compound semiconductor single crystal

    JP1994107416A

  • Method and system for vertical gradient freezing 200 mm (8 inch) gallium arsenide substrates

    JP2024511114A