Semiconductor equipment

Abstract

To provide a novel semiconductor device.SOLUTION: A semiconductor device has a function of performing a product-sum operation between a weight value set by an analog current signal and an input value, in which the analog current signal is output by a digital-to-analog conversion circuit having a circuit in which a plurality of variable resistance elements and switches electrically connected in series are electrically connected in parallel, and a ferroelectric element is used as the variable resistance element. The ferroelectric element has a ferroelectric material containing an oxide containing either hafnium or zirconium, or both.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device. Furthermore, the technical fields of the invention disclosed herein, etc. This relates to an object, a method of operation, or a method of manufacture.

[0002] More specifically, one aspect of the present invention disclosed herein is the technical field of semiconductor devices, Display devices, liquid crystal display devices, light-emitting devices, energy storage devices, imaging devices, memory devices, signal processing devices, Rossessors, electronic devices, systems, methods for driving them, methods for manufacturing them, or their One example of an inspection method is to give this. [Background technology]

[0003] Currently, there is a lot of activity in developing integrated circuits that mimic the structure of the human brain. The pathway is an electronic circuit that incorporates the brain's structure, and the "neurons" and "s It has a circuit equivalent to a "naps." Therefore, such an integrated circuit is called a "neuromorph." It is sometimes called "brain-morphic," "brain-inspired," or "brain-referred." The integrated circuit has a non-von Neumann architecture, and its power consumption increases with increasing processing speed. Compared to the von Neumann architecture, which generates greater power, it offers parallel processing with extremely low power consumption. It is expected that this will be possible.

[0004] Information processing models that mimic neural networks with "neurons" and "synapses" are artificial This is called a neural network (ANN). It uses artificial neural networks. Therefore, it is possible to perform inferences with accuracy comparable to or exceeding that of humans. (Neural Network) In the work, the main operation is the weighted sum of neuron outputs, i.e., the sum-of-products operation. ru.

[0005] Non-patent document 1 proposes a sum-of-accumulate circuit using a non-volatile memory element. In the multiply-accumulate circuit, each memory element has a transistor with silicon in the channel formation region. By utilizing the operation of the zista in the subthreshold region, the multiplier stored in each memory element is used It outputs a current corresponding to the multiplication of the corresponding data and the input data corresponding to the multiplicand. The sum of the currents output by the memory elements in each column is used to obtain data corresponding to the sum-of-products operation. Because the sum-of-accumulate circuit has internal memory elements, it does not require external memory for multiplication and addition. It is possible to prevent data reading and writing from the source. Therefore, reading Furthermore, the number of data transfers caused by writing and other operations can be reduced, thus reducing power consumption. It is expected that this will lower the cost. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] X. Guo et al., “Fast, Energy-Efficient, Robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology” IEDM2017, pp.151-154. [Overview of the project] [Problems that the invention aims to solve]

[0007] When performing a sum-of-accumulate operation in a digital circuit, the digital data that becomes the multiplier (multiplier data) and The multiplication of digital data serving as a multiplicand (multiplicand data) is performed by a digital multiplication circuit, and the addition of the digital data (product data) obtained by this multiplication is performed by a digital addition circuit, and the digital data (product-sum data) is acquired as a result of the product-sum operation. The digital multiplication circuit, and the digital addition circuit preferably have a specification capable of handling multi-bit operations. However, in this case, since it is necessary to increase the circuit scale of each of the digital multiplication circuit and the digital addition circuit, the circuit area increases, and there is also a risk that the power consumption increases.

[0008] One aspect of the present invention has an object of providing a semiconductor device capable of performing a product-sum operation. Also one aspect of the present invention has an object of providing a semiconductor device with low power consumption. Also one aspect of the present invention has an object of providing a semiconductor device with a reduced circuit area.

Means for Solving the Problems

[0009] One aspect of the present invention is a semiconductor device (artificial neural network) having a function of performing a product-sum operation on a weight value set by an analog current signal and an input value.

[0010] Note that an analog current signal can also be used for writing the input value.

[0011] One aspect of the present invention is a semiconductor device (analog memory) that inputs data using an analog current signal.

[0012] One aspect of the present invention is a current output type digital-to-analog conversion circuit (current output type DAC (Digital to Analog Converter)) that converts a digital signal into an analog current signal. ​​​​

[0013] One aspect of the present invention is a transistor and a switch to which a bias potential is input to the gate. It has a first circuit electrically connected in a row, and multiple first circuits are electrically connected in parallel. This is a digital-to-analog conversion circuit having a second circuit. The total current flowing through the second circuit The sum can be output as an analog current signal. In the first circuit, the switch The on or off state is controlled by a signal corresponding to each bit of the digital signal. This is possible. The gate of a transistor is used to set the current value of the current flowing through the transistor. A bias potential is input for this purpose. The magnitude of the current flowing through each transistor is determined by the digital signal. The current value can be set to be weighted according to each bit of the number.

[0014] One aspect of the present invention is a first circuit in which a variable resistor element and a switch are electrically connected in series. A digital amplifier has a second circuit in which multiple first circuits are electrically connected in parallel. This is an analog conversion circuit. The sum of the currents flowing through the second circuit is output as an analog current signal. It is possible. In the first circuit, the on or off state of the switch is digital It can be controlled by the signal corresponding to each bit of the signal. The magnitude of the current is such that it corresponds to a weighted current value for each bit of the digital signal. It can be set to that.

[0015] The variable resistor element can be constructed using a ferroelectric material.

[0016] For example, a device made of a ferroelectric material (ferroelectric device) can be used. As an example, an FTJ (ferroelectric tunnel junction) element can be used. Therefore, a transistor (FeFET element) that includes a ferroelectric material as a gate insulating layer It can be used.

[0017] The ferroelectric material includes either hafnium or zirconium, or both. A configuration using oxides can be used.

[0018] One aspect of the present invention is a digital-to-analog conversion using a ferroelectric element as a variable resistance element. It is a circuit.

[0019] Furthermore, the output current of the second circuit is used as the input current of the current mirror circuit, and the current mirror circuit The output current of the circuit can be used as an analog current signal.

[0020] The output current of the second circuit is used as the input current of the current mirror circuit, and the output current is amplified. The current can be used as an analog current signal. The amplification factor can be set to multiple levels depending on the digital signal.

[0021] Furthermore, one aspect of the present invention, the digital-to-analog conversion circuit, is an artificial neural network. or not limited to those used in analog memory. For example, video signal input of a display device, etc. It can be used for a variety of purposes, such as those listed above. [Effects of the Invention]

[0022] According to one aspect of the present invention, a semiconductor device with reduced footprint can be provided. A semiconductor device that supports multi-bit digital signals can be provided. Or, the present invention In one embodiment, a semiconductor device with reduced power consumption can be provided. Alternatively, According to one aspect of the present invention, a semiconductor device with improved operating speed can be provided. Also or, according to one aspect of the present invention, a novel semiconductor device can be provided.

Brief Description of the Drawings

[0023] [Figure 1] FIGS. 1(A) to 1(C) are diagrams for explaining a configuration example of a DAC. [Figure 2] FIGS. 2(A) to 2(C) are diagrams for explaining a configuration example of a DAC. [Figure 3] FIG. 3 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 4] FIG. 4 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 5] FIG. 5 is a diagram for explaining a configuration example of an arithmetic circuit of an artificial neural network. [Figure 6] FIG. 6 is a top view photograph of an actually fabricated arithmetic circuit. [Figure 7] FIG. 7 is a circuit diagram showing the configuration of a DAC included in an actually fabricated arithmetic circuit. [Figure 8] FIG. 8 is a graph showing the input / output characteristics of a DAC.

Modes for Carrying Out the Invention

[0024] (Embodiment 1) The DAC 100 according to one aspect of the present invention will be described with reference to the drawings.

[0025] <Configuration Example of DAC100> FIGS. 1(A) to 1(C) show a configuration example of a DAC 100 that converts an n (n is a natural number of 2 or more) -bit digital signal into an analog current signal.

[0026] In FIG. 1(A), the DAC 100 is a transistor to which a bias potential is input to the gate The terminal 102-k (where k is a natural number between 1 and n) and the switch 101-k are electrically connected in series. It has a connected circuit 110-k, and circuits 110-1 to 110-n are electrically connected in parallel. A configuration having a connected circuit 120 can be provided. Note that transistor 102-k, Switch 101-k and circuit 110-k are not shown in Figure 1(A). Circuit 12 The sum of the currents flowing through 0 (corresponding to current Iin) can be output as an analog current signal. can.

[0027] Note that the current Iin is supplied to the wiring with the power supply potential V1, and the wiring has a potential difference with the power supply potential V1. A current flows between the wiring to which the power supply potential V2 is applied. For example, power supply potential V1 is equal to power supply potential V2 It can be set to a lower potential than that.

[0028] In circuit 110-k, the ON or OFF state of switch 101-k is digital Each bit of the signal can be controlled by the signal wd[k]. This can be a digital voltage signal.

[0029] The gate of transistor 102-k contains the current value of the current flowing through transistor 102-k. A bias potential BIAS is input to set the bias. The magnitude of the current is a weighted current value corresponding to the corresponding bit in the digital signal. It can be configured in this way.

[0030] The magnitude of the current flowing through transistor 102-k corresponds to the corresponding bit of the digital signal. When setting the current value to be weighted accordingly, for example, transistor 102- The channel width of k is 2 of transistor 102-1. k-1 You can double it. Also, transition Transistor 102-k is a transistor with the same configuration as transistor 102-1. k-1 pieces in parallel It may also be configured to be electrically connected.

[0031] The current Iin output from circuit 120 is used as the input current to the current mirror circuit 130. The output current Iout of the Rentmirror circuit 130 is output as an analog current signal.

[0032] It is also possible to use the output current of DAC100 as the current Iin.

[0033] Figure 1(B) shows that in Figure 1(A), the current mirror circuit 130 is made up of multiple transistors. This is an example of a configuration using the components. The connection relationships are as shown in the circuit diagram in Figure 1(B). In Figure 1(B), the current mirror circuit 130 is constructed using a p-channel transistor. However, it is not limited to this. It may also be constructed using n-channel transistors. Furthermore, the magnitudes of power supply potentials V1 and V2 depend on the polarity of the transistors that make up the circuit. The relationship can be changed.

[0034] Figure 1(C) shows a different configuration example of the current mirror circuit 130 from Figure 1(B). In configuration C), the current mirror circuit 130 has an output current Io for the current Iin. The amplification factor of ut can be changed. For example, a digital signal d1 to dm (where m is 2 or greater) can be changed. By controlling the natural number of the output current Iout, the current value of the output current Iout can be changed from 0 times the current value of the current Iin to 2 m It is possible to select and output a current value from -1 times the current value. For example, when m is 8, 0 The output can be selected from current values ​​ranging from double to 255 times (255 different current values).

[0035] In this case, when the current flowing through the switch to which the digital signal d1 is input is Iin, the current flowing through the switch to which the digital signal dm is input is 2 m-1 ×Iin, and the transistors in the current mirror circuit 130 may be designed.

[0036] Thus, a circuit corresponding to a more multi-bit digital signal can be provided.

[0037] This embodiment can be appropriately combined with other embodiments shown in this specification and the like. .

[0038] (Embodiment 2) The DAC100 according to one aspect of the present invention will be described with reference to the drawings.

[0039] <Configuration example of DAC100> Another configuration example of the DAC100 that converts an n (n is a natural number of 2 or more) -bit digital signal into an analog current signal is shown in FIGS. 2(A) to 2(C). Note that the same parts as FIGS. 1(A) to 1( C) show the same configuration and the description thereof is omitted.

[0040] In FIG. 2(A), the DAC100 has a circuit 110-k in which a variable resistance element 202-k (k is a natural number from 1 to n) and a switch 101-k are electrically connected in series. Note that the variable resistance element 202-k is not shown in FIG. 2(A).

[0041] The magnitude of the current flowing through the variable resistance element 202-k can be set to be a weighted current value according to the corresponding bit of the digital signal.

[0042] FIG. 2(B) shows the current mirror circuit 130 in FIG. 2(A) with a plurality of transistors This is an example of a configuration using the above. Note that the current mirror circuit 130 in Figure 2(B) is actually Refer to the explanation in Figure 1(B) of the implementation form 1.

[0043] Figure 2(C) shows a different configuration example of the current mirror circuit 130 from that shown in Figure 2(B). Regarding the current mirror circuit 130 in Figure 2(C), see the explanation of Figure 1(C) in Embodiment 1. To drink.

[0044] The variable resistor element 202-k is a device (ferroelectric element) that uses a ferroelectric material. One example is the use of an FTJ (ferroelectric tunnel junction) element. This can be done. Another example is using a ferroelectric material as the gate insulating layer of a transistor. FeFET elements can be used.

[0045] Materials that can possess ferroelectric properties include hafnium oxide, zirconium oxide, and zirconium oxide. Um hafnium (HfZrO) X (X is a real number greater than 0) is sometimes written as such. ), hafnium oxide with element J1 (where element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum Materials to which elements such as ions (La), strontium (Sr), etc. are added, zirconium oxide J2 (where J2 refers to the elements hafnium (Hf), silicon (Si), and aluminum (A) l), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium Examples include materials to which (Sr, etc.) is added. Also, materials that may have ferroelectric properties. And lead titanate (PbTiO X (It may be written as follows), barium titanate strontium Um (BST), strontium titanate, lead zirconate titanate (PZT), tantalum Strontium bismuth acid (SBT), bismuth ferrite (BFO), vari-titanium titanate Piezoelectric ceramics having a perovskite structure, such as um, may also be used. Materials that may possess electrical properties include, for example, multiple materials selected from the materials listed above. A mixture or compound can be used. By the way, hafnium oxide, zirconium oxide Materials containing nium, zirconium oxide hafnium, and hafnium oxide with element J1 added. The crystal structure (properties) of these materials can change not only depending on the film deposition conditions but also on various processes. Therefore, in this specification, we do not refer only to materials that exhibit ferroelectricity as ferroelectrics, but rather to materials that exhibit ferroelectricity as ferroelectrics. These are called materials that can possess electrical properties.

[0046] Among them, materials that can possess ferroelectric properties include hafnium oxide, or hafnium oxide and Materials containing zirconium oxide can retain ferroelectric properties even when processed into thin films of a few nanometers. This is preferable because it allows for this. Furthermore, in this specification, materials that may have ferroelectric properties are referred to as When referring to a layered structure, it is sometimes called a ferroelectric layer or a metal oxide film.

[0047] Furthermore, when using hafnium zirconium oxide as a material that can possess ferroelectric properties, atoms Atomic Layer Deposition (ALD) method, especially thermal ALD It is preferable to deposit the film using the method. Furthermore, it is preferable to use the thermal ALD method to deposit a material that can have ferroelectric properties. When forming a film with this material, hydrocarbons (also known as HC) are used as precursors. It is preferable to use a material that does not contain (u). A material that can have ferroelectric properties contains hydrogen and carbon. If either or both of the elements are present, it inhibits the crystallization of materials that may have ferroelectric properties. This can occur. Therefore, as mentioned above, by using a hydrocarbon-free precursor... , reducing the concentration of either or both hydrogen and carbon in a material that may have ferroelectric properties. It is preferable to do so. For example, a hydrocarbon-free precursor is a chlorine-based material. It can be made. Furthermore, as materials that can have ferroelectric properties, hafnium oxide and zirconium oxide When using a material containing 'm' (hafnium zirconium oxide), the precursor is H fCl4 and / or ZrCl4 can be used.

[0048] Furthermore, when forming a film using a material that may have ferroelectric properties, impurities in the film, in this case water, may be a concern. By thoroughly eliminating elements, hydrocarbons, and at least one of carbon, high-purity, genuine strength is achieved. A dielectric film can be formed. Furthermore, a film with high purity and intrinsic ferroelectric properties, The high-purity intrinsic oxide semiconductors shown in the embodiments described later have very high consistency in their manufacturing processes. It is highly efficient. Therefore, it is possible to provide a method for manufacturing semiconductor devices with high productivity.

[0049] Furthermore, when using hafnium zirconium oxide as a material that can possess ferroelectric properties, heat A Using the LD method, hafnium oxide and zirconium oxide are alternately mixed to achieve a 1:1 composition. Deposition of a film is preferable.

[0050] Furthermore, when depositing a ferroelectric material using the thermal ALD method, the oxidizing agent is H2O. Alternatively, O3 can be used. However, as an oxidizing agent in the thermal ALD method, it is not limited to this. It cannot be done. For example, as an oxidizing agent in the thermal ALD method, O2, O3, N2O, NO2, H2O, It may include one or more of the following selected from H2O2.

[0051] Furthermore, the crystal structure of a material that may possess ferroelectric properties is not particularly limited. For example, The possible crystal structures of the material include cubic, tetragonal, orthorhombic, and monoclinic systems. You may choose one or more of the following. In particular, as materials that may possess ferroelectric properties, A crystal structure with orthorhombic properties is preferable because it exhibits ferroelectricity. Alternatively, ferroelectricity The material may have a composite structure that includes both an amorphous structure and a crystalline structure.

[0052] This embodiment can be appropriately combined with other embodiments shown in this specification and elsewhere. .

[0053] (Embodiment 3) One aspect of the present invention relates to a semiconductor device, for example, an artificial neural network computing circuit. It can be used for this purpose.

[0054] The calculation circuit 350 shown in Figure 3 includes, as an example, an array unit ALP, a circuit ILD, and a circuit W LD, circuit XLD, circuit AFP, and circuit TW[1] to circuit TW[n] (where n is n). (where is an integer greater than or equal to 1) and has

[0055] Circuit ILD and circuit AFP are connected via circuit TW[1] to circuit TW[n], wiring OL[ Electrically connected to wiring OL[n] and wiring OLB[1] to wiring OLB[n]. It will be done.

[0056] Circuits TW[1] through TW[n] function as switching circuits. In each of the circuits TW[n], wiring OL[1] to wiring OL[n] and wiring OLB[ 1] When the output signal of wiring OLB[n] is input to circuit AFP, and the output of circuit ILD The signal is sent to wiring OL[1] through wiring OL[n] and wiring OLB[1] through wiring OLB[n]. You can switch between inputting text and other modes.

[0057] Circuit WLD consists of wiring WL[1] to wiring WL[m] (where m is an integer of 1 or more) and It is electrically connected to wire WX1L[1] or wiring WX1L[m]. Circuit XLD is connected to wiring W It is electrically connected to X1L[1] or wiring WX1L[m].

[0058] The arithmetic circuit 350 shown in Figure 3 has an array section ALP arranged in a matrix of m × n units. It has a circuit MP. Note that in Figure 3, row i, column j (where i is an integer between 1 and m). There exists such that j is an integer between 1 and n (inclusive). The circuit MP located at ( ) is called circuit MP[i,j] This is how it is written. However, in Figure 3, circuit MP[1,1], circuit MP[1,m], circuit MP Only [i,j], circuit MP[n,1], and circuit MP[n,m] are shown in the diagram; all other circuits are shown. The diagram for route MP has been omitted.

[0059] Circuit MP[i,j] is connected to wiring WL[i], wiring WXL1[i], and wiring OL[j]. It is electrically connected to the wiring OLB[j].

[0060] Circuit MP[i,j] is, for example, a device that holds weight coefficients (also called the first data). It has the ability. The weight coefficient is sometimes also called the weight value. Specifically, the circuit MP[i,j] This is the storage of information according to the weight coefficients input from wiring OL[j] and wiring OLB[j]. To carry out.

[0061] Circuit ILD consists of wiring OL[1] to wiring OL[n] and wiring OLB[1] to wiring OL The function has the capability to output information corresponding to the first data point, which is the weight coefficient, to B[n].

[0062] For example, information corresponding to the weighting coefficient can be electric potential, resistance, or current. Yes, it is possible. When using current values ​​as information corresponding to weight coefficients, Embodiment 1 and the implementation The input current can be generated using the DAC configuration described in Form 2. In other words, As the ILD circuit, a DAC with the configuration described in Embodiment 1 and Embodiment 2 is used. It is possible.

[0063] Furthermore, circuit MP[i,j] receives input values ​​(second data) from wiring WX1L[i]. It also has the function of outputting the product of ( ) and the weight coefficient (first data). Then, when the second data is input from WX1L[i], the circuit MP[i,j] receives the first data. Output a current corresponding to the product of the first data and the second data to wiring OL[j] and wiring OLB[j]. In addition, Figure 3 shows the case where wiring OL[j] and wiring OLB[j] are arranged. Although examples have been given, the present invention is not limited thereto. Wiring OL[j] and Wiring OL Only one of B[j] may be present.

[0064] Circuit XLD inputs the second data value to wiring WXLS[1] through wiring WXLS[m]. It has the function of supplying.

[0065] The information corresponding to the input value can be, for example, electric potential, current value, etc. When current values ​​are used as the corresponding information, the configuration described in Embodiment 1 and Embodiment 2 The input current can be generated using the DAC. In other words, as a circuit XLD, The DAC configuration described in Embodiment 1 and Embodiment 2 can be used.

[0066] The first data and the second data output from circuit MP[1,j] to circuit MP[m,j] The currents corresponding to the product of these two values ​​are added together and output to wiring OL[j] and wiring OLB[j]. In this way, the arithmetic circuit can perform a sum-of-products operation on the weight coefficients and the input values.

[0067] Furthermore, circuits XLD and WLD receive information corresponding to the first data input from circuit ILD. It has a function to select the circuit MP to which the information will be written. For example, row i of the array unit ALP. When writing information to circuits MP[i,1] through MP[i,n] located at the eye, Circuit XLD is, for example, a write included in circuits MP[i,1] through MP[i,n]. Wire the WXLS[i] to control the ON or OFF state of the switching element 1. This supplies power to the circuit MP other than the i-th row, turning off the writing switching element 1 included in the circuit MP. The potential is supplied to the wiring WXLS. Also, circuit WLD is, for example, circuit MP[i,1] Alternatively, the writing switching element 2 included in circuit MP[i,n] can be turned ON or OFF. A signal to set the state is supplied to the wiring WLS[i], and the code included in circuit MP other than the i-th row A potential that turns off the input switching element 2 is supplied to the wiring WLS.

[0068] Circuit AFP has circuits ACTF[1] to ACTF[n]. Circuit ACTF[ j] is connected to wiring OL[j] via circuit TW[j] which has a switching function, and wiring OLB[ j] and are electrically connected to each of them. Circuit ACTF[j] is connected to wiring OL[j] and information corresponding to the result of the sum-of-products operation input from wiring OLB[j] (for example, potential, current value, etc.) to generate a signal according to the information, and output it as z1 (k) to z n (k) can be output . Circuit AFP compares the information (for example, potential, current value, etc.) corresponding to the result of the sum-of-products operation input from wiring OL[j] and wiring OLB[j], and generates a signal according to the comparison result , and output it as z1 to z (k) can be output n (k) .

[0069] <Circuit MP> A circuit configuration example applicable to circuit MP[i, j] is shown in FIG. 4. It has transistors M1 to M3 and capacitor C1. For example, a holding unit HC is constituted by transistor M2 and capacitor C1 .

[0070] In the circuit MP of FIG. 4, circuit MCr has a circuit configuration substantially the same as that of circuit MC . Therefore, in order to distinguish the circuit elements and the like of circuit MCr from those of circuit MC, the symbol is suffixed with "r".

[0071] Transistors M1 to M3 shown in FIG. 4 are, as an example, n-channel type transistors with a multi-gate structure having gates above and below the channel , and each of transistors M1 to M3 has a first gate and a second gate .

[0072] Further, the semiconductor device according to one aspect of the present invention depends on the connection configuration of the back gate of the transistor ​No. Transistors M1 to M3 shown in Figure 4 have a back gate. The back gate is shown in the diagram, but the connection configuration of the back gate is not shown in the diagram. The electrical connections of the back gate can be determined during the design phase. For example, the back gate can be used. In a transistor, in order to increase the on-current of that transistor, the gate and battery are used. The gate and the battery may be electrically connected. That is, for example, the gate and battery of transistor M2 may be connected. The back gate may be electrically connected. Also, for example, a transistor having a back gate In a transistor, in order to change the threshold voltage of that transistor, or the transistor To reduce the off-current of the zista, wiring is provided that is electrically connected to external circuits, etc. Alternatively, a potential may be applied to the back gate of the transistor by the external circuit. Oh, regarding this, the transistors are described not only in Figure 4 but also in other parts of the specification. The same applies to transistors shown in other drawings.

[0073] Furthermore, the semiconductor device according to one aspect of the present invention has a structure of transistors included in the semiconductor device. It does not depend on. It may also be a single-gate transistor. Also, some transistors The transistor has a back gate configuration, and some other transistors have a back gate. It is also acceptable to have a configuration that does not include this. Furthermore, this can be explained not only in the circuit diagram shown in Figure 4, but also in the documentation. Transistors described elsewhere in the manual, or transistors illustrated in other drawings The same applies to sta.

[0074] Furthermore, in this specification, transistors of various structures are used as transistors. This is possible. Therefore, there are no restrictions on the type of transistor used. An example of a transistor is... For example, transistors made of single-crystal silicon, or amorphous silicon, polycrystalline silicon N, microcrystals (also called nanocrystals or semi-amorphous silicon) Transistors having non-single-crystal semiconductor films, such as those represented by , can be used. Alternatively, thin-film transistors (TFTs) made by thinning these semiconductors can be used. It's coming. There are various advantages to using TFTs. For example, compared to single-crystal silicon... Because it can be manufactured at a low temperature, it is possible to reduce manufacturing costs or to increase the size of the manufacturing equipment. Cut.

[0075] For example, a transistor is a compound semiconductor (e.g., SiGe, GaAs, etc.). ), or oxide semiconductors (e.g., Zn-O, In-Ga-Zn-O, In-Zn-O, I n-Sn-O(ITO), Sn-O, Ti-O, Al-Zn-Sn-O(AZTO), I A transistor having elements such as n-Sn-Zn-O can be used. These compound semiconductors, or thin-film transistors made by thinning these oxide semiconductors, etc. These compound semiconductors or oxide semiconductors can be used as transistor channels. It can be used not only in the part but also in other applications. For example, these chemical Compound semiconductors or oxide semiconductors are used for wiring, resistive elements, pixel electrodes, or light-transmitting electrodes, etc. They can be used as such. It is possible to deposit or form them simultaneously with transistors. Therefore, costs can be reduced.

[0076] As an example of a transistor, a transistor formed using an inkjet method or printing method is... Rangistas and the like can be used. These allow for manufacturing at room temperature, manufacturing at low vacuum levels, and It can be manufactured on a large substrate. Therefore, it can be manufactured without using a mask (reticle). This makes it possible to easily change the layout of the transistors. Alternatively, since it is possible to manufacture without using resist, material costs are reduced, and the number of processes is also reduced. It can be reduced. Or, since it is possible to apply the film only to the necessary parts, after forming a film over the entire surface... This method is less wasteful and lower-cost than etching.

[0077] Examples of transistors include those made of organic semiconductors or carbon nanotubes. Transistors and the like can be used. This allows for the creation of transistors on a flexible substrate. A transistor can be formed. A transistor having an organic semiconductor or carbon nanotube. Devices using radiators can be made more resistant to impact.

[0078] In circuit MP of Figure 4, the first terminal of transistor M1 is electrically connected to wiring VE. The second terminal of transistor M1 is electrically connected to the first terminal of transistor M3. The gate of transistor M1 is connected to the first terminal of capacitor C1 and transistor M2. The first terminal is electrically connected to the wiring VE. The second terminal of capacitance C1 is electrically connected to the wiring VE. The connection continues. The second terminal of transistor M2 is electrically connected to wiring OL. The gate of transistor M2 is electrically connected to wiring WL. The terminal is electrically connected to wiring OL, and the gate of transistor M3 is electrically connected to wiring WX1L. They are directly connected.

[0079] In circuit MCr, a different connection configuration from circuit MC will be explained. Transistor M3 The second terminal of r is electrically connected to wiring OLB, not wiring OL. (Transistor) The first terminal of M1r and the first terminal of capacitance C1r are electrically connected to the wiring VEr. ru.

[0080] Furthermore, in the holding part HC shown in Figure 4, the gate of transistor M1 and the first capacitor C1 The point of electrical connection between the terminal and the first terminal of transistor M2 is defined as node n1.

[0081] The holding unit HC has the function of holding the potential according to the weighting coefficient (first data). Figure 4 The retention of the potential in the holding part HC included in the circuit MC is performed by transistor M2, and When inverter M3 is turned ON, a current of a predetermined value is input from wiring OL, and This can be done by writing to quantity C1 and then turning off transistor M2. This allows the potential of node n1 to be retained as a potential corresponding to the weight coefficient (first data). This can be done. At this time, current is input from wiring OL, and a large current corresponding to the magnitude of that current is generated. The potential of the size can be held in the capacitance C1. Therefore, in the input of the first data, This reduces the impact of variations in the current characteristics (threshold voltage, etc.) of transistor M1. ru.

[0082] The current input to the wiring OL is supplied to the DAC with the configuration described in Embodiment 1 or Embodiment 2. It can be generated using [this method].

[0083] Furthermore, transistor M1 maintains the potential of node n1 for a long time, resulting in low off-current. It is preferable to use a transistor with low off-current. For example, If so, an OS transistor can be used. Also, as transistor M1, backgear A transistor with a back gate is applied, and a low-level potential is applied to the back gate to obtain a threshold voltage. Alternatively, the setting may be shifted to the positive side to reduce the off-current.

[0084] This provides a highly reliable arithmetic circuit.

[0085] This embodiment can be freely combined with other embodiments.

[0086] (Embodiment 4) In this embodiment, a semiconductor device according to one aspect of the present invention is a circuit capable of performing multiply-accumulate operations. Let me give you an example.

[0087] Figure 5 shows the sum-of-products operation between a first data point (positive or "0") and a second data point (positive or "0"). This shows an example of the configuration of the arithmetic circuit that performs the following: Perform a sum-of-products operation on the first data corresponding to the potential and the input second data, and the product This is a circuit that performs activation function calculations using the result of a summation operation. Note that the first data and the second The data can be analog data or multi-valued data (discrete data), for example. It is possible.

[0088] This arithmetic circuit also functions as a memory for holding the first data, and is therefore called memory. It is also possible to do so. In particular, when using analog data as the first data, analog memory and You can call them.

[0089] The arithmetic circuit MAC1 consists of circuits WCS, XCS, WSD, and SWS1. Circuit SWS2, cell array CA, and conversion circuit ITRZ[1] to conversion circuit ITRZ[n ] and, have.

[0090] The cell array CA consists of cells IM[1,1] to IM[m,n] (where m is 1 or greater). It is an integer, and here n is an integer greater than or equal to 1. ) and cell IMref[1] It has up to cell IMref[m] and so on. Cells IM[1,1] to cell IM[m,n] Each has the function of holding a potential equivalent to the amount of current corresponding to the first data, and the cell IMr ef[1] or cell IMref[m] is necessary to perform sum-of-products operations with the held potential. A function that supplies a potential corresponding to the second data to signal line XCL[1] to signal line XCL[m]. It has.

[0091] Note that the cell array CA in Figure 5 has n+1 cells in the row direction and m cells in the column direction, and a matrix. Although they are arranged in a row, the cell array CA has two or more cells in the row direction and one or more cells in the column direction. Alternatively, the configuration may be arranged in a matrix.

[0092] Each of cells IM[1,1] through IM[m,n] is, for example, a transistor. It has F1, transistor F2, and capacitance C5, and cell IMref[1] to cell IM Each of ref[m] is, for example, transistor F1m and transistor F2m. It has a capacity of C5m and

[0093] In particular, the transients contained in each of cells IM[1,1] through IM[m,n] The size of the F1 (e.g., channel length, channel width, and transistor configuration) is relative to each other. It is preferable that it be equal to each of cells IM[1,1] to IM[m,n] It is preferable that the sizes of the transistors F2 included in cell I are equal. Transistor F1m contained in each of Mref[1] or cell IMref[m] The sizes of the cells are preferably equal, with cells IMref[1] to IMref[m It is preferable that the sizes of the transistors F2m included in each of the ] are equal. Furthermore, it is preferable that the sizes of transistor F1 and transistor F1m are equal. Preferably, the sizes of transistors F2 and F2m are equal.

[0094] Note that transistors F1 and F1m are in the ON state unless otherwise specified. In this case, it is assumed that the operation ultimately takes place in the linear domain. That is, each of the above The gate voltage, source voltage, and drain voltage of this transistor operate in the linear region. This includes cases where the voltage is appropriately biased within the range. However, one aspect of the present invention The term is not limited to this. For example, transistors F1 and F1m are ON state In this state, it may operate in the saturation region, and it may also operate in the linear region or in the saturation region. It is acceptable to have a mix of cases where this is the case and cases where it is not.

[0095] Also, unless otherwise specified, transistors F2 and F2m are subthreads. When operating in the low-pressure region (i.e., transistor F2 or transistor F2m) And, if the gate-source voltage is lower than the threshold voltage, more preferably, drain This includes the case where the current increases exponentially with respect to the gate-source voltage. That is, the gate voltage, source voltage, and drain voltage of each of the transistors mentioned above. This is when the voltage is properly biased to operate in the subthreshold region. It shall be included. Therefore, transistors F2 and F2m are source-drain. This includes cases where it operates so that an off-current flows between the inputs.

[0096] Furthermore, transistor F1 and / or transistor F1m are, for example, OS transistors. It is preferable that it be a transistor. In addition, transistor F1, and / or transistor F1 The channel-forming region of m is indium, element M (for example, aluminum). Gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel Germanium, Zirconium, Molybdenum, Lanthanum, Cerium, Neodymium, Hafnium One or more elements selected from um, tantalum, tungsten, or magnesium. Examples include, but it is more preferable that the oxide contains at least one zinc.

[0097] OS transistors are used as transistor F1 and / or transistor F1m. This suppresses the leakage current of transistor F1 and / or transistor F1m. This allows for a reduction in the power consumption of the arithmetic circuit. Specifically, the transistor Write from the holding node when transistor F1 and / or transistor F1m are in a non-conductive state. Because the leakage current to the word line can be made very small, the potential lift of the holding node Because the resh operation can be reduced, the power consumption of the multiply-accumulate circuit can be reduced. Yes, it is possible. Furthermore, the leakage current from the holding node to the write word line can be made very small. This allows the cell to maintain the potential of the holding node for a long time, thereby increasing the calculation accuracy of the arithmetic circuit. It can be done.

[0098] Furthermore, for transistor F2 and / or transistor F2m, OS transistors By using this, it is possible to operate in a wide current range in the subthreshold region. Therefore, current consumption can be reduced. Also, transistor F2, and / or transistor For transistor F2m, by using an OS transistor, transistor F1, Since it can be manufactured simultaneously with the ZISTA F1m, the manufacturing process for the multiply-accumulate circuit is shortened. In some cases, this is possible. Also, transistor F2 and / or transistor F2m are O Besides S-transistors, transistors containing silicon in the channel formation region (hereinafter, This can be called a Si transistor. For example, amorphous silicon Silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon Recon, single-crystal silicon, etc., can be used.

[0099] By the way, when semiconductor devices are highly integrated into chips, the chip contains circuits. Heat may be generated during operation. This heat can cause the transistor temperature to rise. As a result, the characteristics of the transistor change, leading to a change in field-effect mobility or a decrease in operating frequency. This can happen. OS transistors have higher thermal tolerance than Si transistors, The field effect mobility is less susceptible to changes due to temperature fluctuations, and the operating frequency is less likely to decrease. Furthermore, even at high temperatures, the drain current of the OS transistor remains constant between the gate and source. It is easy to maintain the characteristic of exponentially increasing with pressure. Therefore, OS transistors are used. This makes it easier to perform the sum-of-products calculation described later, even in high-temperature environments. When constructing a semiconductor device that is resistant to heat generated by motion, the transistor used is an OS transistor. It is preferable to apply the ta.

[0100] In each of cells IM[1,1] through IM[m,n], the transistor F1 The first terminal is electrically connected to the gate of transistor F2. The first terminal is electrically connected to wiring VE. The first terminal of capacitance C5 is connected to the transistor. It is electrically connected to the F2 gate.

[0101] Furthermore, in each of cells IMref[1] through IMref[m], The first terminal of transistor F1m is electrically connected to the gate of transistor F2m. The first terminal of transistor F2m is electrically connected to wiring VE. The first terminal of capacitor C5m The child is electrically connected to the gate of transistor F2m.

[0102] Furthermore, the semiconductor device according to one aspect of the present invention has polarity of the transistors included in the semiconductor device. It does not depend on. For example, transistors F1 and F2 shown in Figure 5 are n Although it is described as a channel-type transistor, some or all of the transistors are p-channel type transistors. It can also be replaced with a lunger.

[0103] The above examples of changes to the structure and polarity of transistors are shown for transistor F1 and This is not limited to transistor F2. For example, transistor F1m, transistor F2m , transistors F3[1] to F3[n] and F4[1] described later ] or transistor F4[n], and furthermore, transistors described elsewhere in the specification The same applies to transistors shown in other drawings.

[0104] Wiring VE is for cell IM[1,1], cell IM[m,1], cell IM[1,n], and Current is passed between the first and second terminals of each transistor F2 of IM[m,n]. The wiring is for cell IMref[1] and cell IMref[m] respectively. It functions as wiring to allow current to flow between the first and second terminals of transistor F2. For example, wiring VE functions as wiring that supplies a constant voltage. This constant voltage is: For example, this could be a low-level potential or ground potential.

[0105] In cell IM[1,1], the second terminal of transistor F1 is connected to wiring WCL[1]. The gate of transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of transistor F2 is electrically connected to wiring WCL[1] and capacitance C5. The second terminal is electrically connected to wiring XCL[1]. Note that in Figure 5, cell IM In [1,1], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of quantity C5 and the node NN[1,1] is defined as node NN[1,1].

[0106] In cell IM[m,1], the second terminal of transistor F1 is connected to wiring WCL[1]. The gate of transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of transistor F2 is electrically connected to wiring WCL[1] and capacitance C5. The second terminal is electrically connected to the wiring XCL[m]. Note that in Figure 5, cell IM At [m,1], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of quantity C5 and the node NN[m,1] is defined as node NN[m,1].

[0107] In cell IM[1,n], the second terminal of transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to the wiring WSL[1]. The second terminal of transistor F2 is electrically connected to the wiring WCL[n] and capacitance C5. The second terminal is electrically connected to wiring XCL[1]. Note that in Figure 5, cell IM At [1,n], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of quantity C5 and the node NN[1,n] is defined as node NN[1,n].

[0108] In cell IM[m,n], the second terminal of transistor F1 is connected to the wiring WCL[n]. The gate of transistor F1 is electrically connected to the wiring WSL[m]. The second terminal of transistor F2 is electrically connected to the wiring WCL[n] and capacitance C5. The second terminal is electrically connected to the wiring XCL[m]. Note that in Figure 5, cell IM In [m,n], the first terminal of transistor F1 and the gate of transistor F2, The connection point between the first terminal of quantity C5 and the other terminal is defined as node NN[m,n].

[0109] In cell IMref[1], the second terminal of transistor F1m is connected to wiring XCL[1] The gate of transistor F1m is electrically connected to wiring WSL[1]. The second terminal of transistor F2m is electrically connected to wiring XCL[1], The second terminal of capacitor C5 is electrically connected to wiring XCL[1]. Note that in Figure 5, In cell IMref[1], the first terminal of transistor F1m and transistor F2m The connection point between the gate of and the first terminal of capacitor C5 is designated as node NNref[1].

[0110] In cell IMref[m], the second terminal of transistor F1m is connected to wiring XCL[m]. The gate of transistor F1m is electrically connected to wiring WSL[m]. The second terminal of transistor F2m is electrically connected to the wiring XCL[m]. The second terminal of capacitor C5 is electrically connected to wiring XCL[m]. Note that in Figure 5, In cell IMref[m], the first terminal of transistor F1m and transistor F2m The connection point between the gate of and the first terminal of capacitor C5 is defined as node NNref[m].

[0111] The above node NN[1,1], node NN[m,1], node NN[1,n], no Node NN[m,n], node NNref[1], and node NMref[m] are, respectively It functions as a holding node for the cell.

[0112] In cells IM[1,1] to IM[m,n], for example, transistor F1 is When in this state, transistor F2 has a diode connection configuration. The wiring VE is With the applied constant voltage as the ground potential (GND), transistor F1 is in the ON state, and wiring W When a current of amount I flows from CL to the second terminal of transistor F2, The potential of the gate (node ​​NN) is determined by the current I. The potential of terminal 2 is, ideally, because transistor F1 is in the ON state, This is equivalent to gate 2 (node ​​NN). Here, we turn off transistor F1. This maintains the potential of the gate (node ​​NN) of transistor F2. The transistor F2 is connected to the ground potential of the first terminal of transistor F2, and the The current I, which corresponds to the potential of the gate (node ​​NN), is supplied to the source-drain of transistor F2. It can flow between inputs. In this specification, such operation is referred to as "transistor F2 is..." The amount of current flowing between the source and drain of transistor F2 is programmed to be I. It is referred to as "do".

[0113] Circuit SWS1, as an example, uses transistors F3[1] to F3[n] It has. The first terminal of transistor F3[1] is electrically connected to wiring WCL[1], The second terminal of transistor F3[1] is electrically connected to the circuit WCS, and transistor F The gate of transistor 3[1] is electrically connected to wiring SWL1. Transistor F3[n] The first terminal is electrically connected to the wiring WCL[n], and the second terminal of transistor F3[n] The child is electrically connected to the circuit WCS, and the gate of transistor F3[n] is connected to the wiring SWL. It is electrically connected to 1.

[0114] Transistors F3[1] to F3[n] are, for example, transistor F1, And / or preferably an OS transistor applicable to transistor F2.

[0115] Circuit SWS1 is connected to circuit WCS and each of the wirings WCL[1] through WCL[n]. It functions as a circuit that makes the space between them either conductive or non-conductive.

[0116] Circuit SWS2, as an example, uses transistors F4[1] to F4[n] It has. The first terminal of transistor F4[1] is electrically connected to wiring WCL[1], The second terminal of transistor F4[1] is electrically connected to the input terminal of the conversion circuit ITRZ[1]. The gate of transistor F4[1] is electrically connected to wiring SWL2. The first terminal of transistor F4[n] is electrically connected to the wiring WCL[n], and the transistor The second terminal of sta F4[n] is electrically connected to the input terminal of the conversion circuit ITRZ[n], The gate of transistor F4[n] is electrically connected to wiring SWL2.

[0117] Transistors F4[1] to F4[n] are, for example, transistor F1, And / or preferably an OS transistor applicable to transistor F2.

[0118] Circuit SWS2 is connected between wiring WCL[1] and conversion circuit ITRZ[1], and wiring WCL The circuit is designed to either conduct or not conduct between [n] and the conversion circuit ITRZ[n]. To be able to.

[0119] The WCS circuit supplies data to be stored in each cell of the CA cell array. It has the function of doing so.

[0120] Circuit XCS is electrically connected to wiring XCL[1] through wiring XCL[m]. The path XCS is a cell IMref[1] to cell IMref[m] of the cell array CA. Each of these functions provides a current that corresponds to either the reference data or the second data. To possess.

[0121] Circuit WSD is electrically connected to wiring WSL[1] through wiring WSL[m]. When the WSD writes the first data to cell IM[1,1] or cell IM[m,n], By supplying a predetermined signal to wiring WSL[1] to wiring WSL[m], the first day It has the function to select the row of the cell array CA to which the data will be written.

[0122] Furthermore, circuit WSD is electrically connected, for example, to wiring SWL1 and wiring SWL2. Circuit WSD is configured to supply a predetermined signal to wiring SWL1, thereby enabling circuit W The function of making the connection between CS and cell array CA conductive or non-conductive, and the wiring SWL2 By supplying a constant signal, the conversion circuit ITRZ[1] to the conversion circuit ITRZ[m] It has the function of making the connection between the cell array CA conductive or non-conductive.

[0123] Each of the conversion circuits ITRZ[1] to ITRZ[m] is, for example, an input It has terminals and output terminals. For example, the output terminal of the conversion circuit ITRZ[1] is wired O Electrically connected to L[1], the output terminal of the conversion circuit ITRZ[n] is connected to wiring OL[n]. They are electrically connected.

[0124] Each of the conversion circuits ITRZ[1] to ITRZ[m] is input to the input terminal. It has the function of converting the current into a voltage corresponding to the current and outputting it from the output terminal. This can be, for example, analog voltage, digital voltage, etc. Also, the conversion circuit IT Each of RZ[1] or the conversion circuit ITRZ[m] may have a function-based arithmetic circuit. In this case, for example, the converted voltage is used to perform the function calculation by the calculation circuit. The result of the calculation may be output to wiring OL[1] through wiring OL[n].

[0125] In particular, when performing operations of a hierarchical artificial neural network, as the above-described function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold value function, etc. can be used.

[0126] As the circuit WCS described in FIG. 5, the DAC described in Embodiment 1 or Embodiment 2 can be used. Also, as the XCS described in FIG. 5, the DAC described in Embodiment 1 or Embodiment 2 can be used.

[0127] This embodiment can be appropriately combined with other embodiments shown in this specification and the like. .

[0128] (Embodiment 5) In this embodiment, an example of an electronic device having a semiconductor device according to an aspect of the present invention will be described.

[0129] In various electronic devices, for example, DA conversion for converting various digital information such as acoustic information, imaging information, illuminance information, temperature information, etc. into analog information may be performed. By using the semiconductor device according to an aspect of the present invention in an electronic device, DA conversion with suppressed increase in power consumption can be performed. That is, by using the semiconductor device according to an aspect of the present invention in an electronic device, power consumption can be reduced. Also, by using the semiconductor device according to an aspect of the present invention, DA conversion with high accuracy can be realized. Also, by using the semiconductor device according to an aspect of the present invention, high-speed DA conversion can be realized.

[0130] This embodiment can be appropriately combined with other embodiments shown in this specification and the like. .

Example

[0131] We will actually prototype the arithmetic circuit equipped with the DAC described in this specification and the operation of the DAC. Verification was performed. In this example, we will explain the DAC that was actually prototyped and the results of the operational verification. I will reveal it.

[0132] Figure 6 is a top view photograph of the die (chip) containing the actual fabricated arithmetic circuit. One side of it is 4 mm. The die shown in Figure 6 is made of silicon and has SiT on a semiconductor substrate. The configuration consists of a transistor formed, with an OS transistor formed above it. In terms of the semiconductor substrate, the following circuit is formed by the process of Si transistors. WD, circuit XD, circuit RD, and circuit GD are formed by the OS transistor process This forms the MCA circuit, which will be described later.

[0133] Circuit WD corresponds to circuit WCS described in Embodiment 4, and circuit XD corresponds to circuit WCS described in Embodiment 4. Circuit XCS described above corresponds to circuit GD, and circuit WSD described in Embodiment 4 corresponds to circuit GD. Furthermore, circuit RD is the conversion circuit ITRZ[1] to conversion circuit ITRZ described in Embodiment 4. This corresponds to [n]. Furthermore, the circuit MCA corresponds to the cell array CA described in Embodiment 4. do.

[0134] In particular, the DAC is included in both circuit WD and circuit XD.

[0135] Furthermore, the circuit configuration of the DAC included in the actual prototype calculation circuit is as shown in Figure 7. The DAC shown in Figure 7 takes into consideration the configuration in Figure 1(B), and in Figure 1(B) The configuration is such that n is 8. Also, transistor 102-k is 2 k-1 The same It has a configuration in which transistors of a certain size are electrically connected in parallel. The STA102-2 has a configuration in which two transistors are electrically connected in parallel. Transistor 102-8 has a configuration in which 128 transistors are electrically connected in parallel. It is configured as follows. Note that transistor 102-1 is a configuration containing one transistor. This configuration consists of two or more transistors electrically connected in parallel. do not have.

[0136] Here, a digital signal from 0 to 255 is input to wiring wd[1] through wiring wd[8]. Therefore, the output current Iout obtained from the current mirror circuit 130 was measured.

[0137] Figure 8 shows the input / output characteristics of the DAC installed in the actual fabricated arithmetic circuit. The input / output characteristics in Figure 8 show the digital input value (IN(digital)) on the horizontal axis. The vertical axis shows the output current Iout [nA]. As shown in Figure 8, the wiring wd[1 By inputting a digital signal of 0 to 255 to the wiring wd[8], the output current Iou The result was that t increased in proportion to the value of the digital signal. It was confirmed that the DAC included in the arithmetic circuit was functioning correctly. [Explanation of Symbols]

[0138] 100: DAC, 101-k: Switch, 102-k: Transistor, 110-k: Circuit , 110-n: circuit, 110-1: circuit, 120: circuit, 130: current mirror circuit, 202-k: Variable resistor element, 350: Arithmetic circuit

Claims

1. A semiconductor device having a first digital-to-analog conversion circuit and a second digital-to-analog conversion circuit, The first digital-to-analog conversion circuit has a first ferroelectric element that functions as a variable resistor element, The second digital-to-analog conversion circuit has a second ferroelectric element that functions as a variable resistor element, The first digital-to-analog conversion circuit has the function of generating a first analog current signal corresponding to the first data, The second digital-to-analog conversion circuit has the function of generating a second analog current signal corresponding to the second data, A semiconductor device having the function of performing a calculation of the product of the first current signal and the second current signal.

2. A semiconductor device having a first digital-to-analog conversion circuit and a second digital-to-analog conversion circuit, The first digital-to-analog conversion circuit has a first ferroelectric element that functions as a variable resistor element, The second digital-to-analog conversion circuit has a second ferroelectric element that functions as a variable resistor element, The first digital-to-analog conversion circuit has the function of generating a first analog current signal corresponding to a weighting coefficient. The second digital-to-analog conversion circuit has the function of generating a second analog current signal corresponding to the input value. A semiconductor device having the function of performing a calculation of the product of the first current signal and the second current signal.

3. In claim 1 or claim 2, A semiconductor device wherein each of the first ferroelectric element and the second ferroelectric element has a ferroelectric tunnel junction.

4. In any one of claims 1 to 3, A semiconductor device wherein each of the first ferroelectric element and the second ferroelectric element has an oxide containing either hafnium or zirconium, or both, as a ferroelectric material.

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