Semiconductor equipment

Abstract

To manufacture a semiconductor device which uses a thin film transistor having favorable electrical characteristics and high reliability as a switching element and has a pixel part and a drive circuit part capable of high-speed operation on the same substrate to achieve high display quality and high reliability.SOLUTION: In a semiconductor device, in a drive circuit part and a pixel part two types of thin film transistors each using an oxide semiconductor layer having a crystalline region on one surface as an active layer are formed, and by selecting a region where a channel is formed by arrangement of a gate electrode layer, electric characteristics of the thin film transistor is selected thereby to allow the semiconductor device having the pixel part and the drive circuit part capable of a high-speed operation on the same substrate to be manufactured.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to semiconductor devices and methods for manufacturing them.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This refers to all aspects, including electro-optical devices such as liquid crystal displays and light-emitting devices, semiconductor circuits, and electronic equipment. It is a semiconductor device. [Background technology]

[0003] In recent years, a technique has emerged to construct transistors using semiconductor films formed on substrates with insulating surfaces. The technology is attracting attention. Transistors are widely used in electronic devices such as ICs and electro-optical devices. It is used in various applications, and its development is being accelerated, particularly as a switching element in image display devices.

[0004] Metal oxides are one example of materials that exhibit semiconductor properties. Examples of monoxides include tungsten oxide, tin oxide, indium oxide, and zinc oxide. There are transistors that use metal oxides exhibiting such semiconductor properties as channel formation regions. This is already known (Patent Documents 1 and 2).

[0005] Furthermore, transistors using oxide semiconductors have high field-effect mobility. Transistors can also be used to construct drive circuits for display devices and other devices. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055

Summary of the Invention

Problems to be Solved by the Invention

[0007] When forming a plurality of different circuits on an insulating surface, for example, when forming a pixel portion and a driving circuit on the same substrate the transistors used in the pixel portion are required to have excellent switching characteristics, for example a large on-off ratio, and the transistors used in the driving circuit are required to have a high operating speed In particular, the higher the definition of the display unit, the shorter the writing time of the display image. Therefore, it is preferable that the transistors used in the driving circuit have a high operating speed. Also the display quality can be improved by improving the aperture ratio, which is contrary to high definition. One aspect of the present invention is to use a transistor with good electrical characteristics and high reliability as a switching element

[0008] and to produce a semiconductor device having a pixel portion and a driving circuit portion capable of high-speed operation on the same substrate, with high display quality and reliability.

Means for Solving the Problems

[0009] One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof, in which a driving circuit portion including a transistor and a pixel portion including a transistor are formed on the same substrate. Two types of transistors are formed using an oxide semiconductor layer having a crystal region on one surface (surface layer portion), and a semiconductor device that selects a region where a channel is formed by the arrangement of the gate electrode layer. More specifically, for example it can have the following configuration.

[0010] A semiconductor device according to one aspect of the present invention has a pixel portion having a first transistor and a second transistor on the same substrate The device has a drive circuit section having two transistors, and the first transistor is located on the substrate. A gate electrode layer and a first insulating layer that functions as a gate insulating layer on the first gate electrode layer A first oxide semiconductor layer having a crystalline region made of nanocrystals in its surface layer is placed on the first insulating layer. , a first source electrode layer and a first drain electrode layer that overlap with a portion of the first oxide semiconductor layer The second transistor has a second insulating layer that is in contact with a part of the first oxide semiconductor layer, and the second transistor is The substrate has a first insulating layer, and the first insulating layer has a crystalline region made of nanocrystals in the surface layer. A second oxide semiconductor layer and a second source electrode layer that overlaps with a portion of the second oxide semiconductor layer. And in contact with the second drain electrode layer and a part of the second oxide semiconductor layer, as a gate insulating layer It has a functional second insulating layer and a second gate electrode layer on the second insulating layer.

[0011] Furthermore, in the semiconductor device described above, the crystalline region is the first oxide semiconductor layer or the second oxide Nanocrystals are formed on the surface of each semiconductor layer, with the c-axis oriented perpendicular to it. .

[0012] Furthermore, in the semiconductor device described above, between the second oxide semiconductor layer and the second source electrode layer, And between the second oxide semiconductor layer and the second drain electrode layer, there is an oxide conductive layer. It's okay to do so.

[0013] Furthermore, in the above semiconductor device, the second transistor is a shift register in the drive circuit section. It is preferable to use it for this purpose.

[0014] The oxide semiconductor layer is an In-Sn-Ga-Zn-O system, which is a quaternary metal oxide. or ternary metal oxides such as In-Ga-Zn-O system, In-Sn-Zn-O system, In- Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z nO-based systems, as well as binary metal oxides such as In-Zn-O, Sn-Zn-O, and Al-Zn -O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn Oxide semiconductor layers such as -O-based and Zn-O-based can be used. The body layer may contain SiO2.

[0015] Furthermore, the oxide semiconductor layer is InMO3(ZnO) m We use thin films denoted as (m>0). This is possible. Here, M is one or more selected from Ga, Al, Mn, and Co. This indicates a metallic element. For example, M could be Ga, Ga and Al, Ga and Mn, or Ga and Examples include Co., InMO3(ZnO). m Oxide semiconductors with a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are subjected to the above-mentioned In-Ga-Zn-O system oxide This material is called a semiconductor, and its thin film is also called an In-Ga-Zn-O film.

[0016] Furthermore, the oxide semiconductor layer undergoes high-temperature, short-time depolymerization using methods such as RTA (Rapid Thermal Annealing). Water or dehydrogenated water is used. This heating process removes the surface layer of the oxide semiconductor layer. The part has a crystalline region composed of a group of microcrystals made of nanocrystals, and the other part This can be amorphous, a mixture of amorphous and microcrystalline materials with microcrystals scattered within amorphous regions, or entirely composed of microcrystalline materials. They form crystal clusters.

[0017] Furthermore, using a transistor according to one aspect of the present invention, the drive circuit and the pixel are mounted on the same substrate. A semiconductor device is fabricated using an EL element, liquid crystal element, or electrophoretic element, etc., on top of the formed surface. It is possible.

[0018] In this specification, the term "gate electrode layer" refers to the gate electrode as well as a part of the gate wiring or It includes everything. Gate wiring refers to the gate electrode of at least one transistor and another electrode. This refers to wiring used to electrically connect to other wiring, for example, the wiring in a display device. Examination lines are also included in gate wiring.

[0019] Furthermore, the source electrode layer includes the source electrode as well as part or all of the source wiring. Wiring refers to the electrical connection between at least one transistor's source electrode and another electrode or another wire. This refers to wiring used to make connections, for example, the signal lines in a display device connecting to the source electrode. When electrically connected, the source wiring also includes signal lines.

[0020] Furthermore, the drain electrode layer includes not only the drain electrode but also part or all of the drain wiring. Drain wiring refers to the connection between the drain electrode of at least one transistor and another electrode or another wiring. This refers to wiring used to electrically connect wires, for example, the signal lines in a display device. When electrically connected to the drain electrode, the drain wiring also includes the signal line.

[0021] Furthermore, in this specification, claims, or drawings, the source and drain of the transistor are described. The inputs can be swapped depending on the transistor's structure and operating conditions, so which one is the input? It is difficult to specify whether it is a drain or a pipe. Therefore, in this specification, claims In the scope or drawings, either source or drain can be arbitrarily selected. One terminal is referred to as one of the source and drain terminals, and the other terminal is referred to as the other of the source and drain terminals. do.

[0022] In this specification, "light-emitting device" refers to an image display device, a light-emitting device, or a light source. This refers to the light source (including the lighting device). It also refers to the connector on the light-emitting device, such as an FPC (Flexible Printed Circuit). (printed circuit) or TAB (Tape Automate d Bonding) Tape or TCP (Tape Carrier Packaging) e) A module to which a TAB tape or TCP has been attached, with a printed circuit board at the end. A module or substrate on which light-emitting elements are formed is coated with COG (Chip On Glas s) All modules with ICs (integrated circuits) directly mounted using this method are also included as light-emitting devices. Let's assume that.

[0023] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything. [Effects of the Invention]

[0024] By implementing one aspect of the present invention, a drive circuit unit capable of high-speed operation is provided on the same substrate, and A semiconductor device having an element can be fabricated. [Brief explanation of the drawing]

[0025] [Figure 1] A cross-sectional process diagram showing one aspect of the present invention. [Figure 2] A cross-sectional process diagram showing one aspect of the present invention. [Figure 3] A circuit diagram showing the configuration of a shift register. [Figure 4] Circuit diagrams and timing charts illustrating the operation of a shift register. [Figure 5] A diagram illustrating the operation of a pulse output circuit. [Figure 6] A diagram illustrating the operation of a pulse output circuit. [Figure 7] A diagram illustrating the operation of a pulse output circuit. [Figure 8] A diagram illustrating the block diagram of a semiconductor device. [Figure 9] A diagram showing the configuration of a signal line drive circuit. [Figure 10] A cross-sectional view and a plan view illustrating one aspect of the present invention. [Figure 11] A cross-sectional view and a plan view illustrating one aspect of the present invention. [Figure 12] A cross-sectional view illustrating one aspect of the present invention. [Figure 13] A cross-sectional view illustrating one aspect of the present invention. [Figure 14] A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 15] A cross-sectional view illustrating one aspect of the present invention. [Figure 16] A cross-sectional view and a plan view illustrating one aspect of the present invention. [Figure 17] A diagram illustrating examples of how electronic paper can be used. [Figure 18] An external view showing an example of an e-book. [Figure 19] External view showing examples of television equipment and digital photo frames. [Figure 20] An external view showing an example of a gaming machine. [Figure 21] An external view showing an example of a mobile phone. [Figure 22] A longitudinal cross-sectional view of an inverse staggered transistor using an oxide semiconductor. [Figure 23] Figure 22 shows the energy band diagram (schematic diagram) between A and A'. (A) When the voltage between the source and drain is equipotential (VD=0), (B) When a positive potential (VD>0) is applied to the drain relative to the source. [Figure 24] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 25] The energy band diagram (schematic) between B and B' in Figure 22 when the gate voltage is 0V. [Figure 26] Energy band diagram (schematic) between B and B' in Figure 22. (A) When a positive potential (VG>0) is applied to the gate (GE1), (B) When a negative potential (VG<0) is applied to the gate (GE1). [Modes for carrying out the invention]

[0026] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. This does not mean that the same part or a similar function is depicted in the drawings in this specification. The same symbols are used to indicate parts that are not the same, and their explanations may be omitted.

[0027] (Embodiment 1) In this embodiment, a semiconductor device and a method for manufacturing a semiconductor device, which are one embodiment of the present invention, are shown in Figure 1. This will be explained using the following. Figure 1(E) shows two transistors with different structures fabricated on the same substrate. An example of the cross-sectional structure of transistors 440 and 450 is shown. Transistor 440 shown in Figure 1(E) is It is a type of bottom-gate structure called an inverse staggered type, and the transistor 450 is a top-gate type. It is a transistor with a T-structure.

[0028] The transistor 440 placed in the pixel has a gate electrode on a substrate 400 having an insulating surface. Layer 451, a first insulating layer 402 that functions as a gate insulating layer, and an acid containing a channel forming region. It includes a ionized semiconductor layer 404b, a source electrode layer 455c, and a drain electrode layer 455d. Furthermore, a second insulating layer 4 covers the transistor 440 and is in contact with a portion of the oxide semiconductor layer 404b. 28 is established.

[0029] Furthermore, the transistor 440 placed in the pixel uses a single-gate structure transistor. As explained above, if necessary, a multi-gate transistor or channel forming region A dual-gate structure can also be formed in which gate electrode layers are placed above and below the region with insulating films in between. can.

[0030] Above the oxide semiconductor layer 404b are the source electrode layer 455c and the drain electrode layer 455 Parts of d are formed by overlapping. Also, the oxide semiconductor layer 404b is the first It overlaps with the gate electrode layer 451 via the insulating layer 402. Transis placed in the pixel The channel formation region of TA440 is the source electrode layer 455c of the oxide semiconductor layer 404b. The region in contact with the first insulating layer 402 is sandwiched between the region in contact with the drain electrode layer 455d and the region in contact with the drain electrode layer 455d. This is a region that is in contact with and overlaps with the gate electrode layer 451.

[0031] Furthermore, transistor 440 has a gate electrode layer 451, a source electrode layer 455c, and a drain By using a light-transmitting conductive film in the electrode layer 455d, a semiconductor device with a high aperture ratio is achieved. This can be achieved. A light-transmitting material is a conductive material that is light-transmitting to visible light. Materials, for example, In-Sn-O system, In-Sn-Zn-O system, In-Al-Zn-O system, Sn -Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn- Acids of the O-based, Sn-Zn-O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based systems Hydrogenated conductive materials can be applied, and when using the sputtering method, SiO2 should be 2% by weight or less. A target containing 10% by weight or less of SiOx is used to form a transparent conductive film. It is best to include (X>0) and maintain an amorphous state.

[0032] The transistor 450, which is arranged in the drive circuit section, is located on a substrate 400 having an insulating surface, and the first Insulating layer 402, oxide semiconductor layer 404a having a channel formation region, source electrode layer 455 a, drain electrode layer 455b, second insulating layer 428 which functions as a gate insulating layer, and It includes an electrode layer 421.

[0033] The gate electrode layer 421, source electrode layer 455a, and drain electrode layer 4 of transistor 450 55b (including wiring formed in the same layer) consists of Al, Cu, Cr, Ta, Ti, M It is formed from a metallic material such as o, W, or an alloy material having said metallic material as a component. Also, Al One or both of the metal layers, such as Cu, are covered with a high-melting-point metal layer such as Cr, Ta, Ti, Mo, or W. A layered configuration of these elements is also acceptable. Furthermore, Si, Ti, Ta, W, Mo, Cr, Nd, Sc A contains elements such as Y that prevent the formation of hillocks and whiskers in Al films. By using L material, it is possible to improve heat resistance.

[0034] The source electrode and drain electrode (including wiring formed in the same layer) are made of conductive metallic acid. It may also be formed from an oxide. Examples of conductive metal oxides include indium oxide (In2O3) and acid Tin oxide (SnO2), zinc oxide (ZnO), indium oxide tin alloy (In2O3) SnO2 (abbreviated as ITO), indium zinc oxide alloy (In2O3-ZnO) Alternatively, the metal oxide material may be made to contain silicon or silicon oxide. can.

[0035] Above the oxide semiconductor layer 404a are the source electrode layer 455a and the drain electrode layer 455 Part of b is formed by overlapping. Also, the oxide semiconductor layer 404a is formed by the gate electrode layer 4 21 and the second insulating layer 428 overlap. Transistors are located in the drive circuit section. The channel formation region 450 is the source electrode layer 455a of the oxide semiconductor layer 404a. It is sandwiched between the contact region and the region in contact with the drain electrode layer 455b, and in contact with the second insulating layer 428. Furthermore, it is a region that overlaps with the gate electrode layer 421.

[0036] Examples of oxide semiconductor layers include the quaternary metal oxide In-Sn-Ga-Zn-O system and the three-layer system. The original metal oxide systems are In-Ga-Zn-O, In-Sn-Zn-O, and In-Al- Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn-O Systems such as the In-Zn-O system, Sn-Zn-O system, and Al-Zn-O system, which are binary metal oxides. Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system, In-O system, Sn-O system Furthermore, an oxide semiconductor layer such as a Zn-O-based layer can be used. It may contain SiO2.

[0037] Furthermore, the oxide semiconductor layer is InMO3(ZnO) m We use thin films denoted as (m>0). This is possible. Here, M is one or more selected from Ga, Al, Mn, and Co. This indicates a metallic element. For example, M could be Ga, Ga and Al, Ga and Mn, or Ga and Examples include Co., InMO3(ZnO). m Oxide semiconductors with a structure represented by (m>0) Among these, oxide semiconductors with a structure containing Ga as M are subjected to the above-mentioned In-Ga-Zn-O system oxide This material is called a semiconductor, and its thin film is also called an In-Ga-Zn-O film.

[0038] Furthermore, the oxide semiconductor layer contains RTA (Rapid Thermal Annealing). The product is treated with a high-temperature, short-time dehydration or dehydrogenation process such as a thermal annealing method. This heating process results in the surface layer of the oxide semiconductor layer having a particle size of 1 nm to 20 nm. It has a crystalline region composed of so-called nanocrystals (also written as nanocrystalline). The rest of the material is amorphous, or contains a mixture of amorphous and microcrystalline regions with microcrystals scattered within the amorphous region. It will be a mixture. Note that the size of the nanocrystals is just one example, and the invention is not limited to the above numerical range. It is not meant to be interpreted.

[0039] By using an oxide semiconductor layer with this configuration, the surface layer is composed of nanocrystals. Because of the presence of dense crystalline regions, n-type formation occurs due to the re-intrusion of water from the surface and the desorption of oxygen. This prevents the degradation of the affected electrical properties. Furthermore, the surface layer of the oxide semiconductor layer is... In the Tomgate type transistor 440, the channel is on the opposite side, and preventing n-type conversion is... It is also effective in suppressing raw channels. Furthermore, the surface layer has improved conductivity due to the presence of crystalline regions. This can reduce the contact resistance between the part and the source electrode layer or drain electrode layer.

[0040] The crystalline region of the surface layer of the oxide semiconductor layer has a direction approximately perpendicular to the surface of the oxide semiconductor layer. It has crystal grains with oriented c-axis. For example, an In-Ga-Zn-O system oxide. When using semiconductor materials, the crystalline region is defined as the c-axis of the In2Ga2ZnO7 crystal grain being oxidized. The elements are oriented in a direction approximately perpendicular to the surface of the semiconductor layer. For example, an oxide semiconductor layer. When using an In-Ga-Zn-O based oxide semiconductor material, the In2Ga2ZnO7 crystal The c-axis of the grain is positioned perpendicular to the substrate plane (or the surface of the oxide semiconductor layer). By arranging the crystals, the direction of current in the transistor is determined by In2Ga2ZnO This corresponds to the b-axis direction (or a-axis direction) of the 7 crystal grains.

[0041] Furthermore, the crystalline region may include elements other than crystal grains. Also, the crystalline structure of the crystal grains may vary. The following is not limited to the above; it may also include crystal grains of other crystal structures. For example, In-Ga-Zn When using an O-based oxide semiconductor material, in addition to the crystal grains of In2Ga2ZnO7, I It may also contain nGaZnO4 crystal grains, etc.

[0042] Hereafter, using Figures 1(A) to 1(E), transistor 440 and transistor 440 are placed on the same substrate. This explains the process for manufacturing the Sta450.

[0043] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 451 is formed by the process. At this time, in order to prevent step breaks, at least the gate electrode layer 451 is formed. It is preferable to etch the electrode layer 451 so that a tapered shape is formed at its edges. .

[0044] The resist mask may also be formed by an inkjet method. Since the photon process does not require a photomask, manufacturing costs can be reduced. Hmm, it can be applied not only to the first photolithography process, but also to other photolithography processes. Cut.

[0045] The substrate 400 may be barium borosilicate glass, aluminobrosilicate glass, or Alkali-free glass produced by fusion or float processes, such as aluminosilicate glass. In addition to lath substrates and ceramic substrates, plastics with heat resistance capable of withstanding the processing temperature of this manufacturing process are also used. A plastic substrate can be used. In addition, an insulating material can be used on the surface of a metal substrate such as a stainless steel alloy. A substrate with a film applied to it may also be used.

[0046] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials, such as crystallized glass, can also be used.

[0047] The gate electrode layer 451 is made of a light-transmitting oxide conductive material in order to improve the aperture ratio of the pixel portion. It is preferable to fabricate it using layers. Examples of oxide conductive layers include indium oxide. Indium tin oxide alloy, indium zinc oxide alloy, zinc oxide, zinc aluminum oxide Aluminum, zinc aluminum oxynitride, or zinc gallium oxide can be used.

[0048] The conductive film forming the gate electrode layer 451 is Al, Cr, Ta, Ti, Mo, An element selected from W, or an alloy containing the above-mentioned elements, or a combination of the above-mentioned elements A crystalline alloy film or a laminated film may also be used.

[0049] Furthermore, an insulating layer serving as the base film may be provided between the substrate 400 and the gate electrode layer 451. The film has the function of preventing the diffusion of impurity elements from the substrate 400, and is a silicon nitride film, silicon oxide A film, silicon nitride film, or silicon oxide film, one or more films selected from these, forming a layer It can be formed by a layered structure.

[0050] Next, a first insulating layer 402 is formed on the gate electrode layer 451. Silicon oxide, silicon oxide nitride, silicon nitride oxide formed by CVD or sputtering methods Using monolayer or multilayer films such as silicon nitride, aluminum oxide, and tantalum oxide. This is possible. Furthermore, the film thickness shall be between 50 nm and 250 nm. Note that the first insulating layer 4 02 acts as the gate insulating layer for transistor 440 and the base insulating layer for transistor 450. It functions as a marginal layer.

[0051] The formation of the first insulating layer 402 can also be carried out using a high-density plasma device. Here, The high-density plasma device is 1 × 10 11 / cm 3 This refers to a device that can achieve the above plasma density. For example, by applying microwave power of 3kW to 6kW to generate plasma, The first insulating layer 402 is formed.

[0052] Monosilane gas (SiH4), nitrous oxide (N2O), and dilute gas are placed in the chamber as material gases. By introducing a system that generates high-density plasma under a pressure of 10 Pa to 30 Pa, it can insulate glass and other materials. An insulating layer is formed on a substrate with a surface. Then, the supply of monosilane gas is stopped, and the atmosphere is exposed. Plasma treatment is performed on the insulating layer surface by introducing nitrous oxide (N2O) and a noble gas without exposure to the elements. It is permissible to do so. At a minimum, it should be done by introducing nitrous oxide (N2O) and a noble gas onto the surface of the insulating layer. The plasma treatment is performed after the deposition of the insulating layer. The insulating layer that has undergone the above process sequence is a film This insulating layer is thin, and can ensure reliability even if its thickness is less than 100 nm. .

[0053] When forming the first insulating layer 402, monosilane gas (SiH4) and sub-silane gas are introduced into the chamber. The flow rate ratio with nitrogen oxide (N2O) should be in the range of 1:10 to 1:200. The noble gases introduced into the bar include helium, argon, krypton, and xenon. While it is possible to use any of these methods, it is preferable to use argon, which is the least expensive.

[0054] Furthermore, the insulating layer obtained by the high-density plasma device can form a film of a consistent thickness. It has excellent step coverage. In addition, the insulating layer obtained by the high-density plasma device is a thin film. The thickness can be precisely controlled.

[0055] The insulating layer obtained through the above process sequence is different from the insulating layer obtained with a conventional parallel plate type PCVD apparatus. The results differ significantly, and when comparing etching rates using the same etchant, Therefore, the insulating layer obtained with a parallel plate type PCVD apparatus is 10% or more slower or 20% or more slower, and high The insulating layer obtained using a density plasma device can be described as a dense film.

[0056] Furthermore, as the first insulating layer 402, silicon oxide is produced by a CVD method using organic silane gas. It is also possible to form layers. As for organic silane gases, ethyl silicate (TEOS: chemical) is used. Formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), Tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane Sun (OMCTS), Hexamethyldisilazane (HMDS), Triethoxysilane (Si H(OC2H5)3), trisdimethylaminosilane (SiH(N(CH3)2)3), etc. A silicon-containing compound can be used.

[0057] Furthermore, the first insulating layer 402 may be made of an oxide of aluminum, yttrium, or hafnium. A substance, nitride, oxidized nitride, or a type of nitride oxide or a compound thereof, containing at least two of these. Compounds containing the above components can also be used.

[0058] In this specification, an oxidized nitride is defined as a compound in which oxygen atoms are more abundant than nitrogen atoms. It refers to a substance with a large number of nitrogen atoms, and nitride oxides, in terms of their composition, have more nitrogen atoms than oxygen atoms. This refers to substances that are present in large quantities. For example, silicon oxidnitride film has a composition that includes nitrogen atoms. The number of oxygen atoms is greater than that of the child, and Rutherford backscattering (RBS) Backscattering Spectrometry and hydrogen forward scattering (H) The measurement was performed using FS (Hydrogen Forward Scattering). In total, the concentration range should be 50 atomic% to 70 atomic% for oxygen and 0.5 atomic% to 1 Less than 5 atomic percent, silicon 25 atomic percent to 35 atomic percent, hydrogen 0.1 atomic percent to 10 This refers to substances included in amounts less than an atomic percent. Furthermore, silicon nitride oxide film refers to its composition as follows: Therefore, when the number of nitrogen atoms is greater than the number of oxygen atoms, and when measured using RBS and HFS, the concentration The range is 5 atomic percent to 30 atomic percent for oxygen, and 20 atomic percent to 55 atomic percent for nitrogen. The range is 25 to 35 atomic percent silicon and 10 to 30 atomic percent hydrogen. This refers to the elements included in silicon oxide nitride or silicon nitride oxide. When the total is set to 100 atomic%, the content ratios of nitrogen, oxygen, silicon, and hydrogen are within the above range. It shall be included within the enclosed area.

[0059] Next, a film thickness of 5 nm to 200 nm, preferably 10 nm, is applied to the first insulating layer 402. A oxide semiconductor film 403 of 20 nm or less is formed (Figure 1(A)).

[0060] Furthermore, before depositing the oxide semiconductor film 403, argon gas is introduced to generate plasma. By performing reverse sputtering, dust adhering to the surface of the first insulating layer 402 can be removed. Preferred. Reverse sputtering is a process where a voltage is not applied to the target side, and the substrate is subjected to an argon atmosphere. A method of modifying the surface by applying a voltage using an RF power supply to form plasma near the substrate. This is the case. Note that nitrogen, helium, etc. may be used instead of an argon atmosphere. The procedure can also be carried out in an argon atmosphere with added oxygen, N2O, etc. Alternatively, in an argon atmosphere... The process may also be carried out in an atmosphere containing Cl2, CF4, etc. After reverse sputtering, expose to the air. By forming an oxide semiconductor film without the first insulating layer 402 and the oxide semiconductor film 40 This prevents dirt and moisture from adhering to the interface of 3.

[0061] Oxide semiconductor films include In-Ga-Zn-O systems, In-Sn-Zn-O systems, and In-Al-Z nO system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system , In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Alternatively, oxide semiconductor films such as Zn-O-based films can be used. , under a noble gas (typically argon) atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) atmosphere It can be formed by sputtering in a gon and oxygen atmosphere. When using the T method, a target containing 2% to 10% by weight of SiO2 is used for film deposition. This process may be carried out to include SiOx (X>0), which inhibits crystallization, in the oxide semiconductor film.

[0062] Here, an oxide semiconductor film deposition target containing In, Ga, and Zn (composition ratio of I n2O3:Ga2O3:ZnO = 1:1:1 [molar ratio], or In2O3:Ga2 Using O3:ZnO=1:1:2 (molar ratio), the distance between the substrate and the target is 100mm, pressure 0.6Pa, DC power supply 0.5kW, oxygen (oxygen flow rate ratio 100) The film is deposited under a %) atmosphere. Note that if a pulsed DC power supply is used, the following will occur during film deposition. This method is preferred because it reduces powdery material (also called particles or dust) and results in a more uniform film thickness distribution. In this embodiment, the oxide semiconductor film is an In-Ga-Zn-O based oxide semiconductor. Using a film deposition target, an In-Ga-Zn-O film with a thickness of 15 nm is deposited by sputtering. To form a film.

[0063] The oxide semiconductor film is preferably 5 nm to 30 nm in size. The appropriate thickness varies depending on the semiconductor material, so you should select the appropriate thickness according to the material.

[0064] Furthermore, it is preferable to continuously deposit the oxide semiconductor film on the first insulating layer 402. This multi-chamber type sputtering apparatus uses silicon or silicon oxide (artificial quartz) sputtering. It has a get and a target for oxide semiconductor films, and at least for oxide semiconductor films The film deposition chamber equipped with the target has a cryopump as an exhaust means. Instead of a lyopump, a turbomolecular pump is used, and water is placed on the intake port of the turbomolecular pump. A configuration that includes a cold trap to adsorb particles and other substances is also possible.

[0065] The deposition chamber, which is evacuated using a cryopump, contains hydrogen atoms, for example, H2O, which contains hydrogen atoms. Because the compounds contained, carbon atoms, and compounds containing carbon atoms are exhausted, the film formation process in the film formation chamber is carried out. This method can reduce the concentration of impurities in the deposited oxide semiconductor film.

[0066] Furthermore, the oxide semiconductor film may be deposited while heating the substrate. In this case, the substrate temperature is set to 100°C. The temperature should be between 5°C and 600°C, preferably between 200°C and 400°C. The substrate is heated while forming By forming a film, the concentration of impurities in the deposited oxide semiconductor film can be reduced. ru.

[0067] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering, which uses a DC power supply. There is DC sputtering, and also pulsed DC sputtering, which applies a pulsed bias. Sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing metal conductive films. It is used when forming thin films.

[0068] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0069] Furthermore, a sputtering apparatus that uses the magnetron sputtering method, which has a magnetic mechanism inside the chamber. Alternatively, ECR sputtering uses plasma generated with microwaves instead of glow discharge. There are sputtering machines that use this method.

[0070] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas components are deposited during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of these compounds, and during film formation... There is also a bias sputtering method that applies voltage to the circuit board.

[0071] Next, a second photolithography process is performed to form a resist mask, and In-Ga-Z The nO-based film is etched. For etching, organic ions such as citric acid and oxalic acid are used. Acids can be used as etchants. Edges of oxide semiconductor layers 404a and 404b By etching it into a tapered shape, it is possible to prevent the wiring from being cut off due to the stepped shape. Note that etching here is not limited to wet etching, but also includes dry etching. It's okay to be there.

[0072] Next, the oxide semiconductor layers 404a and 404b are dehydrated or dehydrogenated. Alternatively, the first heat treatment for dehydrogenation may involve resistance heating or lamp irradiation under an inert gas atmosphere. By which means, at a temperature between 500°C and 750°C (or below the strain point of the glass substrate) RTA for approximately 1 minute to 10 minutes, preferably at 650°C, and approximately 3 minutes to 6 minutes. This can be done through processing. Using the RTA method, dehydration or dehydrogenation can be performed in a short time. Therefore, processing can be performed even at temperatures exceeding the strain point of the glass substrate. This can be done not only at that timing, but also multiple times before and after the photolithography process or film deposition process. good.

[0073] In this specification, heating treatment under an inert gas atmosphere such as nitrogen or a noble gas is referred to as dehydration. Alternatively, this is called a heat treatment for dehydrogenation. In this specification, this heat treatment is used to produce H2. Dehydrogenation is not simply defined as the process of removing H, OH, etc. For convenience, this process, including the dehydration or dehydrogenation, will be referred to as such.

[0074] From the heating temperature T used to dehydrate or dehydrogenate the oxide semiconductor layer, Without exposing the material to the atmosphere in the same furnace where the ionization was performed, and without reintroducing water or hydrogen, It is important to cool the mixture down. Dehydration or dehydrogenation occurs simultaneously with oxygen deficiency, and acid Converting the semiconductor layer to n-type (n - , n + (For example) In other words, after reducing resistance, oxygen is replenished. When a transistor is fabricated using an oxide semiconductor layer that has been made i-type by increasing its resistance, The threshold voltage value of the zista can be set to a positive value, resulting in a switch with so-called normally-off characteristics. A threshold element can be realized. The gate voltage of the transistor is as close to 0V as possible. For display devices, it is desirable that channels are formed by voltage. If the voltage value is negative, even if the gate voltage is 0V, electricity will still be present between the source and drain electrodes. The flow is prone to what is known as the normally-on characteristic. Active matrix display devices In this context, the electrical characteristics of the transistors that make up the circuit are important, and these electrical characteristics are displayed. It affects the performance of the device. In particular, the threshold voltage (Vth) among the electrical characteristics of a transistor. This is important. Even if the field effect mobility is high, the threshold voltage value is high, or the threshold voltage value If it is negative, it is difficult to control as a circuit. The threshold voltage value is high, In the case of a transistor with a large absolute value of key voltage, the transistor will behave differently at low drive voltages. It may not be able to perform its switching function as a station, potentially becoming a load. n-channel In the case of a single-type transistor, a channel is formed only when a positive voltage is applied to the gate voltage. A transistor that allows drain current to flow is desirable. If the drive voltage is not high enough, the channel Transistors in which no loop is formed, or transistors in which a channel is formed even in a negative voltage state and a drain current flows are not suitable as transistors used in circuits.

[0075] Also, the gas atmosphere during the temperature drop from the heating temperature T may be switched to a gas atmosphere different from the gas atmosphere when the temperature is raised to the heating temperature T. For example, without exposing to the atmosphere in the same furnace that has undergone dehydration or dehydrogenation, the inside of the furnace is filled with high-purity oxygen gas or N2O gas, or ultra-dry ether (dew point of -40 °C or lower, preferably -60 °C or lower) and cooled. In addition, in the first heat treatment, it is preferable that water, hydrogen, etc. are not contained in the atmosphere. Or, the purity of the inert gas introduced into the heat treatment apparatus is 6N (99.9999%) or more,

[0076] preferably 7N (99.99999%) or more, (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). When the heat treatment is performed in the above inert gas atmosphere, the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and has a lower resistance, that is, becomes n-type (n type conversion, etc.). After that, by forming an oxide insulating layer in contact with the oxide semiconductor layer, it can be said that the oxygen-deficient part of the oxide semiconductor layer is compensated and the resistance is increased, that is, it becomes i-type. As a result, a transistor with good electrical characteristics and high reliability

[0077] can be manufactured. The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by temperature-programmed desorption spectroscopy - (TDS:Thermal Desorption Spectroscopy) at 45 It can be said that the oxygen-deficient part of the oxide semiconductor layer is compensated by forming an oxide insulating layer in contact with the oxide semiconductor layer, and the resistance is increased, that is, it becomes i-type. As a result, a transistor with good electrical characteristics and high reliability can be manufactured. can be produced.

[0078] The oxide semiconductor layer that has been sufficiently dehydrated or dehydrogenated under the above conditions is analyzed by temperature-programmed desorption spectroscopy (TDS:Thermal Desorption Spectroscopy) at 45 Even when heated to 0°C, the spectrum showing water desorption has two peaks, at least 250-3°C. The single peak that typically appears around 00°C is not detected.

[0079] Furthermore, the oxide semiconductor layers 404a and 404b have many unbonded bonds at the time of film formation. Although it is amorphous, by performing the first heating step of the above dehydration or dehydrogenation treatment, Unbonded bonds in the separated regions can bond together, forming an ordered amorphous structure. As ordering develops, a mixture of amorphous and microcrystalline material is formed, in which microcrystals are scattered within the amorphous region. The entire structure is amorphous, and nanocrystalline material is formed on the surface of the oxide semiconductor layers 404a and 404b. The resulting crystalline regions 405a and 405b are formed (Figure 1(B)). Other regions of layers 404a and 404b are amorphous, with microcrystals scattered within the amorphous regions. It becomes a mixture of solids and microcrystals. Note that the crystalline regions 405a and 405b are oxide semiconductor layers 404 a is part of 404b, and hereafter, the notation for oxide semiconductor layers 404a and 404b will be crystalline. Regions 405a and 405b are included. Furthermore, the particle size of the microcrystals must be 1 nm or larger. These are so-called nanocrystals with a wavelength of 20 nm or less, and are generally called microcrystals. They are smaller than microcrystalline particles.

[0080] Furthermore, in crystalline regions 405a and 405b, the c-axis orientation is perpendicular to the film surface. It is preferable that nanocrystals are formed, in which case the long axis is in the c-axis direction and the short axis is 1 It is preferable that the size is between nm and 20 nm.

[0081] Furthermore, depending on the order of the process, a crystalline region may not be formed on the side surface of the oxide semiconductor layer. Crystalline regions are formed in the surface layer, excluding the surface layer. However, the area ratio of the side surface is small, and in this case... Even if this is done, the effect of preventing deterioration of electrical characteristics will be maintained.

[0082] The oxide semiconductor layers 404a and 404b after the first heat treatment become oxygen-deficient immediately after film formation. The carrier concentration is higher than that, preferably 1 × 10⁻⁶ 18 / cm 3 Having the above carrier concentrations This results in low-resistance oxide semiconductor layers 404a and 404b.

[0083] Furthermore, depending on the conditions of the first heat treatment or the material, the gate electrode layer 421 may also crystallize. It may also be a microcrystalline film or a polycrystalline film. For example, as the gate electrode layer 421, When using tin oxide, crystallization occurs in the first heat treatment at 450°C for 1 hour, but silicon oxide When using indium tin oxide containing [specific compound], crystallization is less likely to occur.

[0084] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is extracted and then subjected to a photolithography process to process it into island-shaped oxide semiconductor layers.

[0085] Next, although not shown in the diagram, there is a gate electrode layer and a source electrode layer or drain electrode, which will be explained later. Openings (also called contact holes) for connecting the layers are formed in the first insulating layer 402. The first insulating layer 402 is then subjected to a mass by photolithography or inkjet method, etc. A mask is formed, and the first insulating layer 402 is selectively etched using the mask to make contact. A hole is formed. Note that the formation of the contact hole occurs after the formation of the first insulating layer 402, by oxidation. This may be performed before the formation of the monosemiconductor film 403.

[0086] Next, sputtering, vacuum deposition, etc. are used on the oxide semiconductor layers 404a and 404b. These are conductive films of W, Ta, Mo, Ti, Cr, etc., or alloys combining the above elements. These materials are used as a conductive film, with a wavelength of 100 nm to 500 nm, preferably 200 nm to 300 nm. It is formed with a thickness of m or less. The conductive film is not limited to a single layer containing the above-mentioned elements, but is not limited to two or more layers. Lamination can be used. The conductive film is subjected to at least the second heat treatment that is performed later. It is preferable that it has sufficient heat resistance to withstand the heat.

[0087] Furthermore, the conductive film may be a transparent conductive oxide containing indium, tin, or zinc. It may be used. For example, indium oxide (In2O3) or indium oxide tin oxide alloy ( It is preferable to use In2O3-SnO2 (abbreviated as ITO). Also, transparent conductive acid A material in which an insulating oxide such as silicon oxide is added to the oxide may also be used. Transparent conductive oxide By using this as a conductive film, the aperture ratio of the display device can be improved.

[0088] The conductive film in contact with the oxide semiconductor layers 404a and 404b is made of a material containing a metal with high oxygen affinity. Preferred. Metals with high oxygen affinity include titanium (Ti), manganese (Mn), and magnesium. Zium (Mg), Zirconium (Zr), Beryllium (Be), Thorium (Th) It is preferable that the material is selected from one or more of the following. In this embodiment, a titanium film Use this.

[0089] When an oxide semiconductor layer and a conductive film with high oxygen affinity are formed in contact, the carrier density near the interface This increases the resistance, forming a low-resistance region, and reducing the contact resistance between the oxide semiconductor and the conductive film. This is because the highly oxygen-affinity conductive film extracts oxygen from the oxide semiconductor layer. At the interface between the oxide semiconductor layer and the conductive film, there is a layer with an excess of metal from the oxide semiconductor layer (also called a composite layer). This is due to the formation of either a conductive film or an oxidized conductive film, or both. For example, in a configuration where an In-Ga-Zn-O oxide semiconductor layer and a titanium film are in contact, Near the interface between the oxide semiconductor layer and the titanium film, there is an excess of indium and the titanium oxide layer. It may also be generated near the interface between the oxide semiconductor layer and the titanium film. In some cases, either an excess layer of ions or a titanium dioxide layer may be formed. In the O-based oxide semiconductor layer, oxygen is deficient, and the layer with excess indium has high electrical conductivity, and acid This makes it possible to reduce the contact resistance between the ionized semiconductor layer and the conductive film.

[0090] Furthermore, a conductive titanium oxide film may be used as the conductive film in contact with the oxide semiconductor layer. In that case, the configuration involves an In-Ga-Zn-O based oxide semiconductor layer and a titanium oxide film in contact. In this case, an excess layer of indium is formed near the interface between the oxide semiconductor layer and the titanium oxide film. It may happen.

[0091] Furthermore, methods for depositing conductive films include arc discharge ion plating and spraying. It may also be used. Furthermore, screen printing methods using conductive nanopastes such as silver, gold, and copper are also possible. They may also be formed by extrusion and firing using methods such as inkjet printing.

[0092] Next, a mask is formed on the conductive film by photolithography or inkjet printing. Then, using the mask, the conductive film is etched to form the source electrode layers 455a, 455c, and Rain electrode layers 455b and 455d are formed (Figure 1(C)). In this embodiment, a conductive film A 200nm thick layer of Ti is formed using the sputtering method, and a resist mask is used. The conductive film is selectively etched using either a wet etching method or a dry etching method, and then... - Electrode layers 455a, 455c and drain electrode layers 455b, 455d are formed.

[0093] Oven, source electrode layer 455a, 455c, drain electrode layer 455b, 455d and exposure A second insulating layer 428 is formed to cover the oxide semiconductor layers 404a and 404b (Figure 1(D The second insulating layer 428 consists of a silicon oxide film, a silicon oxide nitride film, and an aluminum oxide film. An oxide insulating film such as a tantalum oxide film can be used. This acts as the gate insulating layer for transistor 450.

[0094] Furthermore, the second insulating layer 428, which functions as the gate insulating layer of transistor 450, is a multilayer film. It may also be formed using [a specific method]. When forming the second insulating layer using a laminated film, the first layer (acid (Layer in contact with the semiconductor layer) Silicon oxide film, silicon oxide nitride film, aluminum oxide film , an oxide insulating film such as a tantalum oxide film is formed, and from the second layer onwards, it is not limited to oxides, nitriding First insulating layer 40 such as silicon oxide, silicon nitride, aluminum oxide, tantalum oxide A film can be formed using the same material as in 2.

[0095] The second insulating layer 428 is formed by mixing impurities such as water and hydrogen into the oxide insulating film using methods such as sputtering. It can be formed by using appropriate methods to prevent entry. In this embodiment, the second insulating layer and Then, a silicon oxide film is deposited using the sputtering method. The substrate temperature during film deposition is above room temperature. The temperature should be below 0°C, and in this embodiment, it is set to 100°C. Here, water and hydrogen are used during film formation. As a method to prevent the inclusion of such impurities, the film is prepared under reduced pressure at a temperature of 150°C to 350°C before deposition. Perform a pre-bake at 2 to 10 minutes, and without exposure to the air, apply the second insulating layer. Formation is desirable. The deposition of silicon oxide films by sputtering is performed using noble gases (typically... This can be done under an argon atmosphere, an oxygen atmosphere, or a noble gas (typically argon) and oxygen. It can be carried out under atmospheric conditions. Also, silicon dioxide target or A silicon target can be used. For example, a silicon target can be used to extract oxygen and dilute oxygen. Silicon oxide can be formed by sputtering under a gas atmosphere. The oxide insulating film formed in contact with the oxide semiconductor layer contains water, hydrogen ions, and OH - etc. An inorganic insulating film that is free of impurities and blocks their intrusion from the outside is preferred.

[0096] In this embodiment, the purity is 6N, and the silicon target is a columnar polycrystalline B-doped material (resistivity value 0 Using a pressure of 0.01 Ωcm, the distance between the substrate and the target (TS distance) was set to 89 mm, and pressure Pulse test conducted under a pressure of 0.4 Pa, a DC power supply of 6 kW, and an oxygen atmosphere (oxygen flow rate ratio of 100%). The film will be deposited by DC sputtering. The film thickness will be 300 nm.

[0097] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under atmospheric pressure. Alternatively, a high temperature treatment similar to the first heat treatment is performed. A short-duration RTA treatment may be performed. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor are formed. The conductive layers are heated in contact with each other. Note that when the second heating treatment is performed, the first heating treatment is low Oxygen is supplied to the resistive oxide semiconductor layers 404a and 404b, compensating for oxygen deficiencies. Therefore, it is possible to increase the resistance (to an i-type design).

[0098] In this embodiment, a second heat treatment was performed after the silicon oxide film was formed, but the timing of the heat treatment was acid It is not limited to immediately after silicon oxide film formation; any time after the silicon dioxide film formation is sufficient.

[0099] Next, a photolithography process is performed to form a resist mask, and the second insulating layer 428 Etching is used to form contact holes that reach the drain electrode layer 455d. After forming a conductive film on the second insulating layer 428, a photolithography process is performed on the conductive film. The gate electrode layer 421 and the connecting electrode layer 44, which will be connected to the pixel electrode layer in a later step, are then formed. Form 2 (Figure 1(E)). The conductive film can be made of Al, Cr, Cu, Ta, Ti, Mo, A film containing elements selected from W can be used as a single layer or in a laminated form. If the drain electrode layer 455d and the pixel electrode layer are directly connected, the connecting electrode layer 442 is omitted. You can.

[0100] Also, although not shown in the diagram, this process overlaps with the channel formation region of the oxide semiconductor layer 404b. A conductive layer may be formed at this location. By providing a conductive layer, the reliability of the transistor can be improved. This includes a bias-thermal stress test (hereinafter referred to as B) to examine the reliability of transistor 440. In the T test, the change in the threshold voltage of the transistor before and after the BT test is measured. It can be reduced. Also, the conductive layer may have the same potential as the gate electrode layer 451. They can be different, and can also function as a second gate electrode layer. Also, the conductive layer The potential may be GND, 0V, or floating.

[0101] Furthermore, a protective insulating layer may be formed to cover transistors 440 and 450. The layers used may include silicon nitride films, silicon oxide nitride films, or aluminum nitride.

[0102] Furthermore, a planar insulating layer may be provided on transistors 440 and 450. For example, heat-resistant materials such as acrylic, polyimide, benzocyclobutene, polyamide, and epoxy. Organic materials having the above properties can be used. In addition to the above organic materials, low dielectric constant materials (lo wk materials), siloxane resins, PSG (phosphorus glass), BPSG (phosphorus boron glass) ) etc. can be used. That's good. Additionally, the color filter layer can be used as a planarizing insulating layer.

[0103] Furthermore, capacitive wiring that can be manufactured using the same material and process as the gate electrode layer 451, and the gate electrode layer Using a capacitive electrode that can be manufactured using the same material and process as 421, an insulating layer 402 or a second A retaining capacitance with a dielectric including an insulating layer 428 sandwiched in between may also be formed on the same substrate. The pixel section is constructed by arranging the 440 and the retention capacity in a matrix corresponding to each individual pixel, and the image By arranging the drive circuit section having transistor 450 around the element section, an active motor is created. It can be used as one of the substrates for fabricating a Trix-type display device.

[0104] Furthermore, when manufacturing a display device using transistors 440 and 450, the driving transistor A power supply line is provided that is electrically connected to the source electrode layer of the gate, and this power supply line is gate wiring. It intersects with and is formed using the same material and process as the connecting electrode layer 442 which is made of a metal conductive film. .

[0105] Furthermore, when fabricating a light-emitting device, one electrode of the light-emitting element is connected to the source power of the driving transistor. It is electrically connected to the polar layer or drain electrode layer, and electrically connected to the other electrode of the light-emitting element. A common potential line is provided. This common potential line is connected to a connecting electrode layer 4 made of a metal conductive film. Formed using the same materials and process as 42. Alternatively, the common potential line is the same as gate electrode layer 451. The same materials are used and formed using the same process.

[0106] When a transistor is fabricated using the method described above, the oxide semiconductor layers 404a and 404b The hydrogen concentration is reduced, and the transistor's off-current is 1 × 10⁻⁶. -13 This will be less than or equal to A. Such oxide semiconductor layers 404a and 404b have had their hydrogen concentration sufficiently reduced and have been purified. By applying this, transistors with excellent characteristics can be obtained.

[0107] Furthermore, as a semiconductor material that can be compared to oxide semiconductors, silicon carbide (for example, 4H) is a suitable example. There is -SiC). Oxide semiconductors and 4H-SiC have several things in common. The riah density is one example. Using the Fermi-Dirac distribution at room temperature, oxide semiconductors The number of minority carriers in the body is 10 -7 / cm 3 It is estimated to be of a certain degree, but this is for 4H-SiC. 6.7 x 10 -11 / cm3 Similarly, this is an extremely low value. Intrinsic carriers of silicon Density (1.4×10 10 / cm 3 Compared to other degrees, the degree is extraordinary. I understand that very well.

[0108] Furthermore, the energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-S Since the energy bandgap of iC is 3.26 eV, it is a wide-bandgap semiconductor. In this respect, oxide semiconductors and silicon carbide have something in common.

[0109] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. For example, the activation of dopants in silicon carbide is generally 1500°C. Because it requires heat treatment at ~2000℃, carbonization occurs on top of semiconductor devices using other semiconductor materials. It is difficult to form semiconductor devices using silicon. At such high temperatures, semiconductor substrates This is because the plates and semiconductor elements would be destroyed. On the other hand, oxide semiconductors are 300-5 It can be manufactured by heat treatment at 0°C (below the glass transition temperature, with a maximum of approximately 700°C). Yes, and after forming an integrated circuit using other semiconductor materials, an oxide semiconductor element is created. It becomes possible to form this.

[0110] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment. It has the advantage of being able to keep energy costs sufficiently low.

[0111] Furthermore, although oxide semiconductors are generally considered to be n-type, in one aspect of the disclosed invention, impurities, In particular, i-type conversion is achieved by removing water and hydrogen. In this regard, it can be said that this is not i-type conversion by adding impurities as in the case of silicon or the like, but rather includes a novel technical concept. This is not i-type conversion by adding impurities as in the case of silicon or the like, but rather includes a novel technical concept.

[0112] <Conduction mechanism of transistors using oxide semiconductors> Here, the conduction mechanism of transistors using oxide semiconductors will be described with reference to FIGS. 22 to 26. It should be noted that the following description is merely a consideration, and it is appended that the validity of the invention is not denied based on this. Here, the conduction mechanism of transistors using oxide semiconductors will be described with reference to FIGS. 22 to 26. It should be noted that the following description is merely a consideration, and it is appended that the validity of the invention is not denied based on this. [[ID=;11]] It should be noted that the following description is merely a consideration, and it is appended that the validity of the invention is not denied based on this.

[0113] FIG. 22 shows a longitudinal sectional view of an inverted staggered type transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Further, a back gate (GE2) is provided thereon via an insulating layer An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Further, a back gate (GE2) is provided thereon via an insulating layer An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Further, a back gate (GE2) is provided thereon via an insulating layer An oxide semiconductor layer (OS) is provided on a gate electrode (GE1) via a gate insulating film (GI), and a source electrode (S) and a drain electrode (D) are provided thereon. Further, a back gate (GE2) is provided thereon via an insulating layer

[0114] FIG. 23 shows an energy band diagram (schematic diagram) between A-A' shown in FIG. 22. FIG. 23(A) shows the case where the voltage between the source and the drain is set to an equipotential (V =0), and FIG. 23 D =0), and FIG. 23 (B) shows the case where a positive potential (V D >0) is applied to the drain with respect to the source.

[0115] FIGS. 25 and 26 show an energy band diagram (schematic diagram) between B-B' in FIG. 22. FIG. 25 shows the state when the gate voltage is 0V. FIG. 26(A) shows the state where a positive potential (V >0) is applied to the gate (GE1), and shows the on state in which carriers (electrons) flow between the source and the drain. Further, FIG. 26(B) shows the state where a negative potential (V G >0) is applied to the gate (GE1), and shows the on state in which carriers (electrons) flow between the source and the drain. >0) is applied to the gate (GE1), and shows the on state in which carriers (electrons) flow between the source and the drain. G<0) indicates a state where a voltage is applied and the state is off (no minority carriers flow). vinegar.

[0116] The thickness of the oxide semiconductor is about 50 nm, and the higher purity of the oxide semiconductor has resulted in The concentration of nar is 1 × 10 18 / cm 3 If the following conditions are met, in the off state, the depletion layer is the entire oxide semiconductor. It spreads throughout the body. In other words, it can be considered a state of complete depletion.

[0117] Figure 24 shows the relationship between the vacuum level, the work function (φM) of the metal, and the electron affinity (χ) of the oxide semiconductor. This indicates.

[0118] Conventional oxide semiconductors are generally n-type, and in that case, the Fermi level (Ef) is bandg It is located away from the intrinsic Fermi level (Ei) located in the center of the cap, and closer to the conduction band. Furthermore, it is known that hydrogen acts as a donor in oxide semiconductors and is one of the factors that leads to n-type semiconductor formation. It is being done.

[0119] In contrast, the oxide semiconductor according to the present invention removes hydrogen, which is an n-type impurity, from the oxide semiconductor. Furthermore, by purifying the material to the point where it contains as few impurities as possible other than the main components of the oxide semiconductor, It is made to be true (type i), or is intended to be true. That is, by adding impurities Instead of converting to type i, the i is purified by removing as many impurities as possible, such as hydrogen and water. It is characterized by being an intrinsic semiconductor or approaching it. By doing so, The Lumi level (Ef) can be reduced to the same level as the true Fermi level (Ei).

[0120] If the band gap (Eg) of an oxide semiconductor is 3.15 eV, then the electron affinity (χ) is It is said to be 4.3 eV. The work function of titanium (Ti) that constitutes the source electrode and the drain electrode is almost equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface, a Schottky-type barrier is not formed for electrons.

[0121] That is, when the work function (φM) of the metal is equal to the electron affinity (χ) of the oxide semiconductor, when both contact, an energy band diagram (schematic diagram) as shown in Fig. 23(A) is shown.

[0122] In Fig. 23(B), the black circles (●) indicate electrons, and a positive voltage (V D > 0) is applied to the drain, and when no voltage is applied to the gate (V G = 0) is shown by a dashed line, and the case where a positive voltage (V G > 0) is applied to the gate is shown by a solid line. When a positive voltage (V G > 0) is applied to the gate and a positive potential is applied to the drain, when electrons cross the barrier (h) and are injected into the oxide semiconductor, they flow toward the drain. In this case, the height of the barrier (h) changes depending on the gate voltage and the drain voltage, but when a positive voltage (V G > 0) is applied to the gate and a positive drain voltage is applied, the height of the barrier in Fig. 23(A) without voltage application, that is, the band gap (Eg) is smaller than half of the height of the barrier (h). When no voltage is applied to the gate, due to the high potential barrier, carriers (electrons) are not injected from the electrode to the oxide semiconductor side, showing an off state where no current flows. On the other hand, when a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows. When a positive voltage is applied to the gate, the potential barrier decreases, showing an on state where current flows.

[0123] At this time, the electrons injected into the oxide semiconductor move through the oxide semiconductor as shown in Figure 26(A). It flows. Also, in Figure 26(B), when a negative potential is applied to the gate electrode (GE1) Since the minority carriers, such as holes, are practically zero, the current is a value very close to zero. Yes.

[0124] This process aims to achieve high purity by minimizing the inclusion of impurities other than the main components of oxide semiconductors. By making it intrinsic (type i) or substantially intrinsic, the interface characteristics with the gate insulating film are improved. This becomes apparent and needs to be considered separately from the bulk properties. Therefore, the gate insulating film is oxidized. A material capable of forming a good interface with a semiconductor is needed. For example, in the VHF to microwave band. An insulating film, or a superfine film, fabricated by a CVD method using high-density plasma generated at a power supply frequency. It is preferable to use an insulating film fabricated by the puttering method.

[0125] To improve the purity of oxide semiconductors while maintaining a good interface between the oxide semiconductor and the gate insulating film. As a result, the channel width W of the transistor is 1 × 10⁻⁶ 4 Channel length in μm Even with a 3μm element, the off-current at room temperature is 10 -13 A or less, Subthreshold The gate swing value (S value) is 0.1 V / dec. (gate insulating film thickness 100 nm) To be waited for.

[0126] In this way, the purity is increased so that impurities other than the main components of the oxide semiconductor are included as little as possible. This allows for better operation of the transistor.

[0127] In this embodiment, the channel formation region of the transistor 450 is an oxide semiconductor layer 40 Of 4a, the region in contact with the source electrode layer 455a and the region in contact with the drain electrode layer 455b This region is sandwiched between two other regions, is in contact with the second insulating layer 428, and overlaps with the gate electrode layer 421. Furthermore, in transistor 450, the oxide semiconductor layer is in contact with the first insulating layer 402. The region is amorphous or a mixture of amorphous and microcrystalline material, and is the surface layer in contact with the second insulating layer 428. The part has a crystalline region. Therefore, the channel formation region is of the oxide semiconductor layer 404a It is also a crystalline region, and the c-axis (ca) is oriented approximately perpendicular to the surface of the oxide semiconductor layer 404a. It has crystal grains in which xis is oriented. For example, In-Ga-Zn-O based oxide semiconductor materials. When using this material, the c-axis of the crystal grains is relative to the substrate plane (or the surface of the oxide semiconductor layer). By arranging the nanocrystals in a vertical direction, in transistor 450 The direction of the current is in the b-axis direction (or a-axis direction) of the crystal grain. Therefore, transistor 45 A value of 0 achieves high dynamic characteristics (on-response and frequency characteristics (called f-response)), for example, high speed It is suitable as a transistor for use in drive circuits where operation is required.

[0128] Furthermore, the channel formation region of transistor 440 is made of the oxide semiconductor layer 404b, The region in contact with the drain electrode layer 455c and the region in contact with the drain electrode layer 455d are sandwiched together, This region is in contact with the insulating layer 402 and overlaps with the gate electrode layer 451. This results in an i-type or substantially i-type oxide semiconductor layer (high-purity oxide semiconductor layer). The carrier concentration is suppressed in the body layer. Furthermore, it is opposite to the channel formation region of the oxide semiconductor layer. Because a dense crystalline region composed of nanocrystals exists on the opposite surface, moisture can be reabsorbed from the surface. This prevents n-type conversion due to intrusion or oxygen desorption. Therefore, the transistor having the oxide semiconductor layer The ZISTA 440 achieves extremely low off-current and excellent reliability, for example, low leakage current. This transistor is suitable for use in pixel sections where reduction is required.

[0129] As described above, in the drive circuit section and the pixel section, an acid having a crystalline region on one surface (surface layer) Two types of transistors were formed using a semiconductor layer as the active layer, and the arrangement of the gate electrode layer was determined. By selecting the region where the channel is formed, the electrical characteristics of the transistor can be selected. It can be selected. Furthermore, a semiconductor having a high-speed operating drive circuit and a pixel section on the same substrate. We can manufacture the device.

[0130] Furthermore, this embodiment can be freely combined with other embodiments.

[0131] (Embodiment 2) This embodiment presents a semiconductor device and a method for manufacturing a semiconductor device that differ from those in Embodiment 1. This will be explained using Figure 2. In this embodiment, the same parts as in Embodiment 1 and The parts and processes having similar functions can be carried out in the same manner as in Embodiment 1 and can be repeated. I will omit the explanation of "shi".

[0132] First, according to the steps shown in Figures 1(A) and (B) of Embodiment 1, an insulating surface is formed On the substrate 400, a gate electrode layer 451, a first insulating layer 402 and island-shaped oxide semiconductor layers are provided. Form 404a and 404b (Figure 2(A)). Note that the oxide semiconductor layer shown in Figure 2(A) The surface layers of 404a and 404b are crystallized by the first heat treatment and are composed of nanocrystals. It has crystalline regions 405a and 405b. It also has oxide semiconductor layers 404a and 40 The other regions of 4b are amorphous, or amorphous with microcrystals scattered within the amorphous region. It becomes a mixture of crystals. Note that the crystalline regions 405a and 405b are oxide semiconductor layers 404a and 40 It is part of 4b, and thereafter, the notation for oxide semiconductor layers 404a and 404b will include the crystal region 40 Items 5a and 405b are included.

[0133] The oxide semiconductor layers 404a and 404b after the first heat treatment become oxygen-deficient immediately after film formation. The carrier concentration is higher than that, preferably 1 × 10⁻⁶ 18 / cm 3 Having the above carrier concentrations This results in low-resistance oxide semiconductor layers 404a and 404b.

[0134] Furthermore, depending on the conditions of the first heat treatment or the material, the gate electrode layer 451 may also crystallize. It may also be a microcrystalline film or a polycrystalline film. For example, as the gate electrode layer 451, When using tin oxide, crystallization occurs in the first heat treatment at 450°C for 1 hour, but silicon oxide When using indium tin oxide containing [specific compound], crystallization is less likely to occur.

[0135] Next, although not shown in the diagram, there is a gate electrode layer and a source electrode layer or drain electrode, which will be explained later. Openings (also called contact holes) for connecting the layers are formed in the first insulating layer 402. The first insulating layer 402 is then subjected to a mass by photolithography or inkjet method, etc. A mask is formed, and the first insulating layer 402 is selectively etched using the mask to make contact. A hole is formed. Note that the formation of the contact hole occurs after the formation of the first insulating layer 402, by oxidation. This may be performed before the formation of the monosemiconductor film 403.

[0136] Next, an oxide conductive layer is placed on the first insulating layer 402 and the oxide semiconductor layers 404a and 404b. A lamination of 480 and the metal conductive film 482 is formed. If the sputtering method is used, the oxide conductive layer 48 The layering of 0 and the metal conductive film 482 can be carried out continuously without exposure to the atmosphere. See Figure 2(B).

[0137] As for the oxide conductive layer 480, among the materials applied to the gate electrode layer 451 described above, visible It is desirable to use a conductive material that is transparent to light. In this embodiment, silicon dioxide Indium tin oxide containing [the specified element] is used.

[0138] Furthermore, the metal conductive film 482 can be selected from Ti, Mo, W, Al, Cr, Cu, and Ta. The element, or an alloy containing the above-mentioned elements, or an alloy combining the above-mentioned elements, etc. Furthermore, it is not limited to a single layer containing the aforementioned elements, but can also be used with two or more layers. Yes, it is possible. Methods for depositing conductive films include sputtering, vacuum deposition (such as electron beam deposition), and... Sputtering is used, along with ion plating or spraying. In this embodiment, sputtering is used. Titanium formed using [a specific method / technology] is used.

[0139] Next, a resist mask is formed by a photolithography process, and the metal conductive film 482 is selected. Selectively etched source electrode layer 484 of transistor 470 to be placed in the drive circuit section a. After forming the drain electrode layer 484b, the resist mask is removed. The metal conductive film 482 is etched onto the transistor 460, leaving no residue.

[0140] Next, a resist mask is formed by a photolithography process, and the oxide conductive layer 480 is formed. The source electrode layer 48 of the transistor 470, which is selectively etched and placed in the drive circuit section. Oxide conductive layer 486a overlapping with 4a, oxide conductive layer 48 overlapping with drain electrode layer 484b 6b, the source electrode layer 486c of the transistor 460 arranged in the pixel area, and the drain electrode After forming the polar layer 486d, the resist mask is removed (see Figure 2(C)).

[0141] Here, a mixed acid containing phosphoric acid, acetic acid, and nitric acid is used for etching the oxide conductive layer 480. For example, it is composed of 72.3% phosphoric acid, 9.8% acetic acid, 2.0% nitric acid, and 15.9% water. A mixed acid can be used. Oxide conductive layer 480 and oxide semiconductor layers 404a, 404b Because their compositions are similar, many of them have a low etching selectivity ratio. However, this The oxide conductive layer used in the form (indium tin oxide containing silicon oxide) is amorphous. On the surface of the oxide semiconductor layer (In-Ga-Zn-O system film), clusters of nanocrystalline structures are formed. Therefore, a relatively large etching selectivity ratio can be obtained. Etching when using the above mixed acid The emission rate was 18.6 nm / sec. for the oxide conductive layer, compared to from the nanocrystal. The oxide semiconductor layer in which the crystal group was formed had a density of 4.0 nm / sec. Therefore, By etching with the above mixed acid using time control, the surface layer of the lower oxide semiconductor layer The crystalline groups of nanocrystals can be left almost completely unetched.

[0142] Furthermore, an oxide conductive layer is provided between the oxide semiconductor layer and the source electrode layer and drain electrode layer. This reduces contact resistance, enabling the creation of transistors capable of higher-speed operation. Next, the source electrode layer 484a and oxide semiconductor of the transistor 470 installed in the drive circuit section. The oxide conductive layer 486a provided between the body layer 404a functions as a source region, and Oxide conductive layer 486b provided between in electrode layer 484b and oxide semiconductor layer 404a This region functions as a drain region, thereby improving the frequency characteristics of the surrounding circuitry (drive circuitry). It is effective for [purpose].

[0143] On the other hand, the source electrode layer 486c and drain electrode of the transistor 460 installed in the pixel section. Since layer 486d is formed of a translucent oxide conductive layer, the aperture ratio can be improved. can.

[0144] Next, source electrode layer 484a, 486c, drain electrode layer 484b, 486d and exposure A second insulating layer 428 is formed to cover the oxide semiconductor layers 404a and 404b. The border layer 428 consists of a silicon oxide film, a silicon oxide nitride film, an aluminum oxide film, and tantalum oxide. An oxide insulating layer such as a film can be used. The second insulating layer 428 is a transistor It functions as the gate insulating layer for the Ta470.

[0145] Furthermore, the second insulating layer 428, which functions as the gate insulating layer of transistor 470, is a multilayer film. It may also be formed using [a specific method]. When the second insulating layer 428 is formed using a multilayer film, one layer The eye (the layer in contact with the oxide semiconductor layer) consists of a silicon oxide film, a silicon oxide nitride film, and an aluminum oxide film. It forms oxide insulating films such as um film and tantalum oxide film, and the second and subsequent layers are not limited to oxides. First insulating materials such as silicon nitride, silicon nitride, aluminum oxide, and tantalum oxide. A film can be formed using the same material as layer 402.

[0146] The second insulating layer 428 is formed by mixing impurities such as water and hydrogen into the oxide insulating film using methods such as sputtering. It can be formed by using appropriate methods to prevent entry. In this embodiment, the second insulating layer and Then, a silicon oxide film is deposited using the sputtering method. The substrate temperature during film deposition is above room temperature. The temperature should be below 0°C, and in this embodiment, it is set to 100°C. Here, water and hydrogen are used during film formation. As a method to prevent the inclusion of such impurities, the film is prepared under reduced pressure at a temperature of 150°C to 350°C before deposition. Perform a pre-bake at 2 to 10 minutes, and without exposure to the air, apply the second insulating layer. Formation is desirable. The deposition of silicon oxide films by sputtering is performed using noble gases (typically... This can be done under an argon atmosphere, an oxygen atmosphere, or a noble gas (typically argon) and oxygen. It can be carried out under atmospheric conditions. Also, silicon dioxide target or A silicon target can be used. For example, a silicon target can be used to extract oxygen and dilute oxygen. Silicon oxide can be formed by sputtering under a gas atmosphere. The oxide insulating film formed in contact with the oxide semiconductor layer contains water, hydrogen ions, and OH - etc. An inorganic insulating film that is free of impurities and blocks their intrusion from the outside is preferred.

[0147] In this embodiment, the purity is 6N, and the silicon target is a columnar polycrystalline B-doped material (resistivity value 0 Using a pressure of 0.01 Ωcm, the distance between the substrate and the target (TS distance) was set to 89 mm, and pressure Pulse test conducted under a pressure of 0.4 Pa, a DC power supply of 6 kW, and an oxygen atmosphere (oxygen flow rate ratio of 100%). The film will be deposited by DC sputtering. The film thickness will be 300 nm.

[0148] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or a nitrogen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under atmospheric pressure. Alternatively, a high temperature treatment similar to the first heat treatment is performed. A short-duration RTA treatment may be performed. When the second heat treatment is performed, the oxide insulating layer and the oxide semiconductor are formed. The conductive layers are heated in contact with each other. Note that when the second heating treatment is performed, the first heating treatment is low Oxygen is supplied to the resistive oxide semiconductor layers 404a and 404b, compensating for oxygen deficiencies. Therefore, it is possible to increase the resistance (to an i-type design).

[0149] In this embodiment, a second heat treatment was performed after the silicon oxide film was formed, but the timing of the heat treatment was acid It is not limited to immediately after silicon oxide film formation; any time after the silicon dioxide film formation is sufficient.

[0150] Next, a photolithography process is performed to form a resist mask, and the second insulating layer 428 Etching is used to form contact holes that reach the drain electrode layer 486d. After forming a conductive film on the second insulating layer 428, a photolithography process is performed on the conductive film. The gate electrode layer 421 and the connecting electrode layer 44, which will be connected to the pixel electrode layer in a later step, are then formed. Form 2 (Figure 2(D)). The conductive film can be made of Al, Cr, Cu, Ta, Ti, Mo, A film containing elements selected from W can be used as a single layer or in a laminated form. If the drain electrode layer 486d and the pixel electrode layer are directly connected, the connecting electrode layer 442 is omitted. You can.

[0151] Also, although not shown in the diagram, this process overlaps with the channel formation region of the oxide semiconductor layer 404b. A conductive layer may be formed at this location. By providing a conductive layer in the vicinity, the reliability of transistor 460 can be improved. Specifically, in BT testing to examine the reliability of transistors, before and after the BT test... The amount of change in the threshold voltage of the transistor can be reduced. Also, the conductive layer is electrically The position may be the same as or different from that of the gate electrode layer 451, and the second gate electrode layer and It can also be made to function as follows: The potential of the conductive layer is GND, 0V, or floating It may be in a good condition.

[0152] In this embodiment, the channel formation region of the transistor 470 is an oxide semiconductor layer 40 Of 4a, the region in contact with the oxide conductive layer 486a and the region in contact with the oxide conductive layer 486b This region is sandwiched between the two layers, is in contact with the second insulating layer 428, and overlaps with the gate electrode layer 421. Furthermore, in transistor 470, the region of the oxide semiconductor layer that is in contact with the first insulating layer 402 The region is amorphous or a mixture of amorphous and microcrystalline material, and is the surface layer in contact with the second insulating layer 428. It has a crystalline region. Therefore, the channel formation region is the bond of the oxide semiconductor layer 404a. It is also a crystal region, and the c-axis (c-ax) is oriented approximately perpendicular to the surface of the oxide semiconductor layer 404a. It has crystal grains in which is oriented. For example, In-Ga-Zn-O based oxide semiconductor materials. When using this method, the c-axis of the crystal grains is perpendicular to the substrate plane (or the surface of the oxide semiconductor layer). By arranging the nanocrystals in a straight direction, the electrical current in transistor 470 The direction of the flow is the b-axis direction (or a-axis direction) of the crystal grain. Therefore, transistor 470 This achieves high dynamic characteristics (on-response and frequency characteristics (called f-response)), for example, high-speed dynamic It is suitable for use in drive circuits where performance is required.

[0153] Furthermore, between the source electrode layer 484a and the oxide semiconductor layer 404a of transistor 470 The oxide conductive layer 486a, which is exposed, functions as the source region, and the drain electrode layer 484b and acid The oxide conductive layer 486b provided between the oxide semiconductor layer 404a serves as a drain region. Therefore, it is effective in improving the frequency characteristics of the peripheral circuitry (drive circuitry).

[0154] Furthermore, the channel formation region of transistor 460 is made of the oxide semiconductor layer 404b, The region in contact with the drain electrode layer 486c and the region in contact with the drain electrode layer 486d are sandwiched together, This region is in contact with the insulating layer 402 and overlaps with the gate electrode layer 451. This results in an i-type or substantially i-type oxide semiconductor layer (high-purity oxide semiconductor layer). The carrier concentration is suppressed in the body layer. Furthermore, it is opposite to the channel formation region of the oxide semiconductor layer. Because a dense crystalline region composed of nanocrystals exists on the opposite surface, moisture can be reabsorbed from the surface. This prevents n-type conversion due to intrusion or oxygen desorption. Therefore, the transistor having the oxide semiconductor layer The ZISTA 460 achieves extremely low off-current and excellent reliability, for example, low leakage current. This transistor is suitable for use in pixel sections where reduction is required.

[0155] Furthermore, in transistor 460, gate electrode layer 451, source electrode layer 486c and Since the rain electrode layer 486d is formed of a light-transmitting conductive layer, the aperture ratio can be improved. It is possible.

[0156] As described above, in the drive circuit section and the pixel section, an acid having a crystalline region on one surface (surface layer) Two types of transistors were formed using a semiconductor layer as the active layer, and the arrangement of the gate electrode layer was determined. By selecting the region where the channel is formed, the electrical characteristics of the transistor can be selected. Yes, it is possible. Furthermore, a semiconductor device having a high-speed operating drive circuit and a pixel section on the same substrate. It can be manufactured.

[0157] Furthermore, this embodiment can be freely combined with other embodiments.

[0158] (Embodiment 3) In this embodiment, Figure 10 shows an example of the configuration of the terminal section provided on the same substrate as the transistor. This is shown below. Note that in Figure 10, the same reference numerals are used to describe the same parts as in Figure 1.

[0159] Figures 10(A1) and 10(A2) show a cross-sectional view and a top view of the gate wiring terminal section, respectively. This is shown. Figure 10(A1) corresponds to a cross-sectional view along the line C1-C2 in Figure 10(A2). In Figure 10(A1), the conductive layer 415 formed on the second insulating layer 428 is input These are terminal electrodes for connection that function as terminals. Also, in Figure 10(A1), at the terminal portion The first terminal 411 is formed of the same material as the gate wiring of transistor 440, and the saw The connecting electrode 412, which is formed from the same material as the wiring, overlaps with the first insulating layer 402. They are in contact and electrically conductive. Also, the connecting electrode 412 and the conductive layer 415 are connected to the second insulating layer 428. Electrical conductivity is established through direct contact via the provided contact holes.

[0160] Furthermore, Figures 10(B1) and 10(B2) show a cross-sectional view and a top view of the source wiring terminal section. Each is illustrated. Also, Figure 10(B1) follows the line C3-C4 in Figure 10(B2). This corresponds to a cross-sectional view. In Figure 10(B1), a conductive layer is formed on the second insulating layer 428. Layer 418 is a terminal electrode for connection that functions as an input terminal. Also, in Figure 10(B1) In the terminal section, an electrode layer 4 is formed from the same material as the gate wiring of transistor 440. 16 is the first insulating layer 402 below the second terminal 414 which is electrically connected to the source wiring. They overlap via the electrode layer 416. The electrode layer 416 is not electrically connected to the second terminal 414, and the electrode layer Set terminal 416 to a different potential from the second terminal 414, for example, floating, GND, 0V, etc. If determined, it can form capacitance for noise suppression or capacitance for electrostatic discharge suppression. Furthermore, the second terminal 414 is electrically connected to the conductive layer 418 via the second insulating layer 428. It continues.

[0161] Multiple gate lines, source lines, common potential lines, and power supply lines are provided according to the pixel density. Furthermore, at the terminal section, the first terminal is at the same potential as the gate wiring, and the source wiring is... The second terminal is at the same potential as the line, the third terminal is at the same potential as the power supply line, and the fourth terminal is at the same potential as the common potential line. Multiple terminals are arranged in a row. The number of each terminal can be set to any number. It is acceptable as long as it is done as is, and the implementer may decide as appropriate. The terminal connections are as shown in Figure 10. It is not limited to that.

[0162] This embodiment can be freely combined with other embodiments.

[0163] (Embodiment 4) In this embodiment, as a semiconductor device according to one aspect of the present invention, two types of transistors are mounted on the same substrate. A pulse output circuit is fabricated using a sta, and then multiple such pulse output circuits are connected to create a shift. Examples of register configurations will be explained using Figures 3 and 4.

[0164] A transistor is defined as having at least three terminals, including a gate, a drain, and a source. It is an element having a channel region between the drain region and the source region, and the drain Current can be passed through the input region, channel region, and source region. The difference between the drain and the source depends on the transistor's structure and operating conditions, so which one is the source? It is difficult to determine whether it is a source or a drain. Therefore, source and drain and The area that functions in this way is sometimes not called the source or drain. In that case, for example, In some cases, these are referred to as the first terminal and the second terminal, respectively.

[0165] Figure 3(A) shows the configuration of the shift register. The shift register is a first pulse output circuit 1 It has pulse output circuits 10_N (where N is a natural number greater than or equal to 3) from 0_1 to the Nth.

[0166] Furthermore, the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are connected to the first wiring 11, connected to the second wiring 12, the third wiring 13, and the fourth wiring 14, and the first wiring 1 The first clock signal CK1 is transmitted from wire 1, and the second clock signal CK2 is transmitted from wire 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. Unit CK4 will be supplied.

[0167] The clock signal (CK) is raised to a high level (H signal, high power supply potential level) at regular intervals. This is a signal that alternates between L level (also called L signal or low power supply potential level). Here, the first clock signal (CK1) to the fourth clock signal (CK4) are sequentially 1 / 4 cycles. There is a delay of a certain period. In this embodiment, the first clock signal (CK1) to the fourth clock The signal (CK4) is used to control the drive of the pulse output circuit, etc. Depending on the input drive circuit, it may also be GCK or SCK, but here we will use CK. Then, I will explain.

[0168] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N has a first input terminal Child 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input terminal It has a child 25, a first output terminal 26, and a second output terminal 27 (see Figure 3(B)). Although not shown in the diagram, it is also connected to power lines 51, 52, and 53. .

[0169] The first input terminal 21, the second input terminal 22, and the third input terminal 23 of the pulse output circuit are It is electrically connected to one of the first wiring 11 to the fourth wiring 14. For example, Figure 3 ( In A), the first pulse output circuit 10_1 has a first input terminal 21 connected to the first wiring 11 The second input terminal 22 is electrically connected to the second wiring 12, and the third Input terminal 23 is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_2 is such that the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is electrically connected to the third wiring 13, and the third input terminal 23 is electrically connected to the fourth wiring 14. They are directly connected.

[0170] Also, in the first pulse output circuit 10_1, the start pulse SP1 from the fifth wiring 15 ( The first start pulse is input. Also, the nth pulse output circuit 10_n for the second stage and beyond. (where n is a natural number between 2 and N) the signal from the pulse output circuit one stage prior (previous stage signal) The input is OUT(n-1) (where n is a natural number greater than or equal to 2).

[0171] Furthermore, in the first pulse output circuit 10_1, from the second-stage third pulse output circuit 10_3 The following signal is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, The signal from the (n+2)th pulse output circuit 10_(n+2) of the stage (the subsequent stage signal OUT(n+ 2) is input. Therefore, from the pulse output circuit of each stage, the subsequent stage and / or two The first output signal OUT((1)(SR)~OU) is input to the preceding pulse output circuit. T(N)(SR)), a second output signal (OUT(1)~) electrically connected to another wire, etc. OUT(N)) is output.

[0172] That is, in the first pulse output circuit 10_1, the first cross is connected to the first input terminal 21. The clock signal CK1 is input, and the second clock signal CK2 is input to the second input terminal 22. The third clock signal CK3 is input to the third input terminal 23, and the fourth input terminal 24 is input to the station A pulse is input, and the subsequent signal OUT(3) is input to the fifth input terminal 25, and the first The first output signal OUT(1)(SR) is output from output terminal 26, and the second output terminal 27 This indicates that the second output signal OUT(1) is being output.

[0173] Furthermore, as shown in Figure 3(A), the last two stages of the shift register (10_N-1, and Although the subsequent signal OUT(n+2) is not input to 10_N), one example is that, separately, The second start pulse SP2 is received from wire 16 of 6, and the third start pulse is received from wire 17 of 7. The configuration should involve inputting each of the RUSP3 values. Alternatively, within the shift register itself... It may also be a generated signal. For example, the (N+1) that does not contribute to the pulse output to the pixel. ) pulse output circuit 10_(N+1), pulse output circuit 10_(N+2) A dummy stage is provided (also called a dummy stage), and a second start pulse (SP2) and The configuration may also generate a signal corresponding to the start pulse (SP3) of step 3.

[0174] Next, the configuration of a pulse output circuit according to one embodiment of the present invention will be explained using Figure 3(C).

[0175] The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N are connected to the power supply line 51 to the power supply. It is connected to line 53. Power line 51 is the first high power supply potential VDD, and power line 52 is the second The high power supply potential VCC is supplied by power line 53, and the low power supply potential VSS is supplied by power line 51. The relative magnitudes of the power supply potentials of power supply lines 53 are such that, for example, the first high power supply potential VDD is equal to the second high power supply potential The potential is equal to VCC or higher than the second high power supply potential VCC, and the second high power supply potential VC It is assumed that C is at a higher potential than the low power supply potential VSS. Also, the potential VCC of the power line 52 is assumed to be By lowering the potential of source line 51 below VDD, the transients can be controlled without affecting operation. The potential applied to the gate electrode of the transistor can be kept low, and the threshold shift of the transistor can be reduced. This reduces waste and suppresses deterioration.

[0176] The first clock signal (CK1) to the fourth clock signal (CK4) are transmitted at regular intervals. This is a signal that alternates between high and low levels, where VDD is at the high level and V is at the low level. Let's assume it's SS.

[0177] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is a first pulse It has transistors 31 to the 11th transistor 41 (see Figure 3(C)). In this configuration, two types of transistors are fabricated on the same substrate to form a pulse output circuit. Oh, the first pulse output circuit 10_1~ of the shift register illustrated in this embodiment Since the pulse output circuit 10_N of N has the same configuration, here the first pulse output The configuration and operation of circuit 10_1 will be explained.

[0178] The first pulse output circuit 10_1 consists of the first transistor 31 to the eleventh transistor 41. It has the following: The first transistor 31 to the eleventh transistor 41 are n-channel type transistors. A lunger having a highly purified oxide semiconductor layer. In particular, a channel formation region Using an oxide semiconductor layer that has been purified to a high degree and has suppressed carrier concentration, and having a positive threshold voltage A bottom-gate type transistor with extremely low and suppressed off-current is used as the second transistor. This applies to transistor 32 and the fifth transistor 35.

[0179] Furthermore, the pulse output circuit of this embodiment, and a configuration formed by connecting multiple such pulse output circuits. In a shift register, an external signal is input directly to the gate electrode of a transistor. A bottom-gate transistor is also suitable. For example, the first pulse output circuit 10_1 In this case, the first is connected to the fourth input terminal 24 to which a start pulse is input from an external source. Transistor 31 and the fifth transistor 35 can be cited as examples. Gate-type transistors have high breakdown voltage between the gate and source or between the gate and drain. For example, abnormal inputs such as static electricity can cause failures such as fluctuations in the transistor's threshold. This can suppress it.

[0180] Also, the third transistor 33, the sixth transistor 36, the tenth transistor 40, And as the 11th transistor 41, formed on the surface layer of the highly purified oxide semiconductor layer A top-of-the-line A gate-type transistor is used.

[0181] Note that the top-gate type transistor and the bottom-gate type transistor are as described in the embodiment. The top-gate type transistors 450, 470 and bottom described in Embodiment 1 or Embodiment 2 Since it can be manufactured according to the method for manufacturing the gate-type transistors 440 and 460, this implementation I will omit the explanation regarding the form.

[0182] Furthermore, the first transistor 31, the fourth transistor 34, the seventh transistor 37, and so on. The ninth transistor 39 is, for example, a top-gate type transistor, or a bottom-gate type transistor. Either type of transistor can be used, but in this embodiment, a bottom-gate type is applied. It shall be done.

[0183] In Figure 3(C), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate electrode is It is electrically connected to input terminal 24 of 4. The second transistor 32 has the first terminal electrically connected. It is electrically connected to the source line 53, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. It is connected, and the gate electrode is electrically connected to the gate electrode of the fourth transistor 34. The third transistor 33 has its first terminal electrically connected to the first input terminal 21, and the second The terminal is electrically connected to the first output terminal 26. The fourth transistor 34 is the first The terminal is electrically connected to the power line 53, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 53, and its second terminal The terminals are connected to the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34. Electrically connected, the gate electrode is electrically connected to the fourth input terminal 24. The sixth The transistor 36 has its first terminal electrically connected to the power line 52, and its second terminal connected to the second transistor The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. The gate electrode is electrically connected to the fifth input terminal 25. The seventh transistor 37 The first terminal is electrically connected to the power line 52, and the second terminal is connected to the eighth transistor 38. It is electrically connected to terminal 2, and the gate electrode is electrically connected to the third input terminal 23. The eighth transistor 38 has its first terminal connected to the gate electrode of the second transistor 32 and the fourth The gate electrode of transistor 34 is electrically connected, and the gate electrode is connected to the second input terminal 22 It is electrically connected to the first transistor 39. The first terminal of the ninth transistor 39 is connected to the first transistor The second terminal of 31 and the second terminal of the second transistor 32 are electrically connected, and the second terminal is The gate electrode of the third transistor 33 and the gate electrode of the tenth transistor 40 are electrically charged. The terminal is connected to the power line 52. The tenth transistor The terminal 40 has its first terminal electrically connected to the first input terminal 21, and its second terminal is connected to the second output terminal. It is electrically connected to child 27, and the gate electrode is electrically connected to the second terminal of the ninth transistor 39. It is connected. The 11th transistor 41 has its first terminal electrically connected to the power line 53. The second terminal is electrically connected to the second output terminal 27, and the gate electrode is connected to the second transistor The gate electrode of transistor 32 and the gate electrode of the fourth transistor 34 are electrically connected. .

[0184] Note that in Figure 3(C), the gate electrode of the third transistor 33 and the tenth transistor The connection point between the gate electrode of transistor 40 and the second terminal of transistor 39 (number 9) is designated as node A. Also, the gate electrode of the second transistor 32 and the gate electrode of the fourth transistor 34 , the second terminal of the fifth transistor 35, the second terminal of the sixth transistor 36, the eighth transistor The connection point between the first terminal of transistor 38 and the gate electrode of transistor 41 (number 11) is not Let this be node B. Furthermore, in order to maintain the potential of node B, one electrode is electrically connected to node B. A separate capacitive element may be provided. Specifically, one electrode of the capacitive element may be connected to node B. One end can be connected electrically, and the other end electrically connected to the power line 53.

[0185] Next, refer to Figures 4(B), 5-7 for the operation of the pulse output circuit shown in Figure 4(A). Let me explain. Specifically, the first period shown in the timing chart in Figure 4(B) 61. Divided into a second period 62, a third period 63, a fourth period 64, and a fifth period 65. The operation of the LS output circuit will be explained. Note that in Figures 5 and 6, the transistors are shown with solid lines. When indicating this, it means the transistor is in the ON state (conducting state), and this is indicated by a dashed line. In this case, it indicates that the transistor is in the off state (non-conductive state).

[0186] Here, we will explain the output of the first pulse output circuit 10_1. The path 10_1 is the first distribution to which the first input terminal 21 supplies the first clock signal (CK1). The second input terminal 22 is electrically connected to line 11 and supplies the second clock signal (CK2). The second wiring 12 is electrically connected, and the third input terminal 23 receives the third clock signal (C It is electrically connected to a third wiring 13 that supplies K3).

[0187] In the following explanation, the first transistor 31 to the eleventh transistor 41 are N Assuming a channel-type transistor, the gate-source voltage (Vgs) is equal to the threshold voltage (Vt It is assumed that conduction occurs when the value exceeds h).

[0188] Furthermore, for the sake of simplicity in this explanation, we will assume VSS=0, but this is not the only option. Note that VD The difference between D and VCC, and the difference between VCC and VSS (if VDD > VCC) are... It is assumed that the voltage will be greater than the threshold voltage of the transistor, i.e., the transistor will be in the ON state. The circuit shall be made conductive. Furthermore, the potential of power line 52 shall be lower than the potential of power line 51. As a result, the second transistor 32, the fourth transistor 34, and the ninth transistor 3 The potential applied to the gate electrodes of transistors 9 and 11 41 is kept low, and the pulse The second transistor 32, the fourth transistor 34, and the ninth transistor 3 of the output circuit By reducing the threshold shift of transistors 9 and 11 41, degradation can be suppressed. Cut.

[0189] During the first period 61, the first start pulse (SP1) becomes H level, and the first S The fourth input terminal 2 of the first pulse output circuit 10_1 to which the tart pulse (SP1) is input. The first transistor 31 and the fifth transistor 35, which are electrically connected to 4, enter a conductive state. Yes. Also, since the third clock signal (CK3) is at a high level, the seventh transistor 3 7 is also turned on. In addition, the gate of the ninth transistor 39 is marked with the second high power supply potential VCC. This is added, and the ninth transistor 39 is also turned on (see Figure 5(A)).

[0190] At this time, the first transistor 31 and the ninth transistor 39 are on, so the node The potential at A rises. Also, because the fifth transistor 35 is on, the potential at node B is It descends.

[0191] Furthermore, the potential of the second terminal of the first transistor 31 is the same as the potential of the second terminal of the first transistor 31 This serves as the source, and the threshold voltage of the first transistor 31 is determined from the potential of the first power line 51. Since it is the value obtained by subtracting VDD-Vth31 (Vth31 is the first transistor 31) The threshold voltage (Vth39) of the ninth transistor 39 and Vt In h31, if (VDD-Vth31) is greater than or equal to (VCC-Vth39), then no. The potential at node A becomes VCC-Vth39, and the 9th transistor 39 turns off, and node A It remains in a floating state while maintaining the potential (VCC-Vth39). Also, (VDD-Vth3 1) If (VCC - Vth39) is less than (VCC - Vth39), the 9th transistor 39 will turn off. Node A rises to the potential (VDD-Vth31).

[0192] In this embodiment, the first transistor 31 to the eleventh transistor 41 are all the same. Because it has a threshold voltage Vth0, the potential of node A becomes (VCC-Vth0). The ninth transistor 39 turns off, and node A maintains its potential (VCC-Vth0). It enters a state of floating.

[0193] Here, in the third transistor 33, the potential of the gate electrode is (VCC-Vth0) The voltage between the gate and source of the third transistor 33 exceeds its threshold. That is, VCC-Vth0>Vth33 (Vth33 is the third transistor 3 The threshold voltage of 3, which in this embodiment is Vth0, is therefore the third transistor The TA33 is turned on.

[0194] During the second period 62, the first input terminal 21 of the first pulse output circuit 10_1 is first The clock signal (CK1) switches from low level to high level. The third transient has already occurred. Because sta33 is on, a current is generated between the source and drain and appears at output terminal 26. The potential of the output signal (OUT(1)(SR)), that is, the second of the third transistor 33 The potential of the electrode (in this case, the source electrode) begins to rise. The gate of the third transistor 33 Capacitive coupling exists between the source and the output terminal due to parasitic capacitance, and as the potential of the output terminal 26 rises, The potential of the gate electrode of the third transistor 33, which is in a idle state, rises (bootst). (Lapping operation). Ultimately, the potential of the gate electrode of the third transistor 33 is (VDD+ The potential of output terminal 26 becomes higher than Vth33 and equals VDD (Figure 4(B), Figure 4(B) 5(B)).

[0195] Also, at this time, the fourth input terminal 24 of the first pulse output circuit 10_1 is the first start Because the pulse (SP1) is at an H level, the fifth transistor 35 turns on and the node B is maintained at an L level. Therefore, the potential of output terminal 26 changes from an L level to an H level. When starting up, malfunctions caused by capacitive coupling between output terminal 26 and node B can be suppressed. ru.

[0196] Next, in the first half of the third period 63, the first start pulse (SP1) was at the L level and Then the first transistor 31 and the fifth transistor 35 turn off. Also, the second period 6 Following step 2, the first clock signal (CK1) maintains a high level, and the potential of node A also changes. To prevent this from happening, a high-level signal is supplied to the first electrode of the third transistor 33. See Figure 5(C). In addition, during the first half of the third period 63, each transistor connected to node B The terminal is turned off and node B is in a floating state, but the potential of output terminal 26 does not change, so The impact of the capacitive coupling between the B channel and output terminal 26 is almost negligible.

[0197] As shown in Figure 4(A), the ninth gate is subjected to a second high power supply potential VCC. By installing the Rangista 39, the following occurs before and after the bootstrap operation: It has advantages like these.

[0198] If there is no ninth transistor 39 to which the second high power supply potential VCC is applied to the gate electrode, When the potential of node A rises due to the bootstrap operation, the first transistor 31 The potential of the two source terminals rises and becomes greater than the first high power supply potential VDD. Then, the source of the first transistor 31 switches to the first terminal side, that is, to the power line 51 side. Therefore, in the first transistor 31, between the gate and source, and between the gate and drain, During this time, a large bias voltage is applied, causing significant stress on the transient. This could be a factor in the deterioration of the stamina.

[0199] Therefore, a ninth transistor 39 is provided to which a second high power supply potential VCC is applied to the gate electrode. By leaving it as is, although the potential of node A rises due to the bootstrap operation, This prevents an increase in the potential of the second terminal of transistor 31. By providing the ninth transistor 39, the gate and socket of the first transistor 31 are connected. The value of the negative bias voltage applied between the two can be reduced. Therefore, this implementation By using this circuit configuration, a mark is made between the gate and source of the first transistor 31. The applied negative bias voltage can also be reduced, thus reducing stress on the first transistor 31 This can suppress deterioration.

[0200] Furthermore, the location where the ninth transistor 39 is installed is the second transistor 31 The terminal is connected to the gate of the third transistor 33 via the first and second terminals. Any configuration that is set up in this manner is acceptable. Note that the pulse output circuit in this embodiment may be equipped with multiple pulse output circuits. In the case of a sub-register, the signal line drive circuit requires higher dynamic characteristics than the scan line drive circuit. The ninth transistor, 39, can be omitted, which has the advantage of reducing the number of transistors.

[0201] In the latter half of the third period 63, the third clock signal (CK3) switches to the H level. Then, the seventh transistor 37 turns on. Also, following the first half of the third period 63, the second The clock signal (CK2) remains at a high level, and the eighth transistor 38 is on. The potential at node B rises to VCC.

[0202] Because the potential of node B increased, the second transistor 32 and the fourth transistor 34 and The 11th transistor 41 turns on, and the potential of the output terminal 27 (OUT(1)) becomes L It becomes a bell.

[0203] Furthermore, in the latter half of the third period 63, the second transistor 32 turns on, and the ninth transistor Since an L-level signal is supplied to the first terminal of transistor 39, the ninth transistor 39 The device turns on, and the potential at node A drops.

[0204] Furthermore, when the fourth transistor 34 turns on, the potential of the output terminal 26 decreases. (See Figure 5(D)).

[0205] In the first half of the fourth period 64, the second clock signal (CK2) changes from a high level to a low level. As it switches to this state, the 8th transistor 38 turns off. However, the 5th input terminal By maintaining a high level at 25(OUT(3)), the sixth transistor 36 turns on. Because of this state, node B will hold VCC. (See Figure 6(A)).

[0206] Subsequently, in the latter half of the fourth period 64, the fifth input terminal 25 of the first pulse output circuit 10_1 (OUT(3)) becomes L level, and the sixth transistor 36 turns off (see Figure 6(B)). (Illuminate). At this time, node B changes from a state where it maintains the VCC level to a floating state. Furthermore, the second transistor 32, the fourth transistor 34, and the eleventh transistor 4 The state remains ON. However, as shown in Figure 4(B), the potential of node B is V The signal level will drop from the CC level due to factors such as the transistor's off-current.

[0207] Subsequently, the circuit repeats a periodic operation. This period is designated as the fifth period (Figure 6(C)). See Figure 6(D). A fifth period 65 is a period in which the second clock signal (CK2) and When both of the three clock signals (CK3) are at a high level, the seventh transistor Transistors 37 and 38 turn on, and a VCC-level signal is periodically supplied to node B. (See Figure 6(D)).

[0208] Thus, the configuration is such that a VCC-level signal is periodically supplied to node B during the fifth period 65. This can suppress malfunctions in the pulse output circuit. Also, the seventh transistor By periodically switching transistor 37 and the eighth transistor 38 on or off, This makes it possible to reduce the threshold shift of the transistor.

[0209] Furthermore, during the fifth period 65, a VCC level signal is supplied to node B from power line 52. If the potential of node B drops while it is not being worked, a capacitive element should be installed at node B beforehand. A configuration that mitigates the decrease in potential at B may also be used.

[0210] Furthermore, the connection between the second input terminal 22 and the gate electrode of the eighth transistor 38, and the third input By swapping the connections between terminal 23 and the gate electrode of the 7th transistor 37, the 8th transistor The clock signal that was supplied to the gate electrode of transistor 38 is now supplied to the gate electrode of the seventh transistor 37. The clock signal that was supplied to the pole and to the gate electrode of the 7th transistor 37 is now supplied to the 8th The same effect is achieved when supplied to the gate electrode of transistor 38.

[0211] In the pulse output circuit shown in Figure 4(A), the second input terminal 22 and the third input terminal 23 By controlling the potential, both the seventh transistor 37 and the eighth transistor 38 are turned ON. From this state, the seventh transistor 37 is off and the eighth transistor 38 is on. Subsequently, when both the seventh transistor 37 and the eighth transistor 38 are turned off, The potential of the gate electrode of the 7th transistor 37 decreases, and the gate electrode of the 8th transistor 38 decreases. The decrease in the potential of the electrode results in a decrease in the potential of node B occurring twice.

[0212] On the other hand, in the pulse output circuit shown in Figure 4(A), as shown in Figure 4(B), the seventh to When transistors 37 and 8 and 38 are both ON, the 7th transistor 37 is ON, and after passing through the state where the 8th transistor 38 is OFF, the 7th transistor 3 When transistors 7 and 8 38 are both turned off, the gate of transistor 8 38 A decrease in the potential of the electrode causes a decrease in the potential of node B only once, and the number of times the potential decreases The number of steps can be reduced to one.

[0213] In other words, the gate electrode of the seventh transistor 37 receives a clock signal from the third input terminal 23. The clock signal is supplied to the gate electrode of the eighth transistor 38 from the second input terminal 22. Supplying this reduces the potential fluctuations at node B, which in turn reduces noise, thus being preferable. It is suitable.

[0214] In this way, the period during which the potential of the first output terminal 26 and the second output terminal 27 is maintained at the L level In between, by configuring the system so that a VCC-level signal is periodically supplied to node B, This can suppress malfunctions in the output circuit.

[0215] Node B of the pulse output circuit described in this embodiment is VCC in the latter half of the fourth period 64. The bell transitions from a state of being held to a floating state. The potential of node B in the floating state is the fifth transient. There is a risk that the VCC level may drop due to the off-current of ST35, etc. However, in this implementation The fifth transistor 35 of the pulse output circuit in this configuration has a channel formation region that is highly purified. A bottom-gate transistor with extremely low off-current suppression using an oxide semiconductor layer. Because a zista is used, the potential of node B in a floating state is well maintained, from the VCC level. The decrease is minimal. As a result, malfunctions in semiconductor devices are suppressed, and reliability is improved.

[0216] Furthermore, in order to suppress the off-current of the transistor, the gate electrode is made into a double-gate structure, Because it does not require a multi-gate structure such as a pull-gate structure, the transistor can be miniaturized. It is possible. Furthermore, the capacitive element required to maintain the potential of node B is either unnecessary or can be miniaturized. A pulse output circuit constructed using such miniaturized elements, or a miniaturized... By using a shift register configured with a pulse output circuit, a semiconductor device can be used. This will allow for overall miniaturization.

[0217] Furthermore, a bottom-gate type trailer using a highly purified oxide semiconductor layer in the channel formation region. The inverter not only has an extremely low and suppressed off-current, but also has a positive threshold voltage. In the pulse output circuit of this embodiment, the second transistor 32 is made of highly purified oxidized material. Because it uses a bottom-gate type transistor with a solid semiconductor layer, bootstrap When increasing the potential of node A through operation, it can be raised quickly with minimal loss. As a result, Malfunctions in semiconductor devices are suppressed, improving reliability.

[0218] Furthermore, in the pulse output circuit of this embodiment, the third transistor 33 and the sixth transistor Transistor 36, the 10th transistor 40, and the 11th transistor 41 are made of high-purity material. A top-gate type transient using the crystalline region of the oxide semiconductor layer as the channel formation region. A stylus is used. The crystalline region of the highly purified oxide semiconductor layer is used as the channel formation region. Top-gate transistors have excellent frequency characteristics and high field-effect mobility, therefore, 3 transistors 33, 6 transistor 36, 10 transistor 40, and 1 The switching operation of transistor 41 can be made faster. Also, the transistor can be made smaller It can be typed.

[0219] A pulse output circuit configured using such high-speed elements, or a high-speed By using a shift register configured with a pulse output circuit, the entire semiconductor device This will enable faster processing.

[0220] Furthermore, the shift register shown in this embodiment, as shown in Figure 7(A), is the mth pulse The pulse output from the output circuit and the pulse output from the (m+1)th pulse output circuit It uses a drive method that overlaps by half (1 / 4 cycle). This is different from conventional shift registers. The pulse output from the mth pulse output circuit and the (m+1)th pulse output circuit Compared to a driving method where the output pulses do not overlap (see Figure 7(B)), this method charges the wiring. The time can be doubled. In this way, the pulse output from the mth pulse output circuit The pulses output from the (m+1) pulse output circuit overlap by half (1 / 4 period). By using this drive method, a large load can be applied and it can operate at a high frequency. It is possible to provide a pulse output circuit that can significantly change the operating conditions of the pulse output circuit. It is possible.

[0221] Note that the shift register and pulse output circuit shown in this embodiment are not included in other embodiments described herein. This can be implemented in combination with the configuration of the shift register and pulse output circuit shown in the implementation form. It is possible. Furthermore, the invention of this embodiment can also be applied to semiconductor devices. A semiconductor device is a device that functions by utilizing the properties of semiconductors.

[0222] (Embodiment 5) In this embodiment, two types of transistors are used on the same substrate as described in Embodiment 4. The fabricated shift register has a highly purified oxide semiconductor layer in the channel formation region. By combining switching circuits using transistors, an active matrix display device This section describes an example of a drive circuit configuration for an active-matrix display device. The overview of the device will be explained using a block diagram, and then the shift register that the display device has will be explained. The signal line driving circuit and scan line driving circuit used will be described below.

[0223] An example of a block diagram of an active-matrix display device is shown in Figure 8(A). On the plate 5300 are a pixel section 5301, a first scan line drive circuit 5302, and a second scan line drive It has a circuit 5303 and a signal line driving circuit 5304. The pixel section 5301 has multiple signal lines. Multiple scan lines are arranged extending from the signal line drive circuit 5304, and multiple scan lines are driven by the first scan line drive circuit 5 302, and the second scan line drive circuit 5303 are arranged as extensions. In the regions where the signal lines intersect, pixels, each containing a display element, are arranged in a matrix. Furthermore, the substrate 5300 of the display device is FPC (Flexible Printed Circuit). The timing control circuit 5305 (controller, control IC) is connected via a connection part such as cuit. It is connected to (also known as).

[0224] The transistors placed in the pixel section 5301 are as described in Embodiment 1 or Embodiment 2. A transistor according to one aspect of the present invention can be applied. The transistor used in the pixel section 5301 is a bo A Tomgate type is particularly preferred, for example, the transistor 44 shown in Embodiment 1 or 2. Transistor 0, or transistor 460, can preferably be used. Bottom gate type transistor Because the ZISTA has low off-current, it can not only increase the contrast of the displayed image, but also the display The power consumption of the device can be reduced.

[0225] Note that the transistor described in Embodiment 1 or Embodiment 2 is an n-channel type transistor. Because it is a sta, it is one of the drive circuits that can be constructed with n-channel transistors. The part is formed on the same substrate as the transistor in the pixel section.

[0226] Figure 8(A) shows the first scan line drive circuit 5302, the second scan line drive circuit 5303, and the signal The line drive circuit 5304 is formed on the same substrate 5300 as the pixel section 5301. Therefore, Since the number of components such as drive circuits installed outside the display device is reduced, costs can be reduced. It is possible. Also, if a drive circuit is provided outside the circuit board 5300, it becomes necessary to extend the wiring. The number of connections between wires increases. If a drive circuit is provided on the same board 5300, the number of connections between those wires increases. The number of successors can be reduced, leading to improved reliability or yield.

[0227] The timing control circuit 5305 is, for example, related to the first scan line drive circuit 5302. The first scan line drive circuit start signal (GSP1), the scan line drive circuit clock signal (GCK1) is supplied. The timing control circuit 5305 also supplies the second scan line drive circuit For example, for 5303, the start signal (GSP2) for the second scan line drive circuit (start) It supplies the clock signal (GCK2) for the scan line drive circuit (also called a pulse). The drive circuit 5304 receives a start signal (SSP) for the signal line drive circuit and a crossover signal for the signal line drive circuit. SCK signal, video signal data (DATA) (also simply called video signal), A clock signal (LAT) shall be supplied. Each clock signal shall consist of multiple signals with different periods. It can be a clock signal, or it can be supplied along with an inverted clock signal (CKB). It may also be a first scan line drive circuit 5302 and a second scan line drive circuit 53 It is possible to omit either 03 or 03.

[0228] In Figure 8(B), a circuit with a relatively low drive frequency (for example, the first scan line drive circuit 5302) is shown. The second scan line drive circuit (5303) is formed on the same substrate (5300) as the pixel section (5301), and the drive is performed. A configuration in which a signal line driving circuit 5304 with a relatively high frequency is formed on a separate substrate from the pixel section 5301. This shows the characteristics. For example, using a transistor made of a single crystal semiconductor, the driving frequency The signal line drive circuit 5304, which has a relatively high frequency, can also be formed on a separate board. Therefore, This can lead to larger display devices, reduced processing steps, lower costs, or improved yield. can.

[0229] In this embodiment, the signal line drive circuit 5304, which has a relatively high drive frequency, is used in the pixel section 53 It shall be formed on the same substrate 5300 as 01. Furthermore, a drive circuit shall be provided on the substrate 5300. This reduces the number of connections between wires, improving reliability or yield. It is possible.

[0230] Next, we will discuss an example of the configuration and operation of a signal line drive circuit composed of n-channel transistors. This will be explained using Figures 9(A) and 9(B).

[0231] The signal line driving circuit includes a shift register 5601 and a switching circuit 5602. Switching circuit 5602 is a switching circuit 5602_1~5602_N (where N is natural). It has multiple circuits, each of which is called a number. Switching circuits 5602_1 to 5602_N are, , multiple transistors called transistors 5603_1 to 5603_k (where k is a natural number) It has. In this embodiment, transistors 5603_1 to 5603_k have n channels This section describes a configuration that applies a type 1 transistor.

[0232] Regarding the connection relationships of the signal line drive circuit, Figure 9(A) shows the switching circuit 5602_1 as an example. This will be explained using (). The first terminals of transistors 5603_1 to 5603_k are, respectively, Connected to lines 5604_1~5604_k. Transistors 5603_1~5603_k The second terminals are connected to signal lines S1 to Sk, respectively. Transistors 5603_1 to 56 The gate of 03_k is connected to wiring 5605_1.

[0233] The shift register 5601 sequentially sends high-level signals to wiring 5605_1 to 5605_N. It has the function of outputting and sequentially selecting switching circuits 5602_1 to 5602_N. Furthermore, the shift register 5601 can be created using the method described in Embodiment 4, therefore, I will omit the detailed explanation.

[0234] Switching circuit 5602_1 consists of wiring 5604_1~5604_k and signal lines S1~Sk A function to control the conductivity state (conduction between the first terminal and the second terminal), i.e., wiring 5604_ It has a function to control whether or not to supply potentials between 1 and 5604k to signal lines S1 and Sk. Thus, the switching circuit 5602_1 functions as a selector. Rangings 5603_1 to 5603_k are connected to wiring 5604_1 to 5604_k respectively. A function to control the conductivity state with lines S1~Sk, i.e., the electrical conductivity of wiring 5604_1~5604_k It has the function of supplying power to signal lines S1~Sk. Thus, transistor 5603_1 Each of the ~5603_k units functions as a switch.

[0235] In this embodiment, the transistor used in the switching circuit 5602 is, for example, an embodiment As in transistor 450 of form 1, the crystalline region of the highly purified oxide semiconductor layer is A top-gate type transistor is used in the channel formation region. The inverter has excellent frequency response and fast switching operation. Therefore, it is ideal for high-resolution displays with a large number of pixels. It can handle the high-speed writing required by generational display devices. A transistor using a layer as a channel formation region is formed by the method described in Embodiment 1 or 2. Since it can be manufactured, a detailed explanation will be omitted here.

[0236] Note that wiring 5604_1 to 5604_k each contain video signal data (DATA). The input is video signal data (DATA), which is image information or analog corresponding to the image signal. It is often a G signal.

[0237] Next, regarding the operation of the signal line drive circuit in Figure 9(A), refer to the timing chart in Figure 9(B). Refer to the explanation. Figure 9(B) shows signals Sout_1 to Sout_N and signal Vda An example of ta_1~Vdata_k is shown. Signals Sout_1~Sout_N are, respectively, This is an example of the output signals of the 5601 register, where signals Vdata_1 to Vdata_k are These are examples of signals input to wiring 5604_1~5604_k, respectively. One operating period of the drive circuit corresponds to one gate selection period in the display device. The period is divided into, for example, period T1 to period TN. Each of periods T1 to TN is selected. This is the period for writing video signal data (DATA) to the pixels belonging to the row.

[0238] Note that the signal waveform distortions, etc., of each configuration shown in the drawings, etc. of this embodiment are for clarity. The figures may be exaggerated for aesthetic reasons. Therefore, they are not necessarily limited to that scale. It should be noted that...

[0239] During periods T1 to TN, the shift register 5601 receives a high-level signal via wiring 560 Outputs are sent sequentially from 5_1 to 5605_N. For example, during period T1, shift register 5 601 outputs a high-level signal to wire 5605_1. Then transistor 56 Since 03_1~5603_k will be turned on, connect the wiring 5604_1~5604_k and the signal wire S1 to Sk become conductive. At this time, Da is connected to wiring 5604_1 to 5604_k. ta(S1)~Data(Sk) are input. Data(S1)~Data(Sk) are Each of the pixels belonging to the selected row is accessed via transistors 5603_1 to 5603_k. Of these, the pixels from the 1st to the kth column are written. In this way, during the period T1 to TN, the selected Video signal data (DATA) is written sequentially to the pixels belonging to the selected row, in k columns at a time. It can be done.

[0240] As described above, video signal data (DATA) is written to pixels in multiple columns. This allows for a reduction in the number of video signal data (DATA) or the number of wires. Therefore, the number of connections to external circuits can be reduced. Also, the video signal is displayed in multiple columns. By writing directly, the writing time can be extended, and the video signal can be written. This can prevent overcrowding and under-concentration.

[0241] Furthermore, the shift register 5601 of the drive circuit in this embodiment is as described in Embodiment 4. Because it uses a shift register, malfunctions are suppressed, resulting in high reliability. By using a miniaturized shift register, it becomes possible to miniaturize the entire drive circuit. ru.

[0242] Furthermore, the switching circuit 5602 of the drive circuit in this embodiment uses a highly purified oxide By applying a top-gate type transistor that uses the crystalline region of the semiconductor layer as the channel formation region, Therefore, the switching operation is fast. For this reason, the drive circuit illustrated in this embodiment is for pixels It enables high-speed writing and is suitable for next-generation display devices with a large number of pixels and high resolution.

[0243] Furthermore, the shift register described in Embodiment 4 can also be applied to the scan line driving circuit. The drive circuit includes a shift register. In some cases, it may also include a level shifter or buffer. It may also have the following: In a scan line driving circuit, a clock signal (CL) is set to the shift register. A selection signal is generated when K) and the start pulse signal (SP) are input. The generated selection signal is buffered and amplified in a buffer and then supplied to the corresponding scan line. The scan line is connected to the gate electrode of the transistor for one pixel line. Since the transistors for all the pixels in one line must be turned ON simultaneously, the buffer is large. A device capable of conducting a large current is used.

[0244] Furthermore, the active matrix display device and the external device described in this embodiment are connected via a terminal. They are connected in this way. Therefore, due to abnormal input from the outside (for example, static electricity), the transient To prevent malfunctions such as fluctuations in the threshold voltage, a protection circuit is provided within the drive circuit. Because of its high breakdown voltage between the gate and source, and between the gate and drain, it is used in protective circuits. As the transistor, the bottom-gate type transistor shown in Embodiment 1 or 2 is preferred. be.

[0245] (Embodiment 6) A transistor is fabricated as shown in Embodiment 1 or 2, and the transistor is used in the pixel section, and furthermore, It is possible to manufacture a semiconductor device (also called a display device) that has a display function by using it in a drive circuit. It is possible. Also, the transistor shown in Embodiment 1 or 2 can be used as part of or as part of the drive circuit. The pixel section can be integrally formed on the same substrate, allowing for the creation of a system-on-panel configuration.

[0246] A display device includes display elements. Display elements include liquid crystal elements (also called liquid crystal display elements) and light-emitting elements. A light-emitting element (also called a light-emitting display element) can be used. The light-emitting element is activated by current or voltage. This category includes elements whose brightness is controlled, specifically inorganic EL (Electrical LEDs). This includes Luminescence, organic EL, etc. Also, electronic inks, etc. Display media in which contrast changes due to the effect can also be applied.

[0247] Furthermore, the display device includes a panel in which the display elements are sealed, and a controller on the panel. It includes a module on which ICs and the like are mounted. Furthermore, it is a device for manufacturing the display device. With respect to an element substrate that corresponds to one form before the display element is completed in the process, the element substrate is The element substrate is specifically provided with means for supplying current to the display element in each of the multiple pixels. This may be a state where only the pixel electrodes of the display element are formed, or a conductive film that will serve as the pixel electrode may be formed. This may be the state after the film has been formed but before etching to form the pixel electrodes. All forms apply.

[0248] In this specification, the term "display device" refers to an image display device, a display device, or an optical display device. This refers to the power source (including lighting equipment). It also refers to connectors, such as FPC (Flexible Printed Circuit). (inted circuit) or TAB (Tape Automated Bon) (ding) tape or TCP (Tape Carrier Package) Modules that have a printed circuit board attached to the end of the TAB tape or TCP. The display element or IC (integrated circuit board) is integrated using the COG (Chip On Glass) method. All modules in which the road is directly implemented are also included in the display device.

[0249] In this embodiment, the appearance and cross-section of a liquid crystal display panel, which corresponds to one form of semiconductor device, Next, we will explain using Figure 11. Figure 11(A1)(A2) shows the formation on the first substrate 4001. The In-Ga-Zn-O system film shown in Embodiment 1 or 2 is used as an oxide semiconductor layer. The second base includes highly reliable transistors 4010 and 4011, and liquid crystal element 4013. Figure 11 shows a top view of the panel, which is sealed between plate 4006 and a sealing material 4005. (B) corresponds to the cross-sectional view at MN in Figure 11(A1)(A2).

[0250] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0251] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding or TAB method can be used. Figure 11(A1) shows This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 11(A2) is TAB This is an example of implementing the signal line drive circuit 4003 according to the law.

[0252] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple transistors, and in Figure 11(B), the transistors included in the pixel section 4002 The transistor 4010 and the transistor 4011 included in the scan line drive circuit 4004 are shown as examples. There are insulating layers 4020 and 4021 provided on transistor 4010, and the transistor An insulating layer 4021 is provided on 4011. The insulating layer 4020 is on transistor 401 It functions as a gate insulating layer.

[0253] On the insulating layer 4020, the channel shape of the oxide semiconductor layer of the transistor 4010 in the pixel portion A conductive layer 4042 is provided in a position that overlaps with the formation region. The conductive layer 4042 is an oxide semiconductor By placing it in a position that overlaps with the channel formation region of the layer, the transition before and after the BT trial The change in threshold voltage of the zista 4010 can be reduced. Also, conductive layer 4042 The potential may be the same as or different from that of the gate electrode layer of transistor 4010. It can also function as a second gate electrode layer. Furthermore, if the potential of the conductive layer 4042 is G It may be ND, 0V, or floating. Note that the conductive layer 4042 is a trap It can be manufactured using the same materials and process as the gate electrode layer of the 4011.

[0254] Transistors 4010 and 4011 use an In-Ga-Zn-O system film as the oxide semiconductor layer. The transistors shown in the highly reliable embodiment 1 or 2 can be applied. In this embodiment, transistors 4010 and 4011 are n-channel type transistors. ru.

[0255] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the transistor 4010. It is connected to the second substrate 4006. The counter electrode layer 4031 of the liquid crystal element 4013 is connected to the second substrate 4006. The pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 are formed on top of each other. The part that is made up corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode Layer 4031 is provided with insulating layers 4032 and 4033, which function as alignment films, and is insulating The liquid crystal layer 4008 is sandwiched between layers 4032 and 4033. (Note: This is not shown in the diagram.) However, the color filter is provided on either the first substrate 4001 or the second substrate 4006. That's good too.

[0256] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically, glass). Stainless steel, ceramics, and plastics can be used. , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film Film can be used. Also, aluminum foil can be used with PVF film or polyester. It is also possible to use a sheet with a structure sandwiched between layers of film.

[0257] Furthermore, spacer 4035 is a columnar spacer obtained by selectively etching the insulating film. This controls the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. It is provided for this purpose. A spherical spacer may also be used. Furthermore, the counter electrode layer 4031 is electrically connected to a common potential line located on the same board as transistor 4010. It is done. Using a common connection part, the opposing electrode layer is connected via conductive particles placed between the pair of substrates. 4031 and the common potential line can be electrically connected. Note that the conductive particles are a sealing material. It will be included in 4005.

[0258] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs. c. The duration is short, less than 100 μsec, and is optically isotropic, so orientation treatment is unnecessary. It has little dependence on the field of view.

[0259] Although this embodiment is an example of a transmissive liquid crystal display device, the present invention can also be applied to a reflective liquid crystal display device. It can also be applied to semi-transmissive liquid crystal display devices.

[0260] Furthermore, in the liquid crystal display device of this embodiment, a polarizing plate is provided on the outside (viewing side) of the substrate, and on the inside An example is shown where the colored layer and the electrode layer used for the display element are arranged in that order, but the polarizing plate is placed on the inside of the substrate. It may also be done. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the polarizing plate and The coloring layer and the manufacturing process conditions should be set appropriately. A light-shielding film that functions in this way may be provided.

[0261] Furthermore, in this embodiment, in order to reduce surface irregularities caused by transistors, and transistors To improve the reliability of the transistor, the transistor obtained in Embodiment 1 or 2 is protected with a protective film or The structure is covered with insulating layers (insulating layer 4020, insulating layer 4021) that function as a planar insulating film. The protective film is designed to block organic matter, metallic substances, water vapor, and other pollutants and impurities suspended in the atmosphere. This is to prevent the intrusion of [unclear], and a dense film is preferred. The protective film is made using the sputtering method. Silicon oxide film, silicon nitride film, silicon oxide nitride film, silicon oxide film, aluminum oxide Aluminum film, aluminum nitride film, aluminum oxide nitride film, or aluminum nitride oxide film The film can be formed as a single layer or in multiple layers. In this embodiment, the protective film is formed by sputtering. Examples are given, but they are not particularly limited and can be formed in various ways.

[0262] Here, a laminated insulating layer 4020 is formed as a protective film. As the first layer of 0, a silicon oxide film is formed using the sputtering method. When using a recon film, the aluminum film used as the source electrode layer and drain electrode layer is It is effective in preventing lockout.

[0263] Furthermore, an insulating layer is formed as the second layer of the protective film. Here, the second layer of the insulating layer 4020 is Then, a silicon nitride film is formed using the sputtering method. The silicon nitride film is used as a protective film. Then, mobile ions such as sodium penetrate into the semiconductor region, affecting the electrical characteristics of the transistor. It is possible to suppress change.

[0264] Furthermore, after forming the protective film, the oxide semiconductor layer is annealed (300°C to 400°C). You may do so.

[0265] Furthermore, an insulating layer 4021 is formed as a planar insulating film. As the insulating layer 4021, acrylic Heat-resistant resins such as polyimide, benzocyclobutene resins, polyamides, epoxy resins, etc. Organic materials having properties can be used. In addition to the above organic materials, low dielectric constant materials (l (ow-k material), siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass) Materials such as (S) can be used. Furthermore, multiple insulating films formed from these materials can be stacked. This may result in the formation of an insulating layer 4021.

[0266] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0267] The method for forming the insulating layer 4021 is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coater or the like can be used. When forming the insulating layer 4021 using a material liquid, During the manufacturing process, the oxide semiconductor layer is simultaneously annealed (300°C to 400°C). This is also acceptable. By combining the firing process of the insulating layer 4021 and the annealing of the oxide semiconductor layer, efficiency can be improved. This makes it possible to manufacture semiconductor devices.

[0268] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. Conductive materials can be used.

[0269] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or more. Also, the resistance of the conductive polymer contained in the conductive composition The ratio is preferably 0.1 Ω·cm or less.

[0270] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0271] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0272] In this embodiment, the connection terminal electrode 4015 is connected to the pixel electrode layer 40 of the liquid crystal element 4013. Formed from the same conductive film as 30, terminal electrode 4016 is made from transistors 4010, 4011 The source electrode layer and drain electrode layer are formed of the same conductive film.

[0273] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0274] Furthermore, in Figure 11, a signal line drive circuit 4003 is formed separately and implemented on the first substrate 4001. Although an example of the configuration is shown, this embodiment is not limited to this configuration. Scan line drive circuit Alternatively, it may be formed and implemented separately, or it may be part of the signal line drive circuit or part of the scan line drive circuit. It is also acceptable to form and implement the component separately.

[0275] Figure 12 shows a transistor fabricated by applying the transistor shown in Embodiment 1 or 2. This shows an example of configuring a liquid crystal display module as a semiconductor device using substrate 2600. .

[0276] Figure 12 shows an example of a liquid crystal display module, consisting of a transistor substrate 2600 and a counter substrate 260. 1 is fixed by a sealing material 2602, and between them is a pixel section 2603 including a transistor, A display area is formed by providing a display element 2604 including a liquid crystal layer, a colored layer 2605, etc. The colored layer 2605 is necessary for color display; in the case of the RGB system, it contains red, green, and blue. A colored layer corresponding to each color is provided for each pixel. Transistor board 2600 On the outside of the opposing substrate 2601, polarizing plates 2606, 2607, and a diffuser plate 2613 are arranged. The light source consists of a cold cathode tube 2610 and a reflector 2611, and a circuit board 261 2 is the wiring circuit section 26 of the transistor board 2600 via the flexible wiring board 2609. It is connected to the 08 and incorporates external circuits such as control circuits and power supply circuits. The polarizing plate and the liquid crystal layer may be laminated with a phase difference plate between them.

[0277] The LCD display module has TN (Twisted Nematic) mode and IPS (I n-Plane-Switching) mode, FFS (Fringe Field Switching) (witching) mode, MVA (Multi-domain Vertical A) alignment) mode, PVA(Patterned Vertical Alignment) mode, PVA(Patterned Vertical Alignment) mode nment) mode, ASM(Axially Symmetric aligned Micro-cell mode, OCB (Optical Compensated B) irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq. You can use modes such as UID Crystal.

[0278] Through the above process, a highly reliable liquid crystal display panel can be manufactured as a semiconductor device. ru.

[0279] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It is possible to do so.

[0280] (Embodiment 7) In this embodiment, the semiconductor device is configured to use the transistor shown in Embodiment 1 or 2. Here is an example of e-paper.

[0281] Figure 13 shows an active-matrix electronic paper as an example of a semiconductor device. The transistor 581 used in the device is the transistor shown in Embodiment 1 or 2. The tag can be applied.

[0282] The electronic paper in Figure 13 is an example of a display device using a twist ball display method. The Toball display method is an electrode layer that uses spherical particles painted in white and black as display elements. It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles by generating a phenomenon.

[0283] The transistor 581 sealed between substrate 580 and substrate 596 has a bottom gate structure. It is a lampistor, and the first electrode layer 587 is connected by a source electrode layer or a drain electrode layer, and The first electrode layer 5 is electrically connected to the edge layers 583 and 585 through openings formed therein. Between 87 and the second electrode layer 588, there is a black region 590a and a white region 590b, and circumferentially A spherical particle 589 is provided, which includes a cavity 594 filled with liquid, The surrounding area of ​​the shaped particle 589 is filled with a filler material 595 such as resin (see Figure 13). In this configuration, the first electrode layer 587 corresponds to the pixel electrode, and the second electrode layer 588 is common This corresponds to an electrode. The second electrode layer 588 is provided on the same substrate as the transistor 581. It is electrically connected to a common potential line. A common connection part as shown in either Embodiment 1 or 2. Using this, the second electrode layer 588 and the conductive particles placed between the pair of substrates are brought into common potential. It can be electrically connected to a wire.

[0284] Alternatively, an electrophoretic element can be used instead of a twist ball. (Transparent liquid) And, positively charged white particles and negatively charged black particles are enclosed in a 2-inch container with a diameter of 10 μm or more. Microcapsules of approximately 00 μm or less are used. They are placed between the first electrode layer and the second electrode layer. The microcapsules being injected are subjected to an electric field by a first electrode layer and a second electrode layer. Then, the white particles and the black particles move in opposite directions to each other, resulting in either white or black being displayed. Yes, it is possible. An electrophoretic display element, commonly known as electronic paper, utilizes this principle. It is called that. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary It does not require a light, consumes little power, and the display can be seen even in dimly lit places. Furthermore, even if power is not supplied to the display unit, it retains the image that has been displayed. Because it is possible to do so, a semiconductor device with a display function (simply a display device, or Even when the semiconductor device (also called a semiconductor device equipped with a display device) is moved away, the displayed image It becomes possible to save it.

[0285] Through the above process, highly reliable electronic paper can be manufactured as a semiconductor device. .

[0286] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It is possible to do so.

[0287] (Embodiment 8) In this embodiment, the semiconductor device is configured to use the transistor shown in Embodiment 1 or 2. An example of a light-emitting display device is shown. The display element of the display device is, in this case, an electron. This will be demonstrated using a light-emitting element that utilizes light emission. Optical elements are distinguished by whether the light-emitting material is an organic compound or an inorganic compound, generally Generally, the former are called organic EL elements, and the latter are called inorganic EL elements.

[0288] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0289] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0290] Figure 14 shows an example of a semiconductor device to which the present invention is applied, which can be used to apply digital time-gradation driving. This figure shows an example of a basic configuration.

[0291] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This refers to the oxide semiconductor layer (In-Ga-Zn-O system film) shown in Embodiment 1 or 2. This example shows the use of two n-channel transistors in a single pixel for the channel formation region. vinegar.

[0292] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, It has a light-emitting element 6404 and a capacitive element 6403. Switching transistor 64 01 has a gate connected to scan line 6406, and the first electrode (source electrode and drain electrode) The (side) is connected to signal line 6405, and the second electrode (the other of the source electrode and drain electrode) is driven It is connected to the gate of the drive transistor 6402. The drive transistor 6402 is The gate is connected to the power line 6407 via the capacitive element 6403, and the first electrode is connected to the power line 640 It is connected to 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is identical It is electrically connected to a common potential line formed on the substrate. If that connection point is called a common connection point... Yes.

[0293] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0294] Note that the capacitive element 6403 is omitted by substituting the gate capacitance of the drive transistor 6402. This is also possible. Regarding the gate capacitance of the drive transistor 6402, the channel region A capacitance may be formed between the gate electrode and the gate electrode.

[0295] In the case of a voltage input / voltage drive method, the gate of the drive transistor 6402 is: The drive transistor 6402 is either fully on or completely off. The video signal is input. In other words, the driver transistor 6402 is operated in the linear region. The driver transistor 6402 operates in the linear region, therefore the voltage of the power line 6407 is higher than A high voltage is applied to the gate of the drive transistor 6402. The signal line 6405 is connected to... Apply a voltage equal to or greater than (power line voltage + Vth of the drive transistor 6402).

[0296] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 14 can be used.

[0297] When performing analog grayscale driving, the gate of the driving transistor 6402 is connected to the light-emitting element 6404 Apply a voltage equal to or greater than the forward voltage of the drive transistor 6402 + Vth. (Light-emitting element 64) The forward voltage of 04 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage. Note that the drive transistor 6402 operates in the saturation region. By inputting an O signal, current can be supplied to the light-emitting element 6404. The drive transistor... To operate the 6402 in the saturation region, the potential of the power line 6407 is set to the drive transistor The gate potential of the TA6402 is set higher. By making the video signal analog, the light-emitting element... By supplying current to the 6404 according to the video signal, analog grayscale driving can be performed.

[0298] Note that the pixel configuration shown in Figure 14 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 14... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0299] Next, the configuration of the light-emitting element will be explained using Figure 15. Here, the driving transistor The cross-sectional structure of a pixel will be explained using the case where the type is n as an example. Figure 15(A)(B)( Transistors 7001 and 701 are drive transistors used in the semiconductor device of C). 1. The 7021 can be fabricated in the same manner as the transistor shown in Embodiment 1 or 2, and In-G This is a highly reliable transistor that includes an a-Zn-O film as an oxide semiconductor layer.

[0300] A light-emitting element only needs to have at least one of its electrodes, either the anode or the cathode, transparent in order to extract light. Then, a transistor and a light-emitting element are formed on the substrate, and light is extracted from the side opposite to the substrate. This includes top-side emission, bottom-side emission which extracts light from the substrate side, and emission from both the substrate side and the opposite side of the substrate. There is a light-emitting element with a double-sided emission structure that extracts light from a surface, and the pixel configuration of the present invention is which emission structure It can also be applied to light-emitting elements.

[0301] The light-emitting element with a bottom-extrusion structure will be explained using Figure 15(A).

[0302] The driving transistor 7011 is of the n type, and the light emitted from the light-emitting element 7012 is the first electrode. Figure 15(A) shows a cross-sectional view of the pixel when ejected to the 7013 side. On a translucent conductive film 7017 electrically connected to the drain electrode layer of sta 7011 A first electrode 7013 of the light-emitting element 7012 is formed on the first electrode 7013. The L layer 7014 and the second electrode 7015 are stacked in that order.

[0303] The light-transmitting conductive film 7017 includes indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide A transparent conductive film such as indium tin oxide with added inium can be used.

[0304] Furthermore, the first electrode 7013 of the light-emitting element can be made of various materials. For example, the first When using electrode 7013 as the cathode, a material with a small work function is used, specifically, for example For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, Sr, and In addition to alloys containing these (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also included. This is preferable. In Figure 15(A), the film thickness of the first electrode 7013 is such that it transmits light (preferably Or, it should be about 5 nm to 30 nm. For example, an aluminum film with a thickness of 20 nm. This is used as the first electrode 7013.

[0305] Furthermore, after laminating a transparent conductive film and an aluminum film, selective etching is performed. A transparent conductive film 7017 and a first electrode 7013 may be formed, in which case the same This is preferable because etching can be performed using a mask.

[0306] Furthermore, the partition wall 7019 is formed in the protective insulating layer 7035 and the insulating layer 7032, and Dre Displaced on the contact hole that reaches the in electrode layer via a translucent conductive film 7017. The peripheral portion of the first electrode 7013 may be covered with a partition wall. The partition wall 7019 is Liimide, acrylic resin, polyamide, epoxy resin, and other organic resin films, inorganic insulating films or It is formed using organic polysiloxane. The partition wall 7019 is made using a particularly photosensitive resin material. An opening is formed on the first electrode 7013, and the side walls of the opening are formed with a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin material is used as the partition wall 7019. When using this material, the step of forming a resist mask can be omitted.

[0307] Furthermore, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7014 is composed of multiple layers, the cathode is... An electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole are placed on the first electrode 7013 which functions. The layers are stacked in the order of the injection-treated layers. Note that it is not necessary to provide all of these layers.

[0308] Furthermore, the stacking order is not limited to the above, and the first electrode 7013 can function as an anode, and the first electrode A hole injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer are stacked on top of 7013 in that order. This is also acceptable. However, when comparing power consumption, the first electrode 7013 is used as the cathode. On the first electrode 7013, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. Stacking the layers in the order they are placed inside out can suppress the voltage rise in the drive circuit and reduce power consumption. Therefore, it is preferable.

[0309] Furthermore, various materials can be used for the second electrode 7015 formed on the EL layer 7014. This is possible. For example, when the second electrode 7015 is used as the anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, etc., and ITO, IZO, ZnO, etc. A transparent conductive material is preferred. Also, a shielding film 7016, for example, a light shielding film, is placed on the second electrode 7015. A light-shielding metal, a light-reflecting metal, etc., is used. In this embodiment, the second electrode 7015 and An ITO film is used, and a Ti film is used as the shielding film 7016.

[0310] The first electrode 7013 and the second electrode 7015 sandwich the EL layer 7014 which includes the light-emitting layer. The region corresponds to the light-emitting element 7012. In the case of the element structure shown in Figure 15(A), The light emitted from 7012 is directed toward the first electrode 7013, as indicated by the arrow.

[0311] In Figure 15(A), the light emitted from the light-emitting element 7012 is directed to the color filter layer. It passes through 7033, insulating layer 7032, oxide insulating layer 7031, gate insulating layer 7030, and It is then ejected through substrate 7010.

[0312] The color filter layer 7033 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0313] Furthermore, the color filter layer 7033 is covered with an overcoat layer 7034, providing additional protective insulation. It is covered by layer 7035. Note that in Figure 15(A), the overcoat layer 7034 is a thin film. As shown in the diagram, the overcoat layer 7034 uses a resin material such as acrylic resin, and - It has the function of flattening the irregularities caused by the filter layer 7033.

[0314] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 15(B).

[0315] Figure 15(B) shows the drain electrode layer of the drive transistor 7021 and the electrically connected The first electrode 7023 of the light-emitting element 7022 is formed on the light-transmitting conductive film 7027. The EL layer 7024 and the second electrode 7025 are stacked in order on the first electrode 7023. Yes, they are.

[0316] The transparent conductive film 7027 includes indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide A transparent conductive film such as indium tin oxide with added inium can be used.

[0317] Furthermore, the first electrode 7023 can be made of various materials. For example, the first electrode 70 When using 23 as the cathode, a material with a small work function is preferred, specifically, for example, Li or Cs. Alkali metals such as Mg, Ca, Sr and other alkaline earth metals, and those containing these. In addition to alloys (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as the cathode, and its film thickness is such that it transmits light. (Preferably, about 5 nm to 30 nm). For example, aluminum with a film thickness of 20 nm A um film is used as the cathode.

[0318] Furthermore, after laminating a transparent conductive film and an aluminum film, selective etching is performed. A transparent conductive film 7027 and a first electrode 7023 may be formed, in which case the same Etching can be performed using a mask, which is preferable.

[0319] Furthermore, the partition wall 7029 is formed in the protective insulating layer 7045 and the insulating layer 7042, and Dre Displaced on the contact hole that reaches the in electrode layer via a translucent conductive film 7027. The peripheral portion of the first electrode 7023 may be covered with a partition wall. The partition wall 7029 is Liimide, acrylic resin, polyamide, epoxy resin, and other organic resin films, inorganic insulating films or It is formed using organic polysiloxane. The partition wall 7029 is made using a particularly photosensitive resin material. An opening is formed on the first electrode 7023, and the side walls of the opening are formed with a continuous curvature. It is preferable to form it so that it becomes an inclined surface. A photosensitive resin material is used as the partition wall 7029. When using this material, the step of forming a resist mask can be omitted.

[0320] Furthermore, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is fine as long as it is composed of a single layer, or multiple layers stacked on top of each other. Either is fine. If the EL layer 7024 consists of multiple layers, it functions as a cathode. On the first electrode 7023, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. The layers are stacked in this order. Note that it is not necessary to include all of these layers.

[0321] Furthermore, the stacking order is not limited to the above, and the first electrode 7023 may be used as the anode, with holes placed on the anode. The layers may be stacked in the order of injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer. When comparing power consumption, the first electrode 7023 is used as the cathode, and an electron injection layer is placed on the cathode. Stacking the electron transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order consumes less power. It is preferable because it does not exist.

[0322] Furthermore, various materials can be used for the second electrode 7025 formed on the EL layer 7024. This is possible. For example, when the second electrode 7025 is used as the anode, a material with a large work function can be used. Materials such as transparent conductive materials like ITO, IZO, and ZnO can preferably be used. In this embodiment, the second electrode 7025 is used as the anode, and an ITO film containing silicon oxide is used. It forms.

[0323] The first electrode 7023 and the second electrode 7025 sandwich the EL layer 7024 which includes the light-emitting layer. The region corresponds to the light-emitting element 7022. In the device structure shown in Figure 15(B), The light emitted from 7022 is directed towards the second electrode 7025 and the first electrode 70, as indicated by the arrows. It is injected on both sides of the 23 side.

[0324] In Figure 15(B), the light emitted from the light-emitting element 7022 toward the first electrode 7023 is One light passes through the color filter layer 7043, then through the insulating layer 7042, and the oxide insulating layer 704 1. The material is ejected through the gate insulating layer 7040 and the substrate 7020.

[0325] The color filter layer 7043 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0326] Furthermore, the color filter layer 7043 is covered with an overcoat layer 7044, providing additional protection and insulation. It is covered by layer 7045.

[0327] However, when using a double-sided injection-type light-emitting element and both display surfaces are to display in full color, Since the light from the second electrode 7025 does not pass through the color filter layer 7043, a separate color filter is required. - It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0328] Next, the light-emitting element with an upper surface injection structure will be explained using Figure 15(C).

[0329] Figure 15(C) shows that the driving transistor, transistor 7001, is of n type, and the light-emitting element 7 This shows a cross-sectional view of the pixel when the light emitted from 002 passes through to the second electrode 7005. In Figure 15(C), the drain electrode layer of the drive transistor 7001 is electrically connected. A first electrode 7003 of the light-emitting element 7002 is formed on the first electrode 7003, and E The L layer 7004 and the second electrode 7005 are stacked in that order.

[0330] Furthermore, the first electrode 7003 can be made of various materials. For example, the first electrode 70 When using O3 as the cathode, materials with a low work function are preferred, specifically, for example, Li or Cs. Alkali metals such as Mg, Ca, Sr and other alkaline earth metals, and those containing these. In addition to alloys (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also preferred.

[0331] Furthermore, the partition wall 7009 is formed in the protective insulating layer 7052 and the insulating layer 7055, and Dre The first electrode 7003 is placed on the contact hole that reaches the in electrode layer. The periphery of the first electrode 7003 may be covered with a partition wall. The partition wall 7009 is made of polyimide. Organic resin films such as acrylic resin, polyamide, epoxy resin, inorganic insulating film, or organic poly It is formed using roxane. The partition wall 7009 is made using a photosensitive resin material in particular, and the first electrode An opening is formed on 7003, and the side walls of the opening are formed with a continuous curvature. It is preferable to form it into a surface. A photosensitive resin material is used as the partition wall 7009. In this case, the step of forming a resist mask can be omitted.

[0332] Furthermore, the EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7004 is composed of multiple layers, the cathode is On the first electrode 7003 used, an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole layer are placed. The layers are stacked in the order of injection. Note that it is not necessary to provide all of these layers.

[0333] Furthermore, the stacking order is not limited to the above, and a hole injection layer is placed on the first electrode 7003 used as the anode. Alternatively, the layers may be stacked in the order of a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer.

[0334] Figure 15(C) shows a layered film consisting of a Ti film, an aluminum film, and another Ti film, onto which a hole injection is applied. The layers are stacked in the following order: indentation layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer, with Mg:A on top of them. A layer is formed between a g alloy thin film and ITO.

[0335] However, if transistor 7001 is n-type, an electron injection layer is placed on the first electrode 7003, electron Stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order is preferable in the drive circuit. This is preferable because it can suppress voltage rise and reduce power consumption.

[0336] The second electrode 7005 is formed using a light-transmitting conductive material, for example, acid Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with added silicon dioxide, etc. A photosensitive conductive film may also be used.

[0337] The EL layer 7004, which includes the light-emitting layer, is sandwiched between the first electrode 7003 and the second electrode 7005. The region corresponds to the light-emitting element 7002. In the case of the pixel shown in Figure 15(C), the light-emitting element 700 The light emitted from 2 is directed toward the second electrode 7005, as indicated by the arrow.

[0338] The planar insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene, and polyamide. In addition to the above resin materials, low dielectric constant materials can be used. Materials (low-k materials), siloxane resins, PSG (phosphorus glass), BPSG (limb glass) Materials such as ron glass can be used. Furthermore, multiple insulating films formed from these materials can be combined. A planar insulating layer 7053 may be formed by layering. Formation of the planar insulating layer 7053 The method is not particularly limited and may be sputtering, SOG, spin coating, etc., depending on the material. Dropping, spray coating, droplet ejection (inkjet method, screen printing, offset printing) (etc.) Using a doctor's knife, roll coater, curtain coater, knife coater, etc. It is possible.

[0339] Furthermore, in the structure shown in Figure 15(C), when full-color display is performed, for example, the light-emitting element 70 02 is a green light-emitting element, one of the adjacent light-emitting elements is a red light-emitting element, and the other is The light-emitting element will be a blue light-emitting element. In addition to the three types of light-emitting elements, a white element will be added, making it a four-element system. A light-emitting display device capable of full-color display may be manufactured using various types of light-emitting elements.

[0340] Furthermore, in the structure shown in Figure 15(C), all of the multiple light-emitting elements to be arranged are white light-emitting elements. The configuration involves placing a sealing substrate having a color filter or the like above the light-emitting element 7002. A light-emitting device capable of full-color display may be manufactured. By forming a material and combining it with color filters and color conversion layers, full-color display is achieved. It is possible.

[0341] Of course, single-color illumination may also be used. For example, a lighting device can be formed using white light. Alternatively, a monochromatic light emission may be used to form an area-color type light-emitting device.

[0342] Furthermore, if necessary, optical films such as polarizing films, including circular polarizers, may be provided.

[0343] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0344] Furthermore, the transistor that controls the driving of the light-emitting element (driving transistor) and the light-emitting element are electrically connected. An example of a direct connection was shown, but a current control transistor is used between the driving transistor and the light-emitting element. A configuration in which a transistor is connected is also acceptable.

[0345] The semiconductor device shown in this embodiment is not limited to the configuration shown in Figure 15. Various modifications are possible based on the technical concept of this invention.

[0346] Next, we have a semiconductor device that incorporates the transistor shown in Embodiment 1 or 2. The appearance and cross-section of the light-emitting display panel (also called a light-emitting panel) will be explained using Figure 16. Figure 16(A) shows a transistor and light-emitting element formed on a first substrate, and a second This is a top view of the panel, which is sealed with a sealant between it and the substrate. Figure 16(B) is a top view of Figure 1. This corresponds to the cross-sectional view in HI of 6(A).

[0347] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0348] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple transistors. In Figure 16(B), the transistor 4510 included in the pixel unit 4502 and the signal line drive are shown. The example shows transistor 4509 included in circuit 4503a.

[0349] Transistors 4509 and 4510 use an In-Ga-Zn-O system film as an oxide semiconductor layer. The transistors shown in the highly reliable embodiment 1 or 2 can be applied. In this embodiment, transistors 4509 and 4510 are n-channel type transistors. ru.

[0350] The channel shape of the oxide semiconductor layer of the pixel transistor 4510 on the insulating layer 4544 A conductive layer 4540 is provided in a position that overlaps with the formation region. The conductive layer 4540 is an oxide semiconductor By placing it in a position that overlaps with the channel formation region of the layer, the transition before and after the BT trial The change in threshold voltage of the ZISTA 4510 can be reduced. Also, the conductive layer 4540 The potential may be the same as or different from that of the gate electrode layer of transistor 4510. It can also function as a second gate electrode layer. Furthermore, if the potential of the conductive layer 4040 is G It may be ND, 0V, or floating state.

[0351] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode is a pixel electrode of the light-emitting element 4511. Layer 4517 is electrically connected to the source electrode layer or drain electrode layer of transistor 4510. It is continued. The configuration of the light-emitting element 4511 is a first electrode layer 4517 and an electroluminescent layer 45 12. The stacked structure of the second electrode layer 4513 is not limited to the configuration shown in this embodiment. No. The configuration of the light-emitting element 4511 is adjusted according to the direction of the light extracted from the light-emitting element 4511. This can be changed as appropriate.

[0352] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode layer 4517, and the side wall of the opening It is preferable to form it so that it becomes an inclined surface with a continuous curvature.

[0353] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0354] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode layer A protective film may be formed on 4513 and the partition wall 4520. The protective film may be silicon nitride. It can form films, silicon nitride films, DLC films, and the like.

[0355] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0356] In this embodiment, the connection terminal electrode 4515 is connected to the first electrode layer 4 of the light-emitting element 4511. Formed from the same conductive film as 517, terminal electrode 4516 is made from transistors 4509, 451 It is formed from the same conductive film as the source electrode layer and drain electrode layer of 0.

[0357] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0358] The substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. In that case, glass plate, plastic plate, polyester film or acrylic resin film A translucent material, such as film, is used.

[0359] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oil or thermosetting resin can be used, such as PVC (polyvinyl chloride) or acrylic resin. Fat, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used as a filler. In this embodiment, Nitrogen was used.

[0360] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0361] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and this embodiment is configured as shown in Figure 16. Not limited.

[0362] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0363] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It is possible to do so.

[0364] (Embodiment 9) A semiconductor device using the transistor shown in Embodiment 1 or 2 is used as electronic paper. It can be applied. Electronic paper can be used in any field of electronics that displays information. It can be used in sub-devices. For example, using e-paper, e-books (electronic books) (K) Posters, in-vehicle advertisements such as trains, and various cards such as credit cards. It can be applied to displays and other similar systems. Examples of electronic devices are shown in Figures 17 and 18.

[0365] Figure 17(A) shows poster 2631 made with electronic paper. In the case of printed materials, advertisements are changed manually, but with electronic paper... It allows you to change the ad display in a short amount of time. Furthermore, the display remains stable without any distortion. This can be obtained. Furthermore, the poster may be configured to transmit and receive information wirelessly.

[0366] Figure 17(B) also shows in-vehicle advertisements 2632 on trains and other vehicles. In the case of printed paper, advertisements are changed manually, but using electronic paper... This allows you to change the ad display quickly without requiring a lot of manpower. Also, the display will not break down. A stable image can be obtained without any issues. Furthermore, the in-car advertisements are configured to transmit and receive information wirelessly. That is also acceptable.

[0367] Figure 18 also shows an example of an e-book. For example, the e-book 2700 has a casing 27 It consists of two enclosures, 01 and enclosure 2703. Enclosure 2701 and enclosure 270 3 is integrated with the shaft portion 2711, and the shaft portion 2711 is used as the axis for opening and closing operations. This configuration makes it possible to operate like a paper book.

[0368] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 18), and the left-hand display unit An image can be displayed on the display unit 2707 (in Figure 18).

[0369] Furthermore, Figure 18 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. It may also be configured to include a board or pointing device. Furthermore, the back of the enclosure or On the side, there are external connection terminals (earphone jack, USB terminal, or AC adapter and USB A configuration that includes terminals that can connect to various cables such as cables, a recording medium insertion section, and so on. It may also be done this way. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's fine.

[0370] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0371] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It is possible to do so.

[0372] (Embodiment 10) The semiconductor device using the transistor shown in Embodiment 1 or 2 can be used in a variety of electronic devices ( It can be applied to amusement machines, for example. (Also called a television or television receiver), monitors for computers, etc. Cameras, digital video cameras, digital photo frames, mobile phones (mobile phones, portable cameras) (Also known as mobile phone devices), portable game consoles, personal digital assistants, sound playback devices, pachinko machines, etc. Examples include large game consoles.

[0373] Figure 19(A) shows an example of a television system. The television system 9600 is, The display unit 9603 is integrated into the housing 9601. The display unit 9603 displays video. It is possible to do so. In addition, here the stand 9605 supports the housing 9601. This shows the configuration.

[0374] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0375] The television system 9600 will be configured to include a receiver, modem, etc. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0376] Figure 19(B) shows an example of a digital photo frame. For example, a digital photo Frame 9700 has a display unit 9703 integrated into the housing 9701. Display unit 970 3 is capable of displaying various images, such as images taken with a digital camera. By displaying data, it can function just like a regular picture frame.

[0377] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It is desirable to include it as it improves the design. For example, the recording medium of a digital photo frame. A memory device containing image data captured by a digital camera is inserted into the body insertion site. The system can capture data and display the captured image data on the display unit 9703.

[0378] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0379] Figure 20(A) shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. It is connected by a connecting part 9893 so that it can be opened and closed. The housing 9881 has a display unit The 9882 is incorporated, and the display unit 9883 is incorporated into the housing 9891. The portable gaming machine shown in 20(A) also includes a speaker section 9884 and a recording medium insertion section 988 6. LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, vibration Equipped with a function to measure motion, odor, or infrared radiation, a microphone (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least the present invention includes Any configuration that includes such semiconductor equipment is acceptable, and other auxiliary equipment may be provided as appropriate. This is possible. The portable gaming machine shown in Figure 20(A) has a program recorded on the recording medium. It has functions to read data and display it on the display unit, and to communicate wirelessly with other portable gaming machines. It has the function of sharing information. The functions of the portable gaming machine shown in Figure 20(A) are It is not limited to this and can have a variety of functions.

[0380] Figure 20(B) shows an example of a slot machine, which is a large-scale gaming machine. Slot machine 9 The 900 has a display unit 9903 integrated into the casing 9901. Also, slot machine 9 The 900 also includes other features such as a start lever, stop switch, coin slot, It is equipped with speakers, etc. Of course, the configuration of the slot machine 9900 is not limited to those mentioned above. It is not specified, and any configuration that includes at least the semiconductor device according to the present invention is sufficient, and other accessories The configuration can be configured with appropriate equipment provided.

[0381] Figure 21(A) shows an example of a mobile phone. The mobile phone 1000 has a housing 1001 In addition to the display unit 1002 incorporated into it, there are operation buttons 1003, an external connection port 1004, and It is equipped with a speaker (Peaker 1005), microphone (Microphone 1006), etc.

[0382] The mobile phone 1000 shown in Figure 21(A) allows you to touch the display unit 1002 with your finger or the like to receive information. You can enter information. You can also perform operations such as making phone calls or composing emails. This can be done by touching the display unit 1002 with a finger or the like.

[0383] The display unit 1002 has three main modes. The first is a display that primarily displays images. The first mode is display mode, the second is input mode which is primarily for inputting information such as characters. The third is display mode. This is a display + input mode, which is a combination of two modes: display mode and input mode.

[0384] For example, when making a phone call or composing an email, the display unit 1002 is used for text input. The primary mode is text input, and you should perform the input operation for the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002. It seems so.

[0385] Furthermore, the mobile phone 1000 contains sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device, the orientation (vertical or horizontal) of the mobile phone 1000 can be determined, and the display The display on the display unit 1002 can be automatically switched.

[0386] Furthermore, the screen mode can be switched by touching the display unit 1002 or by operating the housing 1001. This is done by operating button 1003. Also, the type of image displayed on display unit 1002 Therefore, it is also possible to switch between them. For example, the image signal displayed on the display unit is a video signal. Switch to display mode if it's data, or to input mode if it's text data.

[0387] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 1002 is detected and displayed If there is no input via touch operation on unit 1002 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from that display mode to a different mode.

[0388] The display unit 1002 can also function as an image sensor. For example, the display unit 10 By touching device 02 with the palm or fingers, the user can be authenticated by capturing images of their palm print, fingerprints, etc. Furthermore, the display unit may have a backlight that emits near-infrared light or a sensing element that emits near-infrared light. By using a light source, it is also possible to image finger veins, palmar veins, and other veins.

[0389] Figure 21(B) is also an example of a mobile phone. The mobile phone in Figure 21(B) has a housing 9411. The display device 9410 includes a display unit 9412 and an operation button 9413, and the housing 9401 Operation buttons 9402, external input terminal 9403, microphone 9404, speaker 9405, and It has a communication device 9400 which includes a light-emitting unit 9406 that emits light when an incoming call is received, and has a display function. The display device 9410 is detachable from the communication device 9400, which has telephone functionality, in two directions indicated by the arrows. Yes. Therefore, it is also possible to attach the short axes of the display device 9410 and the communication device 9400 together. The long axes of the display device 9410 and the communication device 9400 can also be mounted together. If only the function is required, remove the display device 9410 from the communication device 9400, and the display device The 9410 can also be used independently. The communication device 9400 and the display device 9410 are connected wirelessly. Images or input information can be sent and received via wireless or wired communication, and each has a rechargeable battery. Close Terry.

[0390] Note that the configuration shown in this embodiment can be used in combination with the configurations shown in other embodiments as appropriate. It is possible to do so. [Explanation of Symbols]

[0391] 10. Pulse output circuit 11 Wiring 12 Wiring 13 Wiring 14 Wiring 15 Wiring 16 Wiring 17 Wiring 21 Input terminals 22 Input terminals 23 Input terminals 24 input terminals 25 Input terminals 26 output terminals 27 Output terminals 31 transistors 32 transistors 33 transistors 34 transistors 35 transistors 36 transistors 37 transistors 38 transistors 39 Transistors 40 transistors 41 Transistors 51 Power line 52 Power line 53 Power line 61 period 62 period 63 period 64 period 65 period 400 circuit boards 402 Insulating layer 403 Oxide semiconductor film 404a oxide semiconductor layer 404b oxide semiconductor layer 405a Crystal region 405b Crystal region 411 terminals 412 Connecting electrodes 414 terminals 415 Conductive layer 416 Electrode layer 418 Conductive layer 421 Guard plate layer 428 Insulating layer 440 transistors 442 Connecting electrode layer 450 transistors 451 Guard Layer 455a Source electrode layer 455b Drain electrode layer 455c source electrode layer 455d Drain electrode layer 460 transistors 470 transistors 480 Oxide conductive layer 482 Metal conductive film 484a Source electrode layer 484b Drain electrode layer 486a Oxide conductive layer 486b Oxide conductive layer 486c Source electrode layer 486d Drain electrode layer 580 circuit boards 581 transistors 583 Insulating layer 585 Insulating layer 587 Electrode layer 588 Electrode layer 589 Spherical particles 590a black area 590b White area 594 Cavity 595 Filling material 596 circuit boards 1000 mobile phones 1001 enclosure 1002 Display section 1003 Operation Buttons 1004 External connection port 1005 Speaker 1006 Mike 2600 Transistor Board 2601 Opposing substrate 2602 Sealant 2603 pixel section 2604 display elements 2605 Colored layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit section 2609 Flexible Wiring Board 2610 cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2631 Poster 2632 In-car advertisement 2700 eBooks 2701 enclosure 2703 Casing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power supply 2723 Operation Keys 2725 Speaker 4001 circuit board 4002 pixel section 4003 Signal Line Drive Circuit 4004 Scan Line Drive Circuit 4005 Sealant 4006 circuit board 4008 Liquid Crystal Layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4015 Connection terminal electrode 4016 Terminal electrode 4018 FPC 4019 Anisotropic conductive film 4020 Insulating layer 4021 Insulating layer 4030 Pixel electrode layer 4031 Counter electrode layer 4032 Insulating layer 4033 Insulating layer 4035 Spacer 4040 conductive layer 4042 Conductive layer 4501 circuit board 4502 pixel section 4503a Signal Line Drive Circuit 4503b Signal line drive circuit 4504a Scan line drive circuit 4504b Scan line drive circuit 4505 Sealant 4506 circuit board 4507 Filling material 4509 Transistor 4510 Transistor 4511 Light-emitting element 4512 Electroluminescent layer 4513 Electrode layer 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode layer 4518a FPC 4518b FPC 4519 Anisotropic conductive film 4520 Bulkhead 4540 Conductive layer 4544 Insulating layer 5300 circuit boards 5301 pixel section 5302 Scan line drive circuit 5303 Scan line drive circuit 5304 Signal Line Drive Circuit 5305 Timing control circuit 5601 Shift Register 5602 Switching Circuit 5603 Transistor 5604 Wiring 5605 Wiring 6400 pixels 6401 Switching Transistor 6402 drive transistor 6403 Capacitive element 6404 Light-emitting element 6405 signal line 6406 scan lines 6407 Power line 6408 Common electrode 7001 Transistor 7002 Light-emitting element 7003 Electrode 7004 EL layer 7005 Electrode 7009 Bulkhead 7010 circuit board 7011 Driver Transistor 7012 Light-emitting element 7013 Electrode 7014 EL layer 7015 Electrode 7016 Shielding membrane 7017 Conductive film 7019 Bulkhead 7020 circuit board 7021 Driver Transistor 7022 Light-emitting element 7023 Electrode 7024 EL layer 7025 Electrode 7027 Conductive film 7029 Bulkhead 7030 Gate Insulation Layer 7031 Oxide insulating layer 7032 Insulating layer 7033 Color filter layer 7034 Overcoat layer 7035 Protective insulating layer 7040 Gate Insulation Layer 7041 Oxide insulating layer 7042 Insulating layer 7043 Color filter layer 7044 Overcoat layer 7045 Protective insulating layer 7051 Oxide Insulating Layer 7052 Protective insulating layer 7053 Planarized insulating layer 7055 Insulating layer 9400 Communication equipment 9401 enclosure 9402 Operation Buttons 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 cabinet 9412 Display section 9413 Operation Buttons 9600 Television equipment 9601 enclosure 9603 Display section 9605 Stand 9607 Display section 9609 Operation Keys 9610 Remote Control Unit 9700 Digital Photo Frame 9701 enclosure 9703 Display section 9881 cabinet 9882 Display section 9883 Display section 9884 Speaker section 9885 Operation Keys 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 cabinet 9893 Connection section 9900 slot machines 9901 cabinet 9903 Display section

Claims

1. A first conductive layer and A first insulating layer having a region on the first conductive layer, An oxide semiconductor layer having a region on the first insulating layer, A second conductive layer having a region on the oxide semiconductor layer, A third conductive layer having a region on the oxide semiconductor layer, The oxide semiconductor layer has a channel formation region for the transistor, The surface portion of the oxide semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region sandwiched between the first and second regions and overlapping with the first conductive layer. The third region has a crystal whose c-axis is oriented in a first direction and which contains In, Zn, and Ga. A semiconductor device in which the first region and the second region each have crystals whose c-axis is oriented in a direction different from the first direction.

2. A first conductive layer and A first insulating layer having a region on the first conductive layer, A first oxide semiconductor layer having a region on the first insulating layer, A second oxide semiconductor layer having a region on the first insulating layer, A second conductive layer having a region on the first oxide semiconductor layer, A third conductive layer having a region on the first oxide semiconductor layer, A fourth conductive layer having a region on the second oxide semiconductor layer, A fifth conductive layer having a region on the second oxide semiconductor layer, A sixth conductive layer having a region on the second oxide semiconductor layer, The first oxide semiconductor layer has a channel formation region for the first transistor. The second oxide semiconductor layer has a channel formation region for the second transistor. The sixth conductive layer has a region that functions as the gate electrode of the second transistor. The surface portion of the first oxide semiconductor layer has a first region in contact with the second conductive layer, a second region in contact with the third conductive layer, and a third region sandwiched between the first and second regions and overlapping with the first conductive layer. The third region has a crystal whose c-axis is oriented in a first direction and which contains In, Zn, and Ga. The first region and the second region each have crystals whose c-axis is oriented in a direction different from the first direction. A semiconductor device having a crystal in which the surface portion of the second oxide semiconductor layer has its c-axis oriented in the first direction.

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