Display boards and display devices

Abstract

The display substrate includes a first display region and a second display region. At least a portion of the second display region surrounds the first display region. The display substrate includes a first light-emitting element group provided in the first display region, a first pixel circuit group provided in the second display region, a lead group, and a plurality of second pixel circuits provided in the second display region. The first light-emitting element group includes N first light-emitting elements. The first pixel circuit group includes N first pixel circuits. The lead group includes N leads. The i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, and the lengths of the first to N-th leads are gradually increased. N≧2, N is an integer, and i=1 to N. At least one row of second pixel circuits or at least one column of second pixel circuits are provided at intervals between the first first light-emitting element and the first first pixel circuit. The N leads extend from the first display region through at least one row of second pixel circuits or at least one column of second pixel circuits to the second display region.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and particularly to display substrates and display devices.

Background Art

[0002] With the continuous development of science and technology, users' demands for the screen-to-body ratio of display devices are increasing.

[0003] In the related art field, the concept of a full screen has emerged, that is, optical elements such as image collection devices in a display device are installed under the display screen.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, a display substrate is provided. The display substrate includes a first display area and a second display area. At least a part of the second display area surrounds the first display area. The display substrate includes a first light-emitting element group provided in the first display area, a first pixel circuit group provided in the second display area, a lead group, and a plurality of second pixel circuits provided in the second display area. The first light-emitting element group includes N first light-emitting elements. Along a first direction and pointing from the second display area to the first display area, the N first light-emitting elements are respectively the first to the Nth first light-emitting elements. The first pixel circuit group includes N first pixel circuits. The first to the Nth first pixel circuits are sequentially provided along a direction away from the first display area. The set direction is the arrangement direction of the N first pixel circuits. The lead group includes N leads provided in parallel. The ith first light-emitting element is electrically connected to the ith first pixel circuit by the ith lead, and the lengths of the first to the Nth leads gradually increase. N≥2, N is an integer, and i = 1 to N. The plurality of second pixel circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along a second direction. The first direction intersects the second direction. Between the first first light-emitting element and the first first pixel circuit, there is 、At least one row of second pixel circuits or at least one column of second pixel circuits is provided. The N leads extend from the first display area through the at least one row of second pixel circuits or the at least one column of second pixel circuits to the second display area.

[0005] In some embodiments, the first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. Between the first light-emitting element and the first pixel circuit 、 At least one row of second pixel circuits is provided. The N leads extend from the first display area through the at least one row of second pixel circuits along the first direction to the second display area.

[0006] In some embodiments, the display substrate comprises a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting element and the at least one second pixel circuit on the plane in which the display substrate is located overlap at least partially. The display substrate comprises a plurality of pixel units, each pixel unit comprising three subpixels arranged along the first direction, each subpixel comprising an electrically connected second light-emitting element and a second pixel circuit. Between the first first light-emitting element and the first first pixel circuit, there are X second pixel circuits belonging to at least one pixel unit, spaced apart, where X is a multiple of 3.

[0007] In some embodiments, the display substrate comprises a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element being electrically connected to at least one second pixel circuit, and the orthographic projections of the at least one second light-emitting element and the at least one second pixel circuit on the plane in which the display substrate is located overlap at least partially. The display substrate further comprises a plurality of pixel units, each pixel unit comprising a plurality of subpixels, each subpixel comprising an electrically connected second light-emitting element and a second pixel circuit. The arrangement of the plurality of pixel units is a pentile arrangement. Between the first first light-emitting element and the first first pixel circuit, there are Y second pixel circuits belonging to at least one pixel unit, spaced apart, where Y is a multiple of 2.

[0008] In some embodiments, the sequence formed by the length values ​​of the N leads in the first direction is an arithmetic progression.

[0009] In some embodiments, the sequence formed by the resistance values ​​of the N leads is an arithmetic progression.

[0010] In some embodiments, a parasitic capacitance is formed between each lead and the second and / or first pixel circuit through which it passes. The sequence formed by the parasitic capacitance values ​​created by the N leads is an arithmetic progression.

[0011] In some embodiments, the display substrate comprises a plurality of rows of first light-emitting elements located in the first display area, and each row of first light-emitting elements is divided into two groups of first light-emitting elements located on either side of a reference line. The reference line is a straight line extending along the second direction and passing through the first display area, and the second direction is perpendicular to the first direction. Two groups of first pixel circuits electrically connected to the two groups of first light-emitting elements are located on opposite sides of the first display area in the first direction. Two groups of leads electrically connected to the two groups of first light-emitting elements are located on either side of the reference line.

[0012] In some embodiments, the two lead groups electrically connected to the two first light-emitting element groups are arranged symmetrically with respect to the reference line.

[0013] In some embodiments, the first display area has a center, and the reference line is a straight line passing through the center.

[0014] In some embodiments, the first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. The display substrate further comprises a group of transfer holes. The group of transfer holes comprises N transfer holes, which are arranged sequentially along the first direction and each corresponds to one of the N first light-emitting elements. Along the second direction, the i-th lead electrically connected to the i-th first light-emitting element is closer to the group of transfer holes than the i+1-th lead electrically connected to the (i+1)th first light-emitting element. The second direction is perpendicular to the first direction.

[0015] In some embodiments, the first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. The display substrate further comprises a group of transfer holes. The group of transfer holes comprises N transfer holes, which are arranged sequentially along the first direction and each corresponds to one of the N first light-emitting elements. The i-th lead electrically connected to the i-th first light-emitting element and the (i+1)th lead electrically connected to the (i+1)th first light-emitting element are located on opposite sides of the group of transfer holes in the second direction, respectively. The second direction is perpendicular to the first direction.

[0016] In some embodiments, the display substrate comprises a base, a pixel circuit layer provided on the base, wherein the first pixel circuit group and the plurality of second pixel circuits are located in the pixel circuit layer, a light-emitting element layer provided on the side of the pixel circuit layer away from the base, wherein the first light-emitting element group is located in the light-emitting element layer, and a plurality of lead layers provided between the pixel circuit layer and the light-emitting element layer, wherein the material of the plurality of lead layers is a light-transmitting conductive material. The N leads of the lead group are each located in the plurality of lead layers.

[0017] In some embodiments, the number of the multiple lead layers is 2. The N leads In , Odd number of reeds and even number of reeds and the 1st to the Nth teeth, each Two lead layers to It is located.

[0018] In some embodiments, the length ratio between the Nth lead and the first lead among the N leads is α, where α ≤ 25.

[0019] In some embodiments, the length ratio α satisfies α ≤ 15.

[0020] In some embodiments, the number of rows or columns of the second pixel circuit, which is spaced apart from the first first light-emitting element and the first first pixel circuit, is β, where β ≤ 30.

[0021] In some embodiments, the ratio of the number of rows or columns of the pixel circuit spaced apart between the nth first light-emitting element and the nth first pixel circuit to the number of rows or columns of the second pixel circuit spaced apart between the first first light-emitting element and the first first pixel circuit is γ, where 5 ≤ γ ≤ 50.

[0022] In some embodiments, the second display area includes a normal area and a compressed area. The first pixel circuit group is located in the compressed area. A part of the plurality of second pixel circuits is located in the normal area, and another part of the second pixel circuits is located in the compressed area. In the compressed area, along the first direction, at least one second pixel circuit is provided between two adjacent first pixel circuits. The width of the column area where the first pixel circuit or the second pixel circuit located in the compressed area is located is smaller than the width of the column area where the second pixel circuit located in the normal area is located.

[0023] In another aspect, a display device is provided. The display device includes the display substrate described in any of the above embodiments and an optical element provided on the non-light-emitting side of the display substrate. The optical element is located in the first display area of the display substrate.

Brief Description of the Drawings

[0024] [Figure 1] It is a structural diagram of a display substrate according to some embodiments of the present disclosure. [Figure 2] [Figure 3] It is a structural diagram of another display substrate according to some embodiments of the present disclosure. [Figure 4] It is a partially enlarged view of a display substrate according to some embodiments of the present disclosure. [Figure 5] [Figure 6] It is a cross-sectional view along the E-E' direction of the display substrate shown in FIG. 3. ​​​ [Figure 7] These are circuit diagrams of subpixels according to some embodiments of the present disclosure. [Figure 8] This is a structural diagram of a subpixel according to some embodiments of the present disclosure. [Figure 9] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 10] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 11] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 12] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 13] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 14] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 15] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 16] This is a partially enlarged view of another display substrate according to some embodiments of the present disclosure. [Figure 17] Figure 16 is a cross-sectional view of the display board along the G-G' direction. [Figure 18] This is a structural diagram of a display device according to some embodiments of the present disclosure. [Figure 19] This is a structural diagram of another display device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0025] The following describes, with reference to the drawings, some technical examples of embodiments of this disclosure clearly and completely, although it is clear that the embodiments described are only a part of the embodiments of this disclosure and not all of them. All other embodiments obtained by those skilled in the art based on some embodiments of this disclosure are all within the scope of protection of this disclosure.

[0026] Unless otherwise required by context, throughout this specification and the claims, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted as having an open, inclusive meaning, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that a particular feature, structure, material, or property related to that embodiment or example is included in at least one embodiment or example of this disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any particular feature, structure, material, or property described may be included in any one or more embodiments or examples in any suitable manner.

[0027] In the following, the terms “first” and “second” are merely for illustrative purposes and should not be understood as indicating or implying relative importance or the quantity of the indicated technical features. Accordingly, features defined as “first” and “second” may explicitly or implicitly include one or more such features. In the description of the embodiments of this disclosure, unless otherwise specified, “multiple” means two or more.

[0028] When describing certain embodiments, the term "connection" and related expressions may be used. For example, when describing certain embodiments, the term "connection" may be used to indicate that two or more components have direct physical or electrical contact with one another. The embodiments disclosed herein are not necessarily limited to those disclosed herein.

[0029] "At least one of A, B, and C" is the same as "at least one of A, B, or C," and both include A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0030] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0031] As used herein, depending on the context, the term "and" is optionally interpreted to mean "when," "on the occasion of," "in response to a decision," or "in response to the detection of." Similarly, depending on the context, the phrase "when a decision is made" or "[the described condition or event] is detected" is optionally interpreted to mean "when a decision is made," or "in response to a decision," or "[the described condition or event] is detected."

[0032] In this specification, the use of "applicable to..." or "configured to..." means open and inclusive language and does not exclude devices applied to or arranged to perform additional tasks or steps.

[0033] Furthermore, the use of "based on" implies that a process, step, calculation, or other action based on one or more stated conditions or values ​​may, in fact, be based on additional conditions or exceed the stated values, thus being open and inclusive.

[0034] As used herein, “about” or “approximate” includes the stated value and the mean value within an acceptable range of deviation of a particular value, where the acceptable range of deviation is determined taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., limitations of the measurement system) as considered by those skilled in the art.

[0035] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thickness of layers and areas is enlarged for clarity. Therefore, variations in shape from the drawings may be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, exemplary embodiments should be interpreted as including deviations in shape due to manufacturing and other reasons, and not being limited to the shapes of the areas shown herein. For example, an etching area shown as a rectangle typically has curved characteristics. Therefore, the areas shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of the areas in the equipment, nor are they intended to limit the scope of the exemplary embodiments.

[0036] In the circuits provided by the embodiments of this disclosure, it should be noted that the transistors used may be thin-film transistors, field-effect transistors, or other switching elements having the same characteristics, and in the embodiments of this disclosure, thin-film transistors will be described as examples.

[0037] In some embodiments, the control pole of each transistor in which each circuit is used is the gate of the transistor, the first pole is one of the source and drain of the transistor, and the second pole is the other of the source and drain of the transistor. The source and drain of the transistor may be structurally symmetrical, and therefore the source and drain may not be structurally distinguishable, that is, the first pole and the second pole of the transistor in embodiments of this disclosure may not be structurally distinguishable. Exemplarily, if the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain. Exemplarily, if the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

[0038] In the circuits provided by the embodiments of this disclosure, “nodes” do not refer to actual existing components, but rather to the confluence points of relevant electrical connections in the circuit diagram; that is, these nodes are nodes that are equivalently formed from the confluence points of relevant electrical connections in the circuit diagram.

[0039] The transistors provided in the circuits according to the embodiments of this disclosure may all be N-type transistors or P-type transistors. Furthermore, some of the transistors in each circuit may be N-type transistors, while other parts may be P-type transistors.

[0040] In this disclosure, “effective level” refers to the level at which the transistor can be turned on.

[0041] The following description will assume that in the circuits provided by the embodiments of this disclosure, all transistors are P-type transistors (in this case, with a low effective level). By using the same conduction type transistors in each of the following circuits, the process flow can be simplified, the difficulty of the process can be reduced, and the yield of the product (e.g., display board 100, display device 1000) can be improved.

[0042] In some embodiments of the present disclosure, a display board 100 is provided, as shown in Figure 1, which has a first display area A1 and a second display area A2, wherein at least a portion of the second display area A2 surrounds the first display area A1. For example, the area of ​​the second display area A2 is larger than the area of ​​the first display area A1.

[0043] Here, the quantity in the first display area A1 may be at least one, and the quantity in the second display area A2 may be, for example, one. Below, the structure of the display board 100 will be described in general terms, using the case where the quantity in the first display area A1 is one as shown in Figure 1.

[0044] For example, the second display area A2 may surround the first display area A1. In this case, the shape of the first display area A1 may be, for example, a circle, an ellipse, or a rectangle.

[0045] For example, the second display area A2 may enclose a portion of the first display area A1, that is, a portion of the boundary of the second display area A2 may overlap with a portion of the boundary of the first display area A1. In this case, the shape of the first display area A1 may be, for example, a rectangle, a rounded rectangle, a teardrop shape, or a semicircle.

[0046] In some embodiments, as shown in Figure 2, the display board 100 may include a base 1.

[0047] The Base 1 types described above come in various forms and can be selected and installed according to actual needs.

[0048] For example, the base 1 described above may be a rigid base. This rigid base may be a glass base or a PMMA (Polymethyl methacrylate) base, etc.

[0049] For example, the base 1 described above may be a flexible base. This flexible base may be a PET (polyethylene terephthalate) base, a PEN (polyethylene naphthalate two formic acid glycol ester) base, or a PI (polyimide) base, etc. In this case, the display substrate 100 can, for example, achieve flexible display.

[0050] In some embodiments, as shown in Figures 2 to 6, the display substrate 100 may further include a pixel circuit layer 2 located on the side away from the base 1.

[0051] As an example, as shown in Figures 3, 5, and 8, the pixel circuit layer 2 provided on the display substrate 100 may include semiconductor layers, a first gate conductive layer, a second gate conductive layer, and a source-drain conductive layer, which are sequentially stacked in a direction perpendicular to the base 1 and away from the base 1. Alternatively, a first gate insulating layer may be provided between the semiconductor layer and the first gate conductive layer, a second gate insulating layer may be provided between the first gate conductive layer and the second gate conductive layer, and an interlayer insulating layer may be provided between the second gate conductive layer and the source-drain conductive layer.

[0052] For example, as shown in Figures 3, 5, and 8, Display board 100 This is a transfer layer provided on the side of the source-drain conductive layer away from the base substrate 1. 6 The following can be further provided. The material of the transfer layer may be the same as the material of the source-drain conductive layer. A planarizing layer can be provided between the source-drain conductive layer and the transfer layer.

[0053] For example, the pixel circuit layer 2 described above may include a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22.

[0054] The structures of the first pixel circuit 21 and the second pixel circuit 22 described above can vary and can be selected and installed according to actual needs. For example, the structure of the first pixel circuit 21 or the second pixel circuit 22 can be "2T1C", "6T1C", "7T1C", "6T2C", or "7T2C". Here, "T" represents a transistor, the number before "T" represents the number of transistors, and "C" represents a storage capacitor, the number before "C" represents the number of storage capacitors.

[0055] For example, as shown in Figure 7, the structure of the first pixel circuit 21 and the structure of the second pixel circuit 22 may be the same. For example, both structures are 7T1C structures. Figure 7 is the equivalent circuit diagram of the second pixel circuit 22, and Figure 8 is the structural diagram of one second pixel circuit 22 in Figure 3 or Figure 5. The structures of the pixel circuit layer 2 and the second pixel circuit 22 will be described in general terms below with reference to Figures 7 and 8. Of course, the equivalent circuit diagram of the first pixel circuit 21 may be the same as the equivalent circuit shown in Figure 7, and the structural diagram of the first pixel circuit 21 may be the same as the structural diagram shown in Figure 8.

[0056] For example, as shown in Figure 7, the second pixel circuit 22 includes a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, a second reset transistor T7, and a storage capacitor Cst.

[0057] When the level of the reset signal transmitted by the reset signal line RST is at an effective level, the first reset transistor T6 and the second reset transistor T7 turn on under the control of the reset signal and can receive the initial signal transmitted from the initial signal line Vinit. The first reset transistor T6 can transmit the initial signal to one end of the storage capacitor Cst to reset the storage capacitor Cst. The second reset transistor T7 receives the initial signal from the second reset transistor T7 electrodes of the light-emitting element connected to the electrodes Transmit to Light-emitting element This can be reset. Here, the drive transistor T2 can be turned on under the control of the initial signal.

[0058] When the level of the scan signal transmitted by the scan signal line Gate is at an effective level, the switching transistor T1 and the compensation transistor T3 can be turned on under the control of the scan signal. The data signal transmitted by the data signal line Data is then transmitted sequentially through the switching transistor T1, the drive transistor T2, and the compensation transistor T3 to the control pole of the drive transistor T2, and the control pole of the drive transistor T2 can be charged until the drive transistor T2 is cut off. At this time, the threshold voltage compensation of the drive transistor T2 is completed.

[0059] When the level of the enable signal transmitted by the enable signal line EM is at the effective level, the first light emission control transistor T4 and the second light emission control transistor T5 turn on under the control of the enable signal and can receive the first voltage signal from the first voltage signal line ELVDD, and the drive transistor T2 generates a drive signal in accordance with the data signal and the first voltage signal, and the drive signal difference Light-emitting element It can be transmitted to.

[0060] For example, as shown in Figure 8, in the semiconductor layer, the portion covered by the first gate conductive layer constitutes the active layer of each transistor. The portion not covered by the first gate conductive layer may be doped to form a conductor. The portion of the first gate conductive layer covering the semiconductor layer constitutes the control poles of each transistor, including, for example, the control pole T11 of the switching transistor T1, the control pole T21 of the drive transistor T2, the control pole T31 of the compensation transistor T3, the control pole T41 of the first light emission control transistor T4, the control pole T51 of the second light emission control transistor T5, the control pole T61 of the first reset transistor T6, and the control pole T71 of the second reset transistor T7.

[0061] For example, the first plate Cst1 of the storage capacitor Cst, the scan signal line Gate for transmitting a scan signal, the reset signal line RST for transmitting a reset signal, and the enable signal line EM for transmitting an enable signal may be located in the first gate conductive layer. The second plate Cst2 of the storage capacitor Cst and the initial signal line Vinit for transmitting an initial signal may be located in the second gate conductive layer. The data signal line Data for transmitting a data signal and the first voltage signal line ELVDD for transmitting a first voltage signal may be located in the source-drain conductive layer. The transfer layer may further comprise a transfer section 61 for transfers and a shield block 62 for shielding.

[0062] It is understood that conductors in a semiconductor layer can constitute the first and second poles of each transistor. In this disclosure, in order to clearly distinguish between the first and second poles of a transistor, the portion of the source-drain conductive layer connected to a conductor is defined as the first or second pole of the transistor.

[0063] As shown in Figure 8, the first pole T12 of the switching transistor T1 has an integrated structure with the data signal line Data, and Interlayer insulation , second gate insulating layer and 1 gate The active layer located in the semiconductor layer can be connected via a first via hole H1 that sequentially penetrates the insulating layer. The control electrode T11 of the switching transistor T1 can be integrated with the scanning signal line Gate.

[0064] The second pole of the switching transistor T1 and the second pole of the first light-emitting control transistor T4 are located in a conductor in the semiconductor layer and can form an integrated structure. The first pole T42 of the first light-emitting control transistor T4 forms an integrated structure with the first voltage signal line ELVDD, and Interlayer insulation , second gate insulating layer and 1 gate It can be connected to the active layer located in the semiconductor layer via a fifth via hole H5 that sequentially penetrates the insulating layer.

[0065] The first pole of the drive transistor T2 is also located in a conductor in the semiconductor layer and can form an integrated structure with the second pole of the switching transistor T1. The second pole of the drive transistor T2 and the first pole of the compensation transistor T3 are also located in a conductor in the semiconductor layer and can form an integrated structure. The control pole T21 of the drive transistor T2 forms an integrated structure with the first electrode plate Cst1 of the storage capacitor Cst, and Interlayer insulation , second gate insulating layer and 1 gate It can be connected to the second pole T63 of the first reset transistor T6 via a third via hole H3 that sequentially penetrates the insulating layer.

[0066] The second electrode plate Cst2 of the storage capacitor Cst can be connected to the first voltage signal line ELVDD via a fourth via hole H4 that penetrates the interlayer insulating layer.

[0067] The second pole T33 of the compensation transistor T3 can be integrated with the second pole T63 of the first reset transistor T6. The control pole T31 of the compensation transistor T3 can be integrated with the scan signal line Gate. The compensation transistor T3 is a double-gate transistor.

[0068] The control pole T61 of the first reset transistor T6 can be integrated with the reset signal line RST. The first pole T62 of the first reset transistor T6 can be connected to the initial signal line Vinit via a seventh via hole H7 that penetrates the second gate insulating layer.

[0069] The control pole T71 of the second reset transistor T7 can be integrated with the reset signal line RST. The first pole T72 of the second reset transistor T7 can be connected to the initial signal line Vinit via an eighth via hole H8 that penetrates the second gate insulating layer. The second pole T73 of the second reset transistor T7 is integrated with the second pole T53 of the second light emission control transistor T5. In the same second pixel circuit 22, the control poles of the first reset transistor T6 and the second reset transistor T7 are connected to different reset signal lines RST, and the first poles of the first reset transistor T6 and the second reset transistor T7 are connected to different initial signal lines Vinit.

[0070] The first pole of the second light-emitting control transistor T5 is located in the conductor of the semiconductor layer. The first pole of the second light emission control transistor T5 and Second pole of drive transistor T2 and This can form an integrated structure. The control electrode T51 of the second light emission control transistor T5 is connected to the enable signal line EM, forming an integrated structure.

[0071] Selectively, as shown in Figures 9 to 11, the above-mentioned plurality of second pixel circuits 22 may be arranged in a plurality of columns along the first direction X and in a plurality of rows along the second direction Y. Each column of the second pixel circuit may comprise a plurality of second pixel circuits 22, and these plurality of second pixel circuits 22 are arranged sequentially along the second direction Y. Each row of the second pixel circuit may comprise a plurality of second pixel circuits 22, and these plurality of second pixel circuits 22 are arranged sequentially along the first direction X.

[0072] For example, the first direction X intersects with the second direction Y.

[0073] Here, the angle between the first direction X and the second direction Y can be selected and set according to the actual needs. For example, the angle between the first direction X and the second direction Y could be 85°, 88°, or 90°.

[0074] In some examples of this disclosure, both the first pixel circuit 21 and the second pixel circuit 22 can cover the above-mentioned signal lines; however, for the sake of explanation, this disclosure describes the first pixel circuit 21, the second pixel circuit 22, and the signal lines separately.

[0075] In some embodiments, as shown in Figures 2, 4, and 6, the display substrate 100 may further include a light-emitting layer 3 provided on the side of the pixel circuit layer 2 away from the base substrate 1.

[0076] For example, the above-described light-emitting layer 3 may comprise a plurality of first light-emitting elements 31 and a plurality of second light-emitting elements 32. The structure of the first light-emitting element 31 and the structure of the second light-emitting element 32 may be the same, for example. 17 As shown, the first light-emitting element 31 The first light-emitting element comprises an anode, a light-emitting layer, and a cathode arranged in a sequential stack. Correspondingly, the second light-emitting element 32 may also comprise an anode, a light-emitting layer, and a cathode arranged in a sequential stack.

[0077] Exemplary, at least one first pixel circuit 21 may be electrically connected to at least one first light-emitting element 31. For example, a first pixel circuit 21 and a first light-emitting element 31 may be electrically connected in a one-to-one correspondence, or one first pixel circuit 21 may be electrically connected to multiple first light-emitting elements 31, or multiple first pixel circuits 21 may be electrically connected to one first light-emitting element 31. Each first pixel circuit 21 can provide a drive signal to the corresponding first light-emitting element 31 to drive the corresponding first light-emitting element 31 to emit light. As shown in Figure 7, the present disclosure will be illustrated by illustrating the electrical connection between one first pixel circuit 21 and one first light-emitting element 31 as an example.

[0078] Exemplary, at least one second pixel circuit 22 may be electrically connected to at least one second light-emitting element 32. For example, a one-to-one correspondence may exist between the second pixel circuit 22 and the second light-emitting element 32, or one second pixel circuit 22 may be electrically connected to multiple second light-emitting elements 32, or multiple second pixel circuits 22 may be electrically connected to one second light-emitting element 32. Each second pixel circuit 22 can provide a drive signal to the corresponding second light-emitting element 32 to drive the corresponding second light-emitting element 32 to emit light. As shown in Figure 7, the disclosure will be illustrated by illustrating an electrical connection between one second pixel circuit 22 and one second light-emitting element 32.

[0079] For example, the orthographic projections of at least one second light-emitting element 32 and at least one second pixel circuit 22 in the plane on which the display substrate 100 is located overlap at least partially. That is, the orthographic projections of the electrically connected second light-emitting element 32 and second pixel circuit 22 in the plane on which the display substrate 100 is located may partially overlap or may completely overlap.

[0080] The light emitted from the multiple first light-emitting elements 31 and the multiple second light-emitting elements 32 works in conjunction with each other, enabling the display board 100 to display an image. The sum of the areas of the first display area A1 and the second display area A2 is approximately equal to the area of ​​the display board 100, which is advantageous in increasing the area ratio of the displayable area on the display board 100 and improving the screen-to-body ratio of the display board 100, allowing the display board 100 to achieve full-screen display.

[0081] In some examples, 9~ As shown in 11, the plurality of first pixel circuits 21 and the plurality of second pixel circuits 22 in the pixel circuit layer 2 may all be located in the second display area A2. The plurality of first light-emitting elements 31 in the light-emitting element layer 3 may all be located in the first display area A1, and the plurality of second light-emitting elements 32 may all be located in the second display area A2. The transmittance of the portion of the display substrate 100 located in the first display area A1 is greater than the transmittance of the portion of the display substrate 100 located in the second display area A2.

[0082] Here, the first pixel circuit 21, the second pixel circuit 22, and the signal lines in the pixel circuit layer 2 need to transmit electrical signals well. Based on this, a portion of the first pixel circuit 21, a portion of the second pixel circuit 22, and the signal lines may be formed from a metallic material. It is understood that metallic materials can block light rays.

[0083] In some examples of this disclosure, the first pixel circuit 21 that provides a drive signal to the first light-emitting element 31 is located behind the second display area A2, thereby reducing the number of structures that can block light rays in the first display area A1. External light rays can also be emitted from one side (e.g., the light-emitting side) of the portion of the display substrate 100 located in the first display area A1, through the gap between any two adjacent first light-emitting elements 31, and from the other side (e.g., the non-light-emitting side) of the portion of the display substrate 100 located in the first display area A1. As a result, the portion of the display substrate 100 located in the first display area A1 has high transmittance.

[0084] Thus, when the display board 100 is applied to the display device 1000, and the optical element 200 is provided on the non-emitting side of the display board 100 and in the first display area A1, external light rays pass through the portion of the display board 100 located in the first display area A1, enter the optical element 200, are collected by the optical element 200, and the optical element 200 can operate normally.

[0085] For example, the distribution density of the multiple first light-emitting elements 31 is the same as the distribution density of the multiple second light-emitting elements 32. This not only enables the display board 100 to achieve full-screen display, but is also advantageous in ensuring good image display quality of the display board 100.

[0086] For example, the distribution density of the multiple first light-emitting elements 31 is smaller than the distribution density of the multiple second light-emitting elements 32. This increases the spacing between any two adjacent first light-emitting elements 31, reduces shielding from ambient light by the first light-emitting elements 31, and increases the area of ​​the light-transmitting portion in the first display area A1 of the display substrate 100. As a result, the amount of ambient light that can penetrate the portion of the display substrate 100 in the first display area A1 can be further increased. After applying the display substrate 100 to the display device 1000, this is advantageous in improving the amount of ambient light collected by the optical elements 200 and improving the operating performance of the optical elements 200.

[0087] In some examples, as shown in Figures 9 to 11, the display board 100 described above may further include a plurality of leads 41.

[0088] For example, as shown in Figures 9 to 11, one end of each lead 41 may be electrically connected to the first pixel circuit 21 and the other end to the first light-emitting element 31. This allows for an electrical connection between the first pixel circuit 21 and the first light-emitting element 31 using the leads 41, and enables the first pixel circuit 21 to transmit drive signals to the corresponding first light-emitting element 31 via the leads 41.

[0089] It is understood that, in the process of the lead 41 extending from the first pixel circuit 21 to the first light-emitting element 31, it may form parasitic capacitance across the first pixel circuit 21 and / or the second pixel circuit 22.

[0090] The presence of the parasitic capacitance described above tends to affect the accuracy of the drive signal received by the first light-emitting element 31, and further tends to affect the light emission accuracy of the first light-emitting element 31, which in turn affects the display effect of the portion located in the first display area of ​​the display substrate.

[0091] In one implementation method, the lead paths are sometimes adjusted so that the parasitic capacitances of different leads tend to match in order to reduce the effect of parasitic capacitance. However, this increases the variation in the lengths of different leads, lacks regularity, and requires the special design of the lead paths according to the parasitic capacitance of each lead, which tends to increase the difficulty of designing and manufacturing the display board.

[0092] Based on this, in some examples, as shown in Figures 9 to 11, a plurality of first light-emitting elements 31 located in the first display area A1 can be divided into a plurality of first light-emitting element groups 31a. A first light-emitting element group 31a can comprise N first light-emitting elements 31. Correspondingly, a plurality of first pixel circuits 21 located in the second display area A2 can be divided into a plurality of first pixel circuit groups 21a. A first pixel circuit group 21a can comprise N first pixel circuits 21. The plurality of leads 41 described above can be divided into a plurality of lead groups 41a. A lead group 41a can comprise N leads 41, where N ≥ 2 and N is an integer.

[0093] For example, the number of first light-emitting elements 31 provided in different first light-emitting element groups 31a may be the same or different. The number of first pixel circuits 21 provided in different first pixel circuit groups 21a may be the same or different. The number of leads 41 provided in different lead groups 41a may be the same or different.

[0094] In the electrically connected first light-emitting element group 31a, first pixel circuit group 21a, and lead group 41a, the number of first light-emitting elements 31, the number of first pixel circuits 21, and the number of leads 41 are the same.

[0095] For example, in an electrically connected first light-emitting element group 31a, first pixel circuit group 21a, and lead group 41a, the first light-emitting element group 31a comprises 20 first light-emitting elements 31, the first pixel circuit group 21a comprises 20 first pixel circuits 21, and the lead group 41a comprises 20 leads 41. Each first light-emitting element 31 is electrically connected to a corresponding first pixel circuit 21 by one lead 41.

[0096] For example, along the first direction X and pointing from the second display area A2 to the first display area A1, the N first light-emitting elements 31 in the first light-emitting element group 31a are each the 1st to the Nth first light-emitting elements.

[0097] It is understood that, based on the positional relationship between the first display area A1 and the second display area A2, the second display area A2 will surround the opposing sides of the first display area A1 along the first direction X. For example, as shown in Figure 1, the portions of the second display area A2 located on both sides of the first display area A1 along the first direction X are referred to as the first sub-area A21a and the second sub-area A22a, respectively. In this case, "along the first direction X and pointing from the second display area A2 to the first display area A1" means pointing from the first sub-area A21a to the first display area A1 along the first direction X, and / or pointing from the second sub-area A22a to the first display area A1 along the first direction X.

[0098] For example, the phrase "along the first direction X and pointing from the second display area A2 to the first display area A1" means that, when pointing along the first direction X and from the first sub-area A21a to the first display area A1, the first of the N first light-emitting elements 31 in the first light-emitting element group 31a is closest to the first sub-area A21a, that is, it is closest to the boundary of the first display area A1. In other words, the second, third, fourth...N-1, and Nth first light-emitting elements move sequentially away from the first sub-area A21a.

[0099] Furthermore, for example, the phrase "along the first direction X and pointing from the second display area A2 to the first display area A1" means that, when pointing along the first direction X and from the second sub-area A22a to the first display area A1, the first of the N first light-emitting elements 31 in the first light-emitting element group 31a is closest to the second sub-area A22a, that is, it is closest to the boundary of the first display area A1. In other words, the second, third, fourth...N-1, and Nth first light-emitting elements move sequentially away from the second sub-area A22a.

[0100] Furthermore, for example, the phrase "along the first direction X and pointing from the second display area A2 to the first display area A1" means that, when pointing along the first direction X and pointing from the first sub-area A21a to the first display area A1, and also along the first direction X and pointing from the second sub-area A22a to the first display area A1, then in the above-mentioned plurality of first light-emitting element groups 31a, the first first light-emitting element of a portion of the first light-emitting element group 31a is closest to the first sub-area A21a, the other first light-emitting elements move sequentially away from the first sub-area A21a, and there is a certain distance between the Nth first light-emitting element and the second sub-area A22a. In another portion of the first light-emitting element group 31a, the first first light-emitting element is closest to the second sub-area A22a, the other first light-emitting elements move sequentially away from the second sub-area A22a, and there is a certain distance between the Nth first light-emitting element and the first sub-area A21a.

[0101] For example, the N first pixel circuits 21 in the first pixel circuit group 21a are the 1st to the Nth first pixel circuits, respectively. The 1st to the Nth first pixel circuits are arranged sequentially along the direction away from the first display area A1.

[0102] In other words, in the first pixel circuit group 21a, the first pixel circuit 21 closest to the first light-emitting element group 31a is the first first pixel circuit. The second, third, fourth, ... N-1, and Nth first pixel circuits move sequentially away from the first light-emitting element group 31a.

[0103] The arrangement direction of the first to nth first pixel circuits can vary and can be selected and installed according to actual needs.

[0104] For example, the arrangement direction of the first to the Nth first pixel circuits may be the first direction X. That is, the arrangement direction of the multiple first pixel circuits 21 in the first pixel circuit group 21a is the same as the arrangement direction of the multiple first light-emitting elements 31 in the first light-emitting element group 31a.

[0105] Furthermore, for example, the arrangement direction of the first to Nth first pixel circuits may have an angle between it and the first direction X. The dimension of this angle can be selected and set according to the actual needs. Selectively, this angle may be 45° or 90°.

[0106] As an example, as shown in Figures 9 to 11, the N leads 41 provided in the lead group 41a are arranged in parallel. The direction of extension of the N leads 41 is, for example, parallel or substantially parallel.

[0107] For example, the i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, where i = 1 to N. That is, the first first light-emitting element may be electrically connected to the first first pixel circuit by the first lead, the second first light-emitting element may be electrically connected to the second first pixel circuit by the second lead, ... the (N-1)th first light-emitting element may be electrically connected to the (N-1)th first pixel circuit by the (N-1)th lead, and the Nth first light-emitting element may be electrically connected to the Nth first light-emitting element by the N lead.

[0108] For example, the length of the first to the Nth reed gradually increases.

[0109] It is understood that the first to Nth first pixel circuits in the first pixel circuit group 21a move sequentially away from the first light-emitting group 31a along their arrangement direction, which means that the spacing between the first, second, third...N-1, and Nth first pixel circuits and the first light-emitting group 31a gradually increases, and correspondingly, the spacing between the first first pixel circuit and the first first light-emitting element, the spacing between the second first pixel circuit and the second first light-emitting element...N-1 the spacing between the first pixel circuit and the N-1 the first light-emitting element, and the spacing between the Nth first pixel circuit and the Nth first light-emitting element gradually increases. As a result, the length of the first lead connecting the first pixel circuit and the first light-emitting element, the length of the second lead connecting the second pixel circuit and the second light-emitting element, ... the length of the (N-1)th lead connecting the (N-1)th pixel circuit and the (N-1)th light-emitting element, and the length of the Nth lead connecting the (N)th pixel circuit and the (N)th light-emitting element all gradually increase.

[0110] For example, the portion of each lead 41 located between the corresponding first pixel circuit 21 and the corresponding first light-emitting element 31 is straight. In this case, the length of the lead 41 refers to, for example, the distance between the corresponding first pixel circuit 21 and the corresponding first light-emitting element 31. This not only facilitates the manufacturing and formation of the leads 41, but also avoids the formation of bends and sharp tips in the leads 41, ensuring good transmission of the drive signal in the leads 41.

[0111] This disclosure makes it easier to plan the travel path of the leads 41 by using the above-described installation and connection methods, improves the regularity of the length differences between any two adjacent leads 41 in the lead group 41a, reduces the number of leads 41 required to be used, simplifies the structure of the display board 100, and reduces the difficulty of manufacturing and forming the display board 100.

[0112] Furthermore, the first pixel circuit 21, the second pixel circuit 22, and the signal lines in the pixel circuit layer 2 are arranged regularly. This makes it possible to improve the regularity of the quantitative differences between the first pixel circuit 21 and / or the second pixel circuit 22 that any two adjacent leads 41 in the lead group 41a straddle during the extension of the leads 41, and also makes it easier to improve the uniformity of the parasitic capacitance changes formed by any two adjacent leads 41 in the lead group 41a.

[0113] Herein, the present disclosure may, for example, employ an external compensation method, which compensates for parasitic capacitance formed by the lead 41, improves the accuracy of the drive signal received by the first light-emitting element 31 and the emitted light, and ensures the display effect of the portion located in the first display area of ​​the display substrate. The above external compensation method includes, but is not limited to, an external optical compensation (demura) method.

[0114] This disclosure is advantageous for optimizing the algorithm of external optical compensation (demura) by improving the uniformity of the parasitic capacitance change formed by any two adjacent leads 41 in the lead group 41a, and is useful for improving the display uniformity of the display substrate 100 and improving the quality of the image displayed by the display substrate 100.

[0115] In some examples, as shown in Figures 9 to 11, between the first light-emitting element and the first pixel circuit, 、 At least one row of second pixel circuits or at least one column of second pixel circuits is provided. The N leads 41 in the lead group 41a extend from the first display area A1 through the above-mentioned at least one row of second pixel circuits or at least one column of second pixel circuits to the second display area A2.

[0116] For example, one, three, four, or seven rows of second pixel circuits can be installed between the first first light-emitting element and the first first pixel circuit, with spacing between them. Alternatively, one, three, four, eight, ten, or two columns of second pixel circuits can be installed between the first first light-emitting element and the first first pixel circuit, with spacing between them.

[0117] For example, as shown in Figures 9 to 11, between the first light-emitting element and the first pixel circuit 、 If at least one row of second pixel circuits is provided, the first lead in the lead group 41a extends from the first display area A1, across the at least one row of second pixel circuits, to the second display area A2, and the second, third...Nth leads extend from the first display area A1, across the at least one row of second pixel circuits, and then continue to extend across the at least one row of second pixel circuits to the second display area A2.

[0118] In one implementation, the first light-emitting element and the first pixel circuit are provided adjacent to each other, and there is no second pixel circuit spaced between them. In this case, the length of the first lead, which has the smallest length in the lead group, is, for example, L. For example, the difference in length between any two adjacent leads in the lead group is m, and in this case, the length of the Nth lead, which has the largest length, is L + m(N-1). The ratio of the length of the Nth lead to the length of the first lead is shown in Equation 1 below.

[0119]

number

[0120] In some examples of this disclosure, between the first light-emitting element and the first pixel circuit, 、After at least one row of second pixel circuits or at least one column of second pixel circuits are provided, the length of the first lead connecting the first first light-emitting element and the first first pixel circuit is, for example, L+p. For example, the difference in length between any two adjacent leads in the lead group is m, and in this case, the length of the Nth lead, which has the longest length, is L+p+m(N-1). The ratio of the length of the Nth lead to the length of the first lead is shown in Equation 2 below.

[0121]

number

number

number

[0122] In other words, this disclosure relates to the relationship between the first light-emitting element and the first pixel circuit. 、 After at least one row of second pixel circuits or at least one column of second pixel circuits is provided, the length of the first lead can be increased by a large multiple, but the length of the Nth lead can be increased by only a small multiple, thereby effectively reducing the ratio between the length of the Nth lead and the length of the first lead, and effectively reducing the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead.

[0123] The smaller the length ratio between the longest Nth lead and the shortest 1st lead, the smaller the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the 1st lead. This reduces the difference between the loss of the drive signal in the Nth lead and the loss in the 1st lead, thereby reducing the difference in the displayed grayscale during the image display process of the display board 100 and improving display quality. Furthermore, in the subsequent process of compensating for the grayscale difference using the external optical compensation (DEMURA) algorithm, the smaller the difference in the displayed grayscale, the lower the workload of the external optical compensation (DEMURA) algorithm, which is advantageous for further optimizing the external compensation (DEMURA) algorithm. In addition, after the difference in the displayed grayscale has decreased to a certain extent, it may no longer be necessary to use the external optical compensation (DEMURA) algorithm for compensation, thus ensuring good image quality of the display board 100.

[0124] As described above, the display substrate 100 provided by some embodiments of this disclosure includes a first display area A1 and a second display area A2, and a first light-emitting element 31 is provided in the first display area A1. A first pixel circuit 21 for providing a drive signal to the first light-emitting element 31 is provided in the second display area A2. This prevents the first pixel circuit 21 from being shielded by light rays incident on the first display area A1 and improves the transmittance of the portion of the display substrate 100 located in the first display area A1. After the display substrate 100 is applied to the display device 1000, ambient light rays can pass through the portion of the display substrate 100 located in the first display area A1 and be incident on the optical elements 200 of the display device 1000. This allows the optical elements 200 to operate normally and increases the ratio of the displayable area on the display substrate 100, enabling the display substrate 100 and the display device 1000 to achieve full-screen display.

[0125] Furthermore, this disclosure provides a lead 41 connecting the first light-emitting element 31 and the first pixel circuit 21, and by providing N leads 41 in parallel in the lead group, the length of the first to N leads gradually increases, and between the first first light-emitting element of the first light-emitting element group 31a and the first first pixel circuit of the first pixel circuit group 21a 、 By providing at least one row of second pixel circuits or at least one column of second pixel circuits, it becomes easier to plan the path of the lead 41, improving the regularity of the length difference between any two adjacent leads 41 in the lead group 41a, improving the uniformity of the parasitic capacitance change formed by any two adjacent leads 41 in the lead group 41a, as well as between the first first light-emitting element and the first first pixel circuit. to By using at least one row of second pixel circuits or at least one column of second pixel circuits, the length of the first lead can be significantly increased, the ratio between the length of the Nth lead and the length of the first lead can be reduced, the ratio between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead can be reduced, the difference in the display grayscale of the display board 100 can be reduced, the external optical compensation (DEMURA) algorithm can be optimized, and the external optical compensation (DEMURA) algorithm can be reduced.

[0126] In some embodiments, among the N leads 41 provided in the lead group 41a, the ratio of the length of the Nth lead to the length of the 1st lead is α, where α ≤ 25.

[0127] In some cases, α = 25, α ≤ 24, α ≤ 22, α ≤ 20, or α ≤ 18, etc.

[0128] By setting the length ratio between the Nth lead and the First lead to 25 or less, the length ratio between the longest Nth lead and the shortest First lead can be effectively reduced, thereby reducing the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the First lead, and further reducing the grayscale difference of the image displayed by the display board 100. Furthermore, in the subsequent process of compensating for the grayscale difference using the external optical compensation (DEMURA) algorithm, the workload of the external optical compensation (DEMURA) algorithm can be reduced, and the external compensation (DEMURA) algorithm can be optimized.

[0129] For example, the above length ratio α satisfies α ≤ 15.

[0130] By setting the length ratio of the Nth lead to the length of the first lead to 15 or less, the length ratio of the longest Nth lead to the shortest first lead can be further reduced, thereby further reducing the difference between the parasitic capacitance formed by the Nth lead and the parasitic capacitance formed by the first lead, and further reducing the grayscale difference of the image displayed by the display board 100. Furthermore, in the subsequent process of compensating for the grayscale difference using the external optical compensation (DEMURA) algorithm, the workload of the external optical compensation (DEMURA) algorithm can be further reduced, and the external compensation (DEMURA) algorithm can be further optimized.

[0131] For example, the range of the length ratio α could be 5-10, 10-15, 15-20, or 7-13, etc.

[0132] For example, the value of the length ratio α may be 5, 6, 7.5, 9.1, 10, 12, 14, or 15, etc.

[0133] In some embodiments, the number of rows or columns of the second pixel circuit, which is spaced apart between the first first light-emitting element and the first first pixel circuit, is β, where β ≤ 30.

[0134] In some examples, as shown in Figures 9 to 11, the N first pixel circuits in the first pixel circuit group 21a are arranged sequentially along the first direction X. In this case, at least one row of second pixel circuits is provided with a gap between the first first light-emitting element and the first first pixel circuit. The number of rows of the second pixel circuits 22 provided with a gap is β, where β ≤ 30.

[0135] For example, the above β satisfies β=30, β≦28, β≦25, β≦21, β≦20, or β≦15, etc.

[0136] By using the above installation method, it is possible to keep the multiple of the length increase of the Nth lead small, thereby keeping the ratio of the length of the Nth lead to the length of the first lead small, and ensuring a good improvement effect on the grayscale difference of the image displayed by the display board 100, as well as a good optimization effect on the external compensation (demura) algorithm.

[0137] In some embodiments, the ratio of the number of rows or columns of the pixel circuit spaced between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of the second pixel circuit spaced between the first first light-emitting element and the first first pixel circuit is γ, where 5 ≤ γ ≤ 50.

[0138] It is understood that, in addition to the first first light-emitting element and the first first pixel circuit, a first pixel circuit 21 and a second pixel circuit 22 are provided at intervals between the i-th first light-emitting element and the i-th first pixel circuit. That is, the pixel circuit provided at intervals between the Nth first light-emitting element and the Nth first pixel circuit comprises a first pixel circuit and a second pixel circuit.

[0139] Furthermore, since the shape of the first display area A1 is deformable, the number of first light-emitting elements 31 provided in different first light-emitting element groups 31a may be different. For example, as shown in Figure 1, along the second direction Y, the closer the first light-emitting element group 31a gets to the upper or lower boundary of the first display area A1, the fewer the first light-emitting elements 31 provided in the first light-emitting element group 31a become, and the closer the first light-emitting element group 31a gets to the middle boundary of the first display area A1, the more the first light-emitting element group 31a gets.

[0140] In a first light-emitting element group 31a with a small number of elements, the ratio γ of the number of rows or columns of the pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of the second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit may be small. In a first light-emitting element group 31a with a large number of elements, the ratio γ of the number of rows or columns of the pixel circuits spaced apart between the Nth first light-emitting element and the Nth first pixel circuit to the number of rows or columns of the second pixel circuits spaced apart between the first first light-emitting element and the first first pixel circuit may be large.

[0141] By using the above installation method, the length of the Nth lead does not become too long, and the ratio of the length of the Nth lead to the length of the first lead can be kept small, thereby ensuring a good improvement effect on the grayscale difference of the image displayed by the display board 100, and a good optimization effect on the external compensation (demura) algorithm.

[0142] In some embodiments, the sequence formed by the length values ​​of the N leads 41 in the lead group 41a is an arithmetic progression. That is, the difference in length between any two adjacent leads 41 is equal. Alternatively, the sequence formed by the length values ​​of the N leads 41 in the first direction X in the lead group 41a is an arithmetic progression. That is, the difference in length between any two adjacent leads 41 is equal.

[0143] If there is an angle between the extension direction of lead 41 and the first direction X, it is understood that the length of lead 41 in the first direction X is the actual length of lead 41 equal to the portion in the first direction X.

[0144] For example, the length of the first lead is, for instance, L, and the difference in length between any two adjacent leads 41 in the lead group 41a is m. In this case, the sequence formed by the length values ​​of the N leads 41 is L, L+m, L+2m, L+3m...L+m(N-2), L+m(N-1). The length value of the lead 41 in the first direction X can be found in the explanation provided here and will not be repeated.

[0145] By arranging the sequence of the length values ​​of the N leads 41 or the length value of the first direction X in an arithmetic progression, it is possible to ensure that the length values ​​of the N leads 41 change uniformly, which is advantageous for optimizing the external optical compensation (DEMURA) algorithm and for improving the display quality of the display board 100. Furthermore, by using this arrangement method, it is also advantageous to improve the uniformity of the changes in parasitic capacitance formed by the N leads 41, which is advantageous for further optimization of the external optical compensation (DEMURA) algorithm and for further improving the display quality of the display board 100.

[0146] In some embodiments, the sequence formed by the resistance values ​​of the N leads 41 in the lead group 41a is an arithmetic progression. That is, the difference in resistance values ​​of any two adjacent leads 41 is equal.

[0147] For example, the resistance of the first lead is, for instance, R, and the difference in resistance between two adjacent leads 41 in lead group 41a is t. In this case, the sequence formed by the resistances of the N leads 41 is R, R+t, R+2t, R+3t...R+t(N-2), R+t(N-1).

[0148] It is understood that after the drive signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of resistance in the lead 41 causes some loss in the drive signal, resulting in a decrease in the accuracy of the drive signal received by the first light-emitting element 31.

[0149] By arranging the sequence of resistance values ​​of the N leads 41 in an arithmetic progression, it is possible to ensure that the resistance values ​​of the N leads 41 change uniformly. This is advantageous in reducing the difficulty of compensating for the resistance of the leads 41 and improves the display quality of the display board 100.

[0150] In some embodiments, parasitic capacitance is formed between each lead 41 and the second pixel circuit 22 and / or first pixel circuit 21 through which it passes. The sequence formed by the parasitic capacitance values ​​formed by the N leads 41 is an arithmetic progression. That is, the difference between the parasitic capacitances formed by any two adjacent leads 41 is equal.

[0151] For example, the parasitic capacity value formed by the first lead is, for example, Cs, and the difference in parasitic capacity between any two adjacent leads 41 in the lead group 41a is u. In this case, the above N leads 41 Parasitic capacity value formed by The sequence constructed by this is Cs, Cs+u, Cs+2u, Cs+3u...Cs+u(N-2), Cs+u(N-1).

[0152] It is understood that after the drive signal provided by the first pixel circuit 21 is transmitted to the lead 41, the presence of parasitic capacitance in the lead 41 causes a significant loss in the drive signal, resulting in a substantial decrease in the accuracy of the drive signal received by the first light-emitting element 31 and a delay in the time it takes for the first light-emitting element 31 to receive the drive signal.

[0153] By arranging the sequence of parasitic capacitance values ​​formed by the N leads 41 in an arithmetic progression, it is possible to ensure that the parasitic capacitance values ​​formed by the N leads 41 change uniformly. This facilitates compensation of the parasitic capacitance values ​​and delay time, which is advantageous for optimizing the external optical compensation (demura) algorithm and for improving the display quality of the display board 100.

[0154] It is understood that there may be multiple arrangement methods for the first to Nth first pixel circuits in the first pixel circuit group 21a.

[0155] In some examples, as shown in Figures 9 to 11, the above arrangement direction is the first direction X.

[0156] For example, the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting element group 31a are arranged in the same row. That is, along the first direction X, the first light-emitting element group 31a and the first pixel circuit group 21a are located in the same row. Correspondingly, the N leads 41 in the lead group 41a can extend along the first direction X.

[0157] In this case, between the first first light-emitting element and the first first pixel circuit 、 At least one row of second pixel circuits can be installed. Correspondingly, the N leads 41 can extend from the first display area A1 through the at least one row of second pixel circuits along the first direction X to the second display area A2.

[0158] Array direction By arranging the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting element group 31a in the same row, the arrangement of signal lines (e.g., gate lines) in the pixel circuit layer 2 is made easier, the driving of the first pixel circuit group 21a is made easier, and the difficulty of designing and manufacturing the display board 100 is reduced.

[0159] It is understood that since the first pixel circuit group 21a can be installed in the same row as the row of second pixel circuits, it is advantageous to drive the pixel circuit group 21a and the row of second pixel circuits simultaneously. Since at least one second pixel circuit 22 can be installed between any two adjacent first pixel circuits 21, the misalignment between the second pixel circuit 22 and the corresponding second light-emitting element 32 can be reduced. For example, the number of second pixel circuits 22 spaced apart between any two adjacent first pixel circuits 21 is the same. This is advantageous in improving the uniformity of the length changes of the N leads 41 in the lead group 41a and improving the uniformity of the parasitic capacitance changes formed by the N leads 41.

[0160] Exemplary, as shown in Figure 9, the first pixel circuit group 21a may comprise 20 first pixel circuits 21, the first light-emitting element group 31a may comprise 20 first light-emitting elements 31, and the lead group 41a may comprise 20 leads 41. A gap is provided between the first first light-emitting element and the first first pixel circuit. 4 A second pixel circuit of a row can be installed between any two adjacent first pixel circuits 21. 、 Two second pixel circuits 22 are provided, that is, one first pixel circuit 21 is provided with a gap between each pair of second pixel circuits 22.

[0161] For example, as shown in Figure 9, along the first direction X, the dimension of the area occupied by each second pixel circuit 22 or each first pixel circuit 21 is b, and the dimension of the area occupied by each first light-emitting element 31 is c, so 3b = 2c.

[0162] In this case, if there is no second pixel circuit spaced between the first first light-emitting element and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the area occupied by the first first pixel circuit and the first first pixel circuit, i.e., b+c=2.5b. The length difference between any two adjacent leads is the sum of the dimensions of the area occupied by the two second pixel circuits, one first pixel circuit, and one first light-emitting element, i.e., 2b+b+c=3b+c. Nth lead( for example The length of the 20th reed is (b+c)+19(3b+c)=88b. The ratio of the length of the 20th reed to the length of the 1st reed is 35.20.

[0163] If six rows of second pixel circuits are spaced apart between the first first light-emitting element and the first first pixel circuit, the length of the first lead is the sum of the dimensions of the area occupied by the first first pixel circuit, the first first light-emitting element, and the six second pixel circuits spaced apart between the first first pixel circuit and the first first light-emitting element, i.e., b+c+6b=7b+c. Since 3b=2c, 7b+c=8.5b. The difference in length between any two adjacent leads is the sum of the dimensions of the area occupied by the two second pixel circuits, one first pixel circuit, and one first light-emitting element, i.e., 2b+b+c=3b+c. The length of the Nth (i.e., the 20th) lead is (7b+c)+19(3b+c)=94b. The ratio of the length of the 20th lead to the length of the first lead is 11.06 (retaining two decimal places).

[0164] As can be seen from the above, when six rows of second pixel circuits are provided with spacing between the first first light-emitting element and the first first pixel circuit, the length of the first lead increases by 6b, and the multiplier of increase is relatively large, while the length of the Nth lead also increases by 6b, and the multiplier of increase is relatively small. Correspondingly, the ratio between the length of the 20th lead and the length of the first lead decreases significantly, which is advantageous for optimizing the external optical compensation (DEMURA) algorithm.

[0165] Selectively, this disclosure also relates to the relationship between each of the four second pixel circuits 22 、 One first pixel circuit 21 can be installed, or between each of the six second pixel circuits 22 、 One first pixel circuit 21 can be installed, or between each of the seven second pixel circuits 22 、 One first pixel circuit 21 can be installed, thereby the Nth lead lengthand the first lead length This allows for a reduction in the ratio of [the negative factor] and an optimization of the external optical compensation (DEMURA) algorithm.

[0166] In some other examples, the angle between the above-mentioned array direction and the first direction X is 45°. In this case, the N leads 41 in the lead group 41a can extend, for example, along a direction perpendicular to the first direction X, and extend from the first display area A1 to the second display area A2 through at least one row or at least one column of second pixel circuits along the direction perpendicular to the first direction X.

[0167] Furthermore, in some examples, the angle between the above-mentioned arrangement direction and the first direction X is 90°. In this case, the angle between the extending direction of the N leads 41 in the lead group 41a and the first direction X is, for example, 45°. These N leads 41 can extend from the first display area A1 to the second display area A2, passing through at least one row or at least one column of second pixel circuits along a direction that forms an angle of 45° with respect to the first direction X.

[0168] It is understood that, since the number of rows or columns of the second pixel circuit, which is spaced apart between the first first light-emitting element and the first first pixel circuit, can be selected and installed according to actual needs, the ratio of the length of the Nth lead 41 to the first lead 41 can be kept below a preset value.

[0169] The number of rows or columns of the second pixel circuit, which is selectively spaced between the first first light-emitting element and the first first pixel circuit, is related to the arrangement of sub-pixels P on the display board 100. That is, different arrangements of sub-pixels P may be different, and the number of rows or columns of the second pixel circuit, which is spaced between the first first light-emitting element and the first first pixel circuit, may be different. This is advantageous in ensuring the normal use of the external optical compensation algorithm (demura) and avoids confusion in the algorithm.

[0170] Exemplary, the sub-pixel P described above may include an electrically connected second pixel circuit 22 and a second light-emitting element 32. Of course, the sub-pixel P may also include an electrically connected first pixel circuit 21 and a first light-emitting element 31.

[0171] Hereinafter, assuming the above arrangement direction is the first direction X, and taking as an example the case where the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the light-emitting element group 31a are installed in the same row, we will briefly explain the number of columns of the second pixel circuit provided at intervals between the first first light-emitting element and the first first pixel circuit, depending on the arrangement method of the sub-pixels P.

[0172] In some examples, as shown in Figure 12, the display board 100 comprises multiple pixel units, each pixel unit comprising three sub-pixels P arranged along a first direction X.

[0173] For example, the three subpixels P described above include a red subpixel (R), a green subpixel (G), and a blue subpixel (B). Here, RGB are arranged periodically along the first direction X.

[0174] For example, between the first first light-emitting element and the first first pixel circuit, there are X second pixel circuits 22 belonging to at least one pixel unit, spaced apart, where X is a multiple of 3.

[0175] For example, three, six, nine, or twelve second pixel circuits 22 can be placed between the first first light-emitting element and the first first pixel circuit, with some spacing between them.

[0176] In some other examples, as shown in Figure 13, the display board 100 comprises multiple pixel units, each pixel unit comprising multiple sub-pixels P. The arrangement of these multiple pixel units is a pentile arrangement.

[0177] Exemplary, a PenTile array means that, for example, to realize RGBG, RGBW, RGBY, etc., one subpixel is added based on RGB, and a portion of the subpixels P in the PenTile array are "shared," thus achieving a higher resolution than the actual resolution in terms of visual effect. W represents a white subpixel, and Y represents a yellow subpixel. The number of subpixels P provided in each pixel unit can be determined depending on the sharing situation, and is not limited to this disclosure.

[0178] For example, between the first first light-emitting element and the first first pixel circuit, there are Y second pixel circuits belonging to at least one pixel unit, spaced apart, where Y is a multiple of 2.

[0179] For example, two, four, six, or eight second pixel circuits 22 can be installed between the first first light-emitting element and the first first pixel circuit, with a gap in between.

[0180] In some embodiments, as shown in Figures 10 and 11, the display substrate 100 has a straight line extending along a second direction Y and passing through the first display area A1, which can be called a reference line D-D'. The second direction Y is, for example, perpendicular to the first direction X.

[0181] The positional relationship between the first pixel circuit group 21a, the first light-emitting element group 31a, the lead group 41a, and the reference line D-D' on the display board 100 can vary and can be selected and installed according to actual needs.

[0182] In some examples, the first pixel circuit group 21a, the first light-emitting element group 31a, and the lead group 41a can all be located on the same side of the reference line D-D'.

[0183] In some other examples, as shown in Figures 10 and 11, the multiple first light-emitting elements 31 located in the first display area A1 may be arranged in multiple rows along the second direction Y, and each row of first light-emitting elements 31 may comprise a plurality of first light-emitting elements 31 arranged sequentially along the first direction X. The first light-emitting elements in each row may be divided into two groups of first light-emitting elements 31a located on either side of the reference line D-D'.

[0184] Correspondingly, two first pixel circuit groups 21a, electrically connected to two first light-emitting element groups 31a located in the same row, can each be located on opposite sides of the first direction X of the first display area A1. In this case, the two first pixel circuit groups 21a are located on both sides of the reference line D-D'.

[0185] Correspondingly, the two lead groups 41a electrically connected to the two first light-emitting element groups 31a located in the same row are located on either side of the reference line D-D'.

[0186] By arranging the first pixel circuit group 21a, the first light-emitting element group 31a, and the lead group 41a on both sides of the reference line D-D', the number of first pixel circuits 21 in the first pixel circuit group 21a, the number of first light-emitting elements 31 in the first light-emitting element group 31a, and the number of leads 41 in the lead group 41a can be reduced. This is advantageous in reducing the complexity of the lead paths and also in reducing the pressure on the external optical compensation (DEMURA) algorithm.

[0187] As an example, as shown in Figures 10 and 11, the two lead groups 41a electrically connected to the two first light-emitting element groups 31a are arranged symmetrically with respect to the reference line D-D'.

[0188] This not only further reduces the complexity of the lead paths of the leads 41, but is also advantageous in making the length change rules for the two lead groups 41a and the parasitic capacitance change rules formed thereby the same, further reducing the pressure on the external optical compensation (DEMURA) algorithm and allowing the external optical compensation (DEMURA) algorithm to be optimized.

[0189] As an example, as shown in Figures 10 and 11, the first display area A1 has a center O, and the above reference line D-D' is a straight line passing through the center O.

[0190] This makes it possible to make the number of first light-emitting elements 31 in the two first light-emitting element groups 31a located in the same row the same, and furthermore, the two corresponding first pixel circuits group The number of first pixel circuits provided in 21a can be made the same, and the number of reads 41 provided in the two corresponding read groups 41a can be made the same. This is advantageous in reducing the pressure on the external optical compensation (demura) algorithm.

[0191] It is understood that the first light-emitting element 31 and the corresponding lead 41 are electrically connected via a transfer hole 5 (i.e., a via hole) to avoid a short circuit.

[0192] Based on this, in some examples, as shown in Figures 14 and 15, the display board 100 further comprises a group of transfer holes 5a. The group of transfer holes 5a comprises N transfer holes 5. The N transfer holes 5 are arranged sequentially along a first direction X and each corresponds to one of the N first light-emitting elements 31 in the first light-emitting element group 31a.

[0193] For example, the N transfer holes 5 in the transfer hole group 5a and the N first light-emitting elements 31 in the first light-emitting element group 31a are provided in a one-to-one correspondence. Similarly, the N transfer holes 5 in the transfer hole group 5a and the N leads 41 in the lead group 41a are provided in a one-to-one correspondence. As a result, each first light-emitting element 31 can be electrically connected to the corresponding lead 41 via the corresponding transfer hole 5.

[0194] The orthographic shape of the transfer hole 5 on the base 1 can be selectively chosen and installed according to the actual needs. For example, the orthographic shape of the transfer hole 5 on the base 1 may be circular or rectangular, etc.

[0195] Here, the positional relationship between the N leads 41 in the lead group 41a and the transfer hole group 5a can vary. The following is a schematic explanation using the case where the first light-emitting element group 31a and the first pixel circuit group 21a electrically connected to the first light-emitting element group 31a are installed in the same row along the first direction X as an example.

[0196] As an example, as shown in Figure 14, along the second direction Y, the i-th lead electrically connected to the i-th first light-emitting element is closer to the transfer hole group 5a than the (i+1)th lead electrically connected to the (i+1)th first light-emitting element.

[0197] In other words, the N leads 41 in the lead group 41a are located on the same side of the transfer hole group 5a, and along the second direction Y, the 1st, 2nd, 3rd...N-1th, and Nth leads move sequentially away from the transfer hole group 5a.

[0198] As an example, as shown in Figure 15, the i-th lead electrically connected to the i-th first light-emitting element and the (i+1)th lead electrically connected to the (i)-1th first light-emitting element are located on opposite sides of the transfer hole group 5a in the second direction Y.

[0199] In other words, in the lead group 41a, odd-numbered leads can be located on one side of the second direction Y of the transfer hole group 5a, and even-numbered leads can be located on the other side of the second direction Y of the transfer hole group 5a.

[0200] In some embodiments, as shown in Figures 2 to 6, the display substrate 100 may further include a plurality of lead layers 4 provided between the pixel circuit layer 2 and the light-emitting element layer 3. These plurality of lead layers 4 can be sequentially stacked along a direction perpendicular to the base 1. For example, the number of lead layers 4 may be two, three, or more.

[0201] Between the pixel circuit layer 2 and the multiple lead layers 4 described above 、 An insulating layer can be installed between any two adjacent lead layers 4. 、 An insulating layer can be installed between the multiple lead layers 4 and the light-emitting element layer 3. 、 An insulating layer can be installed. As shown in Figure 4, the transfer hole group 5a may be located in the insulating layer between the multiple lead layers 4 and the light-emitting element layer 3. In Figure 4, the light-emitting element layer 3 is represented as the anode.

[0202] In some examples, the N leads 41 in lead group 41a are each located in one of the multiple lead layers 4 described above.

[0203] Exemplary, each lead layer 4 may have at least one lead 41 out of N leads 41.

[0204] Exemplary, as shown in Figures 4, 6, and 17, each lead layer 4 may further comprise a plurality of connection portions 42. These connection portions 42 can change the layer of leads 41 electrically connected to them, and the leads 41 may be electrically connected to the corresponding first light-emitting element 31 or first pixel circuit 21.

[0205] For example, as shown in Figures 3 and 4, taking the number of lead layers 4 as three, as shown in Figure 4, the three lead layers 4 are the first lead layer 4a, the second lead layer 4b, and the third lead layer 4c, respectively, along the vertical direction and away from the base 1.

[0206] As shown in Figure 4, each second pixel circuit 22 can be electrically connected to the corresponding second light-emitting element 32 sequentially via a connection part 42 located on the first lead layer 4a, a connection part 42 located on the second lead layer 4b, and a connection part 42 located on the third lead layer 4c. 4 Next, the anode of the second light-emitting element 32 is used to represent the second light-emitting element 32, and in the second pixel circuit 22 Second light emission control The second pixel circuit 22 is represented using transistor T5.

[0207] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located in the first lead layer 4a, and the other end of the lead 41 may be electrically connected to the corresponding first light-emitting element 31 via a connecting portion 42 located in the second lead layer 4b and a connecting portion 42 located in the third lead layer 4c, in sequence.

[0208] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located in the second lead layer 4b via a connection portion 42 located in the first lead layer 4a, and the other end of the lead 41 may be electrically connected to the corresponding first light-emitting element 31 via a connection portion 42 located in the third lead layer 4c.

[0209] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located in the third lead layer 4c via a connecting portion 42 located in the first lead layer 4a and a connecting portion 42 located in the second lead layer 4b, and the other end of the lead 41 may be electrically connected to the corresponding first light-emitting element 31.

[0210] For example, as shown in Figures 5 and 6, the number of lead layers 4 is 2. 6As shown, the two lead layers 4 are the first lead layer 4a and the second lead layer 4b, respectively, along the vertical direction and away from the base 1.

[0211] As shown in Figure 6, each second pixel circuit 22 can be electrically connected to the corresponding second light-emitting element 32 sequentially via a connection portion 42 located on the first lead layer 4a and a connection portion 42 located on the second lead layer 4b. 6 Next, the anode of the second light-emitting element 32 is used to represent the second light-emitting element 32, and in the second pixel circuit 22 Second light emission control The second pixel circuit 22 is represented using transistor T5.

[0212] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located in the first lead layer 4a, and the other end of the lead 41 may be electrically connected to the corresponding first light-emitting element 31 by a connection portion 42 located in the second lead layer 4b.

[0213] For example, a portion of the first pixel circuit 21 may be electrically connected to one end of a lead 41 located in the second lead layer 4b by a connection portion 42 located in the first lead layer 4a, and the other end of the lead 41 may be electrically connected to the corresponding first light-emitting element 31.

[0214] In some examples, the material of the multiple lead layers 4 described above comprises a light-transmitting conductive material.

[0215] It is understood that light-transmitting conductive materials have high transmittance. By forming the lead layer 4 using a light-transmitting conductive material, the leads 41 located in the lead layer 4 are given high transmittance, and shielding of light rays that pass through the portion located in the first display area A1 of the display substrate 100 can be avoided, thereby ensuring high transmittance in the portion located in the first display area A1 of the display substrate 100.

[0216] Exemplary, the translucent conductive material described above may include at least one of the following materials: indium tin oxide, indium zinc oxide, indium gallium zinc oxide, etc.

[0217] In some embodiments, as shown in Figures 3 to 6, the display substrate 100 further comprises a transfer layer 6 provided between the pixel circuit layer 2 and the plurality of lead layers 4. The material of the transfer layer 6 includes a metallic material.

[0218] For example, the material of the transfer layer 6 may be the same as the material of the source-drain conductive layer. This ensures that the transfer layer 6 has good conductivity.

[0219] For example, the above-mentioned metal material may include copper or aluminum.

[0220] In some examples, as shown in Figures 4 and 6, the transfer layer 6 is provided with a plurality of transfer units 61. Each of these transfer units 61 corresponds to a plurality of first pixel circuits 21 and a plurality of second pixel circuits 22 provided on the display board 100, and is provided, for example, in a one-to-one correspondence. Each transfer unit 61 may be connected to the second pole of the second light emission control transistor T5 and to the lead layer 4 closest to the base 1.

[0221] By providing the transfer layer 6, the wiring space of the display board 100 can be increased, which is advantageous in reducing the difficulty of wiring.

[0222] In Figure 16, the broken dashed line represents the boundary between the first display area A1 and the second display area A2. The rightmost first light-emitting element 31 is the first first light-emitting element, and the leftmost first pixel circuit 21 is the first first pixel circuit. The lead 41 connecting the first first light-emitting element and the first first pixel circuit is the first lead. The first pixel circuit 21 is located in the area enclosed by the H-shaped solid line in Figure 16, and the second pixel circuit 22 is located in the area between two adjacent H-shaped solid lines. For information on virtual pixel circuits, please refer to the following explanation, which will not be repeated here.

[0223] In some examples, as shown in Figure 17, the number of lead layers 4 provided on the display board 100 is 2. The above N leads 41 In , The first, the Nth, odd-numbered leads and even-numbered leads teeth, Each Two lead layers 4 to It is located.

[0224] This allows for a large gap to be maintained between any two adjacent leads 41 located on the same lead layer 4, thereby avoiding the formation of a short circuit between two adjacent leads 41 and ensuring the transmission accuracy of the drive signal.

[0225] Furthermore, there are various installation methods between the first pixel circuit 21 and the second pixel circuit 22 located in the second display area A2, and these can be selected and installed according to actual needs.

[0226] In some examples, as shown in Figure 10, the second display area A2 comprises a normal area A21b and a compressed area A22b. The first pixel circuit group 21a is located in the compressed area A22b, some of the second pixel circuits 22 of the plurality of second pixel circuits 22 are located in the normal area A21b, and another portion of the second pixel circuits 22 are located in the compressed area A22b. In the compressed area A22b, at least one second pixel circuit 22 is provided between two adjacent first pixel circuits 21 along the first direction X. The width of the column area where the first pixel circuit 21 or second pixel circuit 22 located in the compressed area A22b is located is smaller than the width of the column area where the second pixel circuit 22 located in the normal area A21b is located.

[0227] For example, the width of the column region in which the first pixel circuit 21 is located is: First pixel circuit This refers to the dimension of the region occupied by the pixel circuit array where 21 is located in the first direction X. The width of the array region where the second pixel circuit 22 is located is: Second pixel circuit This refers to the dimensions of the region occupied by the pixel circuit array where 22 is located in the first direction X.

[0228] The width of the column region where the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is situated is smaller than the width of the column region where the second pixel circuit 22 located in the normal region A21b is situated. In other words, the width of the column region where the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is situated is compressed, while the width of the column region where the second pixel circuit 22 located in the normal region A21b is situated is not compressed.

[0229] By compressing the width of the column region where the first pixel circuit 21 or the second pixel circuit 22 located in the compressed region A22b is situated, space for arranging the first pixel circuit 21 can be created in the compressed region A22b.

[0230] In some other embodiments, as shown in Figure 11 、 In the first direction X, the width of the column region where the first pixel circuit 21 or the second pixel circuit 22 is located is compressed.

[0231] This is advantageous in further expanding the space in which the first pixel circuit 21 can be placed, and makes it easier to place more first pixel circuits 21 in the second display area A2.

[0232] Furthermore, the virtual pixel circuits shown in Figures 9, 14, 15, and 16 mean that no pixel circuits are provided in the area occupied by the rectangular pattern, and that the width of the rectangular pattern in the first direction X is the same as the width of the column area where the first pixel circuit 21 or the second pixel circuit 22 is located. This is advantageous in improving the regularity of the arrangement of the second pixel circuit 22 and improving the regularity of the change in the length of the lead 41.

[0233] Some embodiments of this disclosure provide a display device 1000. As shown in Figures 18 and 19, the display device 1000 comprises a display substrate 100 as described in any of the above embodiments and an optical element 200 provided on the non-emitting side of the display substrate 100. The optical element 200 is located in a first display area A1 of the display substrate 100.

[0234] In some examples, the optical element 200 described above may include a photosensitive device. Exemplarily, the photosensitive device may include an image acquisition device (e.g., a camera) or an infrared receiving device.

[0235] Here, the number of optical elements 200 can be selected and installed according to the actual needs.

[0236] For example, if the optical element 200 is placed in the first display area A1 and positioned on the non-emitting side of the display substrate 100, then ambient light can pass through the portion of the display substrate 100 located in the first display area A1 and enter the optical element 200, thereby operating the optical element 200.

[0237] For example, when the optical element 200 is not operating, the portion located in the first display area A1 of the display board 100 can be displayed, so the entire display board 100 and the display device 1000 can also display an image.

[0238] For example, when the optical element 200 (e.g., an image acquisition device) is operating (e.g., a user is taking a selfie), the first display area A1 may display a black screen, and the second display area A2 may display the screen showing the user taking a selfie, making the location of the image acquisition device clearer. Alternatively, the entirety of the first display area A1 and the second display area A2 may display the screen showing the user taking a selfie, without showing the location of the image acquisition device.

[0239] The beneficial effects that can be realized by the display device 1000 provided by some embodiments of the present invention are the same as the beneficial effects that can be realized by the display substrate 100 described in the above embodiments, and will not be described again here.

[0240] In some examples, the display device 1000 may further include a frame, a circuit board provided within the frame, a display driver IC (Integrate Circuit), and other electronic elements.

[0241] In some embodiments, the display device 1000 described above may be any product or component having display and image acquisition functions, such as a mobile phone, tablet computer, notebook computer, laptop computer, personal computer, display, or wearable device.

[0242] The foregoing describes only specific embodiments of the Disclosure, and the scope of protection of the Disclosure is not limited thereto. Any modifications or substitutions that are readily conceivable to a person skilled in the art within the technical scope of the Disclosure are all included within the technical scope of the Disclosure. Accordingly, the scope of protection of the Disclosure shall be governed by the scope set forth in the claims.

Claims

1. A display board including a first display area and a second display area, wherein at least a portion of the second display area surrounds the first display area. A first light-emitting group provided in the first display area, wherein the first light-emitting group comprises N first light-emitting elements, and along a first direction and pointing from the second display area to the first display area, the N first light-emitting elements are each the 1st to the Nth first light-emitting elements, A first pixel circuit group provided in the second display area, the first pixel circuit group comprises N first pixel circuits, the first to the Nth first pixel circuits being provided sequentially along the direction away from the first display area, A group of leads comprising N leads arranged in parallel, wherein the i-th first light-emitting element is electrically connected to the i-th first pixel circuit by the i-th lead, the lengths of the first to N leads gradually increase, N ≥ 2, N is an integer, and i = 1 to N; A plurality of second pixel circuits provided in the second display area, wherein the plurality of second pixel circuits are arranged in a plurality of columns along the first direction and in a plurality of rows along the second direction, and the first direction intersects the second direction with the plurality of second pixel circuits, Equipped with, Between the first first light-emitting element and the first first pixel circuit, at least one row of second pixel circuits or at least one column of second pixel circuits is provided, and the N leads extend from the first display area through the at least one row of second pixel circuits or the at least one column of second pixel circuits to the second display area. The aforementioned display board is Bass and, A pixel circuit layer provided on the base, wherein the first pixel circuit group and the plurality of second pixel circuits are located on the pixel circuit layer, A light-emitting element layer provided on the side of the pixel circuit layer away from the base, wherein the first light-emitting element group comprises a light-emitting element layer located on the light-emitting element layer, Two lead layers are provided between the pixel circuit layer and the light-emitting element layer, wherein the material of the two lead layers is a light-transmitting conductive material, Equipped with, In the N leads of the aforementioned lead group, the odd-numbered leads and the even-numbered leads are located in the two lead layers, respectively. Display board.

2. The first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. Between the first light-emitting element and the first pixel circuit, at least one row of second pixel circuits is provided. The N leads extend from the first display area through the at least one row of second pixel circuits along the first direction to the second display area. The display board according to claim 1.

3. The display comprises a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element is electrically connected to at least one second pixel circuit, and the at least one second light-emitting element and the at least one second pixel circuit have orthographic projections in the plane on which the display substrate is located that overlap at least partially. The display board comprises a plurality of pixel units, each pixel unit comprises three subpixels arranged along the first direction, and each subpixel comprises an electrically connected second light-emitting element and a second pixel circuit. Between the first light-emitting element and the first pixel circuit, at least X second pixel circuits belonging to one pixel unit are provided at intervals, where X is a multiple of 3. The display board according to claim 2.

4. The display comprises a plurality of second light-emitting elements provided in the second display area, at least one second light-emitting element is electrically connected to at least one second pixel circuit, and the at least one second light-emitting element and the at least one second pixel circuit have orthographic projections in the plane on which the display substrate is located that overlap at least partially. The display board further comprises a plurality of pixel units, each pixel unit comprises a plurality of subpixels, each subpixel comprises an electrically connected second light-emitting element and a second pixel circuit, and the arrangement of the plurality of pixel units is a pentile arrangement. Between the first light-emitting element and the first pixel circuit, at least Y second pixel circuits belonging to one pixel unit are provided at intervals, where Y is a multiple of 2. The display board according to claim 2.

5. The sequence formed by the length values ​​of the N leads in the first direction is an arithmetic progression. The display board according to claim 1.

6. The sequence formed by the resistance values ​​of the N leads is an arithmetic progression. The display board according to claim 5.

7. A parasitic capacitance is formed between each lead and the second and / or first pixel circuit through which it passes. The sequence formed by the parasitic capacity values ​​created by the N leads is an arithmetic progression. The display board according to claim 5 or 6.

8. The display board comprises a plurality of rows of first light-emitting elements located in the first display area, the first light-emitting elements in each row are divided into two groups of first light-emitting elements located on either side of a reference line, the reference line is a single straight line extending along the second direction and passing through the first display area, and the second direction is perpendicular to the first direction. The two first pixel circuit groups electrically connected to the two first light-emitting element groups are located on opposite sides in the first direction of the first display area, The two lead groups electrically connected to the two first light-emitting element groups are located on both sides of the reference line, The display board according to claim 1.

9. The two lead groups electrically connected to the two first light-emitting element groups are arranged symmetrically with respect to the reference line. The display board according to claim 8.

10. The first display area has a center, and the reference line is a straight line passing through the center. The display board according to claim 8 or 9.

11. The first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. The display board further comprises a group of transfer holes, the group of transfer holes comprises N transfer holes, the N transfer holes are arranged sequentially along the first direction, and each corresponds to one of the N first light-emitting elements. Along the second direction, the i-th lead electrically connected to the i-th first light-emitting element is closer to the transfer hole group than the i+1-th lead electrically connected to the (i+1)-th first light-emitting element, and the second direction is perpendicular to the first direction. The display board according to claim 1.

12. The first group of light-emitting elements and the first group of pixel circuits electrically connected to the first group of light-emitting elements are arranged in the same row along the first direction. The display board further comprises a group of transfer holes, the group of transfer holes comprises N transfer holes, the N transfer holes are arranged sequentially along the first direction, and each corresponds to one of the N first light-emitting elements. The i-th lead electrically connected to the i-th first light-emitting element and the (i+1)th lead electrically connected to the (i)-th first light-emitting element are located on opposite sides of the transfer hole group in the second direction, and the second direction is perpendicular to the first direction. The display board according to claim 1.

13. Of the N leads mentioned above, the length ratio between the Nth lead and the first lead is α, where α ≤ 25. The display board according to claim 1.

14. The number of rows or columns of the second pixel circuit, which is spaced apart from the first first light-emitting element and the first first pixel circuit, is β, and β ≤ 30. The display board according to claim 1.

15. The ratio of the number of rows or columns of the pixel circuit spaced apart between the nth first light-emitting element and the nth first pixel circuit to the number of rows or columns of the second pixel circuit spaced apart between the first first light-emitting element and the first first pixel circuit is γ, where 5 ≤ γ ≤ 50. The display board according to claim 1.

16. The second display area includes a normal area and a compressed area, the first pixel circuit group is located in the compressed area, a portion of the plurality of second pixel circuits is located in the normal area, another portion of the second pixel circuits is located in the compressed area, and in the compressed area, at least one second pixel circuit is provided between two adjacent first pixel circuits along the first direction. The width of the column region in which the first or second pixel circuit located in the compression region is situated is smaller than the width of the column region in which the second pixel circuit located in the normal region is situated. The display board according to claim 1.

17. The display board according to claim 1, An optical element provided on the non-light-emitting side of the display substrate, wherein the optical element is located in the first display area of ​​the display substrate, Equipped with, Display device.

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