Delay chain circuits and electronic devices

Abstract

To provide a delay chain circuit and an electronic device, which can achieve a delay chain switching function without a glitch.SOLUTION: A delay chain circuit includes: a delay branch circuit 100; an inversion processing branch circuit 110; and a glitch elimination branch circuit 120. The delay branch circuit receives an input signal IN and acquires a first delay signal intAC and a second delay signal intBD. The inversion processing branch circuit receives the first delay signal and acquires a third delay signal, and receives the second delay signal and acquires a fourth delay signal. The glitch elimination branch circuit integrates the third delay signal with the fourth delay signal, acquires a signal intCD after the integration, performs inversion processing on the signal after the integration and acquires an output signal OUT. When the delay chain is required to be adjusted, a delay amount of either the first delay signal or the second delay signal is adjusted, the third delay signal is integrated with the fourth delay signal, and a glitch is eliminated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application relates to the technical field of circuits, and more specifically to delay chain circuits and electronic devices. [Background technology]

[0002] A configurable delay chain is a circuit structure that can achieve different delay effects by controlling the input of delay code values. It is widely used in various PHY designs and is an important circuit configuration in many interface modules, especially an essential component in high-speed interface systems such as DDR and Serdes PHYs. How to design an accurate and efficient delay chain is often a performance bottleneck in high-speed interface systems.

[0003] Current delay chain designs all lack glitch-free switching capabilities and essentially rely on the same circuit structure to achieve several fixed delay units. In such designs, regardless of how the delay code value is converted, there is a possibility that the transmitted signal will collide with the conversion of the delay code value, resulting in glitches in the transmitted signal and posing a risk to the transmission system. Therefore, mainstream designs generally require no signal transmission when the delay code value is converted, and signal transmission can only continue after the code value has stabilized. Such designs have significant limitations in practical applications, as many systems cannot interrupt data stream transmission, requiring the delay code value to remain unchanged, thus imposing many constraints on high-speed interface systems. [Overview of the project]

[0004] In view of the above issues, the present invention provides a delay chain circuit and electronic device that can realize a glitch-free delay chain switching function while imposing certain constraints on each change in the delay code value. This allows for dynamic adjustment of the delay chain delay without interrupting data stream transmission, thereby significantly improving the operating performance of high-speed interface systems.

[0005] The embodiments of this application are realized by the following technical means. The delay chain circuit includes a delay branch circuit, an inverting branch circuit, and a glitch removal branch circuit. The delay branch circuit performs a delay process on an input signal, then obtains a first delay signal and a second delay signal, with a delay amount between the first and second delay signals. The inverting branch circuit performs an inverting delay process on the first delay signal to obtain a third delay signal, and performs an inverting delay process on the second delay signal to obtain a fourth delay signal. The glitch removal branch circuit integrates the third and fourth delay signals to obtain an integrated signal, and performs an inverting process on the integrated signal to obtain an output signal, the delay amount of the output signal being between the delay amount of the third delay signal and the delay amount of the fourth delay signal.

[0006] Preferably, the delay branch circuit includes a first coarse delay chain and a second coarse delay chain installed in parallel, wherein the first coarse delay chain delays the input signal by a plurality of coarse delay times to obtain the first delayed signal, and the second coarse delay chain delays the input signal by a plurality of coarse delay times to obtain the second delayed signal.

[0007] Preferably, the first coarse delay chain includes a plurality of first coarse delay groups connected in series in sequence, each of the first coarse delay groups receives one first coarse delay code signal, each of the first coarse delay groups includes at least two first coarse delay units, and for each of the first coarse delay groups, if the first coarse delay code signal corresponding to the first coarse delay group is valid, each of the first coarse delay units in the first coarse delay group is valid, and if the first coarse delay units are valid, the first coarse delay units delay the input signal by one coarse delay time, and the first coarse delay chain determines the amount of delay for the input signal based on the number of corresponding valid first coarse delay code signals in the plurality of first coarse delay groups and the number of first coarse delay units included in the first coarse delay group, and performs delay processing on the input signal based on the determined amount of delay to obtain the first delayed signal.

[0008] Preferably, the second coarse delay chain includes one forced delay unit and a plurality of second coarse delay groups connected in series in order, the forced delay unit being connected in series to the second coarse delay groups, each second coarse delay group receiving one second coarse delay code signal, each second coarse delay group including at least two second coarse delay units, and for each second coarse delay group, if the second coarse delay code signal corresponding to the second coarse delay group is valid, then each second coarse delay unit in the second coarse delay group is valid, If the second coarse delay unit is enabled, the second coarse delay unit delays the input signal by one coarse delay time, the forced delay unit delays the input signal by one coarse delay time, the second coarse delay chain determines the amount of delay for the input signal based on the number of corresponding enabled second coarse delay code signals in a plurality of second coarse delay groups, the number of second coarse delay units included in the second coarse delay group, and the forced delay unit, and performs delay processing on the input signal based on the determined amount of delay to obtain the second delayed signal.

[0009] Preferably, the glitch-removal branch circuit includes two precision delay chains, one of which inverts the first delay signal and delays it by a plurality of precision delay times to obtain a third delay signal, and the other precision delay chain inverts the second delay signal and delays it by a plurality of precision delay times to obtain a fourth delay signal, wherein the delay amounts provided by the two precision delay chains are the same, and the maximum total delay amount provided by the plurality of precision delay times in one precision delay chain is equal to the delay amount provided by one coarse delay time.

[0010] Preferably, the precision delay chain includes a first switch and a second switch, wherein the first switch conducts the glitch-removal branch circuit to the high level when the first delay signal or the second delay signal is at a low level, and the second switch grounds the glitch-removal branch circuit when the first delay signal or the second delay signal is at a high level.

[0011] Preferably, both the first switch and the second switch are electronic switches, the control terminals of both the first and second switches receive either the first or second delay signal, the input terminal of the first switch is connected to a high level, the output terminal is connected to the input terminal of the second switch, the output terminal of the second switch is grounded, and the glitch-removal branch circuit is connected between the first and second switches.

[0012] Preferably, the precision delay chain includes a plurality of precision delay units connected in parallel, each of which includes one charge current source and one discharge current source connected in series, and the precision delay unit receives one precision delay code signal, and if the precision delay code signal is valid, increases the signal delay amount by the precision delay unit by one precision delay time by turning off the corresponding charge current source and discharge current source, and if the precision delay code signal is invalid, decreases the signal delay amount by the precision delay unit by one precision delay time by turning on the corresponding charge current source and discharge current source, and the precision delay chain determines the number of charge current sources and discharge current sources to be turned off based on the number of valid precision delay code signals corresponding to the plurality of precision delay units, thereby determining the delay amount for the first delay signal or the second delay signal, and performs delay processing on the inverted first delay signal or the second delay signal based on the determined delay amount to obtain the third delay signal or the fourth delay signal.

[0013] Preferably, the glitch-removal branching circuit includes an output inverter and a capacitor, the capacitor having one end connected to the input terminal of the output inverter, connected between the negative terminal of the charging current source and the positive terminal of the discharge current source, and the other end grounded, the capacitor integrating the third delay signal and the fourth delay signal to obtain the integrated signal, and the output inverter inverting the integrated signal to obtain an output signal.

[0014] The electronic device according to the embodiment of the present application includes the above-mentioned delay chain circuit.

[0015] Compared to the prior art, the delay chain circuit and electronic device according to the embodiment of the present application obtain a first delay signal and a second delay signal having different delay amounts by performing different delay processing on the input signal using the delay chain circuit, obtain a third delay signal by performing inverting delay processing on the first delay signal using the inverting branch circuit, obtain a fourth delay signal by performing inverting delay processing on the second delay signal using the inverting branch circuit, integrate the third delay signal and the fourth delay signal using the glitch removal branch circuit to obtain an integrated signal, and obtain an output signal by performing inverting processing on the integrated signal, and delay of the output signal The delay chain needs to be adjusted so that the amount is between the delay amount of the third delay signal and the delay amount of the fourth delay signal. If it is necessary to adjust the delay chain, the delay amount of either the first delay signal or the second delay signal is adjusted to cause a glitch in only the first delay signal or only the second delay signal. If the glitch removal branch circuit integrates the third and fourth delay signals, the third and fourth delay signals are integrated to remove the glitch, and the integrated signal is inverted to obtain the output signal. This dynamically adjusts the delay of the delay chain without interrupting the input signal, achieving glitch-free delay chain switching.

[0016] These or other aspects of the present application can be understood more concisely in the following description of the embodiments. [Brief explanation of the drawing]

[0017] To more clearly explain the technical means in the embodiments of this application, the drawings necessary for the description of the embodiments are briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without creative effort. [Figure 1] It is a module block diagram of a delay chain circuit according to an embodiment of this application. [Figure 2] It is a schematic diagram of a first coarse delay chain according to an embodiment of this application. [Figure 3] It is a schematic diagram of a second coarse delay chain according to an embodiment of this application. [Figure 4] It is a circuit principle diagram of a precision delay chain according to an embodiment of this application. [Figure 5] It is a principle diagram of a precision delay chain and a glitch removal branch circuit according to an embodiment of this application. [Figure 6] It is a waveform diagram of a first delay signal and a third delay signal according to an embodiment of this application. [Figure 7] It is a waveform diagram of a first delay signal and a third delay signal according to another embodiment of this application. [Figure 8] It is a waveform diagram of each signal before the switching of the code value according to an embodiment of this application. [Figure 9] It is a waveform diagram of each signal after the switching of the code value according to an embodiment of this application. [Figure 10] It is another waveform diagram of each signal after the switching of the code value according to an embodiment of this application. [Figure 11] It is yet another waveform diagram of each signal after the switching of the code value according to an embodiment of this application.

Embodiments for Carrying out the Invention

[0018] Embodiments of the present application are described in detail below, examples of which are shown in the drawings, where the same or similar reference numerals throughout the drawings indicate the same or similar components or components having the same or similar function. The embodiments described below with reference to the drawings are illustrative for interpretation of the present application and should not be construed as limiting the present application.

[0019] For a person skilled in the art to better understand the means of the present application, the technical means in the embodiments of the present application are described below clearly and completely with reference to the accompanying drawings of the embodiments. Clearly, the embodiments described are only a selection of the embodiments of the present application, not all of them. All other embodiments that a person skilled in the art can derive from the embodiments of the present application without any creative work are all included within the scope of the present application.

[0020] As shown in Figure 1, Figure 1 schematically shows a modular schematic diagram of the delay chain circuit according to the present invention, which includes a delay branch circuit 100, an inversion processing branch circuit 110, and a glitch removal branch circuit 120. The delay branch circuit 100 performs delay processing on the input signal IN, and then obtains a first delay signal int AC and a second delay signal int BD, and there is a delay amount between the first delay signal int AC and the second delay signal int BD. Specifically, the delay branch circuit 100 includes a first coarse delay chain Delay A and a second coarse delay chain Delay B installed in parallel. The input terminal in A of the first coarse delay chain Delay A and the input terminal in B of the second coarse delay chain Delay B simultaneously receive an input signal IN, which may be a clock signal or another periodic signal. The first coarse delay chain Delay A delays the input signal IN by a plurality of coarse delay times CD and outputs a first delay signal int AC from its output terminal out A. The second coarse delay chain Delay B delays the input signal IN by a plurality of coarse delay times CD and obtains a second delay signal int BD from its output terminal out B.

[0021] The inverting branch circuit 110 performs an inverting delay process on the first delay signal int AC to obtain the third delay signal output Delay C, and performs an inverting delay process on the second delay signal int BD to obtain the fourth delay signal output Delay D. Specifically, the inverting branch circuit 110 includes two precision delay chains, Delay C and Delay D, with the same configuration for Delay C and Delay D. The input terminal in C of one precision delay chain, Delay C, is connected to the output terminal out A of the first coarse delay chain, Delay A. The precision delay chain Delay C inverts the first delay signal int AC and delays it by a multiple precision delay time FD to obtain a third delay signal output Delay C. The input terminal in D of another precision delay chain Delay D is connected to the output terminal out B of a second coarse delay chain Delay B. The precision delay chain Delay D inverts the second delay signal int BD and delays it by a precision delay time FD to obtain a fourth delay signal output Delay D.

[0022] The maximum total delay given by multiple precise delay times FD in precision delay chains Delay C and Delay D is equal to the delay given by a single coarse delay time CD, i.e., CD = mFD (where m is a positive integer).

[0023] The glitch-removal branch circuit 120 is simultaneously connected to the two output terminals out C and out D of the precision delay chain, and integrates the third delay signal output Delay C and the fourth delay signal output Delay D to obtain the integrated signal int CD. The integrated signal int CD is then inverted to obtain the output signal OUT, and the delay amount of the output signal OUT is between the delay amount of the third delay signal output Delay C and the delay amount of the fourth delay signal output Delay D.

[0024] The first coarse delay chain Delay A and the second coarse delay chain Delay B simultaneously receive the input signal IN, and perform different delay processing on the input signal IN to obtain a first delay signal int AC and a second delay signal int BD having different delay amounts. The precision delay chain Delay C performs an inverting delay process on the first delay signal int AC to obtain a third delay signal output Delay C, and the precision delay chain Delay D performs an inverting delay process on the second delay signal int BD to obtain a fourth delay signal output Delay D. The glitch removal branch circuit 120 integrates the third delay signal output Delay C and the fourth delay signal output Delay D to obtain the integrated signal int CD, and performs an inverting process on the integrated signal int CD to obtain the output signal OUT. If it is necessary to adjust the delay chain so that the delay amount of the output signal OUT is between the delay amount of the third delay signal output Delay C and the delay amount of the fourth delay signal output Delay D, the first delay signal int AC and the second delay signal int By adjusting the delay amount of either BD, a glitch is generated only in the first delay signal int AC or only in the second delay signal int BD. When the glitch removal branch circuit 120 integrates the third delay signal output Delay C and the fourth delay signal output Delay D, the third delay signal output Delay C and the fourth delay signal output Delay D are integrated to remove the glitch, and the integrated signal int CD is inverted to obtain the output signal OUT. This dynamically adjusts the delay of the delay chain without interrupting the input signal IN, achieving glitch-free delay chain switching.

[0025] As shown in Figure 2, Figure 2 shows a schematic diagram of the first coarse delay chain Delay A, which includes a plurality of first coarse delay groups connected in series in order, each first coarse delay group receiving one first coarse delay code signal, each first coarse delay group including at least two first coarse delay units, and for each first coarse delay group, if the first coarse delay code signal corresponding to the first coarse delay group is valid, each first coarse delay unit in the first coarse delay group is valid, and if the first coarse delay unit is valid, the first coarse delay unit delays the input signal IN by one coarse delay time CD, and if the first coarse delay unit is invalid, the delay amount of the input signal IN by the first coarse delay unit is zero.

[0026] To make it understandable, once the input signal IN passes through, the input signal IN can be delayed by one coarse delay time CD, and unless the polarity of the input signal IN is changed, the first coarse delay unit can use a delay circuit such as an RC delay circuit or a transistor delay circuit, and is not specifically limited in the embodiments of the present application.

[0027] The first coarse delay chain Delay A determines the amount of delay for the input signal IN based on the number of corresponding valid first coarse delay code signals in a plurality of first coarse delay groups and the number of first coarse delay units included in the first coarse delay group. Based on the determined amount of delay, it performs delay processing on the input signal IN to obtain the first delayed signal int AC.

[0028] In some embodiments, the first coarse delay chain Delay A is controlled by code code A, and code code A is a first coarse delay code C0, C2…C of n+1 bits. 2n The first coarse delay group is formed by combinations of (n is any positive integer), where n+1 groups are connected in series, and one first coarse delay group contains two first coarse delay units, and each first coarse delay group receives one first coarse delay code signal.

[0029] To make it easier to understand, when code A advances by 1, i.e., when the number of valid first coarse delay codes increases by 1, the delay amount of the first delay signal increases by 2 coarse delay time CDs, and the entire first coarse delay chain Delay A can give a delay level of up to n+1 steps, giving 2 coarse delay time CDs per step, and can give a maximum of 2n+2 coarse delay time CDs.

[0030] As shown in Figure 3, Figure 3 shows a schematic diagram of the second coarse delay chain Delay B, which includes one forced delay unit and a plurality of second coarse delay groups connected in series in sequence, the forced delay unit being connected in series with the second coarse delay groups, each second coarse delay group receiving one second coarse delay code signal, and each second coarse delay group including at least two second coarse delay units. For each second coarse delay group, if the second coarse delay code signal corresponding to the second coarse delay group is active, then each second coarse delay unit in the second coarse delay group is active. If the second coarse delay unit is active, the second coarse delay unit delays the input signal IN by one coarse delay time CD. If the second coarse delay unit is inactive, the delay amount of the input signal IN by the second coarse delay unit is zero, and the forced delay unit delays the input signal IN by one coarse delay time CD.

[0031] To make it understandable, once the input signal IN passes through, the input signal IN can be delayed by one coarse delay time CD, and unless the polarity of the input signal IN is changed, the forced delay unit and the second coarse delay unit can use an RC delay circuit, a transistor delay circuit, etc., and are not specifically limited in the embodiments of this application.

[0032] The second coarse delay chain, Delay B, determines the amount of delay for the input signal IN based on the number of corresponding valid second coarse delay code signals in multiple second coarse delay groups, the number of second coarse delay units included in the second coarse delay group, and the forced delay units. Based on the determined amount of delay, it performs delay processing on the input signal IN to obtain the second delayed signal int BD.

[0033] In some embodiments, the second coarse delay chain Delay B is controlled by code code B, and code code B is a second coarse delay code C1, C3…C of n bits. 2n-1 The second coarse delay group is formed by combinations of (n is any positive integer), and n groups are set up, each second coarse delay group receives one second coarse delay code signal, and one second coarse delay group contains two second coarse delay units, and the entire second coarse delay chain Delay B can give a delay level of up to n steps (n is any positive integer), giving two coarse delay times CD per step, and can give a maximum of 2n+1 coarse delay times.

[0034] In some embodiments, Code A and Code B are combined alternately to form a 2n+1 bit sequence code: Code Coarse: C0, C1, C2…C 2n-1 , C 2n This can generate a sequence of codes, which are thermometer codes.

[0035] To make it easier to understand, the presence of the forced delay unit ensures that no matter how the continuous code Code Coarse changes, there is always a delay of one coarse delay time CD between the first delay signal int AC and the second delay signal int BD. Simultaneously, when the continuous code Code Coarse changes one bit at a time, i.e., when the Code Coarse advances by 1 or goes back by 1, only one of the first delay signal int AC and the second delay signal int BD generates a delay of two coarse delay time CDs, thereby causing a glitch only in the first delay signal int AC or the second delay signal int BD.

[0036] As shown in Figure 4, Figure 4 shows the circuit principle diagram of a precision delay chain, where two precision delay chains, Delay C and Delay D, have the same configuration and provide the same amount of delay, with precision delay chain Delay C being taken as an example.

[0037] The precision delay chain Delay C includes a first switch and a second switch, both of which are electronic switches. The control terminals of both the first and second switches receive the first delay signal int AC. The input terminal of the first switch is connected to a high level, and its output terminal is connected to the input terminal of the second switch. The output terminal of the second switch is grounded. The glitch-removal branch circuit 120 is connected between the output terminal of the first switch and the input terminal of the second switch.

[0038] The first switch conducts to a high level with the glitch-removal branch circuit when the first delay signal int AC is at a low level, and the second switch grounds the glitch-removal branch circuit 120 when the first delay signal int AC is at a high level.

[0039] The first switch may be a field-effect transistor, relay, triode, or the like, as long as it conducts a high level to the glitch-removal branch circuit 120 when the input to the control terminal is low level, and is not specifically limited in the embodiments of this application.

[0040] The second switch may be a field-effect transistor, relay, triode, or the like, as long as it grounds the glitch-removal branch circuit 120 when the input to the control terminal is high level, and is not specifically limited in the embodiments of this application.

[0041] In some embodiments, the first switch includes a PMOS transistor, the gate of which receives a first delay signal int AC, the source connected to a high level, and the drain connected to a glitch-removal branch circuit; and the second switch includes an NMOS transistor, the gate of which receives a first delay signal int AC, the drain connected to a glitch-removal branch circuit 120, and the source connected to ground.

[0042] To make it easier to understand, if the first or second delay signal is a low-level signal, the PMOS transistor of the first switch turns on, the NMOS transistor of the second switch turns off, and the glitch-removal branch circuit 120 conducts to a high level. If the first or second delay signal is a high-level signal, the PMOS transistor of the first switch turns off, the NMOS transistor of the second switch turns on, and the glitch-removal branch circuit 120 is grounded.

[0043] As shown in Figure 4, the precision delay chain Delay C further includes a plurality of precision delay units connected in parallel, each precision delay unit including one charge current source and one discharge current source, the charge current source and the discharge current source are connected in series.

[0044] Both the charging current source and the discharging current source adjust the amount of charge input to the glitch-removal branching circuit 120, further adjust the voltage change rate, and further adjust the delay time. Each charging current source has its positive terminal connected to the drain of the PMOS transistor of the first switch and its negative terminal connected to the positive terminal of the discharging current source. Each discharging current source has its negative terminal connected to the input terminal of the NMOS transistor of the second switch. The glitch-removal branching circuit 120 is connected between the multiple charging current sources and the multiple discharging current sources.

[0045] To make it easier to understand, when the first delay signal int AC is low level, the PMOS transistor of the first switch turns on, i.e., the branch circuit where the charging current source is located is in the ON state, and the multiple charging current sources can charge the glitch-removal branch circuit 120. When the NMOS transistor of the second switch is in the OFF state, i.e., the branch circuit where the discharge current source is located is in the OFF state, the discharge current source cannot discharge the glitch-removal branch circuit 120. When the first delay signal int AC is high level, the PMOS transistor of the first switch turns off, i.e., the branch circuit where the charging current source is located is in the OFF state, and the charging current source cannot charge the glitch-removal branch circuit 120. When the NMOS transistor of the second switch is in the ON state, i.e., the branch circuit where the discharge current source is located is in the ON state, the multiple discharge current sources can discharge the glitch-removal branch circuit 120.

[0046] Furthermore, each precision delay unit receives one precision delay code signal. If the precision delay code signal is valid, the charging and discharging current sources of the corresponding precision delay unit are turned off, and the precision delay unit increases the signal delay by one precision delay time FD. If the precision delay code signal is invalid, the charging and discharging current sources of the corresponding precision delay unit are turned on, and the precision delay unit decreases the signal delay by one precision delay time FD.

[0047] The precision delay chain Delay C determines the number of times the charge current source and discharge current source are turned on based on the number of corresponding valid precision delay code signals in multiple precision delay units, thereby determining the delay amount. Based on the determined delay amount, it performs delay processing on the inverted first delay signal int AC to obtain the third delay signal output Delay C.

[0048] In some embodiments, each precision delay chain includes m charge current sources and m discharge current sources, CD = mFD, precision delay chain Delay C is controlled by code Code C, precision delay chain Delay D is controlled by code Code D, and code C and code D have matching code contents and are both m-bit precision delay code signals F0, F1…F m-2 F m-1 It consists of Code C and Code D, and Code Fine is a single consecutive thermometer code.

[0049] Specifically, when the precision delay code signal is enabled, it is equivalent to turning off the current source, the current of the charge / discharge current source decreases, and the delay unit delays the signal by one FD. When the precision delay code signal is disabled, it is equivalent to turning on the current source, the current of the charge / discharge current source increases, and the delay unit reduces the signal delay by one FD. By changing the Code Fine and thus changing the number of enabled precision delay code signals, the number of times the charge current source and discharge current source are turned on is changed, thereby achieving delay control.

[0050] To make it clear, the number of effective precision delay code signals in precision delay chains Delay C and Delay D always matches, and as Code Fine changes, the precision delay code signals in precision delay chains Delay C and Delay D change synchronously, so that the amount of delay provided by precision delay chains Delay C and Delay D is always the same.

[0051] As shown in Figure 5, the glitch removal branch circuit 120 includes an output inverter and a capacitor C. Capacitor C has one end connected to the input terminal of the output inverter and is connected between the negative terminals of the multiple charging current sources and the positive terminals of the multiple discharging current sources, with the other end grounded. Capacitor C integrates the third delay signal output Delay C and the fourth delay signal output Delay D to obtain the integrated signal int CD. The output inverter performs an inversion process on the integrated signal int CD to obtain the output signal OUT.

[0052] When Code Fine changes for the third delay signal output Delay C and the fourth delay signal output Delay D, the number of charging current sources and discharging current sources operating in precision delay chains Delay C and Delay D changes, and by changing the charging and discharging rates of capacitor C by precision delay chains Delay C and Delay D, precision delay chain Delay C can perform an inversion delay process on the first delay signal int AC to obtain the third delay signal output Delay C, and precision delay chain Delay D can perform an inversion delay process on the second delay signal int BD to obtain the fourth delay signal output Delay D. At this time, neither the third delay signal output Delay C nor the fourth delay signal output Delay D will exhibit glitches, and the analysis process is as follows (since the configurations of precision delay chains Delay C and Delay D are the same, precision delay chain Delay C and the third delay signal output Delay C are used as examples here).

[0053] As shown in Figure 6, Figure 6 shows the waveform between the inverted first delay signal int AC and the third delay signal output Delay C.

[0054] When the first delay signal int AC flips from a low level to a high level, the PMOS transistor of the first switch turns off, the branch circuit where the charging current source is located turns off, disabling the charging current source, which cannot charge capacitor C. At this point, the NMOS transistor of the second switch turns on, the branch circuit where the discharge current source is located turns on, the discharge current source discharges capacitor C, and the third delay signal output Delay C gradually decreases.

[0055] For example, when Code C = 0, the number of valid precision delay code signals is zero, all discharge current sources are active, all discharge current sources are turned on, thereby allowing capacitor C to discharge rapidly, and the voltage of the third delay signal output Delay C drops rapidly. As Code C increases, the number of valid precision delay code signals increases, the number of discharge current sources that turn on decreases, the discharge rate of capacitor C slows down, and the voltage of the third delay signal output Delay C drops gradually, thereby achieving an inverted delay with respect to the first delay signal int AC.

[0056] If Code C changes before the third delay signal output Delay C reaches a steady state, the number of effective precision delay code signals increases or decreases. At this time, the waveforms of the first delay signal int AC and the third delay signal output Delay C are shown in Figure 7.

[0057] For example, when Code C changes from 0 to 2, i.e., when Code C increases, the number of effective precision delay code signals increases, the corresponding discharge current source turns off, the discharge rate of capacitor C decreases, the rate of decrease of the third delay signal output Delay C slows down, and the time to reach a steady state is delayed. When Code C changes from m-1 to 0, i.e., when Code C decreases, the number of effective precision delay code signals decreases, the corresponding discharge current source turns on, the discharge rate of capacitor C increases, the third delay signal output Delay C decreases rapidly to reach a steady state, and the time to reach a steady state of the third delay signal output Delay C is shortened.

[0058] To make it understandable, the above process explains the effect of the change in Code C on the discharge rate of capacitor C when the first delay signal int AC flips from a low level to a high level, and realizes delay control for the third delay signal output Delay C. Similarly, when the first delay signal int AC flips from a high level to a low level, it is possible to estimate the effect of the change in Code C on the charge rate of capacitor C and the effect on the steady-state establishment time of the third delay signal output Delay C. As can be seen from this, no matter how Code C changes, only the charge and discharge rate of capacitor C changes, which affects the time it takes for the third delay signal output Delay C to reach a steady state, that is, it affects the delay amount of the third delay signal output Delay C, and no new transformation or glitch occurs in the third delay signal output Delay C.

[0059] Since the configurations of precision delay chains Delay C and Delay D are the same, similarly, no matter how Code D changes, only the charge / discharge rate of capacitor C changes, which affects the time it takes for the fourth delay signal output Delay D to reach a steady state, that is, it affects the amount of delay of the fourth delay signal output Delay D, and it can be seen that no new transformations or glitches occur in the fourth delay signal output Delay D. As described above, when Code Fine changes, no glitches occur in the precision delay chains Delay C and Delay D themselves, that is, no glitches occur in the third delay signal output Delay C and the fourth delay signal output Delay D.

[0060] From this, it can be seen that when Code Fine switches one bit at a time between zero and full, no glitch occurs in the configuration of precision delay chains Delay C and Delay D, and when Code Fine switches one bit at a time between zero and full, it does not affect the first delay signal int AC and the second delay signal int BD, that is, it does not affect the delay amounts of the first coarse delay chain Delay A and the second coarse delay chain Delay B.

[0061] When Code Fine changes continuously, there are situations where Code Fine returns from its full value to zero, or jumps from zero to its full value. In these cases, the corresponding Code Coarse advances by one bit or moves back by one bit, changing the delay amount of the first delay signal int AC or the second delay signal int BD. At this time, the interpolator circuit formed by the precision delay chain Delay C, the precision delay chain Delay D, and capacitor C, as well as the separate arrangement of the first coarse delay chain Delay A and the second coarse delay chain Delay B, can eliminate possible glitches caused by changes in Code Coarse. The specific process is as follows:

[0062] For example, assuming that Code Coarse is 2i-1 (where i is any positive integer less than n) and Code Fine is m-1, as can be seen from the arrangement of Code Coarse, the first coarse delay chain Delay A and the second coarse delay chain Delay B each provide an i-step delay level, and the fine delay chain Delay C and the fine delay chain Delay D each provide an m-1-step delay level. In this case, the delay time provided by branch circuit AC (composed of the first coarse delay chain Delay A and the fine delay chain Delay C, and so on) is 2i × CD + (m-1) × FD, and the delay time provided by branch circuit BD (composed of the second coarse delay chain Delay B and the fine delay chain Delay D, and so on) is (2i + 1) × CD + (m-1) × FD. The delay amount of the output signal OUT lies between 2i × CD + (m-1) × FD and (2i + 1) × CD + (m-1) × FD. The Code Fine thermometer code advances by 1 from m-1, i.e., increases to m, which is actually represented as a zero clear. The Code Coarse advances by 1, i.e., increases to 2i. At this time, the delay time given by branch circuit AC is (2i+2)×CD, and the delay time given by branch circuit BD is (2i+1)×CD. The total delay amount of the circuit lies between (2i+1)×CD and (2i+2)×CD, meaning that the first delay signal int AC increases by 2 CDs, the second delay signal int BD remains unchanged, and the precision delay time FD given by precision delay chains Delay C and Delay D returns to zero.

[0063] As shown in Figure 8, Figure 8 shows the waveform diagrams of each signal when there is no change in Code Coarse before the Code Fine thermometer code advances by 1 from m-1.

[0064] To make it easier to understand, the interval between the inversion of the first delayed signal int AC and the inversion of the second delayed signal int BD is the time difference of one CD, i.e., the t1 interval in Figure 8. In the t0 interval, neither the inversion edge of the first delay signal int AC nor the second delay signal int BD is reached. In the t1 interval, the first delay signal int AC inverts from a low level to a high level, the charging current source branch circuit of the precision delay chain Delay C turns off, the discharge current source branch circuit turns on, capacitor C discharges to ground, and as a result the output current pre Delay C of the precision delay chain Delay C becomes a small negative current -I m-1 The output is as follows: the voltage of the third delay signal output Delay C begins to decrease, at this time the second delay signal int BD has not yet inverted, the output current pre Delay D of the precision delay chain Delay D remains unchanged, the fourth delay signal output Delay D remains unchanged, and the integrated signal int CD voltage obtained after integrating the third delay signal output Delay C and the fourth delay signal output Delay D begins to decrease. In section t2, the second delay signal int BD inverts from a low level to a high level, the charging current source branch circuit of the precision delay chain Delay D turns off, the discharge current source branch circuit turns on, capacitor C discharges to ground, and the output current pre Delay D of the precision delay chain Delay D also becomes a small negative current -I m-1 As a result, the fourth delay signal, output Delay D, begins to decrease, and at this time, the voltage of the integrated signal int CD begins to change rapidly until it falls below the threshold voltage of the output inverter, inverting the output signal OUT in this section. The output inverter then inverts the integrated signal int CD, and the output signal OUT is obtained.

[0065] In the t3 interval, after the charge in capacitor C is released, it stops discharging, the integrated signal int CD reaches a steady state, the precision delay chains Delay C and Delay D stop discharging, and the delay inversion process ends.

[0066] In some embodiments, as shown in FIG. 9, FIG. 9 is a waveform diagram of another embodiment, showing the waveform diagrams of each signal when the Code Fine thermocouple code advances from m - 1 by only 1 and the Code Coarse advances by only 1.

[0067] As can be understood, before the Code Coarse advances by only 1, the inversion of the first delay signal int AC exceeds the inversion of the second delay signal int BD by one CD time difference. However, after the Code Coarse advances by only 1, the first delay signal int AC lags behind the second delay signal int BD by one CD time difference. When the first delay signal int AC just undergoes inversion within two CD times after the Code Coarse advances by only 1, at this time, a glitch occurs in the first delay signal int AC. As shown in FIG. 9, this glitch is not reflected in the output signal OUT. At this time, the interpolator formed by Delay C, Delay D, and capacitor C can remove this glitch, and the specific process is as follows.

[0068] In the t0 interval, neither the inversion edge of the first delay signal int AC nor that of the second delay signal int BD arrives. In the t1 interval, the first delay signal int AC undergoes inversion, and the output current post Delay C of the precision delay chain Delay C is a small negative current -I m-1 At this time, the second delay signal int BD has not yet undergone inversion, and the output current post Delay D of the precision delay chain Delay D does not change much. That is, the voltage of the third delay signal output Delay C begins to decrease, the fourth delay signal output Delay D does not change, and at this time, the integrated signal int CD voltage begins to decrease.

[0069] In the t2 interval, the second delay signal int BD undergoes inversion, and the output current post Delay D of the precision delay chain Delay D is also a small negative current -I m-1Therefore, the fourth delay signal, output Delay D, also begins to decrease, and at this time, the voltage of the integrated signal int CD begins to change rapidly until it falls below the threshold voltage of the output inverter, inverting the output signal OUT in this section.

[0070] In the t3 interval, when the code value is reversed, the Code Coarse advances by 1, and the first delay signal int AC is reversed due to a glitch. At this time, the first delay signal int AC and the second delay signal int BD have opposite polarities, the control code Fine Code for precision delay chains Delay C and Delay D returns to zero, and both the charging current source and the discharging current source are generally on. Therefore, in precision delay chain Delay C, the branch circuit where the charging current source is located turns on, and the branch circuit where the discharging current source is located turns off. The charging current source charges capacitor C, causing the output current post Delay C of precision delay chain Delay C to become a large positive current I0, the third delay signal output Delay C rises rapidly, the branch circuit where the charging current source is located in precision delay chain Delay D turns off, the discharging current source discharges capacitor C, causing the output current post Delay D of precision delay chain Delay D to become a large negative current -I0, and the fourth delay signal output Delay Because D decreases rapidly and cancels each other out after they merge, the voltage of the merged signal int CD remains unchanged and does not affect the state change of the output signal OUT.

[0071] In the t4 interval, the first delay signal int AC inverts again and has the same polarity as the second delay signal int BD. At this time, the output currents post Delay C of the precision delay chain Delay C and post Delay D of the precision delay chain Delay D are both large negative currents -I0, further releasing the charge in capacitor C. This process does not affect the state change of the output signal OUT, and the delay inversion process ends.

[0072] Figure 10 shows the waveform diagrams of each signal in yet another embodiment. In some embodiments, when the Code Fine thermometer code advances by 1 from m-1 and the Code Coarse advances by 1, the integrated signal int CD does not reach the threshold voltage of the output inverter in the t2 section. In this case, the situation from t0 to t2 is the same as the situation from t0 to t2 in Figure 9, and will not be explained again here, but the output signal OUT does not yet invert in the t2 section and still retains its pre-inversion state.

[0073] In the t3 interval, the output current post Delay C of the precision delay chain Delay C is a large positive current I0, causing the third delay signal output Delay C to rise, while the output current post Delay D of the precision delay chain Delay D is a large negative current -I0, causing the fourth delay signal output Delay D to fall. As these two signals cancel each other out, the voltage of the integrated signal int CD remains unchanged, and the output signal OUT is not inverted.

[0074] In the t4 interval, the first delay signal int AC inverts again and has the same polarity as the second delay signal int BD. At this time, the output currents post Delay C and post Delay D of the precision delay chain Delay C and precision delay D are both large negative currents -I0. Capacitor C discharges rapidly until all charge is released. The third delay signal output Delay C and the fourth delay signal output Delay D both decrease. The integrated signal int CD rapidly decreases until it reaches the threshold of the output inverter. During this process, the output signal OUT inverts, and the delay inversion process ends.

[0075] Figure 11 shows the waveform diagrams of each signal in yet another embodiment. In another scenario, namely, when the Code Fine thermometer code advances by 1 from m-1 and the Code Coarse advances by 1, this occurs after the first delay signal int AC inverts and before the second delay signal int BD inverts. In the t1 interval, the first delay signal int AC inverts to a high level, and the output current post Delay C of the precision delay chain Delay C becomes a small negative current -I m-1 As a result, the voltage of the third delay signal, output Delay C, decreases, and the voltage of the integrated signal, int CD, gradually begins to decrease.

[0076] At the start of the t2 interval, Code Coarse advances by 1, Code Fine is cleared, and the first delay signal int AC is inverted to a low level. At this time, the output current post Delay C of the precision delay chain Delay C outputs a large positive current I0, and the charging current source charges capacitor C until it is fully charged. The voltage of the third delay signal output Delay C rises rapidly, and the voltage of the integrated signal int CD rises rapidly to a high level. After capacitor C is fully charged, the output current post Delay C of the precision delay chain Delay C returns to zero.

[0077] In the t3 interval, the second delay signal int BD is inverted and Code Fine is cleared, so the output current post Delay D of the precision delay chain Delay D is a large negative current I0. At this time, the output current post Delay C of the precision delay chain Delay C and the output current post Delay D of the precision delay chain Delay D are both I0 and in opposite directions, so they cancel each other out, and the combined signal int CD voltage does not change.

[0078] In the t4 interval, the first delay signal int AC inverts again. At this time, the output currents post Delay C and post Delay D of the precision delay chain Delay C and precision delay chain Delay D are both large negative currents -I0. Capacitor C discharges rapidly, and the integrated signal int CD rapidly decreases until it reaches the threshold voltage of the output inverter. During this process, the output signal OUT inverts, the delay inversion process ends, and the output currents post Delay C and post Delay D of the precision delay chain Delay D return to zero.

[0079] In some embodiments, the code value change that advances Code Coarse by 1 and clears Code Fine occurs before the t0 interval, in which case no glitch occurs in the first delay signal int AC, and no glitch occurs in the output signal OUT. If the Code Coarse advances by 1 just outside the time of the two CDs after the first delay signal int AC has inverted, i.e., after the t4 interval, then the output signal OUT reaches a steady state, and the Code Coarse advance of 1 does not affect the output signal OUT.

[0080] As described above, when a code value change occurs in which Code Coarse advances by 1 and Code Fine is cleared, the interpolator circuit formed by precision delay chain Delay C, precision delay chain Delay D and capacitor C, as well as the separate arrangement of the first coarse delay chain Delay A and the second coarse delay chain Delay B, can eliminate possible glitches caused by the code value change, and no glitches occur in the output signal OUT.

[0081] In some other embodiments, similarly assuming that the Code Coarse thermometer code is 2i-1 and the Code Fine thermometer code is 0, then the delay time given by branch circuit AC is 2i × CD, the delay time given by branch circuit BD is (2i+1) × CD, and the total delay of the circuit is between 2i × CD and (2i+1) × CD. When the Code Fine thermometer code returns from 0 to 1, i.e., decreases to -1 and is described as actually being full, then the Code Coarse returns to 1, i.e., decreases to 2i-2, and at this time the delay time given by branch circuit AC is 2i × CD + (m-1) × FD, the delay time given by branch circuit BD is (2i-1) × CD + (m-1) × FD, and the total delay of the circuit is between (2i-1) × CD + (m-1) × FD and 2i × CD + (m-1) × FD, i.e., Delay A remains unchanged, Delay B decreases by only two units (CD), and Delay C and Delay D increase to their maximum values.

[0082] If Code Coarse returns by 1 and Code Fine returns from zero to full, performing the same analysis on the process, if a code value change occurs in which Code Coarse returns by 1 and Code Fine becomes full, the interpolator circuit formed by the precision delay chain Delay C, the precision delay chain Delay D and capacitor C, as well as the separate arrangement of the first coarse delay chain Delay A and the second coarse delay chain Delay B, can eliminate possible glitches due to code value changes, and no glitches occur in the output signal OUT.

[0083] The electronic device includes a delay chain circuit according to the above embodiment.

[0084] As described above, the delay chain circuit and electronic device according to the present invention, when it is necessary to adjust the delay chain by the delay chain circuit, adjust the delay amount of either the first delay signal int AC or the second delay signal int BD, causing a glitch to occur only in the first delay signal int AC or only in the second delay signal int BD. When capacitor C integrates the third delay signal output Delay C and the fourth delay signal output Delay D, it integrates the third delay signal output Delay C and the fourth delay signal output Delay D to eliminate the glitch. The output inverter performs an inversion process on the integrated signal int CD to obtain the output signal OUT, thereby dynamically adjusting the delay of the delay chain without interrupting the input signal IN and achieving glitch-free delay chain switching.

[0085] The above are merely preferred embodiments of the present application and do not limit the present application in any way. While the present application is disclosed as described above in preferred embodiments, it does not limit the present application. A person skilled in the art can make equivalent modifications and equivalent embodiments using the technical content disclosed above without departing from the scope of the technical means of the present application. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical substance of the present application without departing from the scope of the technical means of the present application all fall within the scope of the technical means of the present application.

Claims

1. Including coarse delay branch circuits and precision delay branch circuits, The aforementioned coarse delay branching circuit performs delay processing on the input signal, then obtains a first delay signal and a second delay signal, and there is a delay amount between the first delay signal and the second delay signal. The coarse delay branch circuit includes a first coarse delay chain and a second coarse delay chain installed in parallel. The first coarse delay chain obtains the first delayed signal by delaying the input signal by a plurality of coarse delay times, and includes a plurality of first coarse delay groups connected in series in sequence. The second coarse delay chain obtains the second delayed signal by delaying the input signal by a plurality of coarse delay times, and includes one forced delay unit and a plurality of second coarse delay groups connected in series in sequence. The forced delay unit is connected in series with the second coarse delay group, Each of the first coarse delay groups receives one first coarse delay code signal and includes at least two first coarse delay units. Each of the second coarse delay groups receives one second coarse delay code signal and includes at least two second coarse delay units. For each of the first coarse delay groups, if the first coarse delay code signal corresponding to the first coarse delay group is valid, then each of the first coarse delay units in the first coarse delay group is valid, and if the first coarse delay unit is valid, the first coarse delay unit delays the input signal by one coarse delay time. The first coarse delay chain is controlled by a code Code A consisting of a combination of a plurality of first coarse delay code signals, and the amount of delay for the input signal is determined based on the number of corresponding valid first coarse delay code signals in a plurality of first coarse delay groups and the number of first coarse delay units included in the first coarse delay group, and based on the determined amount of delay, delay processing is performed on the input signal to obtain the first delay signal, For each of the second coarse delay groups, if the second coarse delay code signal corresponding to the second coarse delay group is enabled, then each of the second coarse delay units in the second coarse delay group is enabled, and if the second coarse delay unit is enabled, the second coarse delay unit delays the input signal by one coarse delay time. The forced delay unit delays the input signal by one coarse delay time, The second coarse delay chain is controlled by a code Code B consisting of a combination of multiple second coarse delay code signals, and the amount of delay for the input signal is determined based on the number of corresponding valid second coarse delay code signals in multiple second coarse delay groups, the number of second coarse delay units included in the second coarse delay group, and the forced delay unit, and based on the determined amount of delay, delay processing is performed on the input signal to obtain the second delay signal, By alternately combining the aforementioned code Code A and the aforementioned code Code B, a continuous code as a thermometer code is generated, and when the continuous code changes one bit at a time, a glitch can occur in only the first delay signal or only the second delay signal. The precision delay branch circuit includes two precision delay chains, a capacitor, and an output inverter. Each of the precision delay chains includes a plurality of precision delay units connected in parallel, a first switch, and a second switch. Each of the precision delay units includes a charging current source and a discharging current source connected in series. The first switch has its input terminal connected to a high level. The output terminal of the second switch is grounded via the circuit. The positive terminal of each charging current source is connected to the output terminal of the first switch via a circuit, and the negative terminal of each charging current source is connected to the positive terminal of the discharge current source via a circuit. The negative electrode of each discharge current source is connected to the input terminal of the second switch via a circuit. The precision delay chain, on the other hand, is controlled by code Code C and outputs a current for charging and discharging the capacitor. The other precision delay chain is controlled by code D and outputs a current for charging and discharging the capacitor. The control terminal of the first switch of one precision delay chain and the control terminal of the second switch of the other precision delay chain both receive the first delay signal. The control terminal of the first switch of the other precision delay chain and the control terminal of the second switch of the other precision delay chain both receive the second delay signal. Each of the precision delay units in the precision delay chain receives one of several code signals F0, F1…Fm-2, Fm-1, and if one of the code signals is valid, it turns off the corresponding charge current source and discharge current source, and if one of the code signals is invalid, it turns on the corresponding charge current source and discharge current source, where m is a positive integer of 4 or more. Each of the precision delay units of the other precision delay chain receives a plurality of other code signals F0, F1…Fm-2, Fm-1, and turns off the corresponding charge current source and discharge current source if the other code signal is valid, and turns on the corresponding charge current source and discharge current source if the other code signal is invalid. The aforementioned code C consists of one of the code signals F0, F1...Fm-2, Fm-1 received by a plurality of precision delay units of one of the precision delay chains, The aforementioned code D consists of the other code signals F0, F1...Fm-2, Fm-1 received by a plurality of precision delay units of the other precision delay chain, One of the aforementioned code signals F0, F1...Fm-2, Fm-1 matches the other aforementioned code signals F0, F1...Fm-2, Fm-1, Each precision delay chain determines the number of times the charging current source and the discharging current source are turned off based on the number of effective code signals corresponding to a plurality of precision delay units, thereby determining the charging and discharging current to the capacitor. The capacitor is connected at one end to the input terminal of the output inverter via a circuit, and at the other end to ground, to a circuit connecting the negative terminal of the charging current source and the positive terminal of the discharge current source, and is charged and discharged by the current from one precision delay chain and the current from the other precision delay chain, thereby eliminating glitches that may occur due to changes in the continuous code and acquiring a signal. The output inverter performs an inversion process on the signal to obtain an output signal. A delay chain circuit characterized by the following features.

2. Both the first switch and the second switch are electronic switches. The delay chain circuit according to feature 1.

3. An electronic device characterized by including a delay chain circuit as described in claim 1 or 2.

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