Wiring pattern formation method

Abstract

To improve throughput in wiring pattern formation of FO-WLP.SOLUTION: A method for forming a wiring pattern includes: performing a position measurement being measurement of respective positions of a plurality of chips contained in a first substrate disposed on a first tray, and respective positions of a plurality of chips contained in a second substrate disposed on the first tray; and performing data creation being creation of first pattern data being pattern data on wiring for connecting the plurality of chips contained in the first substrate on the basis of the respective positions of the plurality of chips contained in the first substrate, and second pattern data being pattern data on wiring for connecting the plurality of chips contained in the second substrate on the basis of the respective positions of the plurality of chips contained in the second substrate, where the data creation starts in a time period for performing the position measurement.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] It relates to a method for forming a wiring pattern.

Background Art

[0002] In recent years, packages of semiconductor devices called FO-WLP (Fan Out Wafer Level Package) and FO-PLP (Fan Out Plate Level Package) are known.

[0003] For example, in the manufacture of FO-WLP, a plurality of semiconductor chips are arranged on a wafer-shaped support substrate and solidified with a molding material such as resin to form a pseudo-wafer, and a redistribution layer for connecting the pads of the semiconductor chips is formed using an exposure apparatus.

[0004] Improvement in throughput in the formation of the redistribution layer of FO-WLP and FO-PLP is desired (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

[0006] According to the disclosed aspect, an exposure apparatus is provided comprising: a spatial light modulator; a creation unit that acquires measurement results from a measurement system that measures the positions of semiconductor chips included in each of a set of semiconductor chips arranged on a first substrate, determines a wiring pattern connecting the semiconductor chips included in each of the sets based on the measurement results, creates first control data to be used to control the spatial light modulator when generating the determined wiring pattern, and stores the data in a first storage unit; and an exposure processing unit that controls the spatial light modulator using the first control data stored in the first storage unit to expose the wiring pattern connecting the semiconductor chips included in each of the sets, wherein at least one of the following is performed while the exposure processing unit is exposing a second substrate different from the first substrate: measurement of the positions of the semiconductor chips on the first substrate, acquisition of the measurement results, determination of the wiring pattern, creation of the first control data, and storage of the first control data in the first storage unit.

[0007] According to the disclosed aspect, the wiring pattern formation method includes: performing position measurement, which is the measurement of the position of each of the plurality of chips contained in a first substrate arranged in a first tray and the position of each of the plurality of chips contained in a second substrate arranged in the first tray; and performing data creation, which is the creation of first pattern data, which is pattern data of wiring connecting the plurality of chips contained in the first substrate, based on the position of each of the plurality of chips contained in the first substrate, and second pattern data, which is pattern data of wiring connecting the plurality of chips contained in the second substrate, based on the position of each of the plurality of chips contained in the second substrate, wherein the data creation is started during the period in which the position measurement is performed.

[0008] Furthermore, the configuration of the embodiments described later may be modified as appropriate, and at least a part of it may be replaced with other components. Moreover, the configuration elements whose arrangement is not particularly limited may be arranged in positions that can achieve their function, not limited to the arrangement disclosed in the embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a top view showing an overview of a wiring pattern formation system for FO-WLP, including an exposure apparatus according to the first embodiment. [Figure 2] Figure 2 is a schematic perspective view showing the configuration of the exposure apparatus according to the first embodiment. [Figure 3] Figures 3(A) and 3(B) illustrate the wiring patterns formed by the wiring pattern formation system. [Figure 4] Figure 4 is a diagram illustrating the modules arranged on an optical table. [Figure 5] Figure 5(A) shows the optical system of the lighting and projection module, Figure 5(B) shows a schematic representation of the DMD, Figure 5(C) shows the DMD when the power is OFF, Figure 5(D) is a diagram to explain the mirror in the ON state, and Figure 5(E) is a diagram to explain the mirror in the OFF state. [Figure 6] Figure 6 is a magnified view of the area around the lighting and projection module. [Figure 7] Figure 7 is a block diagram showing the control system of the exposure apparatus according to the first embodiment. [Figure 8] Figure 8(A) is a schematic diagram showing a wafer WF with all chips positioned at the design location, and Figure 8(B) is a schematic diagram showing a wafer WF with chips positioned off-center from the design location. [Figure 9] Figure 9 is a conceptual diagram showing the wiring pattern formation procedure for FO-WLP in an exposure apparatus. [Figure 10] Figure 10 is a top view showing an overview of the wiring pattern formation system according to the second embodiment. [Figure 11] Figure 11 is a conceptual diagram of the manufacturing procedure for FO-WLP in the second embodiment. [Figure 12] Figure 12 is a top view showing an overview of the wiring pattern formation system according to the third embodiment. [Modes for carrying out the invention]

[0010] 《First Embodiment》 The exposure apparatus according to the first embodiment will be described with reference to Figures 1 to 9. In the following description, when simply referred to as substrate P, a rectangular substrate will be indicated, and a wafer-shaped substrate will be referred to as wafer WF. Furthermore, the normal direction of the substrate P or wafer WF placed on the substrate stage 30, which will be described later, will be the Z-axis direction, the direction in which the substrate P or wafer WF is scanned relative to the spatial light modulator (SLM) in a plane perpendicular to the Z-axis will be the X-axis direction, the direction perpendicular to the Z-axis and Y-axis will be the Y-axis direction, and the rotation (tilting) directions around the X-axis, Y-axis, and Z-axis will be described as θx, θy, and θz directions, respectively. Examples of spatial light modulators include liquid crystal elements, digital mirror devices (digital micromirror devices, DMDs), and magneto-optical spatial light modulators (MOSLMs). The exposure apparatus EX according to the first embodiment is equipped with a DMD204 as the spatial light modulator, but other spatial light modulators may also be equipped.

[0011] Figure 1 is a top view showing an overview of a wiring pattern formation system 500 for FO-WLP and FO-PLP, including an exposure apparatus EX according to one embodiment. Figure 2 is a perspective view showing a schematic configuration of the exposure apparatus EX.

[0012] The wiring pattern formation system 500 is a system for forming wiring patterns that connect semiconductor chips (hereinafter referred to as "chips") arranged on a wafer WF, as shown in Figure 3(A), or between chips arranged on a substrate P, as shown in Figure 3(B).

[0013] In this embodiment, a wiring pattern is formed to connect chip C1 and chip C2 in each set of chips (shown by a dashed line) arranged on a wafer WF or substrate P. In this embodiment, the number of chips in each set is two, but this is not limited to two, and there may be three or more.

[0014] Hereinafter, a case of forming a wiring pattern for connecting chips arranged on a wafer WF will be described.

[0015] As shown in FIG. 1, the wiring pattern forming system 500 includes a coater developer device CD and an exposure device EX.

[0016] The coater developer device CD applies a photosensitive resist to the wafer WF. The wafer WF coated with the resist is carried into a buffer unit PB that can store a plurality of wafers WF. The buffer unit PB also serves as a transfer port for the wafer WF.

[0017] More specifically, the buffer unit PB is composed of a carry-in unit and a carry-out unit. Into the carry-in unit, the wafer WF coated with the resist is carried in one by one from the coater developer device CD. The wafer WF coated with the resist is carried into the carry-in unit one by one at a predetermined time interval from the coater developer device CD, but since a plurality of wafers WF are mounted together on a tray TR described later, the carry-in unit functions as a buffer for storing the wafer WF.

[0018] Also, the carry-out unit functions as a buffer when carrying out the exposed wafer WF to the coater developer device CD. The coater developer device CD can only take out the exposed wafer WF one by one. Therefore, the tray TR on which a plurality of exposed wafers WF are mounted is placed in the carry-out unit. Thereby, the coater developer device CD can take out the exposed wafer WF one by one from the tray TR.

[0019] <> The exposure device EX is composed of a main body unit 1 and a substrate exchange unit 2. As shown in FIG. 1, a robot RB is installed in the substrate exchange unit 2. The robot RB arranges a plurality of wafers WF placed in the buffer unit PB on one tray TR.

[0020] As shown in Figures 1 and 2, in this first embodiment, it is possible to place 4 wafers x 3 rows of wafers WF on the substrate stages 30R and 30L, which will be described later. The tray TR according to this first embodiment is a grid-shaped tray that can sequentially place 4 wafers x 1 row of wafers WF on the substrate stages 30R and 30L. The tray TR may also be a tray that can place wafers WF on the entire surface of the substrate stages 30R and 30L at once (i.e., a tray capable of arranging 4 wafers x 3 rows of wafers WF).

[0021] Furthermore, as shown in Figure 2, the substrate replacement unit 2 is equipped with replacement arms 20R and 20L. Replacement arm 20R loads and unloads wafers WF (more specifically, trays TR on which multiple wafers WF are placed) into and out of the substrate holder PH of the substrate stage 30R, and replacement arm 20L loads and unloads wafers WF into and out of the substrate holder PH of the substrate stage 30L. In the following description, unless there is a need to distinguish between replacement arms 20R and 20L, they will be referred to as replacement arm 20. Also, the substrate holder PH is not shown in Figures other than 2.

[0022] Generally, the replacement arms 20R and 20L consist of two parts: a loading arm for loading trays TR and a loading arm for unloading trays TR. This allows for high-speed replacement of trays TR. When loading wafers WF, the grid-shaped tray TR is supported by substrate replacement pins 10. When the substrate replacement pins 10 descend, the tray TR sinks into grooves (not shown) formed in the substrate stage 30, and the wafers WF are attracted and held by the substrate holders PH on the substrate stage 30. As shown in Figure 2, when a row of substrates is placed on the tray TR, the positions of the substrate stages 30R and 30L or the replacement arms 20R and 20L are changed to match the position where each tray TR is placed on the substrate stages 30R and 30L.

[0023] When a wafer WF is attracted to the substrate holder PH, the position of the alignment marks or wiring pads on the wafer WF is measured using the alignment system ALG-R or ALG-L mounted on the optical table 110. Typically, the number and arrangement of measurement points are determined so that the position of each wafer WF can be measured, and six parameters can be calculated for the wafer WF placed on the substrate holder PH: X-direction shift (X), Y-direction shift (Y), rotation (Rot), X-direction magnification (X_Mag), Y-direction magnification (Y_Mag), and orthogonality (Oth).

[0024] As shown in Figure 4, the optical base plate 110, which is kinematically supported on the column 100, has multiple illumination / projection modules 200, an autofocus system AF, and alignment systems ALG_R, ALG_L, and ALG_C arranged on it.

[0025] As shown in Figure 2, in this embodiment, multiple rows (four rows in Figure 2) containing multiple lighting and projection modules 200 are arranged. Note that in Figure 1, for simplification, only one row containing multiple lighting and projection modules 200 is shown. Also, in Figure 2, for simplification, the alignment systems ALG_R and ALG_L are not shown.

[0026] Furthermore, multiple illumination / projection modules 200 are provided so that wiring patterns in different sets can be exposed at once, and the number of rows of illumination / projection modules 200 may be 1 to 3, or 5 or more. Also, the number of illumination / projection modules 200 in each row may be 2 or more. In addition, when multiple wafers WF are placed on the substrate holder, the different sets that the illumination / projection modules 200 expose at once may be different sets within the same wafer WF, or sets within different wafer WFs.

[0027] Figure 5(A) shows the optical system of the illumination / projection module 200. The illumination / projection module 200 includes a collimator lens 201, a fly-eye lens 202, a main condenser lens 203, and a DMD 204, etc.

[0028] The laser light emitted from the light source LS is taken into the illumination / projection module 200 via a delivery fiber FB. The laser light passes through the collimator lens 201, the fly-eye lens 202, and the main condenser lens 203, illuminating the DMD 204 almost uniformly.

[0029] Figure 5(B) is a schematic diagram of the DMD204, and Figure 5(C) shows the DMD204 when the power is OFF. In Figures 5(B) to 5(E), the ON state of Miller is indicated by hatching.

[0030] The DMD204 has multiple micromirrors 204a whose reflection angle can be changed. Each micromirror 204a is turned ON when tilted around the Y-axis. Figure 5(D) shows the case where only the central micromirror 204a is turned ON, and the other micromirrors 204a are in a neutral state (neither ON nor OFF). Each micromirror 204a is turned OFF when tilted around the X-axis. Figure 5(E) shows the case where only the central micromirror 204a is turned OFF, and the other micromirrors 204a are in a neutral state. The DMD204 generates exposure patterns (hereinafter referred to as wiring patterns) for wiring connecting chips by switching the ON and OFF states of each micromirror 204a.

[0031] The illumination light reflected by the mirror in the OFF state is absorbed by the OFF light absorbing plate 205, as shown in Figure 5(A). The illumination / projection module 200 has a magnification for projecting one pixel of the DMD 204 at a predetermined size, and the magnification can be slightly corrected by focusing by driving the lens along the Z axis and by driving some of the lenses. In addition, the DMD 204 itself can be driven in the X, Y, and θz directions, and is used, for example, to correct for deviations from the target value of the substrate stage 30.

[0032] Although the DMD204 was described as a reflective type that reflects laser light, a spatial light modulator can also be a transmissive type that transmits laser light, or a diffractive type that diffracts laser light. A spatial light modulator can modulate laser light both spatially and temporally.

[0033] Returning to Figure 4, the autofocus system (AF) is positioned so as to sandwich the illumination / projection module 200. This allows the autofocus system (AF) to perform measurements before the exposure operation, which forms wiring patterns connecting the chips placed on the wafer WF, regardless of the scanning direction of the wafer WF.

[0034] Figure 6 is an enlarged view of the area around the lighting and projection module 200. As shown in Figure 6, a fixed mirror 54 for measuring the position of the substrate stage 30 is provided near the lighting and projection module 200.

[0035] Furthermore, as shown in Figure 6, the substrate stage 30 is equipped with an alignment device 60. The alignment device 60 includes a reference mark 60a and a two-dimensional image sensor 60e, etc. The alignment device 60 is used for measuring and calibrating the positions of various modules and is also used for calibrating the alignment systems ALG_R, ALG_L, and ALG_C placed on the optical table 110.

[0036] The position of each module is measured and calibrated by projecting a calibration DMD pattern onto a reference mark 60a on the alignment device 60 using the illumination / projection module 200, and then measuring the relative position of the reference mark 60a and the DMD pattern.

[0037] Furthermore, the alignment systems ALG_R, ALG_L, and ALG_C can be calibrated by measuring the reference mark 60a of the alignment device 60 using the alignment systems ALG_R, ALG_L, and ALG_C. In other words, the positions of the alignment systems ALG_R, ALG_L, and ALG_C can be determined by measuring the reference mark 60a of the alignment device 60 using the alignment systems ALG_R, ALG_L, and ALG_C. In addition, the relative position with respect to the module can be determined using the reference mark 60a.

[0038] Furthermore, the substrate stage 30 is equipped with a movable mirror MR, a DM monitor 70, and the like, which are used to measure the position of the substrate stage 30.

[0039] The alignment systems ALG_R and ALG_L are equipped with multiple measuring microscopes and measure the position of chips placed on each wafer WF placed on the substrate holder of the substrate stage 30, or the position of the pads of the chips to be wired, with reference to the reference mark 60a of the alignment device 60. More specifically, the alignment systems ALG_R and ALG_L measure the position of each chip based on the design position of each chip, with reference to the reference mark 60a. The measurement results are output to the data creation device 300, which will be described later.

[0040] The alignment system ALG_C measures the position of the wafer WF placed on the substrate holder of the substrate stage 30 before exposure begins, using the reference mark 60a of the alignment device 60 as a reference. Based on the measurement results of the alignment system ALG_C, a misalignment of the wafer WF relative to the substrate stage 30 is detected, and the exposure start position and other settings are changed.

[0041] Figure 7 is a block diagram showing the control system 600 of the exposure apparatus EX according to this embodiment. As shown in Figure 7, the control system 600 comprises a data creation device 300, a first storage device 310R, a second storage device 310L, and an exposure control device 400.

[0042] The data creation device 300 receives measurement results of the positions of each chip or the pads of each chip on the wafer WF placed on the substrate holder of the substrate stage 30 from the alignment systems ALG_R and ALG_L. Based on the measurement results of the positions of each chip, the data creation device 300 determines the wiring pattern connecting the chips and creates control data to be used to control the DMD204 when generating the determined wiring pattern. Next, the creation of the control data will be described in more detail.

[0043] Figure 8(A) is a schematic diagram showing a wafer WF with all chips positioned at their design locations (hereinafter referred to as "design locations"). As shown in Figure 8(A), the wiring pattern WL connecting chip C1 and chip C2 is exposed (formed) by the exposure apparatus EX. In FO-WLP, the chips are solidified on the wafer WF with a molding material such as resin, so as shown in Figure 8(B), the positions of individual chips may shift relative to their design locations. In this case, if the DMD204 is controlled and the wiring pattern is exposed using data indicating the wiring pattern connecting the chips at their design locations (hereinafter referred to as "design value data"), the wiring pattern may shift from the pad positions, potentially causing connection failures or short circuits.

[0044] Therefore, in this embodiment, the positions of the chips included in each set of multiple chips arranged on the wafer WF are measured by the alignment system ALG_R or ALG_L. The data creation device 300 creates wiring pattern data with a portion of the design value data corrected based on the measurement results obtained from the alignment system ALG_R or ALG_L.

[0045] The generated wiring pattern data is stored in the first storage device 310R or the second storage device 310L. The first storage device 310R and the second storage device 310L are, for example, SSDs (Solid State Drives).

[0046] The first storage device 310R stores wiring pattern data used to control the DMD204 when exposing the wafer WF placed on the substrate stage 30R. The second storage device 310L stores wiring pattern data used to control the DMD204 when exposing the wafer WF placed on the substrate stage 30L. The wiring pattern data stored in the first storage device 310R or the second storage device 310L is transferred to the exposure control device 400.

[0047] Next, an example of the procedure for forming the wiring pattern of the FO-WLP in the exposure apparatus EX according to this embodiment will be described. Figure 9 is a conceptual diagram of the procedure for forming the wiring pattern of the FO-WLP in the exposure apparatus EX.

[0048] As shown in Figure 9, in this embodiment, for example, while the wafer WF on the substrate stage 30R is being exposed, the wafer WF is loaded onto the substrate stage 30L, and the chip position is measured by the alignment system ALG_L. Based on the measurement results of the chip position, the data creation device 300 sequentially creates wiring pattern data and stores (transfers) the created wiring pattern data to the second storage device 310L. The wiring pattern data stored in the second storage device 310L is sequentially transferred to the exposure control device 400 in conjunction with the start of exposure of the wafer WF on the substrate stage 30L.

[0049] Furthermore, as shown in Figure 2, when arranging four wafers WF in a single tray TR in a single row, the tray TR may be placed on the substrate stage 30L after all four wafers WF have been placed on the tray TR, and the measurement of chip positions may be started using the alignment system ALG_L. In this case, the measurement of chip positions by the alignment system ALG_L and the process of placing another wafer WF on the next tray TR can be performed in parallel. Then, in parallel with the process of placing the tray TR with the other wafer WF on the substrate stage 30L, the wiring pattern data of the wafer WF whose chip position has already been measured can be created based on the measurement results from the alignment system ALG_L, and stored in the second storage device 310L. Such parallel processing is particularly effective when the creation, transfer, and storage of wiring pattern data takes time. Furthermore, if the time required for measuring the chip position and creating and storing the wiring pattern data is shorter than the exposure time, for example, four wafers in three rows (WF) may be placed on a single tray TR, then transferred to the substrate stage 30L, and measurement may be performed using the alignment system ALG_L. In addition, the placement process only requires either a placement operation to place the wafer WF on the tray TR, or a preparation operation to prepare the tray TR for placement.

[0050] Meanwhile, when exposure of the wafer WF on the substrate stage 30L begins, the exposed wafer WF on the substrate stage 30R is removed, and a new wafer WF is loaded onto the substrate stage 30R. Subsequently, the chip position is measured by the alignment system ALG_R. Based on the measurement results of the chip position, the data creation device 300 sequentially creates wiring pattern data and transfers the created wiring pattern data to the first storage device 310R. The wiring pattern data stored in the first storage device 310R is sequentially transferred to the exposure control device 400 in conjunction with the start of exposure of the wafer WF on the substrate stage 30R.

[0051] In this embodiment, while exposure processing is being performed using one of the two substrate stages 30R and 30L, the other substrate stage performs tasks such as unloading the exposed wafer, loading a new wafer, measuring the chip position, and creating and transferring wiring pattern data. By performing parallel processing using the two substrate stages 30R and 30L in this way, the time required for chip position measurement and the creation and transfer of wiring pattern data can be hidden within the exposure processing time. This improves the throughput in forming the wiring pattern of FO-WLP. The exposure processing includes a series of operations from driving the substrate stage for exposure to driving the substrate stage to the substrate exchange position after exposure is complete.

[0052] As described in detail above, the exposure apparatus EX according to this first embodiment comprises a spatial light modulator (DMD204 in the first embodiment), a data creation device 300, and an exposure control device 400. The exposure apparatus EX also comprises a plurality of substrate stages 30R, 30L and alignment systems ALG_R, ALG_L. The alignment system ALG_L measures the positions of chips C1 and C2 included in each set of semiconductor chips arranged on the wafer WF placed on the substrate stage 30L while a wiring pattern is being exposed on the wafer WF placed on the substrate stage 30R. The data creation device 300 obtains the measurement results from the alignment system ALG_L and determines the wiring pattern WL connecting chips C1 and C2 included in each set of chips arranged on the wafer WF on the substrate stage 30L based on the measurement results. The data creation device 300 then creates wiring pattern data to be used to control the DMD204 when generating the determined wiring pattern WL and stores it in the second storage device 310L. When the exposure process on the substrate stage 30R is completed, the exposure control device 400 uses the wiring pattern data stored in the second storage device 310L to control the DMD 204 and expose the wiring patterns WL that connect chips C1 and C2 in each set on the wafer WF placed on the substrate stage 30L. This allows for measurement of the chip positions on the substrate placed on the substrate stage 30L, and creation and transfer of wiring pattern data based on the measurement results, while the wafer WF on the substrate stage 30R is being exposed. This allows for efficient use of time and improves the throughput in forming the wiring patterns of FO-WLP.

[0053] Furthermore, in this first embodiment, multiple wafers WF are arranged on substrate stages 30R and 30L provided by the exposure apparatus EX. This allows wiring patterns connecting semiconductor chips to be formed on multiple wafers WF, thereby improving the throughput in forming FO-WLP wiring patterns.

[0054] Furthermore, in this first embodiment, the exposure apparatus EX includes a plurality of exchange arms 20R, 20L for exchanging wafers WF held by substrate stages 30R, 30L, respectively. For example, while the wafer WF on substrate stage 30R is being exposed, the exchange arms 20L exchange the wafer WF on substrate stage 30L. This allows for efficient use of time, thereby improving the throughput in forming the wiring pattern of the FO-WLP.

[0055] Furthermore, in this first embodiment, the exposure apparatus EX is equipped with multiple DMD204s, each of which forms wiring patterns connecting semiconductor chips within different sets. This allows for the simultaneous formation of wiring patterns connecting semiconductor chips within different sets, thereby improving the throughput in forming FO-WLP wiring patterns.

[0056] In the first embodiment described above, while exposure processing was being performed using one of the two substrate stages 30R and 30L, the other substrate stage was used to remove the exposed wafer, load a new wafer, measure the chip position, and create and transfer wiring pattern data. However, the embodiment is not limited to this. While exposure processing is being performed using one of the two substrate stages 30R and 30L, at least one of the following is performed on the other substrate stage: removal of the exposed wafer, loading a new wafer, measurement of the chip position, and creation and transfer of wiring pattern data.

[0057] (modified version) The data creation device 300 may also create drive data that specifies the drive amount of the DMD204 and the drive amount of the lens actuator, rather than wiring pattern data. That is, the DMD204 generates a wiring pattern using design value data, and by changing the drive amount of the DMD204 and the drive amount of the lens actuator, the position of the projected image of the wiring pattern projected onto the wafer WF may be changed, thereby changing the shape of the wiring pattern formed on the wafer WF. The shape of the wiring pattern may also be changed by optically correcting the image of the wiring pattern.

[0058] 《Second Embodiment》 Since the process of attaching chips to the wafer WF is performed before the formation of the wiring pattern in the exposure apparatus EX, the data creation apparatus 300 may create wiring pattern data or drive data using measurement data acquired in the inspection process for checking the position of each chip on the wafer WF.

[0059] Figure 10 is a top view showing an overview of the wiring pattern formation system 500A according to the second embodiment. The wiring pattern formation system 500A according to the second embodiment includes a chip measurement station CMS for measuring the position of chips on a wafer WF.

[0060] The chip measurement station CMS is equipped with multiple measuring microscopes 61 to measure the positions of chips in different sets. Here, the positions of chips in different sets measured by the multiple measuring microscopes 61 may be the positions of chips in different sets on the same wafer WF, or the positions of chips in each set on different wafer WFs. In this embodiment, the multiple measuring microscopes 61 measure the positions of chips in each set on different wafer WFs.

[0061] The measurement results of the chip position are transmitted to the data creation device 300. Based on the measurement results of the chip position received from the chip measurement station CMS, the data creation device 300 creates wiring pattern data (which may also be drive data). The wiring pattern data created by the data creation device 300 is stored in a different storage device than the storage device that stores the wiring pattern data currently used for exposure control of the substrate being exposed. That is, if the wiring pattern data currently used for exposure control of the wafer WF is stored in the first storage device 310R, the data creation device 300 stores (transfers) the created wiring pattern data to the second storage device 310L.

[0062] In the exposure apparatus EX-A according to the second embodiment, the main body 1A includes one substrate stage 30. In the second embodiment, since the chip position is measured by the chip measurement station CMS, the alignment systems ALG_L and ALG_R can be omitted.

[0063] After the chip position measurement is complete, the wafers WF are coated with a photosensitive resist using the coater-developer device CD and then transported to the buffer section PB. The wafers WF placed in the buffer section PB are then arranged in multiples (4 wafers x 3 rows in the second embodiment) on a single tray TR by the robot RB installed in the substrate exchange section 2A, transported to the main unit 1A, and placed on the substrate holder of the substrate stage 30.

[0064] The alignment system ALG_C measures the position of each wafer WF relative to the substrate holder and corrects the exposure start position, etc. However, if the wafer WF rotates around the Z-axis when placed on the substrate holder, causing the chip position to shift from the position of the wiring pattern data created by the data creation device 300, there is a risk that the connections between chips will not be made correctly if wiring is formed using that wiring pattern data.

[0065] In this case, the data creation device 300 can correct the shape of the wiring pattern so that the chips are connected by creating wiring pattern data or drive data, as described in the first embodiment and its modifications. For example, the data creation device 300 detects the positional deviation of each chip from the position of the wiring pattern data based on the position of each wafer WF measured by the chip measurement station CMS and the position of each wafer WF measured by the alignment system ALG_C. Based on this deviation, the data creation device 300 corrects the wiring pattern data or creates drive data. This makes it possible to form wiring that connects the chips even if the wafer WF rotates around the Z axis when the wafer WF is placed on the substrate holder.

[0066] Furthermore, the alignment system ALG_C may use the alignment marks on the chip to measure the position of the wafer WF.

[0067] Figure 11 is a conceptual diagram of the wiring pattern formation procedure for FO-WLP in the second embodiment. Similar to the first embodiment, during the exposure process in the main body 1A, the chip position is measured, wiring pattern data (which may also be drive data) is created and transferred, resist is applied to the wafer WF, and the wafer WF is placed on the tray TR, thereby improving the throughput in forming the wiring pattern of FO-WLP.

[0068] The exposure apparatus EX according to this second embodiment comprises a spatial light modulator (DMD204), a data creation device 300, and an exposure control device 400. The data creation device 300 acquires measurement results from a chip measurement station CMS that measures the positions of chips C1 and C2 included in each set of semiconductor chips arranged on a wafer WF, determines a wiring pattern WL connecting chips C1 and C2 included in each set based on the measurement results, creates wiring pattern data to be used to control the DMD204 when generating the determined wiring pattern WL, and stores it in a first storage device 310R or a second storage device 310L. The exposure control device 400 controls the DMD204 using the wiring pattern data stored in the first storage device 310R or the second storage device 310L to expose the wiring pattern WL connecting chips C1 and C2 included in each set. The measurement of the chip positions on the wafer WF is performed while a set of wafer WF different from the set of wafer WFs whose chip positions are measured together with the wafer WF is being exposed. This allows for the measurement of chip positions and the creation and transfer of wiring pattern data based on the measurement results during the relatively time-consuming exposure process, enabling efficient use of time and improving the throughput in forming wiring patterns for FO-WLP.

[0069] 《Third Embodiment》 The wafer WF may be attached to the base substrate B, and the position of each chip relative to the base substrate B may be measured using a chip measurement station CMS.

[0070] Figure 12 is a top view showing an overview of the wiring pattern formation system 500B according to the third embodiment. The wiring pattern formation system 500B according to the third embodiment has a wafer placement device WA that attaches a plurality of wafers WF on which chips are placed to a base substrate B. The wafer placement device WA is designed to prevent the position of the wafers WF relative to the base substrate B from changing.

[0071] The base substrate B, to which multiple wafers WF have been attached by the wafer placement device WA, is then transported to the chip measurement station CMS.

[0072] The chip measurement station CMS is equipped with multiple measuring microscopes 61 to measure the position of each chip relative to the base substrate B. The multiple measuring microscopes 61 measure the position of chips in different sets. The measurement results of the chip positions are transmitted to the data creation device 300.

[0073] The data creation device 300 creates wiring pattern data (which may also be drive data) based on the chip position measurement results received from the chip measurement station CMS. The wiring pattern data created by the data creation device 300 is stored in a different storage device than the one that stores the wiring pattern data currently used for exposure control of the wafer WF on the base substrate B that is currently being exposed. That is, if the wiring pattern data currently used for exposure control of the wafer WF on the base substrate B that is currently being exposed is stored in the first storage device 310R, the data creation device 300 stores (transfers) the created wiring pattern data to the second storage device 310L.

[0074] After the chip position measurement is complete, the wafer WF, along with the base substrate B, is loaded into the coater-developer device CD, where a photosensitive resist is applied, and then it is loaded into the port PT of the substrate exchange unit 2B. Subsequently, the wafer WF, along with the base substrate B, is placed on the substrate holder of the substrate stage 30.

[0075] The subsequent processing is the same as in the second embodiment, so a detailed explanation is omitted. In the third embodiment, everything can be managed and exposure can be performed using the position of the base substrate B on which the wafer WF is placed and fixed. For example, even during alignment, EGA measurement and correction can be performed on the base substrate B. In other words, since the wafer WF is placed and fixed on the base substrate B, when the base substrate B is placed on the substrate holder of the substrate stage 30, alignment for each wafer WF / chip is unnecessary, and alignment of only the base substrate B is required. Note that although the wafer placement apparatus WA attached the wafer WF to the base substrate B, the wafer WF may also be placed and fixed directly on the tray TR.

[0076] In the third embodiment as well, the throughput for forming the redistribution layer of the FO-WLP can be improved by measuring the chip position, creating and transferring wiring pattern data, and applying resist to the wafer WF during the exposure process in the main body 1A.

[0077] (modified version) In the third embodiment, the wafer placement apparatus WA and the chip measurement station CMS are separate devices, but the configuration is not limited to this. The measurement microscope 61 may start measuring the chip position from the wafer WF attached to the base substrate B by the wafer placement apparatus WA. In other words, the measurement operation is performed by the measurement microscope 61 in parallel with the operation of attaching multiple wafers WF to the base substrate B. The measurement microscope 61 may start the measurement operation after one wafer WF has been attached to the base substrate B, or after multiple wafers WF have been attached to the base substrate B. The measurement microscope 61 may temporarily interrupt the measurement operation when the wafer WF is placed on the base substrate B. This is to prevent vibrations generated when the wafer WF is placed on the base substrate B from affecting the measurement results of the measurement microscope 61.

[0078] In the first to third embodiments and their modifications described above, the first storage device 310R and the second storage device 310L were separate storage devices. However, the data used for the exposure processing of the wafer WF placed on the substrate stage 30R (at least one of wiring pattern data and drive data) and the data used for the exposure processing of the wafer WF placed on the substrate stage 30L (at least one of wiring pattern data and drive data) may be stored in different storage areas of a single storage device. However, if different storage areas of a single storage device are used, access to one storage area is unavailable while the other storage area is being accessed, which may increase the overall processing time. Also, SSDs degrade with each write operation, and usage time affects their lifespan. Therefore, since the number of data writes to the storage device in this first embodiment is relatively high, if a single SSD is used, it may be necessary to replace the SSD in a short period of time. For this reason, it is preferable to use two storage devices.

[0079] In the first to third embodiments and their variations described above, the case in which multiple wafer-shaped substrates are placed on the substrate stage 30 has been explained, but multiple rectangular substrates may also be placed on the substrate stage 30.

[0080] Furthermore, the first to third embodiments and their modifications can also be applied to the formation of wiring patterns connecting chips on a substrate P as shown in Figure 3(B).

[0081] The embodiments described above are preferred examples of the present invention. However, the invention is not limited thereto, and various modifications are possible without departing from the spirit of the invention. [Explanation of symbols]

[0082] EX, EX-A, EX-B exposure equipment 204 DMD 204a Micromirror 300 Data Creation Devices 310R 1st storage device 310L 2nd storage device 400 Exposure control device C1, C2 semiconductor chips WF wafer P board

Claims

1. While an exposure apparatus including a spatial light modulator is performing substrate exposure, which is the exposure of a plurality of substrates arranged on a second tray, Position measurement is performed, which is the measurement of the position of each of the multiple chips contained in the first substrate arranged in the first tray and the position of each of the multiple chips contained in the second substrate arranged in the first tray, and This includes creating data, which consists of first pattern data, which is pattern data for wiring connecting the plurality of chips included in the first substrate, based on the respective positions of the plurality of chips included in the first substrate, and second pattern data, which is pattern data for wiring connecting the plurality of chips included in the second substrate, based on the respective positions of the plurality of chips included in the second substrate. During the period in which the position measurement is performed, the data creation is started. Method for forming wiring patterns.

2. Includes data transfer, which is the transfer of the first pattern data and the second pattern data to the exposure apparatus, During the period in which the aforementioned data is created, the aforementioned data transfer is initiated. The wiring pattern formation method according to claim 1.

3. This includes storing the first pattern data and the second pattern data in a first storage device, During the period in which pattern data used for exposure of the plurality of substrates arranged in the second tray is transferred from a second storage device different from the first storage device to the exposure apparatus, the storage is performed. The wiring pattern formation method according to claim 2.

4. The wiring pattern forming method according to any one of claims 1 to 3, wherein the substrate is a wafer substrate.

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