Digital-to-Time Converter

Abstract

To reduce power consumption of a circuit.SOLUTION: A digital-to-time converter receives an input signal, applies a delay corresponding to a control code, and generates an output signal. The digital-to-time converter includes: a slope generation circuit which includes a capacitor and a current source and generates a slope voltage; a pre-charge circuit which applies, to the capacitor, an analog voltage corresponding to the control code; a comparison circuit which compares the slope voltage with a threshold value and generates an output signal corresponding to a comparison result; and a control circuit controlling the slope generation circuit and the pre-charge circuit according to the input signal and the output signal. The control circuit repeats the following operations: (i) turning on the pre-charge circuit during a pre-charge period; (ii) transitioning to a slope period in response to the input signal, and turning off the pre-charge circuit and turning on the slope generating circuit during the slope period; and (iii) turning off the slope generating circuit in response to transition of the output signal.SELECTED DRAWING: Figure 23

Description

[Technical Field]

[0001] This invention relates to a digital-to-time converter. [Background technology]

[0002] A phase-locked loop (PLL) is used to generate a clock of any desired frequency by multiplying a reference clock. One form of PLL is the digital PLL (D-PLL).

[0003] Figure 1 is a circuit diagram showing the basic architecture of a fractional-N D-PLL circuit 100R. The D-PLL circuit 100R receives a reference clock REF and a frequency control word (FCW) that specifies the multiplication factor, and generates an output clock OUT by multiplying the reference clock REF according to the FCW.

[0004] It includes a digital-to-time converter (DTC) 102, a time-to-digital converter (TDC) 104, a digital loop filter (DLF) 106, a digitally-controlled oscillator (DCO) 108, a buffer 110, a multi-modulous divider (MMD) 112, a controller 114, and a retiming circuit 116.

[0005] DCO108 is a digital control data D CNTIt oscillates at a frequency corresponding to the specified value. The output clock OUT of DCO108 is input to MMD112 via buffer 110. MMD112 divides the output clock OUT by a division ratio set by controller 114. Controller 114 is designed based on the architecture of a ΔΣ modulator. In a fractional N-type PLL circuit, controller 114 switches the division ratio of MMD112 by multiple integer values ​​in a time-division manner to obtain a fractional multiplication ratio. The reciprocal of the average value of the division ratio set in MMD112 is the multiplication ratio N of the D-PLL circuit 100R. F This is the result.

[0006] The divided clock DIV is input to the retiming circuit 116. The retiming circuit 116 retiming the divided clock DIV with the output clock CKV via the buffer 110 generates a feedback clock FB.

[0007] The DTC102 outputs the reference clock REFA, adding a delay set by the controller 114 to the reference clock REF. This delay amount is selected according to the frequency division ratio given to the MMD112.

[0008] TDC104 converts the time difference between the reference clock REFA and the feedback clock FB into a digital value. DLF106 removes the high-frequency components from the output of TDC104 and outputs the control data D CNT Generates.

[0009] The above is the basic architecture of the D-PLL circuit 100R. Figure 2 is the timing chart of the D-PLL circuit 100R shown in Figure 1. The divided clock DIV is retiming by the clock CKV. Sampling delay τ in the retiming circuit 116. SAM Therefore, the edge E1 of the feedback clock FB is relative to the edge E2 of the clock CKV, τ SAMIt is delayed by only a fraction of a second. A feedback loop consisting of TDC104 and DLF106 applies feedback so that the time difference between edge E3 of the reference clock REFA and edge E1 of the feedback clock FB becomes zero, and the phase is locked. At this time, the frequency of the output clock OUT (and CKV) of DCO108 is N of the frequency of the reference clock REFA (and REF). F It doubles. [Overview of the project] [Problems that the invention aims to solve]

[0010] The D-PLL circuit 100R in Figure 1 has the advantages of high frequency accuracy and robustness against frequency interference. However, because the MMD 112 and retiming circuit 116 continue to operate in synchronization with the high-frequency clock CKV, there is a problem of high power consumption.

[0011] The present invention has been made in view of the aforementioned problems, and one exemplary objective of a certain embodiment thereof is to provide a D-PLL circuit with reduced power consumption. [Means for solving the problem]

[0012] Aspects related to the present invention relate to a phase-synchronous circuit that receives a first reference clock and generates an output clock. The phase-synchronous circuit includes a delay circuit that delays the first reference clock and generates a second reference clock, a feedback circuit that generates a control signal corresponding to the phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency corresponding to the control signal and generates an output clock, and a frequency divider that is switchable on and off and, when on, divides the output clock. This phase-synchronous circuit is switchable between a first mode and a second mode. In the first mode, the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock. In the second mode, the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0013] Aspects related to the present invention relate to a digital phase-synchronous circuit that receives an input reference clock and a frequency control word and generates an output clock. The digital phase-synchronous circuit includes a digital-to-time converter that receives an input reference clock and generates a first reference clock, a delay circuit that delays the first reference clock and generates a second reference clock, a time-to-digital converter that converts the phase difference between the second reference clock and a feedback clock into a digital signal, a digitally controlled oscillator that oscillates at a frequency corresponding to the output of the time-to-digital converter and generates an output clock, and a frequency divider that is switchable on and off, and in the ON state divides the output clock by a frequency division ratio corresponding to the frequency control word. A first mode and a second mode are switchable, in which the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock, and in which mode the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0014] An aspect relating to the present invention is a digitally controlled oscillator. This digitally controlled oscillator comprises an upper unit and a lower unit connected in series between a power line and a ground line, and a variable capacitor connected to at least one of the upper unit and the lower unit. The upper unit and the lower unit each include a pair of cross-coupled circuit elements and an inductor connected to the pair of circuit elements. The inductors of the upper unit and the lower unit are coupled to form a transformer.

[0015] One aspect of the present invention is a digital-to-time converter. This digital-to-time converter is A digital-to-time converter that receives an input signal, applies a delay according to a control code, and generates an output signal, A current source connected in series between the power line and the ground line via a slope voltage node, and Capacitor and , a first switch that controls the supply of current to the slope voltage node by the current source and Includes, When the first switch is turned on, the slope voltage node A slope generation circuit that generates a slope voltage, Includes a second switch, and when the second switch is turned ON Analog voltage corresponding to the control code Slope voltage node The pre-charge circuit to be applied, A comparison circuit that compares the slope voltage with a threshold and generates an output signal according to the comparison result, Depending on the input signal and output signal, Switch 1 and Switch 2 It includes a control circuit that controls the following. The control circuit (i) during the precharge period Turn off the first switch and turn on the second switch. (ii) In response to the input signal, it transitions to a slope period, and in the slope period Turn off the second switch and turn on the first switch. (iii) In response to the transition of the output signal Switch 1 Repeat the action of turning it off.

[0016] Furthermore, any combination of the above components, or any substitution of components or expressions of the present invention between methods, apparatus, systems, etc., is also valid as an embodiment of the present invention. [Effects of the Invention]

[0017] According to one aspect of the present invention, power consumption can be reduced. [Brief explanation of the drawing]

[0018] [Figure 1] This is a circuit diagram showing the basic architecture of a fractional-N D-PLL circuit. [Figure 2] Figure 1 is a time chart of the D-PLL circuit. [Figure 3] This is a circuit diagram showing the basic architecture of a D-PLL circuit according to an embodiment. [Figure 4] This is an equivalent circuit diagram of a D-PLL circuit in subsampling mode (EN=0). [Figure 5] This is a timing chart of the D-PLL circuit in subsampling mode. [Figure 6] Figures 6(a) and 6(b) are time charts comparing the operation of the D-PLL circuit in sampling mode and subsampling mode. [Figure 7] This is a waveform diagram of the output frequency fOUT of a D-PLL circuit in subsampling mode. [Figure 8]This is a circuit diagram of the D-PLL circuit according to Example 1. [Figure 9] Figures 9(a) and 9(b) illustrate the operation of the mode selector in the D-PLL circuit shown in Figure 8. [Figure 10] This is a circuit diagram of the D-PLL circuit according to Example 2. [Figure 11] This diagram illustrates the operation of the mode selector in a D-PLL circuit. [Figure 12] Figure 8 shows the waveform of the output frequency fOUT of the D-PLL circuit. [Figure 13] This is a circuit diagram of the D-PLL circuit according to Example 3. [Figure 14] Figures 14(a) and (b) are circuit diagrams of a conventional DCO. [Figure 15] This is a circuit diagram showing the basic architecture of a DCO according to an embodiment. [Figure 16] Figure 15 is the equivalent circuit diagram of the DCO. [Figure 17] This figure shows the relationship between the bias current IBIAS and the output signal amplitude VAMP. [Figure 18] This is a circuit diagram of the DCO relating to Modification Example 1. [Figure 19] This is a circuit diagram of the DCO relating to Modification Example 2. [Figure 20] Figures 20(a) to (f) are circuit diagrams showing further variations of the DCO. [Figure 21] This is a circuit diagram of a conventional DTC. [Figure 22] Figure 21 shows the operating waveform of the DTC. [Figure 23] This is a circuit diagram of a DTC according to an embodiment. [Figure 24] This is a circuit diagram showing an example of a control circuit configuration. [Figure 25] Figure 23 is a time chart illustrating the operation of the DTC. [Figure 26] This figure shows the operating waveform (i) of the DTC according to this embodiment and the operating waveform (ii) of a conventional DTC. [Modes for carrying out the invention]

[0019] (Summary of the embodiment) 1. One embodiment disclosed herein relates to a phase-synchronous circuit that receives a first reference clock and generates an output clock. The phase-synchronous circuit includes a delay circuit that delays the first reference clock and generates a second reference clock; a feedback circuit that generates a control signal corresponding to the phase difference between the second reference clock and a feedback clock; an oscillator that oscillates at a frequency corresponding to the control signal and generates an output clock; and a frequency divider that is switchable on and off, and in the ON state divides the output clock. This phase-synchronous circuit is switchable between a first mode and a second mode. In the first mode, the feedback clock is a signal obtained by retiming the output of the frequency divider with the output clock. In the second mode, the feedback clock is a signal obtained by retiming the first reference clock with the output clock.

[0020] According to this embodiment, by selecting the second mode, the operation of the frequency divider is stopped, and phase synchronization is applied using the second reference clock as a feedback clock, thereby reducing power consumption. Furthermore, by selecting the first mode as needed, the phase synchronization state can be restored if it is lost.

[0021] In one embodiment, the phase-locked circuit may include a mode controller that generates enable signals indicating a first mode and a second mode, a multiplexer that receives the output of a frequency divider and a first reference clock and selects one of them according to the enable signal, and a retiming circuit that retimings the output of the multiplexer with the output clock. The on / off state of the frequency divider is controlled according to the enable signal, and the output of the retiming circuit may be a feedback clock.

[0022] In one embodiment, the phase-synchronization circuit further includes a dead zone detector that determines whether the phase error between the second reference clock and the feedback clock falls within the dead zone range, and the first and second modes may correspond to the output of the dead zone detector. This prevents the circuit from falling into a mode where phase synchronization does not occur.

[0023] In one embodiment, the dead zone detector may include a phase-frequency detector that compares the phase difference or frequency difference between a second reference clock and a feedback clock and outputs a pulse based on the comparison result, and a determination unit that generates a phase error based on the output of the phase-frequency detector and determines whether or not the phase error is included in the dead zone.

[0024] In one embodiment, the digital phase-locking circuit may further include a frequency-locking loop that monitors the relationship between the frequency of the output clock and the frequency of the input reference clock, and detects a frequency error where the frequency of the output clock deviates from a target frequency determined based on the division ratio of the frequency divider. The first and second modes may correspond to the output of the frequency-locking loop. This prevents phase locking at an incorrect frequency.

[0025] The frequency-locked loop may include a counter that counts the output clock for a period of K times (where K is an integer) the period of the input reference clock. Frequency errors may be detected based on the counter's count value and the multiplication ratio, which is the reciprocal of the division ratio, multiplied by K.

[0026] In one embodiment, the phase-locked circuit may further include a duty cycle controller that generates control pulses having a predetermined duty cycle. The frequency-locked loop may operate intermittently in response to the control pulses. By operating the frequency-locked loop intermittently, an increase in power consumption can be suppressed.

[0027] In one embodiment, the digital phase-locked circuit may further include a phase-frequency detector that compares the phase difference or frequency difference between a second reference clock and a feedback clock and outputs a pulse based on the comparison result, and a PLL (Phase Locked Loop) circuit that operates in the first mode and feedback-controls the frequency of a digital control oscillator based on the output of the phase-frequency detector. The accuracy of the feedback loop including the phase-frequency detector and the PLL circuit may be coarser than the accuracy of the feedback circuit. This makes it possible to quickly pull the phase lock from an unlocked state to a locked state.

[0028] The phase-locked circuit may be a digital phase-locked circuit. The feedback circuit may include a second reference clock and a time-to-digital converter that converts the phase difference of the feedback clock into a digital signal. The oscillator may be a digitally controlled oscillator that oscillates at a frequency corresponding to the output of the time-to-digital converter.

[0029] The phase-locked circuit may be of fractional frequency division type. The frequency divider may be a multimodulus frequency divider. The phase-locked circuit may further include a digital-to-time converter that receives an input reference clock and generates a first reference clock, and a controller that controls the digital-to-time converter and the multimodulus frequency divider according to a frequency control word that specifies the frequency of the output clock.

[0030] 2. One aspect of the present invention is a digitally controlled oscillator. This digitally controlled oscillator comprises an upper unit and a lower unit connected in series between a power line and a ground line, and a variable capacitor connected to at least one of the upper unit and the lower unit. The upper unit and the lower unit each include a pair of cross-coupled circuit elements and an inductor connected to the pair of circuit elements. The inductors of the upper unit and the lower unit are coupled to form a transformer.

[0031] With this configuration, the gain amplification effect of the transformer allows for a reduction in the bias current required to obtain the same amplitude, or, if the bias current is maintained, the amplitude can be increased.

[0032] At least one of the upper and lower units may be an N-type circuit where the pair of circuit elements is an NMOS (N-channel Metal Oxide Semiconductor) transistor. Both the upper and lower units may be N-type.

[0033] At least one of the upper and lower units may be a P-type configuration in which the pair of circuit elements is a PMOS (P-channel Metal Oxide Semiconductor) transistor.

[0034] At least one of the upper and lower units may be a CMOS type, where the pair of circuit elements is a CMOS (Complementary Metal Oxide Semiconductor) inverter.

[0035] The digitally controlled oscillator may further include a bias current source inserted between the power line and the ground line.

[0036] The digitally controlled oscillator may further include capacitors connected to the connection nodes between the upper and lower units.

[0037] 3. Yet another aspect of the present invention is a digital-to-time converter. This digital-to-time converter receives an input signal, applies a delay according to a control code, and generates an output signal. The digital-to-time converter includes a slope generation circuit that generates a slope voltage, which includes a capacitor and a current source; a precharge circuit that applies an analog voltage to the capacitor according to a control code; a comparison circuit that compares the slope voltage with a threshold and generates an output signal according to the comparison result; and a control circuit that controls the slope generation circuit and the precharge circuit according to the input signal and the output signal. The control circuit repeats the following operations: (i) turning on the precharge circuit during the precharge period; (ii) transitioning to the slope period in response to the input signal, turning off the precharge circuit and turning on the slope generation circuit during the slope period; and (iii) turning off the slope generation circuit in response to the transition of the output signal.

[0038] According to this embodiment, power consumption can be reduced by suppressing unnecessary charging and discharging of the capacitor.

[0039] The comparator circuit is configured to be switchable on and off, and the control circuit may turn off the comparator circuit during the pre-charge period.

[0040] (Embodiment) The present invention will be described below with reference to the drawings, based on preferred embodiments. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the invention.

[0041] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0042] Similarly, "the state in which member C is provided between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions or effects produced by their combination.

[0043] (D-PLL circuit) Figure 3 is a circuit diagram showing the basic architecture of a D-PLL circuit 100 according to an embodiment. The D-PLL circuit 100 is a fractional frequency divider type PLL circuit that receives an input reference clock REF and a frequency control word FCW, and input reference clock REF An output clock OUT is generated, having a frequency that is a fractional multiple of the frequency F.

[0044] The D-PLL circuit 100 includes, in addition to the D-PLL circuit 100R shown in Figure 1, a multiplexer 120, a delay circuit 122, and a mode selector 130. Furthermore, the MMD112A is configured to be switchable between enable and disable (on / off).

[0045] The D-PLL circuit 100 is switchable between two modes (referred to as sampling mode and subsampling mode), and the two modes are selected according to the enable signal EN. When the enable signal EN is 1 (high), the D-PLL circuit 100 is set to sampling mode, and when the enable signal EN is 0 (low), it is set to subsampling mode.

[0046] The multiplexer 120 receives the divided clock DIV, which is the output of the MMD 112, and the first reference clock REFA, which is output by the DTC 102, and selects one of them according to the enable signal EN. The output of the multiplexer 120 is retimed by the retiming circuit 116 to become the feedback clock FB. The output clock CKV, which has passed through the buffer 110, can be used for retiming. Note that if the output impedance of the DCO 108 is sufficiently low, the buffer 110 may be omitted.

[0047] Here, when the enable signal EN is 1 (high), the feedback clock FB is generated based on the divided clock DIV, and when it is 0 (low), the feedback clock FB is generated based on the first reference clock REFA.

[0048] The function of the MMD112A is the same as that of the MMD112 in Figure 1, but it is configured to be switchable on and off in response to the enable signal EN. For example, the MMD112A includes a gate circuit 113 in addition to the MMD112 in Figure 1. The gate circuit 113 is inserted before the MMD112 and gates the clock signal CKV in response to the enable signal EN. That is, when the enable signal EN is 1, the clock CKG that has passed through the gate circuit 113 is input to the MMD112, and the MMD112 is enabled. When the EN signal is 0, the clock CKG is fixed low, and therefore the MMD112 is disabled.

[0049] The delay circuit 122 is inserted after the DTC102 and adds a delay τ to the first reference clock REFA. FB It provides a second reference clock REFB and outputs it. TDC104 is fed back so that the edges of the second reference clock REFB and the edges of the feedback clock FB coincide.

[0050] The mode selector 130 generates an enable signal EN based on the operating state of the D-PLL circuit 100 and controls the mode of the D-PLL circuit 100.

[0051] The above is the basic configuration of the D-PLL circuit 100. Next, its operation will be described. FIG. 4 is an equivalent circuit diagram of the D-PLL circuit 100 in the sub-sampling mode (EN = 0). In the sub-sampling mode, the operation of the MMD 112 stops. Since the frequency of the first reference clock REFA is equal to the frequency of the divided clock DIV, instead of the divided clock DIV, the first reference clock REFA is input to the timing circuit 116. Then, the timing circuit 116 retimes the first reference clock REFA at the edge of the clock signal CKV and generates the feedback clock FB.

[0052] FIG. 5 is a timing chart of the D-PLL circuit 100 in the sub-sampling mode. In the sub-sampling mode, instead of the divided clock DIV, the first reference clock REFA is retimed by the clock CKV. Due to the sampling delay τ SAM in the timing circuit 116, the edge E1 of the feedback clock FB is delayed by τ SAM with respect to the edge E2 of the clock CKV. Feedback is applied by the feedback loop including the TDC 104 and the DLF 106 so that the time difference between the edge E4 of the second reference clock REFB and the edge E1 of the feedback clock FB becomes zero, and the phase is locked.

[0053] In the sub-sampling mode, since the feedback clock FB is generated by retiming the first reference clock REFA, the edge of the feedback clock FB will be delayed compared to the edge of the first reference clock REFA. Therefore, even if feedback is applied, the edge (phase) of the feedback clock FB cannot be aligned with the edge of the first reference clock REFA. Thus, considering the phase delay when generating the feedback clock FB by retiming, the delay amount τ FB of the delay circuit 122 is determined so that it can be canceled out. As a result, the phase of the second reference clock REFB (= REFA + τ FB ) and the phase of the feedback clock FB delayed by retiming (= REFA + Δt + τSAM This means that the ) is included within one cycle of the clock signal CKV, making it possible to apply phase synchronization.

[0054] Figures 6(a) and 6(b) are time charts comparing the operation of the D-PLL circuit 100 in sampling mode and subsampling mode. The operation in sampling mode in Figure 6(a) is the same as that in Figure 2. The difference is that the phase of the feedback clock FB is locked relative to the phase of the second reference clock REFB, rather than the first reference clock REFA. The operation in subsampling mode in Figure 6(b) is the same as in Figure 5.

[0055] The above describes the operation of the D-PLL circuit 100. Next, we will explain its advantages. When the D-PLL circuit 100 is operated in subsampling mode, the operation of the MMD112 is stopped, so power consumption can be reduced significantly compared to sampling mode.

[0056] Note that in subsampling mode, the frequency f of the output clock OUT is used. OUT However, that target value (=f REF Once locked to ×N), phase synchronization can be maintained with low power consumption, but f OUT ≠f REF From the state of ×N, f OUT =f REF It is not possible to transition to the ×N state. This is because MMD112 is not used, and therefore the multiplication ratio N does not affect the circuit operation.

[0057] Therefore, the mode selector 130 monitors the operating status of the D-PLL circuit 100, and when starting up or when phase synchronization is lost, the enable signal EN is temporarily set to high (1) to set it to sampling mode, f OUT =f REF It is possible to transition to a state of ×N.

[0058] The above describes the basic architecture of the D-PLL circuit 100 according to the embodiment. Next, the specific implementation of the D-PLL circuit 100 will be described with reference to several examples.

[0059] First, we will explain the problems that can occur in subsampling mode. Figure 7 shows the output frequency f of the D-PLL circuit 100 in subsampling mode. OUT This is the waveform diagram (simulation). REF =10MHz, N=240+0.5. In phase-locked state, the output frequency f OUT The frequency will be stabilized at 2405MHz (=2.405GHz).

[0060] Figure 7 shows waveforms (i) to (iii) when frequency interferences of -1 MHz, +6 MHz, and +11 MHz are injected. As shown in (i), when a frequency interference of -1 MHz is introduced, the phase-locked state can be maintained.

[0061] In subsampling mode, the edges of the CKV clock used for retiming shift due to the retiming of the wide first reference clock REFA with the CKV clock. As a result, as shown in Figure 7(ii), there is a possibility of incorrect locking when N'=241+0.5. Alternatively, as shown in Figure 7(iii), there is a possibility of a situation where phase synchronization is not applied and the frequency oscillates.

[0062] In other words, the mode selector 130 needs to be implemented to monitor the state of the D-PLL circuit 100 and control the mode of the D-PLL circuit 100 so as not to fall into situations like (ii) or (iii) in Figure 7.

[0063] (Example 1) Figure 8 is a circuit diagram of the D-PLL circuit 100A according to Embodiment 1. In this embodiment, the mode selector 130A is configured to detect a state of non-phase synchronization, as shown in waveform (iii) of Figure 7.

[0064] The mode selector 130A includes a dead zone detector 140 and a state machine 132. The dead zone detector 140 detects the phase error t between REFB and FB. ERR However, the dead zone DZ The system determines whether the condition falls within a specified range and generates a detection signal ODZ (Out of Dead Zone) which is a first level (e.g., high, 1) if it is outside the range and a second level (e.g., low, 0) if it is within the range.

[0065] The configuration of the dead zone detector 140 is not particularly limited, but may include, for example, a phase frequency detector (PFD) 142 and a determination unit 144. The PFD 142 compares the phase difference or frequency difference between the second reference clock REFB and the feedback clock FB, and outputs two pulses (UP pulse and DN pulse) based on the comparison result.

[0066] The determination unit 144 receives the output UP / DN from the PFD 142 and determines the phase error t based on them. ERR It generates a phase error t. ERR However, it determines whether or not it is included in the dead zone and outputs an ODZ signal.

[0067] State machine 132 generates an enable signal EN by synchronizing the ODZ signal with the reference clock REF. State machine 132 can be constructed using flip-flops.

[0068] The above describes the configuration of the D-PLL circuit 100A. Next, its operation will be explained. Figures 9(a) and 9(b) illustrate the operation of the mode selector 130A in the D-PLL circuit 100A shown in Figure 8. Figure 9(a) shows the input / output characteristics of the dead zone detector 140.

[0069] Figure 9(b) shows the overall operation of the D-PLL circuit 100A. Before time t0, it operates in subsampling mode. Due to some factor, the phase error t between the feedback clock FB and the reference clock REFB occurs. ERR is the dead zoneDZ When the value falls outside this range, the ODZ signal periodically goes high, and the enable signal EN goes high (1). As a result, the system switches to sampling mode. When operating in sampling mode, the phase error t ERR It becomes smaller, and at time t2, the dead zone t DZ When it returns to within the range, the ODZ signal returns to low. This causes the enable signal EN to go low, and the system switches to subsampling mode.

[0070] The above describes the operation of the D-PLL circuit 100A. By implementing the dead zone detector 140 and operating it in the background, it is possible to prevent situations where phase synchronization is not possible, as shown in Figure 7(iii).

[0071] (Example 2) Figure 10 is a circuit diagram of the D-PLL circuit 100B according to Embodiment 2. In this embodiment, the mode selector 130B is configured to detect frequency jumps of integer multiples, as shown in waveform (ii) of Figure 7.

[0072] The mode selector 130B includes a dead zone detector 140, a state machine 132, and an intermittent frequency-locked loop (FLL) 150. The intermittent FLL is also referred to as DC-FLL (Duty Cycled FLL).

[0073] The intermittent operation FLL150 includes FLL152 and duty cycle controller 154.

[0074] FLL152 is configured to be switchable between enable and disable. When enabled, FLL152 monitors the relationship between the frequency of the clock signal CKV(OUT) and the frequency of the reference clock REF. If the frequency of the clock signal CKV deviates from the target frequency determined by FCW, it asserts (e.g., high) the frequency lock error signal FLE. Conversely, FLL152 monitors how many times the period of the reference clock REF is compared to the period of the clock signal CKV and determines whether it matches the multiplication ratio based on FCW. In response to the assertion of the frequency lock error signal FLE, state machine 132 switches the enable signal EN high.

[0075] The configuration of the FLL152 is not limited, but may include, for example, a frequency detector 160, a subtractor 170, and a comparator 172. The frequency detector 160 counts the clock signal CKV for an integer multiple of the period of the reference clock REF (K=4 in this example). When frequency locked, this count value is K times the frequency multiplier FCW.

[0076] The frequency detector 160 includes a frequency divider 162, D flip-flops 164 and 168, and a counter 166. The frequency divider 162 divides the reference clock REF by 1 / K (K=4). The divided clock is synchronized with the clock CKV in the flip-flop 164. The counter 166 counts the number of pulses of the clock CKV. The flip-flop 168 captures the count value of the counter 166 at the timing of the output of the frequency divider 162. The output of the flip-flop 168 indicates how many times the clock CKV is contained in a period that is K times the period of the reference clock REF.

[0077] The subtractor 170 calculates the difference (frequency error) between the output of the flip-flop 168 and its target value (K × FCW). The comparator 172 compares the output of the subtractor 170 with a threshold value and asserts the frequency lock error signal FLE if the frequency error exceeds the allowable value.

[0078] FLL152 is a high-frequency signal (f OUTBecause it includes a counter 166 operating at 2.4GHz, continuous operation would result in high power consumption. Therefore, the duty cycle controller 154 generates a control pulse DC with a predetermined duty cycle, and the FLL 152 is operated intermittently based on this control pulse DC. For example, the duty cycle can be 1% or less, for example, around 0.5%. This reduces the power consumption of the FLL 152.

[0079] The above describes the configuration of the D-PLL circuit 100B. Next, its operation will be explained. Figure 11 is a diagram illustrating the operation of the mode selector 130B in the D-PLL circuit 100B.

[0080] The intermittently operating FLL150 switches on and off at a predetermined cycle. If a frequency error is detected during the on period, it transitions to sampling mode and operates to lock the frequency.

[0081] Figure 11 shows the power consumption of the D-PLL circuit 100B. The power consumption of the intermittently operating FLL 150 during its shutdown period is, for example, 262 μW. During the operation period of the intermittently operating FLL 150, the power consumption of the D-PLL circuit 100B jumps (for example, 762 μW), but when the duty cycle is 0.5%, the average power consumption P AVE This is 265 μW, and the increase can be limited to just 3 μW.

[0082] The above describes the operation of the D-PLL circuit 100B. The mode selector 130B can detect frequency jumps of integer multiples, and by operating in sampling mode in such cases, it is possible to prevent the system from continuing to phase-synchronize in an incorrect state as shown in Figure 7(ii). Furthermore, the mode selector 130B in Figure 10 is equipped with a dead zone detector 140 in addition to the intermittent operation FLL 150, so, similar to Example 1, it is also possible to prevent the system from falling into the state shown in Figure 7(iii).

[0083] Figure 12 shows the output frequency f of the D-PLL circuit 100B in Figure 8. OUTThis is a waveform diagram (simulation). Similar to Figure 7, waveforms (i) to (iii) are shown when frequency interferences of -1MHz, +6MHz, and +11MHz are injected. As shown in (i), when a frequency interference of -1MHz is introduced, the phase-locked state can be maintained.

[0084] As shown in (ii), if a frequency interference of +11 MHz is introduced, the intermittent operation FLL150 dead zone detector 140 detects the abnormal condition and switches to sampling mode, thereby restoring the correct phase-locked state. Note that in waveform (ii), the high frequency state persists for a while, which is a detection delay caused by the intermittent operation of the intermittent operation FLL150.

[0085] As shown in (iii), if a +6MHz frequency interference is introduced, the dead zone detector 140 can detect the abnormal condition and switch to sampling mode to return to the correct phase-locked state.

[0086] (Example 3) Figure 13 is a circuit diagram of the D-PLL circuit 100C according to Embodiment 3. The D-PLL circuit 100C has an additional coarse second PLL circuit 180. The second PLL circuit 180 is supplied with a clock CKG when the enable signal EN is high. The second PLL circuit 180 operates during the period when the enable signal EN is high, i.e., in subsampling mode, and feedback controls the frequency of DCO108 based on the output (UP / DN) of PFD182. In other words, the D-PLL circuit 100C in Figure 13 has a fine feedback loop including TDC104 and DLF106 and a coarse feedback loop including PFD182 and the second PLL180 operating in parallel. The PFD182 can be the same as the PFD142 built into the mode selector 130. In Example 3, the configuration of the mode selector 130 is not limited, and any configuration from Examples 1 and 2 or other configurations can be adopted.

[0087] According to Example 3, by adding a coarser second PLL 180, the phase pull-in speed can be increased in subsampling mode.

[0088] Next, we will explain a modified version of the D-PLL circuit 100.

[0089] (Variation 1) A circuit in which the dead zone detector 140 is omitted from the mode selector 130B in Figure 10 is also valid as one embodiment. In this case, errors that result in a lack of phase synchronization can be dealt with by other methods.

[0090] (Modification 2) While the embodiments described a fractional-N PLL, the present invention is not limited to integer-N PLLs. In this case, the DTC102 and controller 114 can be removed, and the MMD112 can be replaced with a simple divider.

[0091] (Variation 3) Furthermore, the present invention is applicable not only to D-PLL circuits but also to analog PLL circuits. In this case, the set of TDC104, DLF106, and DCO108 can be replaced with a phase-frequency comparator (PFD), a charge pump circuit, an analog loop filter, and a voltage-controlled oscillator (VCO).

[0092] (DCO) In the D-PLL circuit 100, or in other applications, the DCO is an important elemental technology. Figures 14(a) and (b) show the circuit diagram of a conventional DCO200R. The DCO200R is a CMOS oscillator comprising a pair of inverters 202 and 204 with cross-coupled inputs and outputs, a tank circuit 206 located between the outputs of the inverter pair 202 and 204, and a current source 208 that supplies bias current to the inverter pair 202 and 204. The tank circuit 206 is a parallel resonant circuit including an inductor L and a variable capacitor C. The resistance Rs is the series resistance component of the inductor L. The capacitance value of the variable capacitor C is digitally controllable, and the DCO200R oscillates at an oscillation frequency corresponding to the impedance of the tank circuit 206.

[0093] Figure 14(b) shows the equivalent circuit of the tank circuit 206. The equivalent parallel resistance R in this equivalent circuit TANK R TANK It is given by =ωL·Q. Q is the Q value of the LC resonant circuit in Figure 12, and is expressed as Q=ωL / Rs.

[0094] The amplitude V of the output of the DCO200R in Figure 14(a) AMP This is expressed by equation (1), and the equivalent parallel resistance R TANK and bias current I BIAS It is proportional to. V AMP ≈ 4 / π × R TANK ×I BIAS …(1)

[0095] To reduce the power consumption of the DCO200R, the bias current I BIAS It is necessary to reduce the output amplitude V. However, in order to make the DCO200R oscillate stably, the output amplitude V AMP Since it is necessary to make it somewhat large, the bias current I BIAS In exchange for a decrease in resistance R, TANK It is necessary to increase the value. However, when the tank circuit 206 is made into an MMIC (Monolithic Microwave Integrated Circuit) and integrated onto the same chip as the CMOS circuit, the resistor RTANK It is at most around 200 to 1000 ohms.

[0096] Therefore, the power consumption of the DCO200R in Figure 14(a) is limited by the impedance of the tank circuit. Below, we will describe a novel DCO that can further reduce power consumption.

[0097] Figure 15 is a circuit diagram showing the basic architecture of a DCO200 according to an embodiment. The DCO200 comprises an upper unit 210 and a lower unit 220. The upper unit 210 includes a pair of cross-coupled circuit elements 212, 214 and an inductor (primary winding) L1 with a tap T1. The inductor L1 is connected between the outputs (inputs) of the pair of circuit elements 212, 214. The tap T1 of the inductor L1 is connected to the power supply V DD It is directly connected to, or a bias current source is connected as described later.

[0098] In Figure 15, circuit elements 212 and 214 are NMOS transistors, and the sources of the NMOS transistors are connected to the reference node 216.

[0099] Similarly, the lower unit 220 includes a pair of cross-coupled circuit elements 222,224 and an inductor L2 (secondary winding) with a tap T2. The inductor L2 is connected between the outputs (between the inputs) of the pair of circuit elements 222,224.

[0100] Tap T2 of the lower unit 220 is connected to reference node 216 of the upper unit 210. This reference node 216 is connected to capacitor 242 and forms a virtual ground. This node is denoted as CEN.

[0101] Circuit elements 222 and 224 are also NMOS transistors, and the sources of the NMOS transistors are connected in common. The sources of NMOS transistors 222 and 224 are connected to reference node 226. Reference node 226 is connected to bias current source 240.

[0102] As shown in Figure 15, the upper unit 210 and the lower unit 220, when the cross-coupled circuit elements are NMOS transistors, is called an N-type unit.

[0103] The inductor L1 of the upper unit 210 and the inductor L2 of the lower unit 220 are coupled to form a transformer 230. Let k be the coupling coefficient between the winding Ls of inductor L1 and the winding Lp of inductor L2.

[0104] A variable capacitor Cv is connected to the upper unit 210. The variable capacitor Cv, together with the transformer 230, forms an LC tank circuit, and the DCO200 oscillates at a frequency corresponding to the capacitance value of the variable capacitor Cv. The output can be taken from anywhere, but for example, it may be taken from the drains of the NMOS transistors 222 and 224 of the lower unit 220.

[0105] The above describes the basic configuration of the DCO200. Next, we will explain its operation. Figure 16 is the equivalent circuit diagram of the DCO200 shown in Figure 15. N is the passive gain, and is expressed as N = k√(Ls / Lp) using the coupling coefficient k.

[0106] In Figure 16, the amplitude V of the output signal OUTP. AMP This is expressed by equation (2). V AMP ≈ 4 / π × I BIAS ×R TANKP ×G TF …(2) G TF This is the gain due to transformer 230, and is expressed by equation (3). G TF =k 2 ·Ls / Lp+k√(Ls / Lp)+R TANKS / R TANKP …(3) G TF For example, it can take a value of 2 or more, and in the circuit designed by the inventors, G TF The result was 4.35.

[0107] Figure 17 shows the bias current I BIAS and the amplitude V of the output signal AMP This is a diagram (simulation) showing the relationship. (i) shows the characteristics of the DCO200 in Figure 15, and (ii) shows the characteristics of the conventional DCO200R. When compared with the same bias current, the DCO200 in Figure 15 can increase the amplitude by 46% compared to the conventional one. In other words, the bias current required to obtain the same amplitude can be significantly reduced.

[0108] Next, we will explain a modified version of the DCO200.

[0109] Figure 18 is a circuit diagram of the DCO200A according to Modification 1. In this Modification 1, the lower unit 220 is of type N, similar to the lower unit 220 in Figure 15, but the upper unit 210 is replaced with a type P unit.

[0110] The P-type unit is an inverted configuration of the N-type unit, with the pair of circuit elements 212 and 214 replaced by PMOS transistors. Specifically, inductor L1 is connected between the drains of PMOS transistors 212 and 214, and the tap of inductor L1 is connected to the virtual ground line CEN. The sources of PMOS transistors 212 and 214 become the reference node 216, and the power supply voltage V DD It will be supplied.

[0111] Figure 19 is a circuit diagram of the DCO200B according to Modification 2. In this Modification 2, the upper unit 210 and the lower unit 220 are composed of CMOS type (push-pull type) units.

[0112] In a CMOS unit, the pair of cross-coupled circuit elements constitutes a CMOS inverter. Furthermore, the tap on the inductor L can be omitted.

[0113] Figures 20(a) to (f) are circuit diagrams showing further modifications of the DCO200. In Figures 20(a) to (f), N represents an N-type unit, P represents a P-type unit, and C represents a CMOS-type unit.

[0114] The combinations of the upper unit 210 and the lower unit 220 are not limited to those described above. Figure 20(a) shows the upper unit 210 being CMOS type and the lower unit 220 being NMOS type. Figure 20(b) shows both the upper unit 210 and the lower unit 220 being PMOS type. Figure 20(c) shows the upper unit 210 being NMOS type and the lower unit 220 being CMOS type. Figure 20(d) shows the upper unit 210 being PMOS type and the lower unit 220 being CMOS type.

[0115] As shown in Figure 20(e), the bias current source 240 may be omitted, or as shown in Figure 20(f), it may be provided on the power supply side.

[0116] The output signal of the DCO200 may be taken from either the upper unit 210 or the lower unit 220. Alternatively, the variable capacitor Cv may be connected to the lower unit 220.

[0117] (TDC) In the D-PLL circuit 100, or in other applications, the digital-to-time converter (DTC) is also an important elemental technology.

[0118] Figure 21 is a circuit diagram of the conventional DTC300R. This DTC300R is called a Single Slope DTC. The DTC300R includes a charging circuit 302, a capacitor 304, switches S1~S3, inverters 306, 308, and a DAC (Digital-to-Analog Converter) 310. The DTC300R applies a delay to the input signal IN according to the digital control code CODE and outputs it. The DAC 309 outputs an analog voltage V according to the control code CODE. DAC The inverter 306 outputs the voltage V of the capacitor 304. The charging circuit 302 charges the capacitor 304 when the first switch S1 is ON. P The threshold V TH (=V DDIt functions as a comparison means (comparison circuit) for comparison with (2). When the third switch S3 is ON, it discharges the capacitor 304 and the voltage V P Initialize it.

[0119] Figure 22 is an operating waveform diagram of the DTC300R shown in Figure 21. At time t0, the third switch S3 turns on and capacitor 304 discharges, and voltage V P It is initialized.

[0120] At time t1, the second switch S2 is turned on, and capacitor 304 controls the output voltage V of DAC309. DAC It is charged by this. This causes V P =V DAC This is the result.

[0121] At time t2, the first switch S1 turns on in response to the input signal IN. As a result, the current I in the charging circuit 302 C The capacitor 304 is charged by this, and the voltage V P It increases linearly.

[0122] At time t3, the voltage V P is threshold V TH When it reaches this point, the output OUT changes. The delay amount τ of the output OUT relative to the input IN is: τ=(V TH -V DAC ) × C / I C This is the result. C is the capacitance of capacitor 304.

[0123] The inventors, after examining the DTC300R shown in Figure 21, have come to recognize the following problems.

[0124] In other words, as can be seen from the time chart in Figure 22, only a portion of the current generated by the charging circuit 302 contributes to the delay, and the rest is wasted. The inventors' investigation revealed that as much as 58% of the power is consumed by the current source during periods T1 and T2.

[0125] In other words, there is room for further power consumption reduction in the DTC300R. The following describes the DTC with reduced power consumption.

[0126] Figure 23 is a circuit diagram of the DTC300 according to an embodiment. The DTC300 comprises a slope generation circuit 310, a precharge circuit 320, a comparison means (comparison circuit) 330, and a control circuit 340.

[0127] The slope generation circuit 310 includes a capacitor 312, a current source 314, and a first switch S1. The current source 314 supplies a constant current Ic to the capacitor 312, and supplies a slope voltage V that changes with a constant slope to the capacitor 312. P This generates the current. The first switch S1 is provided to cut off the constant current Ic. The first switch S1 may be incorporated inside the current source 314.

[0128] The pre-charge circuit 320 supplies an analog voltage V corresponding to the control code CODE to the capacitor 312. DAC The voltage is applied. The precharge circuit 320 includes a D / A converter 322 and a second switch S2. When the second switch S2 is on, the output voltage V of the D / A converter 322 is DAC When a current is applied to capacitor 312 and the second switch S2 is off, the D / A converter 322 is disconnected from capacitor 312. However, if the D / A converter 322 can take on a high impedance output state, the second switch S2 may be omitted, and the off state of the second switch S2 may be achieved by controlling the D / A converter 322.

[0129] The comparison means 330 measures the slope voltage V generated in the capacitor 312. P threshold V TH The system compares the results and generates an output signal OUT according to the comparison. The comparison means 330 may include two inverters 332 and 334 connected in cascade. The first-stage inverter 332 generates a slope voltage V Pis compared with the threshold value of the inverter 332 and converted into a binary signal according to the comparison result. The subsequent inverter 334 is provided to convert the logical value of the signal and / or provide a sufficiently low impedance to drive the load.

[0130] Preferably, the comparison means 330 is configured to be switchable between on and off, and for this purpose, a third switch S3 is provided. The third switch S3 is provided between the inverter 332 and the ground. The third switch S3 may be inserted on the power line side.

[0131] The control circuit 340 controls the slope generation circuit 310 and the precharge circuit 320 according to the input signal IN and the output signal OUT.

[0132] The control circuit 340 turns on the precharge circuit 320 during the precharge period. Specifically, it turns on the second switch S2. Thereby, the capacitor 312 is charged by the voltage V DAC The length of the precharge period may be determined in consideration of the time constant determined according to the output impedance of the D / A converter 322 and the capacitance C of the capacitor 312, that is, the time required for charging.

[0133] Also, the control circuit 340 turns off the comparison means 330 during the precharge period. Specifically, it turns off the third switch S3.

[0134] Also, the control circuit 340 transitions to the slope period in response to the input signal IN. The control circuit 340 turns off the precharge circuit 320 and turns on the slope generation circuit 310 during the slope period. Specifically, it turns off the second switch S2, turns on the first switch S1, and turns on the third switch S3.

[0135] During the slope period, when the slope generation circuit 310 is turned on, the slope voltage V P changes with a constant slope. And the slope voltage V P reaches the threshold value V THWhen it crosses, the output signal OUT transitions.

[0136] The control circuit 340 turns off the slope generation circuit 310 in response to the transition of the output signal OUT, and a constant current I C The signal is blocked. The control circuit 340 repeats this series of operations.

[0137] Figure 24 is a circuit diagram showing an example configuration of the control circuit 340. The control circuit 340 is composed of logic circuits. The control circuit 340 includes a first edge detection circuit 342, a second edge detection circuit 344, a first delay circuit 346, a second delay circuit 348, a first flip-flop FF1, a second flip-flop FF2, a first inverter INV1, and a second inverter INV2.

[0138] The first edge detection circuit 342 responds to the positive edge (also called the rising edge or leading edge) of the input signal IN and generates a first pulse signal Sp1 having a predetermined pulse width. The second edge detection circuit 344 responds to the positive edge of the output signal OUT and generates a second pulse signal Sp2 having a predetermined pulse width.

[0139] The first delay circuit 346 delays the first pulse signal Sp1 by a delay amount τ1 and supplies the delayed signal to the set terminal (S) of the first flip-flop FF1. This delay amount τ1 ensures that the third switch S3 is reliably turned on, and that the first switch S1 is turned on only after a state where voltage comparison is possible. The second pulse signal Sp2 is input to the reset terminal (R) of the first flip-flop FF1. The on / off state of the first switch S1 is controlled by the output Sig1 of the first flip-flop FF1.

[0140] The second delay circuit 348 delays the second pulse signal Sp2 by a delay amount τ2 and supplies it to the set terminal of the second flip-flop FF2. Capacitor voltage V P is threshold V THAfter reaching that point, there is a delay of two stages of the inverter 332 and the inverter 334 until the output OUT fully rises to high (VDD). Therefore, by introducing the delay amount τ2, after the output OUT fully rises to high (VDD), the third switch S3 can be turned off.

[0141] Also, the first pulse signal Sp1 is input to the reset terminal of the second flip - flop FF2. The second switch S2 and the third switch S3 are controlled based on the state of the second flip - flop FF2. Specifically, the inverted signal Sig3 of the output Q of the second flip - flop FF2 is supplied to the third switch S3, and the inverted signal Sig2 of the inverted output QB of the second flip - flop FF2 is supplied to the second switch S2.

[0142] The second flip - flop FF2 is reset at the timing of the negative edge of the first pulse signal Sp1. Therefore, the timing when the second switch S2 is turned on and the third switch S3 is turned off is defined by the pulse width of the first pulse signal Sp1.

[0143] The above is the configuration of the DTC300. Next, its operation will be described. FIG. 25 is a time chart for explaining the operation of the DTC300 in FIG. 23.

[0144] At time t0, the second switch S2 is turned on, and the capacitor 312 is charged by the DAC309. As a result, the voltage V of the capacitor P becomes the voltage value V corresponding to the control code DAC .

[0145] At time t1, when the input signal IN transitions to high, the first switch S1 is turned on, and the capacitor 312 is charged by the current I generated by the current source 314 C , and the voltage V of the capacitor 312 P increases with a constant slope. At this time, the third switch S3 is also turned on, and the inverter 306 becomes in a state where voltage comparison is possible.

[0146] At time t2, the voltage VP is threshold V TH When this value is reached, the output OUT transitions to high. In response, the control circuit 340 turns off the first switch S1. As a result, charging of the capacitor 312 stops. Consequently, the voltage V P The threshold voltage V TH It is maintained in the vicinity of the second switch. Then, at time t3, after a time corresponding to the delay amount of the second delay circuit 348 has elapsed, the second switch S2 turns on and the third switch S3 turns off. This completes one cycle of operation. Next, the advantages will be explained.

[0147] Figure 26 shows the operating waveform (i) of the DTC according to this embodiment and the operating waveform (ii) of a conventional DTC. In this embodiment, the voltage V of capacitor 312 is lower than in the conventional embodiment. P The fluctuations are kept to a minimum. In other words, the wasted supply of charge to capacitor 312 and the wasted discharge of charge from capacitor 312 are reduced, and power consumption can be reduced. In particular, in this embodiment, the first switch S1 is turned on only during the slope generation period. In other words, the current I generated by the current source 314 is turned on only during the slope generation period. C This will be used 100% for generating the slope, thus reducing power consumption.

[0148] Furthermore, the third switch S3 is placed on the path of the inverter 306 and is turned on only during the voltage comparison period. As a result, the output voltage V of the DAC309 DAC The threshold V of the inverter (comparator) 306 TH When the current is close to the specified value, it is possible to prevent through-current from flowing through the inverter 306, further reducing power consumption.

[0149] In Figure 23, the comparison means 330 may be configured as a voltage comparator. In this case, the switch S3 may be incorporated into the voltage comparator to interrupt the bias current of the voltage comparator.

[0150] Although the present invention has been described using specific terminology based on the embodiments, the embodiments merely illustrate the principles and applications of the present invention, and many modifications and changes in arrangement are permitted in the embodiments, as long as they do not depart from the spirit of the present invention as defined in the claims. [Industrial applicability]

[0151] This invention can be used in electronic circuits. [Explanation of symbols]

[0152] 100 D-PLL circuit 102 DTC 104 TDC 106DLF 108 DCO 110 buffers 112 MMD 113 Gate Circuits 114 Controllers 116 Retiming Circuit 120 Multiplexer 122 Delay Circuit 130 Mode Selector 132 State Machines 140 Dead Zone Detector 142 PFD 144 Judgment section 150 Intermittent Operation FLL 152 FLL 154 Duty Cycle Controller 160 frequency detector 162 Frequency divider 164 Flip-flops 166 counters 168 Flip-flops 170 Subtractors 172 Comparator 180 2nd PLL 200 DCO 210 Upper unit 220 Lower Unit 230 transformers 300 DTC 310 Slope generation circuit 312 Capacitors 314 Current Source S1 1st Switch 320 Precharge Circuit 322 D / A Converter S2 Second Switch 330 Means of comparison 332,334 inverters 340 Control circuits 342 First edge detection circuit 344 Second edge detection circuit 346 First Delay Circuit 348 Second Delay Circuit FF1 First Flip-Flop FF2 Second Flip-Flop INV1 First Inverter INV2 2nd Inverter

Claims

1. A digital-to-time converter that receives an input signal, applies a delay according to a control code, and generates an output signal, A current source and a capacitor connected in series between a power line and a ground line via a slope voltage node, and a first switch that controls the supply of current from the current source to the slope voltage node, the slope generating circuit which generates a slope voltage at the slope voltage node when the first switch is turned on, A pre-charge circuit including a second switch, which applies an analog voltage corresponding to a control code to the slope voltage node when the second switch is turned on, A comparison circuit that compares the slope voltage with a threshold and generates the output signal according to the comparison result, A control circuit that controls the first switch and the second switch in accordance with the input signal and the output signal, Equipped with, The control circuit is characterized by repeatedly performing the following operations: (i) turning off the first switch and turning on the second switch during the precharge period; (ii) transitioning to a slope period in response to the transition of the input signal, turning off the second switch and turning on the first switch during the slope period; and (iii) turning off the first switch in response to the transition of the output signal.

2. The digital-to-time converter according to claim 1, wherein the comparison circuit has a third switch that controls the connection between the comparison circuit and a ground wire or a power wire, and the control circuit turns off the third switch during the pre-charge period.

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