Isolators, isolation modules, and gate drivers

Abstract

This isolator includes an insulating layer and a capacitor embedded in the insulating layer. The capacitor includes a first electrode section, a second electrode section, and an intermediate electrode section. The first electrode section is provided within the insulating layer and is connected to a first pad formed on the surface of the insulating layer. The second electrode section is provided within the insulating layer and is connected to a second pad formed on the surface of the insulating layer. The intermediate electrode section is provided within the insulating layer and is connected to the first electrode section and the second electrode section. The intermediate electrode section includes a first intermediate layer and a second intermediate layer in positions differing from each other in the thickness direction of the insulating layer, and a connection section extending in the thickness direction of the insulating layer and connecting the first intermediate layer and the second intermediate layer. The capacitor is formed by joining the first electrode section and the second electrode section via the intermediate electrode section.

Description

Technical Field

[0001] The present disclosure relates to isolators, insulating modules, and gate drivers.

Background Art

[0002] As a gate driver for applying a gate voltage to the gate of a switching element such as a transistor, for example, an insulated gate driver is known. For example, Patent Document 1 describes a semiconductor integrated circuit as an insulated gate driver including a transformer having a primary-side first coil and a secondary-side second coil.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Here, the gate driver may include a low-voltage circuit configured to operate when a first voltage is applied, and a high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied. In this case, the transformer is used to insulate the low-voltage circuit and the high-voltage circuit. In such a gate driver, an improvement in the withstand voltage of insulation may be required. Note that the insulation structure between the low-voltage circuit and the high-voltage circuit is not limited to a transformer, and may be, for example, an insulation structure using a capacitor.

Means for Solving the Problems

[0005] An isolator that solves the above problems comprises an insulating layer and a capacitor embedded in the insulating layer. The capacitor includes a first electrode portion provided within the insulating layer and connected to a first pad formed on the surface of the insulating layer, a second electrode portion provided within the insulating layer and connected to a second pad formed on the surface of the insulating layer, and an intermediate electrode portion provided within the insulating layer and not connected to the first electrode portion and the second electrode portion. The intermediate electrode portion includes a first intermediate layer and a second intermediate layer whose positions in the thickness direction of the insulating layer are different from each other, and a connecting portion extending in the thickness direction of the insulating layer and connecting the first intermediate layer and the second intermediate layer. The capacitor is configured such that the first electrode portion and the second electrode portion are coupled via the intermediate electrode portion.

[0006] An isolation module that solves the above problem comprises the isolator, the isolator being connected between a low-voltage circuit chip and a high-voltage circuit chip included in a gate driver that drives a switching element, and the isolation module further comprises the low-voltage circuit chip.

[0007] An isolation module that solves the above problem comprises the isolator, which is used to isolate a low-voltage circuit chip and a high-voltage circuit chip included in a gate driver that drives a switching element, and the isolation module further comprises the high-voltage circuit chip.

[0008] A gate driver that solves the above problems is a gate driver that applies a drive voltage signal to the gate of a switching element, and comprises a low-voltage circuit chip including a low-voltage circuit configured to operate when a first voltage is applied, a high-voltage circuit chip including a high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied, and an isolator connected between the low-voltage circuit chip and the high-voltage circuit chip, wherein the isolator comprises an insulating layer, a first electrode portion provided in the insulating layer and connected to a first pad formed on the surface of the insulating layer, a second electrode portion provided in the insulating layer and connected to a second pad formed on the surface of the insulating layer, and an intermediate electrode portion provided in the insulating layer and not connected to the first electrode portion and the second electrode portion, wherein the intermediate electrode portion has a first intermediate layer and a second intermediate layer whose positions in the thickness direction of the insulating layer are different from each other, and a connecting portion extending in the thickness direction of the insulating layer and connecting the first intermediate layer and the second intermediate layer, and a capacitor is formed by coupling the first electrode portion and the second electrode portion via the intermediate electrode portion.

[0009] An insulating module that solves the above problems is an insulating module comprising an isolator having an insulating layer and a capacitor embedded in the insulating layer, wherein the isolator comprises an insulating layer, a first electrode portion provided in the insulating layer and connected to a first pad formed on the surface of the insulating layer, a second electrode portion provided in the insulating layer and connected to a second pad formed on the surface of the insulating layer, and an intermediate electrode portion provided in the insulating layer and not connected to the first electrode portion and the second electrode portion, wherein the intermediate electrode portion comprises a first intermediate layer and a second intermediate layer whose positions in the thickness direction of the insulating layer are different from each other, and a connecting portion extending in the thickness direction of the insulating layer and connecting the first intermediate layer and the second intermediate layer, and the capacitor is configured such that the first electrode portion and the second electrode portion are coupled via the intermediate electrode portion. [Effects of the Invention]

[0010] The above-described gate driver and isolation module make it possible to improve the dielectric strength. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a schematic circuit diagram of the gate driver of the first embodiment. [Figure 2] Figure 2 is a plan view showing the internal configuration of the gate driver of the first embodiment. [Figure 3] Figure 3 is a schematic plan view of the capacitor in the capacitor chip of the gate driver shown in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the capacitor chip shown in Figure 2. [Figure 5] Figure 5 is a schematic cross-sectional view of a comparative example capacitor chip. [Figure 6] Figure 6 is a schematic circuit diagram of the gate driver of the second embodiment. [Figure 7] Figure 7 is a plan view showing the internal configuration of the gate driver of the second embodiment. [Figure 8] Figure 8 is a schematic circuit diagram of the gate driver according to the third embodiment. [Figure 9] Figure 9 is a schematic cross-sectional view of the isolation module in the gate driver of the third embodiment. [Figure 10] Figure 10 is a schematic circuit diagram of the gate driver according to the fourth embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view of the isolation module in the gate driver of the fourth embodiment. [Figure 12] Figure 12 is a schematic circuit diagram of the gate driver according to the fifth embodiment. [Figure 13] Figure 13 is a schematic cross-sectional view of the isolation module in the gate driver of the fifth embodiment. [Figure 14] Figure 14 is a schematic cross-sectional view of the capacitor chip in the modified gate driver. [Figure 15] Figure 15 is a schematic cross-sectional view of the capacitor chip in the modified gate driver. [Figure 16]FIG. 16 is a schematic cross-sectional view of a part of the gate driver of the modified example. [Figure 17] FIG. 17 is a schematic cross-sectional view of a part of the gate driver of the modified example. [Figure 18] FIG. 18 is a schematic cross-sectional view of the capacitor chip of the modified example. [Figure 19] FIG. 19 is a schematic circuit diagram of the gate driver of the modified example. [Figure 20] FIG. 20 is a plan view showing the internal configuration of the gate driver of FIG. 19.

Mode for Carrying Out the Invention

[0012] Hereinafter, embodiments of the gate driver will be described with reference to the drawings. The embodiments shown below are examples of configurations and methods for embodying the technical idea, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are not limited to the following.

[0013] [First Embodiment] Referring to FIGS. 1 to 4, the gate driver 10 of the first embodiment will be described. FIG. 1 schematically shows an example of the circuit configuration of the gate driver 10.

[0014] As shown in Figure 1, the gate driver 10 applies a drive voltage signal to the gate of a switching element and is applied, for example, to an inverter device 500 installed in an electric vehicle or a hybrid vehicle. The inverter device 500 comprises a pair of switching elements 501 and 502 connected in series, the gate driver 10, and an ECU (Electronic Control Unit) 503 that controls the gate driver 10. Switching element 501 is, for example, a high-side switching element connected to a power supply, and switching element 502 is a low-side switching element. Examples of switching elements 501 and 502 include transistors such as SiMOSFET (Si Metal-Oxide-Semiconductor Field-Effect Transistor), SiCMOSFET, and IGBT (Insulated Gate Bipolar Transistor). In this embodiment, the gate driver 10 applies a drive voltage signal to the gate of switching element 501. In the following description, the case in which MOSFETs are used for switching elements 501 and 502 will be described.

[0015] A gate driver 10 is provided for each switching element 501 and 502, and drives the switching elements 501 and 502 individually. In this embodiment, for the sake of explanation, the gate driver 10 that drives the switching element 501 will be described.

[0016] The gate driver 10 includes a low-voltage circuit 20 configured to operate when a first voltage V1 is applied, a high-voltage circuit 30 configured to operate when a second voltage V2 higher than the first voltage V1 is applied, and a capacitor 40. The first voltage V1 and the second voltage V2 are DC voltages.

[0017] In this embodiment, the gate driver 10 is configured such that, based on a control signal from an external control unit (ECU) 503, a signal is transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 via the capacitor 40, and a drive voltage signal is output from the high-voltage circuit 30.

[0018] The signals transmitted from the low-voltage circuit 20 to the high-voltage circuit 30, that is, the signals output from the low-voltage circuit 20, are, for example, signals for driving the switching element 501, and examples include the set signal and the reset signal. The set signal is a signal that transmits the rising edge of the control signal from the ECU 503, and the reset signal is a signal that transmits the falling edge of the control signal from the ECU 503. The set signal and the reset signal can also be said to be signals for generating the drive voltage signal for the switching element 501. For this reason, the set signal and the reset signal correspond to the first signal.

[0019] The low-voltage circuit 20 is electrically connected to the ECU 503 and generates set signals and reset signals based on control signals input from the ECU 503. For example, the low-voltage circuit 20 generates a set signal in response to the rising edge of the control signal, and a reset signal in response to the falling edge of the control signal. The low-voltage circuit 20 then transmits the generated set signals and reset signals to the high-voltage circuit 30.

[0020] The high-voltage circuit 30 is electrically connected to the gate of the switching element 501. Based on the set signal and reset signal received from the low-voltage circuit 20, it generates a drive voltage signal to drive the switching element 501 and applies this drive voltage signal to the gate of the switching element 501. In other words, the high-voltage circuit 30 also generates a drive voltage signal to apply to the gate of the switching element 501 based on the first signal output from the low-voltage circuit 20. More specifically, the high-voltage circuit 30 generates a drive voltage signal to turn on the switching element 501 based on the set signal and applies it to the gate of the switching element 501. On the other hand, the high-voltage circuit 30 generates a drive voltage signal to turn off the switching element 501 based on the reset signal and applies this drive voltage signal to the gate of the switching element 501. In this way, the on / off state of the switching element 501 is controlled by the gate driver 10.

[0021] The high-voltage circuit 30 includes, for example, an RS-type flip-flop circuit to which a set signal and a reset signal are input, and a driver unit that generates a drive voltage signal based on the output signal of the RS-type flip-flop circuit. However, the specific circuit configuration of the high-voltage circuit 30 is arbitrary.

[0022] Capacitor 40 is located between the low-voltage circuit 20 and the high-voltage circuit 30. That is, the low-voltage circuit 20 and the high-voltage circuit 30 are electrically connected via capacitor 40. In the gate driver 10 of this embodiment, the low-voltage circuit 20 and the high-voltage circuit 30 are isolated by capacitor 40. More specifically, the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30 is restricted by capacitor 40, while the transmission of various signals such as set signals and reset signals is possible.

[0023] In other words, the state in which the low-voltage circuit 20 and the high-voltage circuit 30 are isolated means that the transmission of DC voltage between the low-voltage circuit 20 and the high-voltage circuit 30 is blocked, while the transmission of signals between the low-voltage circuit 20 and the high-voltage circuit 30 is permitted.

[0024] The dielectric strength of the gate driver 10 is, for example, 2500 Vrms or more and 7500 Vrms or less. In this embodiment, the dielectric strength of the gate driver 10 is approximately 3750 Vrms. However, the specific value of the dielectric strength of the gate driver 10 is not limited to this and is arbitrary.

[0025] In this embodiment, the dielectric strength of the capacitor 40 is, for example, 2500 Vrms or more and 7500 Vrms or less. However, the dielectric strength of the capacitor 40 may be 2500 Vrms or more and 5700 Vrms or less. However, it is not limited to this, and the dielectric strength of the capacitor 40 is arbitrary.

[0026] In this embodiment, the ground of the low-voltage circuit 20 and the ground of the high-voltage circuit 30 are provided independently. Hereinafter, the ground potential of the low-voltage circuit 20 will be referred to as the first reference potential, and the ground potential of the high-voltage circuit 30 will be referred to as the second reference potential. In this case, the first voltage V1 is the voltage from the first reference potential, and the second voltage V2 is the voltage from the second reference potential. The first voltage V1 is, for example, 4.5V or more and 5.5V or less, and the second voltage V2 is, for example, 9V or more and 24V or less.

[0027] The following provides a detailed explanation of capacitor 40. The gate driver 10 of this embodiment is equipped with two capacitors 40 to correspond to the transmission of two types of signals from the low-voltage circuit 20 to the high-voltage circuit 30. Specifically, the gate driver 10 is equipped with a capacitor 40 used for transmitting a set signal and a capacitor 40 used for transmitting a reset signal. For the sake of explanation, the capacitor 40 used for transmitting the set signal will be referred to as capacitor 40A, and the capacitor 40 used for transmitting the reset signal will be referred to as capacitor 40B.

[0028] The gate driver 10 includes a low-voltage signal line 21A connecting the low-voltage circuit 20 and the capacitor 40A, and a low-voltage signal line 21B connecting the low-voltage circuit 20 and the capacitor 40B. Therefore, the low-voltage signal line 21A transmits a set signal from the low-voltage circuit 20 to the capacitor 40A. The low-voltage signal line 21B transmits a reset signal from the low-voltage circuit 20 to the capacitor 40B.

[0029] The gate driver 10 includes a high-voltage signal line 31A connecting capacitor 40A to high-voltage circuit 30, and a high-voltage signal line 31B connecting capacitor 40B to high-voltage circuit 30. Therefore, high-voltage signal line 31A transmits a set signal from capacitor 40A to high-voltage circuit 30. High-voltage signal line 31B transmits a reset signal from capacitor 40B to high-voltage circuit 30.

[0030] Capacitor 40A has a first electrode 41A and a second electrode 42A. The first electrode 41A is electrically connected to the low-voltage circuit 20, and the second electrode 42A is electrically connected to the high-voltage circuit 30.

[0031] Capacitor 40B has a first electrode 41B and a second electrode 42B. The first electrode 41B is electrically connected to the low-voltage circuit 20, and the second electrode 42B is electrically connected to the high-voltage circuit 30.

[0032] The structure of the gate driver 10 will be explained below using Figure 2. Figure 2 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Figure 1 shows a simplified circuit configuration of the gate driver 10, so the number of external terminals of the gate driver 10 in Figure 2 is greater than the number of external terminals of the gate driver 10 in Figure 1. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 1). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 of Figure 2 is greater than the number of signal lines of the gate driver 10 in Figure 1.

[0033] As shown in Figure 2, the gate driver 10 is a semiconductor device in which multiple semiconductor chips are packaged together, and is mounted on a circuit board provided in, for example, an inverter device 500. Note that each switching element 501, 502 is mounted on a separate mounting board from the circuit board. A cooler is attached to this mounting board.

[0034] The gate driver 10 is packaged in an SO-type package, and in this embodiment, it is packaged in an SOP. The gate driver 10 comprises a low-voltage circuit chip 60, a high-voltage circuit chip 70, and a capacitor chip 80 as semiconductor chips, a low-voltage lead frame 90 on which the low-voltage circuit chip 60 is mounted, a high-voltage lead frame 100 on which the high-voltage circuit chip 70 is mounted, and a sealing resin 110 that seals parts of each lead frame 90, 100 and each chip 60, 70, 80. In this embodiment, the capacitor chip 80 corresponds to an "isolator". The capacitor chip 80 and the sealing resin 110 correspond to an "insulation module" that insulates the low-voltage circuit 20 and the high-voltage circuit 30. Also, in Figure 2, the sealing resin 110 is shown with a dashed line for the purpose of explaining the internal structure of the gate driver 10. Furthermore, the package type of the gate driver 10 can be arbitrarily changed.

[0035] The sealing resin 110 is made of an electrically insulating material, for example, a black epoxy resin. The sealing resin 110 is formed in the shape of a rectangular plate with the z direction as the thickness direction. The sealing resin 110 has four resin sides 111 to 114. In detail, the sealing resin 110 has resin sides 111 and 112 as end faces in the x direction, and resin sides 113 and 114 as end faces in the y direction. The x and y directions are perpendicular to the z direction. The x and y directions are orthogonal to each other. In the following description, "plan view" means viewing from the z direction.

[0036] The low-voltage lead frame 90 and the high-voltage lead frame 100 are each made of a conductor, which in this embodiment is made of Cu (copper). Each lead frame 90, 100 is provided spanning both the inside and outside of the sealing resin 110.

[0037] The low-voltage lead frame 90 includes a low-voltage die pad 91 located within the sealing resin 110, and a plurality of low-voltage leads 92 arranged to span both the inside and outside of the sealing resin 110. Each low-voltage lead 92 constitutes an external terminal that electrically connects to an external electronic device such as an ECU 503 (see Figure 1).

[0038] The low-voltage die pad 91 is mounted on a low-voltage circuit chip 60 and a capacitor chip 80. In a plan view, the low-voltage die pad 91 is positioned such that its center in the y-direction is closer to the resin side surface 113 than the center of the sealing resin 110 in the y-direction. In this embodiment, the low-voltage die pad 91 is not exposed from the sealing resin 110. In a plan view, the shape of the low-voltage die pad 91 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0039] Multiple low-pressure leads 92 are arranged spaced apart from each other in the x-direction. Each of the low-pressure leads 92 located at both ends in the x-direction is integrated with the low-pressure die pad 91. A portion of each low-pressure lead 92 protrudes outward from the resin side surface 113 toward the sealing resin 110.

[0040] The high-voltage lead frame 100 includes a high-voltage die pad 101 located within the sealing resin 110, and a plurality of high-voltage leads 102 arranged to span both the inside and outside of the sealing resin 110. Each high-voltage lead 102 constitutes an external terminal that electrically connects to external electronic equipment such as the gate of a switching element 501 (see Figure 1).

[0041] A high-voltage circuit chip 70 is mounted on the high-voltage die pad 101. In a plan view, the high-voltage die pad 101 is positioned closer to the resin side surface 114 than the low-voltage die pad 91 in the y-direction. In this embodiment, the high-voltage die pad 101 is not exposed from the sealing resin 110. In a plan view, the shape of the high-voltage die pad 101 is rectangular, with the x-direction being the longer side and the y-direction being the shorter side.

[0042] The low-pressure die pad 91 and the high-pressure die pad 101 are spaced apart in the y-direction. Therefore, the y-direction can also be described as the direction in which the two die pads 91 and 101 are aligned. The y-direction dimensions of the low-voltage die pad 91 and the high-voltage die pad 101 are determined by the size and number of semiconductor chips to be mounted. In this embodiment, the low-voltage die pad 91 is mounted with a low-voltage circuit chip 60 and a capacitor chip 80, and the high-voltage die pad 101 is mounted with a high-voltage circuit chip 70. Therefore, the y-direction dimension of the low-voltage die pad 91 is larger than that of the high-voltage die pad 101.

[0043] Multiple high-voltage leads 102 are arranged spaced apart from each other in the x-direction. One pair of the multiple high-voltage leads 102 is integrated with the high-voltage die pad 101. A portion of each high-voltage lead 102 protrudes outward from the resin side surface 114 toward the sealing resin 110.

[0044] In this embodiment, the number of high-voltage leads 102 is the same as the number of low-voltage leads 92. As can be seen from Figure 2, the multiple low-voltage leads 92 and the multiple high-voltage leads 102 are arranged in a direction (x direction) perpendicular to the arrangement direction (y direction) of the low-voltage die pads 91 and high-voltage die pads 101. Note that the number of high-voltage leads 102 and the number of low-voltage leads 92 can be changed as needed.

[0045] In this embodiment, the low-voltage die pad 91 is supported by a pair of low-voltage leads 92 integrated with the low-voltage die pad 91, and the high-voltage die pad 101 is supported by a pair of high-voltage leads 102 integrated with the high-voltage die pad 101. Therefore, each die pad 91, 101 is not provided with suspension leads exposed on the resin sides 111, 112. As a result, a large insulation distance can be achieved between the low-voltage lead frame 90 and the high-voltage lead frame 100.

[0046] The low-voltage circuit chip 60, the high-voltage circuit chip 70, and the capacitor chip 80 are arranged spaced apart from each other in the y-direction. In other words, in a plan view, the low-voltage circuit chip 60, the high-voltage circuit chip 70, and the capacitor chip 80 are also arranged spaced apart from each other in the direction of arrangement of both die pads 91 and 101. In this embodiment, the low-voltage circuit chip 60, the capacitor chip 80, and the high-voltage circuit chip 70 are arranged in the y-direction from the resin side surface 113 toward the resin side surface 114.

[0047] Furthermore, considering that each lead 92,102 is arranged in the x-direction, the x-direction can also be said to be the arrangement direction of each lead 92,102, and the y-direction can be said to be perpendicular to the arrangement direction of each lead 92,102 in a plan view. For this reason, the low-voltage circuit chip 60, the high-voltage circuit chip 70, and the capacitor chip 80 can be said to be spaced apart from each other in a direction perpendicular to the arrangement direction of each lead 92,102 in a plan view. And, in a plan view, it can be said that the low-voltage circuit chip 60, the capacitor chip 80, and the high-voltage circuit chip 70 are arranged in the order of low-voltage lead 92 to high-voltage lead 102.

[0048] The low-voltage circuit chip 60 includes the low-voltage circuit 20 shown in Figure 1. In plan view, the low-voltage circuit chip 60 has a rectangular shape with a short side and a long side. In plan view, the low-voltage circuit chip 60 is mounted on the low-voltage die pad 91 such that the long side is along the x-direction and the short side is along the y-direction. The low-voltage circuit chip 60 has a main chip surface 60s and a chip back surface (not shown) that face opposite each other in the z-direction. The chip back surface of the low-voltage circuit chip 60 is bonded to the low-voltage die pad 91 by a conductive bonding material such as solder or Ag (silver) paste.

[0049] Multiple first electrode pads 61, multiple second electrode pads 62, and multiple third electrode pads 63 are formed on the main surface 60s of the low-voltage circuit chip 60. Each electrode pad 61 to 63 is electrically connected to the low-voltage circuit 20 shown in Figure 1.

[0050] Multiple first electrode pads 61 are positioned closer to the low-voltage leads 92 than to the center of the chip main surface 60s in the y-direction. Multiple first electrode pads 61 are arranged in the x-direction. Multiple second electrode pads 62 are positioned at the ends of the chip main surface 60s in the y-direction that are closer to the capacitor chip 80. Multiple second electrode pads 62 are arranged in the x-direction. Multiple third electrode pads 63 are positioned at both ends of the chip main surface 60s in the x-direction.

[0051] The capacitor chip 80 includes both capacitors 40A and 40B, and more specifically, both capacitors 40A and 40B are integrated into a single chip. In this embodiment, as shown in Figure 2, the capacitor chip 80 includes two capacitors 40A and two capacitors 40B. In other words, the capacitor chip 80 shown in Figure 2 has four transmission paths for transmitting signals, unlike the circuit diagram in Figure 1, with respect to the low-voltage circuit 20 and the high-voltage circuit 30 (both seen in Figure 1). Note that the capacitor chip 80 may also have two capacitors 40A and 40B, as shown in the circuit diagram in Figure 1.

[0052] In plan view, the capacitor chip 80 has a rectangular shape with a short side and a long side. In this embodiment, in plan view, the capacitor chip 80 is mounted on the low-voltage die pad 91 such that its long side is along the x-direction and its short side is along the y-direction. The two capacitors 40A and the two capacitors 40B are spaced apart from each other in the direction of the long side of the capacitor chip 80 (the x-direction in this embodiment). In plan view, the two capacitors 40A and the two capacitors 40B are also arranged in a direction perpendicular to the direction in which each of the chips 60, 70, and 80 are arranged.

[0053] For convenience, it is assumed that capacitors 40A and 40B are arranged alternately in the x-direction. More specifically, capacitor 40A is defined as the capacitor closest to the resin side surface 113 of the sealing resin 110, and capacitors 40A and 40B are arranged alternately in the x-direction.

[0054] The capacitor chip 80 is positioned adjacent to the low-voltage circuit chip 60 in the y-direction. In this embodiment, the capacitor chip 80 is positioned closer to the high-voltage circuit chip 70 than to the low-voltage circuit chip 60.

[0055] As shown in Figure 4, the capacitor chip 80 has a main chip surface 80s and a back chip surface 80r that face opposite each other in the z direction. The main chip surface 80s faces the same side as the main chip surface 60s of the low-voltage circuit chip 60 (see Figure 2), and the back chip surface 80r faces the same side as the back chip surface of the low-voltage circuit chip 60. The back chip surface 80r of the capacitor chip 80 is bonded to the low-voltage die pad 91 by a conductive bonding material SD.

[0056] As shown in Figure 2, the main surface 80s of the capacitor chip 80 has a plurality of first electrode pads 81 and a plurality of second electrode pads 82 formed thereon. The plurality of first electrode pads 81 are located, for example, at the end of the main surface 80s in the y-direction that is closer to the low-voltage circuit chip 60. The plurality of first electrode pads 81 are arranged in the x-direction. The plurality of second electrode pads 82 are located at the end of the main surface 80s in the y-direction that is closer to the high-voltage circuit chip 70. The plurality of second electrode pads 82 are arranged in the x-direction.

[0057] In order to set the dielectric strength of the gate driver 10 to a predetermined dielectric strength, it is necessary to separate the low-voltage die pad 91 and the high-voltage die pad 101, where each lead frame 90, 100 is closest, by a predetermined distance or more. For this reason, in a plan view, the distance between the high-voltage circuit chip 70 and the capacitor chip 80 is greater than the distance between the low-voltage circuit chip 60 and the capacitor chip 80.

[0058] The first electrode 41A of capacitor 40A and the first electrode 41B of capacitor 40B are individually electrically connected to a plurality of first electrode pads 81. The second electrode 42A of capacitor 40A and the second electrode 42B of capacitor 40B are individually electrically connected to a plurality of second electrode pads 82.

[0059] As shown in Figure 2, the high-voltage circuit chip 70 includes a high-voltage circuit 30 (see Figure 1). In plan view, the high-voltage circuit chip 70 has a rectangular shape with a short side and a long side. In plan view, the high-voltage circuit chip 70 is mounted on the high-voltage die pad 101 such that the long side is along the x-direction and the short side is along the y-direction. The high-voltage circuit chip 70 has a main chip surface 70s and a back surface (not shown) that face opposite each other in the z-direction. The main chip surface 70s faces the same side as the main chip surface 80s of the capacitor chip 80, and the back surface of the high-voltage circuit chip 70 faces the same side as the back surface 80r (see Figure 4) of the capacitor chip 80. The back surface of the high-voltage circuit chip 70 is bonded to the high-voltage die pad 101 by a conductive bonding material.

[0060] As shown in Figure 2, the main surface 70s of the high-voltage circuit chip 70 has a plurality of first electrode pads 71, a plurality of second electrode pads 72, and a plurality of third electrode pads 73 formed thereon. The plurality of first electrode pads 71 ​​are located at the end of the main surface 70s in the y-direction that is closer to the capacitor chip 80. The plurality of first electrode pads 71 ​​are arranged in the x-direction. The plurality of second electrode pads 72 are located at the end of the main surface 70s in the y-direction that is further away from the capacitor chip 80. The plurality of second electrode pads 72 are arranged in the x-direction. The plurality of third electrode pads 73 are located at both ends of the main surface 70s in the x-direction. Each electrode pad 71 to 73 is electrically connected to the high-voltage circuit 30 (see Figure 1) within the high-voltage circuit chip 70.

[0061] Multiple wires W are connected to each of the low-voltage circuit chip 60, capacitor chip 80, and high-voltage circuit chip 70. Each wire W is a bonding wire formed by a wire bonding apparatus and consists of a conductor such as Au (gold), Al (aluminum), or Cu.

[0062] The low-voltage circuit chip 60 is electrically connected to the low-voltage lead frame 90 by wire W. More specifically, the multiple first electrode pads 61 and multiple low-voltage leads 92 of the low-voltage circuit chip 60 are connected by wire W. The multiple third electrode pads 63 of the low-voltage circuit chip 60 and a pair of low-voltage leads 92 integrated with the low-voltage die pad 91 are connected by wire W. As a result, the low-voltage circuit 20 (see Figure 1) and the multiple low-voltage leads 92 (external electrodes of the gate driver 10 that are electrically connected to the ECU 503) are electrically connected. In this embodiment, the pair of low-voltage leads 92 integrated with the low-voltage die pad 91 constitute the ground terminal, and the low-voltage circuit 20 and the low-voltage die pad 91 are electrically connected by wire W, so the low-voltage die pad 91 is at the same potential as the ground of the low-voltage circuit 20.

[0063] The low-voltage circuit chip 60 and the capacitor chip 80 are electrically connected by wire W. More specifically, the multiple second electrode pads 62 of the low-voltage circuit chip 60 and the multiple first electrode pads 81 of the capacitor chip 80 are connected by wire W. This electrically connects the low-voltage circuit 20 to the first electrodes 41A and 41B of the capacitors 40A and 40B (see Figure 1).

[0064] The capacitor chip 80 and the high-voltage circuit chip 70 are electrically connected by wire W. More specifically, the multiple second electrode pads 82 of the capacitor chip 80 and the multiple first electrode pads 71 ​​of the high-voltage circuit chip 70 are connected by wire W. As a result, the second electrode 42A of capacitor 40A and the high-voltage circuit 30 (see Figure 1 for both) are electrically connected, and the second electrode 42B of capacitor 40B and the high-voltage circuit 30 (see Figure 1 for both) are electrically connected.

[0065] Each of the high-voltage circuit chip 70 and the multiple high-voltage leads 102 of the high-voltage lead frame 100 are electrically connected by wire W. More specifically, the multiple second electrode pads 72 and multiple third electrode pads 73 of the high-voltage circuit chip 70 are connected to the multiple high-voltage leads 102 by wire W. As a result, the high-voltage circuit 30 and the multiple high-voltage leads 102 (external electrodes of the gate driver 10 that are electrically connected to the inverter device 500, such as the switching element 501) are electrically connected. In this embodiment, a pair of high-voltage leads 102 integrated with the high-voltage die pad 101 constitute the ground terminal, and the high-voltage circuit 30 and the high-voltage die pad 101 are electrically connected by wire W, so that the high-voltage die pad 101 is at the same potential as the ground of the high-voltage circuit 30.

[0066] (Capacitor chip configuration) Next, the detailed configuration of the capacitor chip 80 will be described with reference to Figures 3 and 4. Note that capacitor 40B has the same configuration as capacitor 40A, so its description will be omitted. In the following description, the direction from the back surface 80r of the capacitor chip 80 toward the main surface 80s will be considered upward, and the direction from the main surface 80s toward the back surface 80r will be considered downward. Figure 3 is a schematic plan view showing the positional relationship of capacitors 40A and 40B within the capacitor chip 80. Figure 4 is a cross-sectional view of capacitor 40A cut by planes along the y and z directions. In Figure 4, some of the hatching has been omitted for the sake of readability.

[0067] As described above, the capacitor chip 80 includes both capacitors 40A and 40B, or more specifically, both capacitors 40A and 40B are integrated into a single chip. In other words, the capacitor chip 80 is a semiconductor chip dedicated to both capacitors 40A and 40B, separate from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (both seen in Figure 2).

[0068] As shown in Figure 4, the capacitor chip 80 has a substrate 84 and an insulating layer 85 formed on the substrate 84. The substrate 84 is made of, for example, a semiconductor substrate, and in this embodiment, a substrate formed from a material containing Si (silicon). The substrate 84 may be a wide-bandgap semiconductor or a compound semiconductor. Alternatively, instead of a semiconductor substrate, the substrate 84 may be an insulating substrate formed from a material containing glass.

[0069] A wide-bandgap semiconductor is a semiconductor substrate having a bandgap of 2.0 eV or greater. The wide-bandgap semiconductor may be SiC (silicon carbide). The compound semiconductor may be a III-V compound semiconductor. The compound semiconductor may contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0070] The substrate 84 has a main substrate surface 84s and a substrate back surface 84r that face opposite each other in the z direction. The substrate back surface 84r constitutes the chip back surface 80r of the capacitor chip 80.

[0071] In this embodiment, multiple insulating layers 85 are laminated on the main surface 84s of the substrate 84 in the z direction. In other words, the z direction can also be said to be the thickness direction of the insulating layers 85. The insulating layers 85 are formed on the main surface 84s of the substrate 84. In this embodiment, the total thickness of the multiple insulating layers 85 is greater than the thickness of the substrate 84. However, the number of layers of insulating layers 85 is set according to the required dielectric strength of the capacitor chip 80. Therefore, depending on the number of layers of insulating layers 85, the total thickness of the insulating layers 85 may be less than the thickness of the substrate 84.

[0072] The insulating layer 85 has a first insulating film 85A and a second insulating film 85B formed on the first insulating film 85A. The first insulating film 85A is, for example, an etching stopper film and is formed from a material containing SiN (silicon nitride), SiC, SiCN (nitrogen-doped silicon carbide), etc. In this embodiment, the first insulating film 85A is formed from a material containing SiN. The second insulating film 85B is, for example, an interlayer insulating film and is an oxide film formed from a material containing SiO2 (silicon oxide). As shown in Figure 4, the thickness of the second insulating film 85B is greater than the thickness of the first insulating film 85A. The thickness of the first insulating film 85A may be 100 nm or more and less than 1000 nm. The thickness of the second insulating film 85B may be 1000 nm or more and 3000 nm or less. In this embodiment, the thickness of the first insulating film 85A is, for example, about 300 nm, and the thickness of the second insulating film 85B is, for example, about 2000 nm.

[0073] The surface 85s of the insulating layer 85 is provided with a first electrode pad 81 and a second electrode pad 82. In this embodiment, the surface 85s of the insulating layer 85 is the surface of the uppermost insulating layer 85 among a plurality of insulating layers 85 stacked in the z direction. The first electrode pad 81 and the second electrode pad 82 are each formed of a material containing, for example, Al.

[0074] The capacitor chip 80 further comprises a protective film 86 formed on the surface 85s of the insulating layer 85, and a passivation film 87 formed on the protective film 86. The protective film 86 is a film that protects the insulating layer 85 and is made of, for example, a silicon oxide film. The passivation film 87 is a surface protective film of the capacitor chip 80 and is made of, for example, a silicon nitride film. The passivation film 87 constitutes the main chip surface 80s of the capacitor chip 80.

[0075] The first electrode pad 81 and the second electrode pad 82 are covered by a protective film 86 and a passivation film 87. On the other hand, the protective film 86 and the passivation film 87 have openings that expose the first electrode pad 81 and the second electrode pad 82. As a result, each electrode pad 81, 82 has an exposed surface for connecting the wire W.

[0076] Capacitor 40A includes a first electrode portion 51 electrically connected to a first electrode pad 81, a second electrode portion 52 electrically connected to a second electrode pad 82, and intermediate electrode portions 53 and 54 that are not connected to the first electrode portion 51 and the second electrode portion 52. Capacitor 40A has a plurality of capacitor cells 55 composed of each electrode portion 51, 52 and each intermediate electrode portion 53, 54. Capacitor 40A is constructed by the coupling of the first electrode portion 51 and the second electrode portion 52 via each intermediate electrode portion 53 and 54. It can also be said that each intermediate electrode portion 53 and 54 is in an electrically floating state and is not fixed to the potential applied to the first electrode portion 51 and the second electrode portion 52.

[0077] Here, the first electrode portion 51 constitutes the first electrode 41A of the capacitor 40A (see Figure 1), and the second electrode portion 52 constitutes the second electrode 42A of the capacitor 40A (see Figure 1). In this embodiment, it can be said that there are multiple intermediate electrode portions in the capacitor 40A. Furthermore, in the following description, the intermediate electrode portion 53 will be referred to as the "first intermediate electrode portion 53," and the intermediate electrode portion 54 will be referred to as the "second intermediate electrode portion 54."

[0078] The first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 are formed from, for example, the same metallic material. The metallic material constituting the first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 includes one of Cu, Al, Ti (titanium), or W (tungsten). In this embodiment, the metallic material constituting the first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 is formed from a material containing Cu.

[0079] The first electrode portion 51, the second electrode portion 52, and each of the intermediate electrode portions 53, 54 are each provided within the insulating layer 85. The first electrode portion 51, the second electrode portion 52, and each of the intermediate electrode portions 53, 54 have portions that are positioned at different locations in the z-direction.

[0080] The first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 are each positioned at mutually offset locations in the z-direction within the insulating layer 85. In other words, the first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 each have portions that are positioned at mutually different locations in the z-direction within the insulating layer 85.

[0081] The first electrode portion 51 is positioned closer to the substrate 84 in the z-direction than the second electrode portion 52 and the intermediate electrode portions 53 and 54. On the other hand, the first electrode portion 51 is positioned further away from the substrate 84 in the z-direction. In other words, an insulating layer 85 is interposed between the first electrode portion 51 and the substrate 84 in the z-direction.

[0082] The second electrode portion 52 is positioned further from the substrate 84 in the z-direction than the first electrode portion 51 and each of the intermediate electrode portions 53, 54. On the other hand, the second electrode portion 52 is positioned closer to the substrate 84 in the z-direction than the surface 85s of the insulating layer 85. In this embodiment, the second electrode portion 52 is provided on the insulating layer 85 one layer below the uppermost insulating layer 85 among the multiple insulating layers 85.

[0083] In this embodiment, each intermediate electrode portion 53, 54 is positioned between the first electrode portion 51 and the second electrode portion 52 in the z direction. The first intermediate electrode portion 53 is positioned between the first electrode portion 51 and the second intermediate electrode portion 54 in the z direction. The second intermediate electrode portion 54 is positioned between the first intermediate electrode portion 53 and the second electrode portion 52 in the z direction.

[0084] As shown in Figure 3, in this embodiment, the shape of the first electrode portion 51 as viewed from the z direction is rectangular, with the long side (x direction) of the capacitor chip 80 being the long side and the short side (y direction) of the capacitor chip 80 being the short side. In a plan view, the first electrode portion 51 is positioned, for example, in the center of the capacitor chip 80 in the y direction. As shown in Figure 4, in this embodiment, the thickness of the first electrode portion 51 (the z-direction dimension of the first electrode portion 51) is equal to the thickness of the insulating layer 85 (the z-direction dimension of the insulating layer 85). Here, the thickness of the insulating layer 85 is the sum of the thickness of the first insulating film 85A (the z-direction dimension of the first insulating film 85A) and the thickness of the second insulating film 85B (the z-direction dimension of the second insulating film 85B). Furthermore, if the difference between the thickness of the first electrode portion 51 and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the first electrode portion 51, then the thickness of the first electrode portion 51 and the thickness of the insulating layer 85 can be said to be equal.

[0085] As shown in Figure 4, the first electrode portion 51 is electrically connected to the first electrode pad 81 by a first connecting wire 121. The first connecting wire 121 is a wire that connects the first electrode portion 51 and the first electrode pad 81 and is provided within a plurality of insulating layers 85. In other words, the first electrode portion 51 and the first electrode pad 81 are electrically connected within the capacitor chip 80. It can also be said that the first electrode portion 51 and the first electrode pad 81 are electrically connected within the plurality of insulating layers 85.

[0086] The first intermediate electrode section 53 is positioned opposite the first electrode section 51 in the z-direction. The first intermediate electrode section 53 has a first upper electrode layer 53A and a first lower electrode layer 53B which are at different positions in the z-direction, and a first connecting section 53C which connects the first upper electrode layer 53A and the first lower electrode layer 53B. In this embodiment, the first upper electrode layer 53A corresponds to the "first intermediate layer of the first intermediate electrode section," and the first lower electrode layer 53B corresponds to the "second intermediate layer of the first intermediate electrode section."

[0087] The first upper electrode layer 53A is positioned opposite the first electrode portion 51 in the z direction. An insulating layer 85 is interposed between the first upper electrode layer 53A and the first electrode portion 51. In this embodiment, the first upper electrode layer 53A is positioned relative to the first electrode portion 51 via three insulating layers 85. The first upper electrode layer 53A and the first electrode portion 51 constitute the first capacitor cell 55A among the plurality of capacitor cells 55.

[0088] As shown in Figure 3, the shape of the first upper electrode layer 53A as viewed from the z direction is rectangular, with the longer side being the x-direction of the capacitor chip 80 and the shorter side being the y-direction of the capacitor chip 80. In a plan view, the first upper electrode layer 53A is positioned, for example, in the center of the capacitor chip 80 in the y-direction. In this embodiment, the y-direction dimension of the first upper electrode layer 53A is larger than the y-direction dimension of the first electrode portion 51, and the x-direction dimension of the first upper electrode layer 53A is larger than the x-direction dimension of the first electrode portion 51. In other words, the first upper electrode layer 53A can be said to cover the entire first electrode portion 51 in a plan view. As shown in Figure 4, the thickness of the first upper electrode layer 53A (the z-direction dimension of the first upper electrode layer 53A) is equal to the thickness of the insulating layer 85. Here, if the difference between the thickness of the first upper electrode layer 53A and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the first upper electrode layer 53A, then the thickness of the first upper electrode layer 53A can be said to be equal to the thickness of the insulating layer 85.

[0089] As shown in Figure 3, the shape of the first lower electrode layer 53B in plan view is a rectangular ring shape where the longer side (x direction) of the capacitor chip 80 is the longer side and the shorter side (y direction) of the capacitor chip 80 is the shorter side.

[0090] The first lower electrode layer 53B has a portion that is positioned differently from the first upper electrode layer 53A in a plan view. It can also be said that the first lower electrode layer 53B has a portion that protrudes outward from the first upper electrode layer 53A in a plan view. More specifically, the inner surface 53Ba of the first lower electrode layer 53B is located inward from the outer surface 53Aa of the first upper electrode layer 53A, and the outer surface 53Bb of the first lower electrode layer 53B is located outward from the outer surface 53Aa of the first upper electrode layer 53A. It can also be said that the first lower electrode layer 53B is formed to surround the first upper electrode layer 53A in a plan view.

[0091] The first lower electrode layer 53B is positioned differently from the first electrode portion 51 in a plan view. More specifically, the inner surface 53Ba of the first lower electrode layer 53B is located outward from the outer surface 51a of the first electrode portion 51. In other words, in a plan view, the first lower electrode layer 53B is positioned so as not to overlap with the first electrode portion 51 and is formed to surround the first electrode portion 51.

[0092] As shown in Figure 4, in this embodiment, the first lower electrode layer 53B and the first electrode portion 51 are positioned at different locations in the z direction. More specifically, the first lower electrode layer 53B is positioned closer to the first upper electrode layer 53A than the first electrode portion 51 in the z direction. The first lower electrode layer 53B is positioned closer to the first electrode portion 51 than the first upper electrode layer 53A in the z direction. In other words, the first lower electrode layer 53B is positioned between the first upper electrode layer 53A and the first electrode portion 51 in the z direction. In this embodiment, one insulating layer 85 is interposed between the first lower electrode layer 53B and the first electrode portion 51 in the z direction. One insulating layer 85 is interposed between the first lower electrode layer 53B and the first upper electrode layer 53A in the z direction.

[0093] The thickness of the first lower electrode layer 53B (the z-direction dimension of the first lower electrode layer 53B) is equal to the thickness of the insulating layer 85. Here, if the difference between the thickness of the first lower electrode layer 53B and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the first lower electrode layer 53B, then the thickness of the first lower electrode layer 53B can be said to be equal to the thickness of the insulating layer 85.

[0094] As shown in Figure 4, the first connection portion 53C extends in the z direction. In this embodiment, the shape of the first connection portion 53C in plan view is a rectangular ring shape where the longer side is in the direction of the longer side (x direction) of the capacitor chip 80 and the shorter side is in the direction of the shorter side (y direction) of the capacitor chip 80. The first connection portion 53C connects the portion where the first upper electrode layer 53A and the first lower electrode layer 53B face each other in the z direction. In other words, in plan view, the first connection portion 53C is positioned to overlap with both the first upper electrode layer 53A and the first lower electrode layer 53B. In this embodiment, since the outer peripheral end of the first upper electrode layer 53A and the inner peripheral end of the first lower electrode layer 53B face each other in the z direction, the first connection portion 53C is in contact with both the outer peripheral end of the first upper electrode layer 53A and the inner peripheral end of the first lower electrode layer 53B. Thus, the first intermediate electrode portion 53 is formed in a stepped manner by the first upper electrode layer 53A, the first lower electrode layer 53B, and the first connecting portion 53C.

[0095] As shown in Figure 4, the second intermediate electrode section 54 is positioned opposite the first intermediate electrode section 53 in the z-direction. The second intermediate electrode section 54 has a second upper electrode layer 54A and a second lower electrode layer 54B which are located at different positions in the z-direction, and a second connecting section 54C which connects the second upper electrode layer 54A and the second lower electrode layer 54B. In this embodiment, the second upper electrode layer 54A corresponds to the "first intermediate layer of the second intermediate electrode section," and the second lower electrode layer 54B corresponds to the "second intermediate layer of the second intermediate electrode section."

[0096] As shown in Figure 3, the shape of the second upper electrode layer 54A, as viewed from the z direction, is a rectangular ring shape where the longer side (x direction) of the capacitor chip 80 is the longer side and the shorter side (y direction) of the capacitor chip 80 is the shorter side.

[0097] The second upper electrode layer 54A is positioned offset from the first lower electrode layer 53B. More specifically, the inner surface 54Aa of the second upper electrode layer 54A is located outward from the inner surface 53Ba of the first lower electrode layer 53B, and inward from the outer surface 53Bb of the first lower electrode layer 53B. The outer surface 54Ab of the second upper electrode layer 54A is located outward from the outer surface 53Bb of the first lower electrode layer 53B. Therefore, in a plan view, the second upper electrode layer 54A is positioned such that its inner circumference overlaps the outer circumference of the first lower electrode layer 53B. It can also be said that the second upper electrode layer 54A is formed to surround the first lower electrode layer 53B in a plan view.

[0098] The second upper electrode layer 54A is positioned offset from the first upper electrode layer 53A in a plan view. The second upper electrode layer 54A is positioned outward from the first upper electrode layer 53A in a plan view. More specifically, the inner surface 54Aa of the second upper electrode layer 54A is positioned outward from the outer surface 53Aa of the first upper electrode layer 53A. In other words, in a plan view, the second upper electrode layer 54A is positioned so as not to overlap with the first upper electrode layer 53A. The second upper electrode layer 54A is formed to surround the first upper electrode layer 53A in a plan view.

[0099] As shown in Figure 4, the second upper electrode layer 54A is positioned opposite the first lower electrode layer 53B in the z direction. The second upper electrode layer 54A is positioned above the first lower electrode layer 53B. It can also be said that the second upper electrode layer 54A is positioned further from the substrate 84 than the first lower electrode layer 53B, or closer to the surface 85s of the insulating layer 85 than the first lower electrode layer 53B. An insulating layer 85 is interposed between the second upper electrode layer 54A and the first lower electrode layer 53B. In this embodiment, the second upper electrode layer 54A is positioned relative to the first lower electrode layer 53B via three insulating layers 85. The second upper electrode layer 54A and the first lower electrode layer 53B constitute the second capacitor cell 55B among the multiple capacitor cells 55. Since the first lower electrode layer 53B is electrically connected to the first upper electrode layer 53A by the first connection part 53C, the second capacitor cell 55B is connected in series with the first capacitor cell 55A via the first connection part 53C.

[0100] Here, because the first lower electrode layer 53B of the first intermediate electrode portion 53 is positioned further away from the surface 85s of the insulating layer 85 than the first upper electrode layer 53A, the separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A becomes larger.

[0101] The thickness of the second upper electrode layer 54A (the z-direction dimension of the second upper electrode layer 54A) is equal to the thickness of the insulating layer 85. Here, if the difference between the thickness of the second upper electrode layer 54A and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the second upper electrode layer 54A, then the thickness of the second upper electrode layer 54A can be said to be equal to the thickness of the insulating layer 85.

[0102] As shown in Figure 3, the shape of the second lower electrode layer 54B in plan view is a rectangular ring shape where the longer side (x direction) of the capacitor chip 80 is the longer side and the shorter side (y direction) of the capacitor chip 80 is the shorter side.

[0103] The second lower electrode layer 54B has a portion that is positioned differently from the second upper electrode layer 54A in a plan view. It can also be said that the second lower electrode layer 54B has a portion that protrudes outward from the second upper electrode layer 54A in a plan view. More specifically, the inner surface 54Ba of the second lower electrode layer 54B is located outward from the inner surface 54Aa of the second upper electrode layer 54A, and inward from the outer surface 54Ab of the second upper electrode layer 54A. The outer surface 54Bb of the second lower electrode layer 54B is located outward from the outer surface 54Ab of the second upper electrode layer 54A. Therefore, in a plan view, the second lower electrode layer 54B is positioned such that its inner circumference overlaps with the outer circumference of the second upper electrode layer 54A. It can also be said that the second lower electrode layer 54B is formed to surround the second upper electrode layer 54A in a plan view.

[0104] The second lower electrode layer 54B is positioned differently from the first lower electrode layer 53B in a plan view. Specifically, the inner surface 54Ba of the second lower electrode layer 54B is located outward from the outer surface 53Bb of the first lower electrode layer 53B. In other words, in a plan view, the second lower electrode layer 54B is positioned so as not to overlap with the first lower electrode layer 53B. The second lower electrode layer 54B is formed to surround the first lower electrode layer 53B in a plan view.

[0105] The second lower electrode layer 54B and the first lower electrode layer 53B are positioned at different locations in the z-direction. More specifically, the second lower electrode layer 54B is positioned closer to the second upper electrode layer 54A than the first lower electrode layer 53B in the z-direction. The second lower electrode layer 54B is positioned closer to the first lower electrode layer 53B than the second upper electrode layer 54A in the z-direction. In other words, the second lower electrode layer 54B is positioned between the second upper electrode layer 54A and the first lower electrode layer 53B in the z-direction. In this embodiment, one insulating layer 85 is interposed between the second lower electrode layer 54B and the first lower electrode layer 53B in the z-direction. One insulating layer 85 is interposed between the second lower electrode layer 54B and the second upper electrode layer 54A in the z-direction. As shown in Figure 4, in this embodiment, the second lower electrode layer 54B is positioned in the z-direction aligned with the first upper electrode layer 53A. In other words, the insulating layer 85 on which the second lower electrode layer 54B is provided and the insulating layer 85 on which the first upper electrode layer 53A is provided are the same.

[0106] The thickness of the second lower electrode layer 54B (the z-direction dimension of the second lower electrode layer 54B) is equal to the thickness of the insulating layer 85. Here, if the difference between the thickness of the second lower electrode layer 54B and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the second lower electrode layer 54B, then the thickness of the second lower electrode layer 54B can be said to be equal to the thickness of the insulating layer 85.

[0107] As shown in Figure 4, the second connection portion 54C extends in the z direction. In this embodiment, the shape of the second connection portion 54C in plan view is a rectangular ring shape where the longer side is in the x-direction of the capacitor chip 80 and the shorter side is in the y-direction of the capacitor chip 80. The second connection portion 54C connects the portion where the second upper electrode layer 54A and the second lower electrode layer 54B face each other in the z direction. In other words, in plan view, the second connection portion 54C is positioned to overlap with both the second upper electrode layer 54A and the second lower electrode layer 54B. In this embodiment, since the outer peripheral end of the second upper electrode layer 54A and the inner peripheral end of the second lower electrode layer 54B face each other in the z direction, the second connection portion 54C is in contact with both the outer peripheral end of the second upper electrode layer 54A and the inner peripheral end of the second lower electrode layer 54B. Thus, the second intermediate electrode portion 54 is formed in a stepped manner by the second upper electrode layer 54A, the second lower electrode layer 54B, and the second connecting portion 54C.

[0108] As shown in Figure 3, the shape of the second electrode portion 52 in plan view is a rectangular ring shape in which the long side direction (x direction) of the capacitor chip 80 is the long side and the short side direction (y direction) of the capacitor chip 80 is the short side.

[0109] The second electrode portion 52 has a portion that is positioned differently from the second lower electrode layer 54B in a plan view. It can also be said that the second electrode portion 52 has a portion that protrudes outward from the second lower electrode layer 54B in a plan view. More specifically, the inner surface 52a of the second electrode portion 52 is located outward from the inner surface 54Ba of the second lower electrode layer 54B and inward from the outer surface 54Bb of the second lower electrode layer 54B. The outer surface 52b of the second electrode portion 52 is located outward from the outer surface 54Bb of the second lower electrode layer 54B. Therefore, the second electrode portion 52 is positioned so that its inner circumference overlaps with the outer circumference of the second lower electrode layer 54B. It can also be said that the second electrode portion 52 is formed to surround the second lower electrode layer 54B in a plan view.

[0110] The second electrode portion 52 is positioned differently from the second upper electrode layer 54A in a plan view. Specifically, the inner surface 52a of the second electrode portion 52 is located outward from the outer surface 54Ab of the second upper electrode layer 54A. In other words, in a plan view, the second electrode portion 52 is positioned so as not to overlap with the second upper electrode layer 54A. The second electrode portion 52 is formed to surround the second upper electrode layer 54A in a plan view.

[0111] As shown in Figure 4, the second electrode portion 52 is positioned opposite the second intermediate electrode portion 54 in the z-direction. More specifically, the second electrode portion 52 is positioned opposite the second lower electrode layer 54B. The second electrode portion 52 is positioned above the second lower electrode layer 54B. It can also be said that the second electrode portion 52 is positioned further from the substrate 84 than the second lower electrode layer 54B, or closer to the surface 85s of the insulating layer 85 than the second lower electrode layer 54B. The second lower electrode layer 54B is positioned above the first lower electrode layer 53B. Therefore, it can be said that the second lower electrode layer 54B is positioned between the first lower electrode layer 53B and the second electrode portion 52 in the z-direction.

[0112] An insulating layer 85 is interposed between the second electrode portion 52 and the second lower electrode layer 54B. In this embodiment, the second electrode portion 52 is positioned above the second lower electrode layer 54B via three insulating layers 85. The second electrode portion 52 and the second lower electrode layer 54B constitute the third capacitor cell 55C among the multiple capacitor cells 55. Since the second lower electrode layer 54B is electrically connected to the second upper electrode layer 54A by the second connection portion 54C, the third capacitor cell 55C is connected in series with the second capacitor cell 55B via the second connection portion 54C.

[0113] Here, because the second lower electrode layer 54B of the second intermediate electrode portion 54 is positioned further away from the surface 85s of the insulating layer 85 than the second upper electrode layer 54A, the separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 becomes larger.

[0114] In this embodiment, the second electrode portion 52 is positioned above the second upper electrode layer 54A. It can also be said that the second electrode portion 52 is positioned further from the substrate 84 than the second upper electrode layer 54A, or closer to the surface 85s of the insulating layer 85 than the second upper electrode layer 54A. In this embodiment, the second electrode portion 52 is positioned above the second upper electrode layer 54A via one insulating layer 85.

[0115] The thickness of the second electrode portion 52 (the z-direction dimension of the second electrode portion 52) is equal to the thickness of the insulating layer 85. Here, if the difference between the thickness of the second electrode portion 52 and the thickness of the insulating layer 85 is, for example, within 20% of the thickness of the second electrode portion 52, then the thickness of the second electrode portion 52 can be said to be equal to the thickness of the insulating layer 85.

[0116] In this embodiment, the second electrode portion 52 is positioned to overlap with the second electrode pad 82 in a plan view. More specifically, the inner surface 52a of the second electrode portion 52 is located inward from the second electrode pad 82, and the outer surface 52b of the second electrode portion 52 is located outward from the second electrode pad 82. Therefore, it can be said that the second electrode portion 52 overlaps with the entire second electrode pad 82 in a plan view.

[0117] The second electrode portion 52 is electrically connected to the second electrode pad 82 by a second connecting wire 122. The second connecting wire 122 is a wire that connects the second electrode portion 52 and the second electrode pad 82 and is provided within a plurality of insulating layers 85. In other words, the second electrode portion 52 and the second electrode pad 82 are electrically connected within the capacitor chip 80.

[0118] The positional relationships of the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53 and 54 in the z direction are summarized as follows. The first electrode portion 51 is positioned closer to the substrate 84 than the second electrode portion 52 and the intermediate electrode portions 53, 54. In other words, the first electrode portion 51 is positioned further away from the surface 85s of the insulating layer 85 than the second electrode portion 52 and the intermediate electrode portions 53, 54.

[0119] The first lower electrode layer 53B of the first intermediate electrode portion 53 is positioned in the z-direction between the first electrode portion 51 and the second lower electrode layer 54B of the second intermediate electrode portion 54. The first upper electrode layer 53A of the first intermediate electrode portion 53 is positioned in the z direction between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode portion 54.

[0120] The second upper electrode layer 54A is positioned between the second lower electrode layer 54B and the second electrode portion 52 in the z-direction. It can also be said that the second upper electrode layer 54A is positioned between the first upper electrode layer 53A and the second electrode portion 52 in the z-direction.

[0121] The second lower electrode layer 54B is positioned between the second upper electrode layer 54A and the first lower electrode layer 53B in the z-direction. The second electrode portion 52 is positioned further from the substrate 84 than the first electrode portion 51 and each intermediate electrode portion 53, 54. In other words, the second electrode portion 52 is positioned closer to the surface 85s of the insulating layer 85 than the first electrode portion 51 and each intermediate electrode portion 53, 54. For this reason, it can also be said that the second electrode portion 52 is positioned closer to the surface 85s of the insulating layer 85 than the second upper electrode layer 54A.

[0122] In this configuration of capacitor 40A, the sum of the z-direction separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A, the z-direction separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A, and the z-direction separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 (D1+D2+D3) is greater than the z-direction distance between the first electrode portion 51 and the second electrode portion 52. Furthermore, the above sum (D1+D2+D3) may be greater than the thickness of the multiple insulating layers 85. Here, the thickness of the multiple insulating layers 85 is the z-direction distance from the main surface 84s of the substrate to the surface 85s of the insulating layer 85.

[0123] In this embodiment, the arrangement positions and sizes of the first electrode section 51, the second electrode section 52, the first intermediate electrode section 53, and the second intermediate electrode section 54 are set so that the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are equal to each other. Specifically, the facing area and separation distance D1 between the first electrode section 51 and the first upper electrode layer 53A of the first intermediate electrode section 53, the facing area and separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode section 54, and the facing area and separation distance D3 between the second lower electrode layer 54B and the second electrode section 52 are set so that the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are the same to each other.

[0124] In one example, the z-direction separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A, the z-direction separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A, and the z-direction separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 are equal to each other. Here, if the maximum variation between the separation distances D1, D2, and D3 is, for example, within 20% of the separation distance D1, then the separation distances D1, D2, and D3 can be said to be equal to each other.

[0125] Furthermore, the first opposing area between the first electrode portion 51 and the first upper electrode layer 53A, the second opposing area between the first lower electrode layer 53B and the second upper electrode layer 54A, and the third opposing area between the second lower electrode layer 54B and the second electrode portion 52 are equal to each other. Here, if the maximum variation between the first opposing area, the second opposing area, and the third opposing area is, for example, within 20% of the first opposing area, then it can be said that the first opposing area, the second opposing area, and the third opposing area are equal to each other.

[0126] By setting the separation distance D1 and the first opposing area, the separation distance D2 and the second opposing area, and the separation distance D3 and the third opposing area to be equal to each other, the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C become the same.

[0127] In Figure 4, the cross-sectional structure of the capacitor chip 80 is schematically shown, and for convenience, the distance D4 between the first electrode portion 51 and the first lower electrode layer 53B is shown to be shorter than the separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A. However, in reality, the distance D4 is greater than or equal to the separation distance D1. Similarly, in Figure 4, the distance D5 between the first upper electrode layer 53A and the second upper electrode layer 54A is shown to be shorter than the separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A. However, in reality, the distance D5 is greater than or equal to the separation distance D2. Similarly, in Figure 4, the distance D6 between the first lower electrode layer 53B and the second lower electrode layer 54B is shown to be shorter than the separation distance D2. However, in reality, the distance D6 is greater than or equal to the separation distance D2. Similarly, in Figure 4, the distance D7 between the second upper electrode layer 54A and the second electrode portion 52 is shown to be shorter than the separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52; however, in reality, the distance D7 is greater than or equal to the separation distance D3.

[0128] (Operation of the gate driver in this embodiment) Figure 5 is a cross-sectional view mainly showing the cross-sectional structure of the first electrode portion 51X and the second electrode portion 52X of the capacitor 40X in the comparative example capacitor chip 80X.

[0129] Both the first electrode portion 51X and the second electrode portion 52X are formed in the shape of rectangular plates. The first electrode portion 51X and the second electrode portion 52X are spaced apart in the z-direction such that, when viewed from the z-direction, both the first electrode portion 51X and the second electrode portion 52X face each other across their entire surfaces. For this reason, an insulating layer 85 is interposed between the first electrode portion 51X and the second electrode portion 52X.

[0130] Here, the dielectric strength of the capacitor 40X mainly depends on the separation distance DX, which is the distance between the first electrode portion 51X and the second electrode portion 52X. For this reason, a large separation distance DX is desirable. On the other hand, as the separation distance DX increases, the number of insulating layers 85 to be stacked increases. As a result, the thickness of the insulating layer laminate, which consists of multiple insulating layers 85 and in which the first electrode portion 51X and the second electrode portion 52X are embedded, increases. When the thickness of this insulating layer laminate increases, it becomes more prone to warping.

[0131] Therefore, in the gate driver 10 of this embodiment, the capacitor 40A in the capacitor chip 80 comprises a first electrode portion 51, a second electrode portion 52, a first intermediate electrode portion 53, and a second intermediate electrode portion 54, and is configured such that the first electrode portion 51 and the second electrode portion 52 are coupled via the respective intermediate electrode portions 53 and 54. The dielectric strength of the capacitor 40A (40B) configured in this way corresponds to the sum of the separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A of the first intermediate electrode portion 53, the separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode portion 54, and the separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 (D1 + D2 + D3). This makes it possible to increase the total value (D1+D2+D3) above compared to the separation distance between the two electrode portions 51X and 52X of the comparative example capacitor chip 80X, without increasing the number of insulating layers 85 between the first electrode portion 51 and the second electrode portion 52. Therefore, the dielectric strength of the capacitor 40A (40B) can be improved.

[0132] In particular, the two intermediate electrode sections 53 and 54 have a stepped shape with upper electrode layers 53A and 54A and lower electrode layers 53B and 54B that are positioned differently in the z direction. This allows the separation distances D2 and D3 to be increased by the amount of the step difference between the upper electrode layers 53A and 54A and the lower electrode layers 53B and 54B. Therefore, the total value can be increased, and the dielectric strength of the capacitor 40A (40B) can be improved.

[0133] In this configuration, where the first electrode section 51 and the second electrode section 52 are connected via the intermediate electrode sections 53 and 54, it can be considered that the capacitor 40A (40B) has multiple capacitor cells 55A, 55B, and 55C connected in series with each other. In this case, the dielectric strength of the capacitor 40A (40B) corresponds to the sum of the dielectric strengths of the multiple capacitor cells 55A, 55B, and 55C.

[0134] In this configuration, the sum of the above values ​​(D1 + D2 + D3) becomes greater than the distance DX between the first electrode portion 51X and the second electrode portion 52X of the comparative example capacitor chip 80X, resulting in the combined breakdown voltage of each capacitor cell 55A to 55C becoming greater than the dielectric breakdown voltage of the comparative example capacitor chip 80X. Therefore, it can be said that the dielectric breakdown voltage of capacitor 40A (40B) can be improved.

[0135] (Effects of the gate driver of this embodiment) The gate driver 10 of this embodiment provides the following benefits. (1-1) The gate driver 10 includes a low-voltage circuit chip 60 including a low-voltage circuit 20, a high-voltage circuit chip 70 including a high-voltage circuit 30, and a capacitor chip 80 connected between the low-voltage circuit chip 60 and the high-voltage circuit chip 70. The capacitor chip 80 includes an insulating layer 85, a first electrode portion 51 embedded in the insulating layer 85 and electrically connected to a first electrode pad 81, a first intermediate electrode portion 53 and a second intermediate electrode portion 54 embedded in the insulating layer 85 and not connected to the first electrode portion 51 and the second electrode portion 52, and a second electrode portion 52 embedded in the insulating layer 85 and electrically connected to a second electrode pad 82. The first intermediate electrode portion 53 has a first upper electrode layer 53A, a first lower electrode layer 53B, and a first connection portion 53C, and the second intermediate electrode portion 54 has a second upper electrode layer 54A, a second lower electrode layer 54B, and a second connection portion 54C. The capacitor 40A (40B) is formed by the coupling of the first electrode portion 51 and the second electrode portion 52 via the respective intermediate electrode portions 53 and 54.

[0136] With this configuration, the separation distance that constitutes the dielectric breakdown voltage of capacitor 40A (40B) is the sum of the separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A of the first intermediate electrode portion 53, the separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode portion 54, and the separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 (D1 + D2 + D3). Therefore, the separation distance that constitutes the dielectric breakdown voltage of capacitor 40A (40B) can be made large.

[0137] In addition, since the upper electrode layers 53A, 54A and lower electrode layers 53B, 54B of each intermediate electrode section 53, 54 are located at different positions in the z-direction, the dielectric strength of the capacitor 40A (40B) can be improved without increasing the distance (separation distance) between the first electrode section 51 and the second electrode section 52. In other words, the dielectric strength of the capacitor 40A (40B) can be improved without increasing the number of insulating layers 85, that is, without increasing the thickness of the laminate of the insulating layers 85. As a result, the occurrence of warping of the laminate of the insulating layers 85 can be suppressed. In this way, the dielectric strength of the capacitor chip 80 can be improved while suppressing a decrease in manufacturing yield.

[0138] Furthermore, in this embodiment, since the capacitor 40 has multiple intermediate electrode sections, such as the first intermediate electrode section 53 and the second intermediate electrode section 54, the separation distance that constitutes the dielectric breakdown voltage of the capacitor 40A (40B), which is the sum of the above values ​​(D1 + D2 + D3), can be made even larger. Therefore, the dielectric breakdown voltage of the capacitor chip 80 can be improved.

[0139] (1-2) The capacitance of the first capacitor cell 55A, which consists of the first electrode portion 51 and the first upper electrode layer 53A of the first intermediate electrode portion 53, is the same as the capacitance of the second capacitor cell 55B, which consists of the first lower electrode layer 53B of the first intermediate electrode portion 53 and the second upper electrode layer 54A of the second intermediate electrode portion 54.

[0140] This configuration allows for an improvement in the dielectric strength of the capacitor chip 80 compared to the case where the capacitance of the first capacitor cell 55A and the capacitance of the second capacitor cell 55B are different.

[0141] Furthermore, the capacitance of the third capacitor cell 55C, which consists of the second lower electrode layer 54B and the second electrode portion 52 of the second intermediate electrode portion 54, is the same as the respective capacitances of each capacitor cell 55A and 55B.

[0142] This configuration improves the dielectric strength of the capacitor chip 80 compared to the case where at least one of the capacitances of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C is different from the others. In other words, the dielectric strength of the capacitor chip 80 can be further improved by making the capacitances of each capacitor cell 55A to 55C the same.

[0143] (1-3) The ring-shaped first lower electrode layer 53B is positioned at a different location from the first electrode portion 51 in the z direction and is positioned further outward than the first electrode portion 51 in a plan view. This configuration makes it easier to increase the distance D4 between the first lower electrode layer 53B and the first electrode portion 51.

[0144] The ring-shaped second upper electrode layer 54A is positioned differently from the first upper electrode layer 53A in the z-direction and is positioned further outward than the first upper electrode layer 53A in a plan view. This configuration makes it easier to increase the distance D5 between the first upper electrode layer 53A and the second upper electrode layer 54A.

[0145] The ring-shaped second lower electrode layer 54B is positioned differently from the first lower electrode layer 53B in the z-direction and is positioned further outward than the first lower electrode layer 53B in a plan view. This configuration makes it easier to increase the distance D6 between the second lower electrode layer 54B and the first lower electrode layer 53B.

[0146] The ring-shaped second electrode portion 52 is positioned differently from the second upper electrode layer 54A in the z-direction and is positioned further outward than the second upper electrode layer 54A in a plan view. This configuration makes it easier to increase the distance D7 between the second electrode portion 52 and the second upper electrode layer 54A.

[0147] In this way, it is possible to suppress the need to enlarge the distance D4 to D7 in the direction perpendicular to the z-direction of the capacitor chip 80 in order to make it the distance required for the set dielectric strength of the capacitor chip 80.

[0148] [Second Embodiment] The gate driver 10 of the second embodiment will be described with reference to Figures 6 and 7. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment mainly in the number of capacitors connected in series. In the following description, the differences from the first embodiment will be explained, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0149] As shown in Figure 6, the gate driver 10 of this embodiment has a double insulation structure with multiple capacitors. Specifically, capacitor 40A has a first capacitor 43A and a second capacitor 44A connected in series with each other. Capacitor 40B has a first capacitor 43B and a second capacitor 44B connected in series with each other. In this way, each of capacitors 40A and 40B has a double insulation structure, so the dielectric strength of the gate driver 10 is higher than that of the first and second embodiments, for example, to about 7500Vrms.

[0150] The first capacitor 43A is electrically connected to the low-voltage circuit 20. The first capacitor 43A has a first electrode 45A and a second electrode 46A. The first electrode 45A is electrically connected to the low-voltage circuit 20 by a low-voltage signal line 21A.

[0151] The second capacitor 44A is electrically connected to the high-voltage circuit 30. The second capacitor 44A connects the first capacitor 43A to the high-voltage circuit 30. The second capacitor 44A has a first electrode 47A and a second electrode 48A. The first electrode 47A is electrically connected to the second electrode 46A of the first capacitor 43A. Both the first electrode 47A of the second capacitor 44A and the second electrode 46A of the first capacitor 43A are electrically floating. The second electrode 48A is electrically connected to the high-voltage circuit 30 by a high-voltage signal line 31A.

[0152] The first capacitor 43B of capacitor 40B is electrically connected to the low-voltage circuit 20 and has a first electrode 45B and a second electrode 46B. The second capacitor 44B of capacitor 40B is electrically connected to the high-voltage circuit 30 and has a first electrode 47B and a second electrode 48B. Since each capacitor 43B and 44B is the same as each capacitor 43A and 44A, a detailed description thereof is omitted.

[0153] Figure 7 shows an example of a plan view illustrating the internal configuration of the gate driver 10. Note that Figure 6 shows a simplified circuit configuration of the gate driver 10, so the number of external terminals of the gate driver 10 in Figure 7 is greater than the number of external terminals of the gate driver 10 in Figure 5. Here, the number of external terminals of the gate driver 10 refers to the number of external electrodes that can connect the gate driver 10 to external electronic components such as the ECU 503 and the switching element 501 (see Figure 6). Also, the number of signal lines (the number of wires W described later) that transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30 in the gate driver 10 in Figure 7 is greater than the number of signal lines of the gate driver 10 in Figure 6.

[0154] As shown in Figure 7, the gate driver 10 includes a first capacitor chip 80A and a second capacitor chip 80B instead of the capacitor chip 80 of the first embodiment. In other words, the gate driver 10 includes a low-voltage circuit chip 60, a high-voltage circuit chip 70, a first capacitor chip 80A, and a second capacitor chip 80B. The low-voltage circuit chip 60, the high-voltage circuit chip 70, the first capacitor chip 80A, and the second capacitor chip 80B are arranged spaced apart from each other in the y-direction. These chips 60, 70, 80A, and 80B can also be said to be arranged in the direction of the arrangement of the low-voltage die pad 91 and the high-voltage die pad 101.

[0155] From the low-voltage lead 92 toward the high-voltage lead 102, the low-voltage circuit chip 60, the first capacitor chip 80A, the second capacitor chip 80B, and the high-voltage circuit chip 70 are arranged in that order. In other words, in a plan view, each capacitor chip 80A and 80B is positioned between the low-voltage circuit chip 60 and the high-voltage circuit chip 70.

[0156] In this embodiment, both the low-voltage circuit chip 60 and the first capacitor chip 80A are mounted on the low-voltage die pad 91 of the low-voltage lead frame 90. Both the high-voltage circuit chip 70 and the second capacitor chip 80B are mounted on the high-voltage die pad 101 of the high-voltage lead frame 100.

[0157] The first capacitor chip 80A includes the first capacitor 43A of capacitor 40A and the first capacitor 43B of capacitor 40B, and more specifically, both capacitors 43A and 43B are packaged together. In other words, the first capacitor chip 80A includes the capacitor 40A and 40B that is circuit-wise positioned closer to the low-voltage circuit 20 than to the high-voltage circuit 30.

[0158] The second capacitor chip 80B includes a second capacitor 44A of capacitor 40A and a second capacitor 44B of capacitor 40B, and more specifically, both capacitors 44A and 44B are packaged together. In other words, the second capacitor chip 80B includes the capacitor 40A and 40B that is circuit-wise positioned closer to the high-voltage circuit 30 than to the low-voltage circuit 20.

[0159] In this embodiment, the configurations of both capacitor chips 80A and 80B are the same as those of capacitor chip 80 in the first embodiment. That is, the configurations of each capacitor 43A and 43B in capacitor chip 80A and each capacitor 44A and 44B in capacitor chip 80B are the same as those of capacitors 40A and 40B in capacitor chip 80. For this reason, a detailed explanation of the configurations of both capacitor chips 80A and 80B is omitted.

[0160] The low-voltage circuit chip 60 and the first capacitor chip 80A are connected by a wire W. More specifically, the second electrode pad 62 of the low-voltage circuit chip 60 and the first electrode pad 81 of the first capacitor chip 80A are connected by a wire W. As a result, the low-voltage circuit 20 is electrically connected to the first electrode 45A of the first capacitor 43A (see Figure 6), and the low-voltage circuit 20 is electrically connected to the first electrode 45B of the first capacitor 43B (see Figure 6).

[0161] The first capacitor chip 80A and the second capacitor chip 80B are connected by a wire W. More specifically, the second electrode pad 82 of the first capacitor chip 80A and the first electrode pad 81 of the second capacitor chip 80B are connected by a wire W. As a result, the second electrode 46A of the first capacitor 43A and the first electrode 47A of the second capacitor 44A are electrically connected, and the second electrode 46B of the first capacitor 43B and the first electrode 47B of the second capacitor 44B are electrically connected.

[0162] The second capacitor chip 80B and the high-voltage circuit chip 70 are connected by a wire W. More specifically, the second electrode pad 82 of the second capacitor chip 80B and the first electrode pad 71 of the high-voltage circuit chip 70 are connected by a wire W. As a result, the second electrode 48A of the second capacitor 44A (see Figure 6) is electrically connected to the high-voltage circuit 30, and the second electrode 48B of the second capacitor 44B (see Figure 6) is electrically connected to the high-voltage circuit 30.

[0163] (Effects of the second embodiment) According to the gate driver 10 of this embodiment, in addition to the effects similar to those of the first embodiment, the following effects can be obtained.

[0164] (2-1) Capacitor 40A has a first capacitor 43A and a second capacitor 44A connected in series with each other. Capacitor 40B has a first capacitor 43B and a second capacitor 44B connected in series with each other. With this configuration, in the signal line that transmits the set signal, the first capacitor 43A and the second capacitor 44A provide a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30, and in the signal line that transmits the reset signal, the first capacitor 43B and the second capacitor 44B provide a double insulation structure between the low-voltage circuit 20 and the high-voltage circuit 30, thereby improving the dielectric strength of the gate driver 10.

[0165] [Third Embodiment] The gate driver 10 of the third embodiment will be described with reference to Figures 8 and 9. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the first embodiment will be described, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals, and their descriptions will be omitted.

[0166] As shown in Figure 8, the circuit configuration of the gate driver 10 in this embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 includes a low-voltage circuit module 200, a high-voltage circuit module 210, and an isolation module 220.

[0167] The low-voltage circuit module 200 includes a low-voltage circuit 20. In one example, although not shown, the low-voltage circuit module 200 includes a low-voltage circuit chip including the low-voltage circuit 20, a low-voltage lead frame including a low-voltage die pad on which the low-voltage circuit chip is mounted, and a sealing resin that seals a portion of the low-voltage lead frame and the low-voltage circuit chip.

[0168] The high-voltage circuit module 210 includes a high-voltage circuit 30. In one example, although not shown, the high-voltage circuit module 210 includes a high-voltage circuit chip including the high-voltage circuit 30, a high-voltage lead frame including a high-voltage die pad on which the high-voltage circuit chip is mounted, and a sealing resin that seals a portion of the high-voltage lead frame and the high-voltage circuit chip.

[0169] The isolation module 220 enables the transmission of set and reset signals from the low-voltage circuit 20 to the high-voltage circuit 30, while insulating the low-voltage circuit 20 from the high-voltage circuit 30. In other words, the isolation module 220 is used to isolate the low-voltage circuit 20 and the high-voltage circuit 30 included in the gate driver 10. The isolation module 220 includes a capacitor 40. The capacitor 40 is used to transmit signals (set and reset signals) between the low-voltage circuit 20 and the high-voltage circuit 30, as in the first embodiment. As shown in Figure 8, the isolation module 220 is circuit-wise positioned between the low-voltage circuit 20 and the high-voltage circuit 30. Therefore, the low-voltage circuit 20 and the high-voltage circuit 30 are configured to be connected via the capacitor 40.

[0170] Figure 9 shows an example of a schematic cross-sectional structure of the insulating module 220. As shown in Figure 9, the insulating module 220 comprises a capacitor chip 80, a low-voltage lead frame 221, a high-voltage lead frame 222, and a sealing resin 223 that seals the capacitor chip 80 and a portion of each lead frame 221, 222.

[0171] Each lead frame 221, 222 is made of a conductor, which in this embodiment is made of Cu. Each lead frame 221, 222 is provided spanning both the inside and outside of the sealing resin 223. The low-voltage lead frame 221 is a lead frame electrically connected to the low-voltage circuit 20 (see Figure 8), and has a low-voltage die pad 221a located within the sealing resin 223, and a plurality of low-voltage leads 221b located both inside and outside the sealing resin 223. Each low-voltage lead 221b constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0172] The high-voltage lead frame 222 is a lead frame electrically connected to the high-voltage circuit 30 (see Figure 8), and has a plurality of high-voltage leads 222b arranged across the inside and outside of the sealing resin 223. Each high-voltage lead 222b constitutes an external terminal electrically connected to the high-voltage circuit 30. In this embodiment, the capacitor chip 80 is mounted on the low-voltage die pad 221a.

[0173] The first electrode pad 81 of the capacitor chip 80 and the low-voltage lead 221b are connected by a wire W. This electrically connects the first electrode 41A of capacitor 40A to the low-voltage lead 221b. Although not shown in the diagram, the first electrode 41B of capacitor 40B is also electrically connected to another low-voltage lead 221b.

[0174] The second electrode pad 82 of the capacitor chip 80 and the high-voltage lead 222b are connected by a wire W. This electrically connects the second electrode 42A of capacitor 40A to the high-voltage lead 222b. Although not shown in the figure, the second electrode 42B of capacitor 40B is also electrically connected to another high-voltage lead 222b.

[0175] (Effects of the third embodiment) According to the gate driver 10 of this embodiment, in addition to the effects similar to those of the first embodiment, the following effects can be obtained.

[0176] (3-1) The capacitor 40 is included in an insulating module 220, which is a semiconductor module separate from the low-voltage circuit module 200 and the high-voltage circuit module 210. This configuration allows a common isolation module 220 to be used for different low-voltage circuit modules 200 and high-voltage circuit modules 210. This reduces manufacturing costs when producing multiple types of gate drivers, at least one of which is different from the other.

[0177] [Fourth Embodiment] The gate driver 10 of the fourth embodiment will be described with reference to Figures 10 and 11. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the first embodiment will be described, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0178] As shown in Figure 10, the circuit configuration of the gate driver 10 in this embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 comprises a low-voltage circuit unit 300 and a high-voltage circuit module 310. The high-voltage circuit module 310 has the same configuration as the high-voltage circuit module 210 in the third embodiment (see Figure 8). Here, the low-voltage circuit unit 300 corresponds to an "insulation module".

[0179] The low-voltage circuit unit 300 includes a low-voltage circuit 20 and a capacitor 40. The low-voltage circuit unit 300 is capable of transmitting set signals and reset signals from the low-voltage circuit 20 to the high-voltage circuit 30, while isolating the low-voltage circuit 20 from the high-voltage circuit 30.

[0180] Figure 11 shows an example of a schematic cross-sectional structure of the low-voltage circuit unit 300. As shown in Figure 11, the low-voltage circuit unit 300 comprises a low-voltage circuit chip 60 including a low-voltage circuit 20, a capacitor chip 80, a low-voltage lead frame 301, a high-voltage lead frame 302, and a sealing resin 320 that seals parts of each chip 60, 80 and each lead frame 301, 302.

[0181] Each lead frame 301, 302 is made of a conductor, which in this embodiment is made of Cu. Each lead frame 301, 302 is provided spanning both the inside and outside of the sealing resin 320. The low-voltage lead frame 301 is a lead frame electrically connected to the low-voltage circuit 20, and includes a low-voltage die pad 301a located within the sealing resin 320, and a plurality of low-voltage leads 301b located both inside and outside the sealing resin 320. Each low-voltage lead 301b constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0182] The high-voltage lead frame 302 is a lead frame electrically connected to the high-voltage circuit 30 (see Figure 10), and has a plurality of high-voltage leads 302a arranged across the inside and outside of the sealing resin 320. Each high-voltage lead 302a constitutes an external terminal electrically connected to the high-voltage circuit 30.

[0183] In this embodiment, the low-voltage circuit chip 60 and the capacitor chip 80 are mounted on the low-voltage die pad 301a. The low-voltage circuit chip 60 and the capacitor chip 80 are spaced apart from each other in the y-direction. In this embodiment, the low-voltage circuit chip 60 and the capacitor chip 80 are arranged in that order from the low-voltage lead 301b toward the high-voltage lead 302a. The connection method of the low-voltage circuit chip 60 and the capacitor chip 80 by wire W is the same as in the first embodiment. According to this embodiment, the same effects as in the first embodiment can be obtained.

[0184] [Fifth Embodiment] The gate driver 10 of the fifth embodiment will be described with reference to Figures 12 and 13. The gate driver 10 of this embodiment differs from the gate driver 10 of the first embodiment mainly in that the gate driver 10 is composed of multiple packages. In the following description, the differences from the first embodiment will be described, and components common to the gate driver 10 of the first embodiment will be denoted by the same reference numerals and their descriptions will be omitted.

[0185] As shown in Figure 12, the circuit configuration of the gate driver 10 in this embodiment is the same as the circuit configuration of the gate driver 10 in the first embodiment. The gate driver 10 comprises a low-voltage circuit module 400 and a high-voltage circuit unit 410. The low-voltage circuit module 400 has the same configuration as the low-voltage circuit module 200 in the third embodiment. Here, the high-voltage circuit unit 410 corresponds to an "insulation module".

[0186] The high-voltage circuit unit 410 includes a high-voltage circuit 30 and a capacitor 40. The high-voltage circuit unit 410 allows the high-voltage circuit 30 to receive set signals and reset signals from the low-voltage circuit 20, while isolating the low-voltage circuit 20 from the high-voltage circuit 30.

[0187] Figure 13 shows an example of a schematic cross-sectional structure of a high-voltage circuit unit 410. As shown in Figure 13, the high-voltage circuit unit 410 comprises a high-voltage circuit chip 70, a capacitor chip 80, a low-voltage lead frame 411, a high-voltage lead frame 412, and a sealing resin 420 that seals parts of each lead frame 411, 412 and each chip 70, 80.

[0188] Each lead frame 411, 412 is made of a conductor, which in this embodiment is made of Cu. Each lead frame 411, 412 is provided spanning both the inside and outside of the sealing resin 420. The low-voltage lead frame 411 is a lead frame electrically connected to the low-voltage circuit 20 (see Figure 12), and has a plurality of low-voltage leads 411a arranged across the inside and outside of the sealing resin 420. Each low-voltage lead 411a constitutes an external terminal electrically connected to the low-voltage circuit 20.

[0189] The high-voltage lead frame 412 is a lead frame electrically connected to the high-voltage circuit 30, and has a high-voltage die pad 412a located within the sealing resin 420, and a plurality of high-voltage leads 412b arranged across the inside and outside of the sealing resin 420. Each high-voltage lead 412b constitutes an external terminal electrically connected to the high-voltage circuit 30.

[0190] In this embodiment, the high-voltage circuit chip 70 and the capacitor chip 80 are mounted on the high-voltage die pad 412a. The high-voltage circuit chip 70 and the capacitor chip 80 are spaced apart from each other in the y-direction. In this embodiment, the capacitor chip 80 and the high-voltage circuit chip 70 are arranged in that order from the low-voltage lead 411a to the high-voltage lead 412b.

[0191] The connection method of the high-voltage circuit chip 70 and the capacitor chip 80 by wire W is the same as in the first embodiment. The first electrode pad 81 of the capacitor chip 80 is connected to a plurality of low-voltage leads 411a by wire W. According to this embodiment, the same effects as in the first embodiment can be obtained.

[0192] [Example of changes] The embodiments described above are illustrative of possible forms of gate drivers and isolation modules according to this disclosure and are not intended to limit their forms. Gate drivers and isolation modules according to this disclosure may take forms different from those illustrated in the embodiments described above. For example, these may be forms in which some of the configurations of the embodiments described above are replaced, modified, or omitted, or in which new configurations are added to the embodiments described above. Furthermore, the following modifications can be combined with each other as long as they do not technically contradict each other. In the following modifications, parts common to the embodiments described above are denoted by the same reference numerals as in the embodiments described above, and their descriptions are omitted.

[0193] In each embodiment, the orientation of capacitors 40A, 40B (capacitors 43A, 44B) in a plan view can be arbitrarily changed. For example, the first electrode portion 51, the second electrode portion 52, and each intermediate electrode portion 53, 54 may be arranged such that their long sides are aligned with the y-direction and their short sides are aligned with the x-direction.

[0194] In each embodiment, the shape of the first electrode portion 51 in plan view can be arbitrarily changed. For example, the shape of the first electrode portion 51 in plan view may be circular. Alternatively, the shape of the first electrode portion 51 in plan view may be triangular or a polygon with pentagons or more sides. Alternatively, the shape of the first electrode portion 51 in plan view may be elliptical or oblong. The shape of the first upper electrode layer 53A of the first intermediate electrode portion 53 in plan view may also be changed in the same way.

[0195] In each embodiment, the shape of the second electrode portion 52 in plan view can be arbitrarily changed. For example, the shape of the second electrode portion 52 in plan view may be annular. Alternatively, the shape of the second electrode portion 52 in plan view may be a ring shape with a triangle or a polygon of pentagons or more. Alternatively, the shape of the second electrode portion 52 in plan view may be an elliptical or oblong ring shape. The shapes of the first lower electrode layer 53B and first connection portion 53C of the first intermediate electrode portion 53, and the second upper electrode layer 54A, second lower electrode layer 54B and second connection portion 54C of the second intermediate electrode portion 54 may be similarly changed in plan view.

[0196] In each embodiment, the position of each intermediate electrode portion 53, 54 in the z direction can be arbitrarily changed. In one example, the first upper electrode layer 53A of the first intermediate electrode portion 53 may be positioned closer to the surface 85s of the insulating layer 85 than the second lower electrode layer 54B of the second intermediate electrode portion 54. In other words, the second lower electrode layer 54B may be positioned between the first upper electrode layer 53A and the second electrode portion 52.

[0197] In one example, the first lower electrode layer 53B of the first intermediate electrode portion 53 may be positioned in a location aligned with the first electrode portion 51 in the z-direction. In one example, the second upper electrode layer 54A of the second intermediate electrode portion 54 may be positioned in a location aligned with the second electrode portion 52 in the z-direction.

[0198] In one example, the second lower electrode layer 54B of the second intermediate electrode portion 54 may be positioned closer to the surface 85s of the insulating layer 85 than the first upper electrode layer 53A. Alternatively, the second lower electrode layer 54B may be positioned further away from the surface 85s of the insulating layer 85 than the first lower electrode layer 53B.

[0199] In each embodiment, the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53, 54 of the capacitor 40A (40B) were offset from each other in the z-direction, but this is not limited to this. For example, as shown in Figure 14, the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53, 54 may be arranged in a state where they are aligned with each other in the z-direction.

[0200] More specifically, both the first lower electrode layer 53B of the first intermediate electrode section 53 and the second lower electrode layer 54B of the second intermediate electrode section 54 are positioned aligned with the first electrode section 51 in the z direction. Both the first upper electrode layer 53A of the first intermediate electrode section 53 and the second upper electrode layer 54A of the second intermediate electrode section 54 are positioned aligned with the second electrode section 52 in the z direction. In this case, the distance D4 to D7 is set so that the capacitor chip 80 has a set dielectric breakdown voltage. It is preferable that the distance D4 to D7 is greater than or equal to the separation distance D1 to D3, but it may be shorter than the separation distance D1 to D3 as long as it is within the range where the capacitor chip 80 has a set dielectric breakdown voltage.

[0201] With this configuration, the separation distances D1 to D3 can each be made larger, so the sum of the separation distances D1 between the first electrode portion 51 and the first upper electrode layer 53A of the first intermediate electrode portion 53, D2 between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode portion 54, and D3 between the second lower electrode layer 54B and the second electrode portion 52, which constitute the separation distances that make up the dielectric strength of the capacitor 40A (40B), can be made larger (D1 + D2 + D3). Therefore, the dielectric strength of the capacitor 40A (40B) can be improved, and thus the dielectric strength of the capacitor chip 80 can be improved.

[0202] In each embodiment, the capacitor 40A (40B) had two intermediate electrode sections 53, 54, but is not limited to this, and the number of intermediate electrode sections can be arbitrarily changed. For example, there may be one intermediate electrode section or three or more.

[0203] Figure 15 is a cross-sectional view showing the cross-sectional structure of a capacitor chip 80 when the capacitor 40A has one intermediate electrode portion 59. As shown in Figure 15, the capacitor 40A has a first electrode section 51, a second electrode section 52, and an intermediate electrode section 59. The intermediate electrode section 59 is not connected to the first electrode section 51 and the second electrode section 52. The intermediate electrode section 59 can also be said to be in an electrically floating state, not fixed to the potential applied to the first electrode section 51 and the second electrode section 52. The first electrode section 51 constitutes the first electrode 41A of the capacitor 40A and is electrically connected to the first electrode pad 81 of the capacitor chip 80. The second electrode section 52 constitutes the second electrode 42A of the capacitor 40A and is electrically connected to the second electrode pad 82 of the capacitor chip 80. The capacitor 40A is constructed by the coupling of the first electrode section 51 and the second electrode section 52 via the intermediate electrode section 59.

[0204] The intermediate electrode section 59 has the same configuration as, for example, the first intermediate electrode section 53. The intermediate electrode section 59 includes an upper electrode layer 59A corresponding to the first upper electrode layer 53A of the first intermediate electrode section 53, a lower electrode layer 59B corresponding to the first lower electrode layer 53B of the first intermediate electrode section 53, and a connecting section 59C corresponding to the first connecting section 53C of the first intermediate electrode section 53.

[0205] The upper electrode layer 59A is positioned opposite the first electrode portion 51 in the z direction. The upper electrode layer 59A is positioned above the first electrode portion 51. It can be said that the upper electrode layer 59A is positioned further from the substrate 84 than the first electrode portion 51. It can also be said that the upper electrode layer 59A is positioned closer to the surface 85s of the insulating layer 85 than the first electrode portion 51. The upper electrode layer 59A and the first electrode portion 51 constitute the first capacitor cell 55D.

[0206] The lower electrode layer 59B is positioned opposite the second electrode portion 52 in the z direction. The lower electrode layer 59B is positioned below the second electrode portion 52. It can be said that the lower electrode layer 59B is positioned closer to the substrate 84 than the second electrode portion 52. It can also be said that the lower electrode layer 59B is positioned further away from the surface 85s of the insulating layer 85 than the second electrode portion 52. The lower electrode layer 59B and the second electrode portion 52 constitute the second capacitor cell 55E. Since the lower electrode layer 59B is electrically connected to the upper electrode layer 59A by the connection portion 59C, the second capacitor cell 55E is connected in series with the first capacitor cell 55D. In this way, the intermediate electrode portion 59 is formed in a stepped manner by the upper electrode layer 59A, the lower electrode layer 59B, and the connection portion 59C. As a result, the separation distance DB between the lower electrode layer 59B and the second electrode portion 52 in the z direction becomes large.

[0207] In the illustrated example, the second electrode portion 52 is positioned differently from the intermediate electrode portion 59 in the z-direction. More specifically, the second electrode portion 52 is positioned above the upper electrode layer 59A. It can be said that the second electrode portion 52 is positioned closer to the surface 85s of the insulating layer 85 than the upper electrode layer 59A.

[0208] In the illustrated example, the sum of the separation distance DA, which is the distance between the upper electrode layer 59A and the first electrode portion 51 in the z direction, and the separation distance DB, which is the distance between the lower electrode layer 59B and the second electrode portion 52 in the z direction, (DA+DB) is greater than the distance between the first electrode portion 51 and the second electrode portion 52 in the z direction. Furthermore, the above sum (DA+DB) may be greater than the thickness of the multiple insulating layers 85. Here, the thickness of the multiple insulating layers 85 is the distance in the z direction from the main surface of the substrate 84s to the surface 85s of the insulating layer 85.

[0209] In a capacitor 40A with this configuration, the opposing area and separation distance DA between the upper electrode layer 59A and the first electrode portion 51, and the opposing area and separation distance DB between the lower electrode layer 59B and the second electrode portion 52 are set so that the capacitance of the first capacitor cell 55D and the capacitance of the second capacitor cell 55E are the same.

[0210] More specifically, the separation distance DA, which is the distance in the z-direction between the upper electrode layer 59A and the first electrode portion 51, and the separation distance DB, which is the distance in the z-direction between the lower electrode layer 59B and the second electrode portion 52, are equal to each other. The first opposing area between the upper electrode layer 59A and the first electrode portion 51 and the second opposing area between the lower electrode layer 59B and the second electrode portion 52 are equal to each other. Here, if the difference between the separation distance DA and the separation distance DB is, for example, within 20% of the separation distance DA, then the separation distance DA and the separation distance DB can be said to be equal to each other. Also, if the difference between the first opposing area and the second opposing area is, for example, within 20% of the first opposing area, then the first opposing area and the second opposing area can be said to be equal to each other.

[0211] In this way, by setting the separation distance DA and the first opposing area, and the separation distance DA and the second opposing area to be equal to each other, the capacitance of the first capacitor cell 55D and the capacitance of the second capacitor cell 55E become the same. With this configuration, effects similar to those of the first embodiment can be obtained.

[0212] In addition, in the modified capacitor chip 80 shown in Figure 15, the upper electrode layer 59A may be positioned so as to be aligned with the second electrode portion 52 in the z direction, and the lower electrode layer 59B may be positioned so as to be aligned with the first electrode portion 51 in the z direction.

[0213] In the first and fourth embodiments, the low-voltage circuit 20 and the capacitor 40 were formed as separate chips, but this is not limited to this. For example, as shown in Figure 16, the capacitor 40 and the low-voltage circuit 20 may be mounted on a single chip. In one example, the low-voltage circuit chip 60 may include both the low-voltage circuit 20 and the capacitor 40. That is, the capacitor 40 may be provided in an insulating layer laminated on the substrate of the low-voltage circuit chip 60. In this case, the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53, 54 of the capacitor 40 are embedded in the insulating layer. Also, in one example, although not shown, the low-voltage circuit 20 may be formed on the substrate 84 of the capacitor chip 80.

[0214] In the first and fifth embodiments, the high-voltage circuit 30 and the capacitor 40 were formed as separate chips, but the invention is not limited to this. For example, as shown in Figure 17, the capacitor 40 and the high-voltage circuit 30 may be mounted on a single chip. In one example, the high-voltage circuit chip 70 may include both the high-voltage circuit 30 and the capacitor 40. That is, the capacitor 40 may be provided in an insulating layer laminated on the substrate of the high-voltage circuit chip 70. In this case, the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53, 54 of the capacitor 40 are embedded in the insulating layer. Also, in one example, although not shown, the high-voltage circuit 30 may be formed on the substrate 84 of the capacitor chip 80. In this case, the capacitor chip 80 is mounted on the high-voltage die pad 101.

[0215] In the third embodiment, the configuration of the capacitor 40 of the second embodiment may be applied. That is, the isolation module 220 may include a first capacitor chip 80A and a second capacitor chip 80B. Thus, the isolation module 220 may include a plurality of capacitor chips.

[0216] In the fourth embodiment, the configuration of the capacitor 40 of the second embodiment may be applied. That is, the low-voltage circuit unit 300 may include a low-voltage circuit chip 60, a first capacitor chip 80A, and a second capacitor chip 80B. Thus, the low-voltage circuit unit 300 may include a plurality of capacitor chips.

[0217] In the fifth embodiment, the configuration of the capacitor 40 of the second embodiment may be applied. That is, the high-voltage circuit unit 410 may include a high-voltage circuit chip 70, a first capacitor chip 80A, and a second capacitor chip 80B. Thus, the high-voltage circuit unit 410 may include a plurality of capacitor chips.

[0218] In the first embodiment, the capacitor chip 80 may be mounted on the high-voltage die pad 101. In this case, the first electrode 41A of the capacitor chip 80 is sufficiently far from the high-voltage die pad 101, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, insulation between the capacitor chip 80 and the high-voltage die pad 101 can be maintained.

[0219] In the second embodiment, both the first capacitor chip 80A and the second capacitor chip 80B may be mounted on the low-voltage die pad 91. Here, in the case of the second capacitor chip 80B, the second electrode 48A (48B) is sufficiently far from the low-voltage die pad 91, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, the insulation between the second capacitor chip 80B and the low-voltage die pad 91 can be maintained.

[0220] Furthermore, both the first capacitor chip 80A and the second capacitor chip 80B may be mounted on the high-voltage die pad 101. In this case, the first capacitor chip 80A is sufficiently far from the high-voltage die pad 101, so that even if the second reference potential of the high-voltage die pad 101 fluctuates and becomes high, the insulation between the first capacitor chip 80A and the high-voltage die pad 101 can be maintained.

[0221] In each embodiment, the configuration of the first electrode portion 51, the second electrode portion 52, and the intermediate electrode portions 53, 54 of the capacitor 40A (40B, 43A, 43B, 44A, 44B) in the capacitor chip 80 (80A, 80B) can be arbitrarily changed. In one example, as shown in Figure 18, the shape of the first electrode portion 51 in plan view is a rectangular ring, and the shape of the second electrode portion 52 in plan view is a rectangular plate. In plan view, the first electrode portion 51 is provided so as to surround the second electrode portion 52.

[0222] The first intermediate electrode portion 53, which is positioned opposite the first electrode portion 51 in the z direction, has a first upper electrode layer 53A, a first lower electrode layer 53B, and a first connecting portion 53C. The first upper electrode layer 53A is positioned opposite the first electrode portion 51 in the z-direction. This constitutes the first capacitor cell 55A. In plan view, the shape of the first upper electrode layer 53A is a rectangular ring.

[0223] The first lower electrode layer 53B is positioned offset from the first upper electrode layer 53A in a plan view. In a plan view, the first lower electrode layer 53B has a portion that protrudes inward from the first upper electrode layer 53A. In a plan view, the shape of the first lower electrode layer 53B is a rectangular ring. In a plan view, the first lower electrode layer 53B is positioned inward from the first electrode portion 51.

[0224] The first connecting portion 53C is configured to connect the first upper electrode layer 53A and the first lower electrode layer 53B, and is in contact with the inner circumferential end of the first upper electrode layer 53A and the outer circumferential end of the first lower electrode layer 53B. The first connecting portion 53C extends along the z-direction.

[0225] The second intermediate electrode portion 54, which is positioned opposite the first intermediate electrode portion 53 in the z direction, has a second upper electrode layer 54A, a second lower electrode layer 54B, and a connecting portion 54C. The second upper electrode layer 54A is positioned opposite the first lower electrode layer 53B in the z-direction. This constitutes the second capacitor cell 55B. Since the first lower electrode layer 53B is connected to the first upper electrode layer 53A via the first connection part 53C, the second capacitor cell 55B is connected in series with the first capacitor cell 55A. In a plan view, the shape of the second upper electrode layer 54A is a rectangular ring. In a plan view, the second upper electrode layer 54A is positioned inward from the first upper electrode layer 53A.

[0226] The second lower electrode layer 54B is positioned offset from the second upper electrode layer 54A in a plan view. In a plan view, the second lower electrode layer 54B has a portion that protrudes inward from the second upper electrode layer 54A. In a plan view, the shape of the second lower electrode layer 54B is rectangular plate-like. In a plan view, the second lower electrode layer 54B is positioned inward from the first lower electrode layer 53B.

[0227] The second connecting portion 54C is configured to connect the second upper electrode layer 54A and the second lower electrode layer 54B, and is in contact with the inner circumferential end of the second upper electrode layer 54A and the outer circumferential end of the second lower electrode layer 54B. The second connecting portion 54C extends along the z-direction.

[0228] The second electrode portion 52 is positioned opposite the second lower electrode layer 54B in the z-direction. This constitutes the third capacitor cell 55C. Since the second lower electrode layer 54B is connected to the second upper electrode layer 54A via the second connection portion 54C, the third capacitor cell 55C is connected in series with the second capacitor cell 55B. In a plan view, the shape of the second electrode portion 52 is a rectangular plate. In a plan view, the second electrode portion 52 is positioned inward from the second upper electrode layer 54A.

[0229] In this embodiment, the arrangement positions and sizes of the first electrode section 51, the second electrode section 52, the first intermediate electrode section 53, and the second intermediate electrode section 54 are set so that the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are equal to each other. Specifically, the facing area and separation distance D1 between the first electrode section 51 and the first upper electrode layer 53A of the first intermediate electrode section 53, the facing area and separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A of the second intermediate electrode section 54, and the facing area and separation distance D3 between the second lower electrode layer 54B and the second electrode section 52 are set so that the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are the same to each other.

[0230] In one example, the z-direction separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A, the z-direction separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A, and the z-direction separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52 are equal to each other. Here, if the maximum variation between the separation distances D1, D2, and D3 is, for example, within 20% of the separation distance D1, then the separation distances D1, D2, and D3 can be said to be equal to each other.

[0231] Furthermore, the first opposing area between the first electrode portion 51 and the first upper electrode layer 53A, the second opposing area between the first lower electrode layer 53B and the second upper electrode layer 54A, and the third opposing area between the second lower electrode layer 54B and the second electrode portion 52 are equal to each other. Here, if the maximum variation between the first opposing area, the second opposing area, and the third opposing area is, for example, within 20% of the first opposing area, then it can be said that the first opposing area, the second opposing area, and the third opposing area are equal to each other.

[0232] By setting the separation distance D1 and the first opposing area, the separation distance D2 and the second opposing area, and the separation distance D3 and the third opposing area to be equal to each other, the capacities of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C become the same. With this configuration, the same effects as those of the first embodiment can be obtained.

[0233] Note that in Figure 18, the cross-sectional structure of the capacitor chip 80 is schematically shown, and for convenience, the distance D4 between the first electrode portion 51 and the first lower electrode layer 53B is shown to be shorter than the separation distance D1 between the first electrode portion 51 and the first upper electrode layer 53A. However, in reality, the distance D4 is greater than or equal to the separation distance D1. Similarly, in Figure 18, the distance D5 between the first upper electrode layer 53A and the second upper electrode layer 54A is shown to be shorter than the separation distance D2 between the first lower electrode layer 53B and the second upper electrode layer 54A. However, in reality, the distance D5 is greater than or equal to the separation distance D2. Similarly, in Figure 18, the distance D6 between the first lower electrode layer 53B and the second lower electrode layer 54B is shown to be shorter than the separation distance D2. However, in reality, the distance D6 is greater than or equal to the separation distance D2. Similarly, in Figure 18, the distance D7 between the second upper electrode layer 54A and the second electrode portion 52 is shown to be shorter than the separation distance D3 between the second lower electrode layer 54B and the second electrode portion 52; however, in reality, the distance D7 is greater than or equal to the separation distance D3.

[0234] The gate driver 10 in each embodiment was configured to transmit signals from the low-voltage circuit 20 to the high-voltage circuit 30, but is not limited to this. For example, the gate driver 10 may have both a configuration for transmitting signals from the low-voltage circuit 20 to the high-voltage circuit 30 and a configuration for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20. As an example, as shown in Figure 19, a configuration in which a signal path for transmitting signals from the high-voltage circuit 30 to the low-voltage circuit 20 is added to the gate driver 10 of the first embodiment will be described.

[0235] As shown in Figure 19, the first electrode 41A (41B) of capacitor 40A (40B) is electrically connected to the low-voltage circuit 20, and the second electrode 42A (42B) is electrically connected to the high-voltage circuit 30. Therefore, both capacitors 40A and 40B correspond to the first signal capacitors.

[0236] Furthermore, since the set signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via capacitor 40A, and the reset signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via capacitor 40B, it can also be said that the first signal output from the low-voltage circuit 20 is transmitted to the high-voltage circuit 30 via the capacitor for the first signal.

[0237] As shown in Figure 19, the gate driver 10 further comprises a capacitor 40C, a low-voltage signal line 21C, and a high-voltage signal line 31C. Here, capacitor 40C corresponds to the second signal capacitor.

[0238] Capacitor 40C transmits a signal from the high-voltage circuit 30 to the low-voltage circuit 20, while isolating the high-voltage circuit 30 from the low-voltage circuit 20. This signal is, for example, a signal to detect a temperature anomaly in the switching element 501, and corresponds to the second signal. Capacitor 40C has a first electrode 41C and a second electrode 42C. The first electrode 41C is electrically connected to the high-voltage circuit 30. The second electrode 42C is electrically connected to the low-voltage circuit 20.

[0239] Thus, in the modified example shown in Figure 19, the gate driver 10 transmits signals bidirectionally between the low-voltage circuit 20 and the high-voltage circuit 30 via the capacitor 40 (40A, 40B, 40C). This signal includes a first signal transmitted from the low-voltage circuit 20 to the high-voltage circuit 30 and a second signal transmitted from the high-voltage circuit 30 to the low-voltage circuit 20.

[0240] Although not shown in the diagram, the capacitor chip 80 includes capacitors 40A, 40B, and 40C, and more specifically, capacitors 40A, 40B, and 40C are integrated into a single chip. Although not shown in the diagram, capacitors 40A to 40C are arranged in a plan view, aligned with each other in the y-direction and spaced apart from each other in the x-direction. The first electrode 41C of capacitor 40C is electrically connected to the second electrode pad 82, and the second electrode 42C is electrically connected to the first electrode pad 81. Since the second electrode pad 82 is connected to the first electrode pad 71 of the high-voltage circuit chip 70 via wire W, the first electrode 41C is electrically connected to the high-voltage circuit 30 via the second electrode pad 82 and wire W. Since the first electrode pad 81 is connected to the second electrode pad 62 of the low-voltage circuit chip 60 via wire W, the second electrode 42C is electrically connected to the low-voltage circuit 20 via the first electrode pad 81 and wire W.

[0241] Although not shown in the diagram, the configuration of capacitor 40C is the same as that of capacitors 40A and 40B. However, the correspondence between the first electrode 41C and the second electrode 42C of capacitor 40C and the first electrode section 51 and the second electrode section 52 is different from that of capacitors 40A and 40B. The second electrode section 52 of capacitor 40C constitutes the first electrode 41C of capacitor 40C, and the first electrode section 51 of capacitor 40C constitutes the second electrode 42C of capacitor 40C.

[0242] Furthermore, the configuration of the capacitor chip in the gate driver 10 in the modified example shown in Figure 19 may be changed as follows. That is, the gate driver 10 equipped with capacitor 40C as shown in Figure 19 may, instead of capacitor chip 80, be equipped with capacitor chip 80T for transmitting a signal (first signal) from the low-voltage circuit 20 to the high-voltage circuit 30, and capacitor chip 80R for transmitting a signal (second signal) from the high-voltage circuit 30 to the low-voltage circuit 20, as shown in Figure 20. In the illustrated example, both capacitor chips 80T and 80R are mounted on the low-voltage die pad 91. Capacitor chips 80T and 80R are arranged so that they are aligned in the y direction and spaced apart in the x direction. Here, capacitor chip 80T corresponds to a first capacitor chip including a capacitor for the first signal, and capacitor chip 80R corresponds to a second capacitor chip including a capacitor for the second signal.

[0243] Capacitor chip 80T includes capacitors 40A and 40B, and more specifically, both capacitors 40A and 40B are integrated into a single chip. In other words, capacitor chip 80T is a semiconductor chip dedicated to both capacitors 40A and 40B, separate from the low-voltage circuit chip 60 and the high-voltage circuit chip 70 (see Figure 2). The configuration of both capacitors 40A and 40B in capacitor chip 80T is the same as the configuration of both capacitors 40A and 40B in capacitor chip 80.

[0244] Capacitor chip 80R includes capacitor 40C, or more specifically, capacitor 40C is integrated into a single chip. In other words, capacitor chip 80R is a semiconductor chip dedicated to capacitor 40C, separate from the low-voltage circuit chip 60, the high-voltage circuit chip 70, and capacitor chip 80T. The configuration of capacitor 40C in capacitor chip 80R is the same as the configuration of both capacitors 40A and 40B in capacitor chip 80.

[0245] In each embodiment, the capacitor chip 80 may have a resin layer consisting of one or more layers as the insulating layer in which the capacitors 40A to 40C are embedded. This resin layer may be made of a material containing polyimide resin, phenolic resin, or epoxy resin. Alternatively, the capacitor chip 80 may have a configuration in which an oxide film and a resin layer are mixed, such as the insulating layer 85, as the insulating layer in which the capacitors 40A to 40C are embedded.

[0246] In each embodiment, the configuration of each connection portion 53C, 54C can be arbitrarily changed. In one example, the first connection portion 53C may be provided in multiple locations that overlap with both the first upper electrode layer 53A and the first lower electrode layer 53B in a plan view, spaced apart from each other in the circumferential direction of these electrode layers 53A and 53B. In another example, the second connection portion 54C may be provided in multiple locations that overlap with both the second upper electrode layer 54A and the second lower electrode layer 54B in a plan view, spaced apart from each other in the circumferential direction of these electrode layers 54A and 54B. In short, the first connection portion 53C only needs to be configured to electrically connect the first upper electrode layer 53A and the first lower electrode layer 53B. The second connection portion 54C only needs to be configured to electrically connect the second upper electrode layer 54A and the second lower electrode layer 54B.

[0247] In the first and third to fifth embodiments, within the range in which the capacitances of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are the same, at least one of the separation distances D1 to D3 may differ from the others by adjusting, for example, the facing area between the first electrode portion 51 and the first upper electrode layer 53A, the facing area between the first lower electrode layer 53B and the second upper electrode layer 54A, and the facing area between the second lower electrode layer 54B and the second electrode portion 52. Similarly, within the range in which the capacitances of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C are the same, at least one of the facing areas between the first electrode portion 51 and the first upper electrode layer 53A, the facing area between the first lower electrode layer 53B and the second upper electrode layer 54A, and the facing area between the second lower electrode layer 54B and the second electrode portion 52 may differ from the others by adjusting, for example, the separation distances D1 to D3. The capacitors 43A (43B) and 44A (44B) in the second embodiment can also be modified in the same way.

[0248] In the first and third to fifth embodiments, at least one of the capacitances of the first capacitor cell 55A, the second capacitor cell 55B, and the third capacitor cell 55C may differ from the others. The same modification can be made to the capacitors 43A (43B) and 44A (44B) in the second embodiment.

[0249] In the modified example shown in Figure 15, the separation distances DA and DB may be different from each other by adjusting, for example, the facing area between the first electrode portion 51 and the upper electrode layer 59A and the facing area between the second electrode portion 52 and the lower electrode layer 59B, within the range in which the capacitances of the first capacitor cell 55D and the second capacitor cell 55E are the same. Also, within the range in which the capacitances of the first capacitor cell 55D and the second capacitor cell 55E are the same, the facing area between the first electrode portion 51 and the upper electrode layer 59A and the facing area between the second electrode portion 52 and the lower electrode layer 59B may be different from each other by adjusting, for example, the separation distances DA and DB.

[0250] In the modified example shown in Figure 15, the capacitances of the first capacitor cell 55D and the second capacitor cell 55E may be different from each other. In the third embodiment, the isolation module 220 may be applied to circuits other than the gate driver 10. Similarly, the low-voltage circuit unit 300 of the fourth embodiment and the high-voltage circuit unit 410 of the fifth embodiment may also be applied to circuits other than the gate driver 10.

[0251] As used in this disclosure, the term “on / above” includes the meanings of “on / above” and “above / beyond” unless the context clearly indicates otherwise. Therefore, the expression “A is formed on B” is intended to mean that in this embodiment, A may be in contact with B and directly positioned on B, but as a modified example, A may be positioned above B without contacting B. In other words, the term “on / above” does not preclude structures in which other members are formed between A and B.

[0252] The z-direction used in this disclosure does not necessarily have to be vertical, nor does it have to coincide perfectly with the vertical. Therefore, the various structures described herein are not limited to the z-direction "up" and "down" being the same as the z-direction "up" and "down" being the same as the vertical. For example, the x-direction may be vertical, or the y-direction may be vertical.

[0253] In this specification, the phrase "at least one of A and B" should be understood to mean "A alone, or B alone, or both A and B." [Note] The technical concepts that can be understood from each of the above embodiments and their respective modifications are described below. The reference numerals for the components of the embodiments corresponding to the components described in each appendix are shown in parentheses. These reference numerals are provided as examples to aid understanding, and the components described in each appendix should not be limited to those indicated by these reference numerals.

[0254] (Note 1) An isolator (80) having an insulating layer (85) and capacitors (40 / 40A, 40B, 40C) embedded in the insulating layer (85), The aforementioned capacitors (40 / 40A, 40B, 40C) are A first electrode portion (51) is provided within the insulating layer (85) and connected to a first pad (81) formed on the surface (85s) of the insulating layer (85), A second electrode portion (52) is provided within the insulating layer (85) and connected to a second pad (82) formed on the surface (85s) of the insulating layer (85), It includes intermediate electrode portions (53, 54) provided within the insulating layer (85) and not connected to the first electrode portion (51) and the second electrode portion (52), The intermediate electrode portions (53, 54) are The insulating layer (85) has first intermediate layers (53A, 54A) and second intermediate layers (53B, 54B) whose positions in the thickness direction (z direction) are different from each other, The insulating layer (85) extends in the thickness direction (z direction) and has connecting portions (53C, 54C) that connect the first intermediate layer (53A, 54A) and the second intermediate layer (53B, 54B), The capacitor (40 / 40A, 40B, 40C) is configured such that the first electrode portion (51) and the second electrode portion (52) are coupled via the intermediate electrode portions (53, 54). Isolator.

[0255] (Note 2) Multiple intermediate electrode portions (53, 54) are provided. The first electrode portion (51) and the second electrode portion (52) are coupled via the plurality of intermediate electrode portions (53, 54) to form the capacitor (40 / 40A, 40B, 40C), The plurality of intermediate electrode portions (53, 54) include a first intermediate electrode portion (53) and a second intermediate electrode portion (54), The first capacitor cell (55A) is formed by the first intermediate layer (53A) and the first electrode portion (51) of the first intermediate electrode portion (53) being spaced apart and facing each other in the thickness direction (z direction) of the insulating layer (85). The second intermediate layer (53B) of the first intermediate electrode portion (53) is positioned differently from the first intermediate layer (53A) of the first intermediate electrode portion (53) when viewed from the thickness direction (z direction) of the insulating layer (85). The second intermediate layer (53B) of the first intermediate electrode portion (53) and the first intermediate layer (54A) of the second intermediate electrode portion (54) are spaced apart and facing each other in the thickness direction (z direction) of the insulating layer (85), thereby forming a second capacitor cell (55B) that is connected in series with the first capacitor cell (55A) via the connection portion (53C) of the first intermediate electrode portion (53). The isolator described in Appendix 1.

[0256] (Note 3) The first intermediate layer (53A) of the first intermediate electrode portion (53) is circular or polygonal when viewed from the thickness direction (z direction) of the insulating layer (85). The second intermediate layer (53B) of the first intermediate electrode portion (53) and the first intermediate layer (54A) of the second intermediate electrode portion (54) are ring-shaped and formed to surround the first intermediate layer (53A) of the first intermediate electrode portion (53) when viewed from the thickness direction (z direction) of the insulating layer (85). The second intermediate layer (54B) of the second intermediate electrode portion (54) is ring-shaped and is formed to surround the first intermediate layer (54A) of the second intermediate electrode portion (54) when viewed from the thickness direction (z direction) of the insulating layer (85). The isolator described in Appendix 2.

[0257] (Note 4) The second intermediate layer (53B) of the first intermediate electrode portion (53) is positioned between the first intermediate layer (53A) and the first electrode portion (51) of the first intermediate electrode portion (53) in the thickness direction (z direction) of the insulating layer (85). The first intermediate layer (54A) of the second intermediate electrode portion (54) is disposed closer to the surface (85s) of the insulating layer (85) than the first intermediate layer (53A) of the first intermediate electrode portion (53) in the thickness direction (z direction) of the insulating layer (85). The isolator according to appended claim 2 or 3.

[0258] (Appended claim 5) The facing area and the separation distance (D1) between the first intermediate layer (53A) of the first intermediate electrode portion (53) and the first electrode portion (51), and the facing area and the separation distance (D2) between the second intermediate layer (53B) of the first intermediate electrode portion (51) and the first intermediate layer (54A) of the second intermediate electrode portion (54) are set such that the capacitance of the first capacitor cell (55A) and the capacitance of the second capacitor cell (55B) are the same. The isolator according to any one of appended claims 2 to 4.

[0259] (Appended claim 6) The second intermediate layer (54B) of the second intermediate electrode portion (54) is disposed at a position different from the first intermediate layer (54A) of the second intermediate electrode portion (54) when viewed from the thickness direction (z direction) of the insulating layer (85). The second intermediate layer (54B) of the second intermediate electrode portion (54) and the second electrode portion (52) face each other with a separation in the thickness direction (z direction) of the insulating layer (85), thereby forming a third capacitor cell (55C) connected in series with the second capacitor cell (55B) through the connection portion (54C) of the second intermediate electrode portion (54). The isolator according to any one of appended claims 2 to 5.

[0260] (Appended claim 7) The second intermediate layer (54B) of the second intermediate electrode portion (54) is disposed between the second intermediate layer (53B) of the first intermediate electrode portion (53) and the second electrode portion (52) in the thickness direction (z direction) of the insulating layer (85). The isolator according to appended claim 6.

[0261] (Appended claim 8) The capacitance of the first capacitor cell (55A) is the same as the capacitance of the second capacitor cell (55B), The facing area and the separation distance (D3) between the second intermediate layer (54B) of the second intermediate electrode portion (54) and the second electrode portion (52) are set such that the capacitances of the first capacitor cell (55A) and the second capacitor cell (55B) are the same as the capacitance of the third capacitor cell (55C). The isolator according to Supplementary Note 6 or 7.

[0262] (Supplementary Note 9) The first intermediate layer (59A) and the first electrode portion (51) face each other with a separation in the thickness direction (z-direction) of the insulating layer (85), thereby forming a first capacitor cell (55D). The second intermediate layer (59B) is provided at a position different from that of the first intermediate layer (59A) when viewed from the thickness direction (z-direction) of the insulating layer (85). The second intermediate layer (59B) and the second electrode portion (52) face each other with a separation in the thickness direction (z-direction) of the insulating layer (85), thereby forming a second capacitor cell (55E) connected in series with the first capacitor cell (55D) via the connection portion (59C). The isolator according to Supplementary Note 1.

[0263] (Supplementary Note 10) The second intermediate layer (59B) is disposed between the first intermediate layer (59A) and the first electrode portion (51) in the thickness direction (z-direction) of the insulating layer (85). The second electrode portion (52) is disposed closer to the surface (85s) of the insulating layer (85) than the first intermediate layer (59A). The isolator according to Supplementary Note 9.

[0264] (Supplementary Note 11) The opposing area and separation distance (DA) between the first intermediate layer (59A) and the first electrode portion (51), and the opposing area and separation distance (DB) between the second intermediate layer (59B) and the second electrode portion (52) are set so that the capacitance of the first capacitor cell (55D) and the capacitance of the second capacitor cell (55E) are the same. The isolator described in Appendix 9 or 10.

[0265] (Note 12) The system includes an isolator as described in any one of the appendices 1 to 11, The isolator (80) is connected between the low-voltage circuit chip (60) and the high-voltage circuit chip (70) included in the gate driver (10) that drives the switching element (501). The low-voltage circuit chip (60) is further comprising The insulating module described in Appendix 15.

[0266] (Note 13) The system includes an isolator as described in any one of the appendices 1 to 11, The isolator (80) is connected between the low-voltage circuit chip (60) and the high-voltage circuit chip (70) included in the gate driver (10) that drives the switching element (501). The high-voltage circuit chip (70) is further comprising The insulating module described in Appendix 15.

[0267] (Note 14) A gate driver (10) that applies a drive voltage signal to the gate of a switching element (501), A low-voltage circuit chip (60) includes a low-voltage circuit (20) configured to operate when a first voltage (V1) is applied, A high-voltage circuit chip (70) includes a high-voltage circuit (30) configured to operate when a second voltage (V2) higher than the first voltage (V1) is applied, The system includes an isolator (80) connected between the low-voltage circuit chip (60) and the high-voltage circuit chip (70), The isolator (80) is an insulating layer (85), a first electrode portion (51) provided in the insulating layer (85) and connected to a first pad (81) formed on a surface (85s) of the insulating layer (85), a second electrode portion (52) provided in the insulating layer (85) and connected to a second pad (82) formed on the surface (85s) of the insulating layer (85), and intermediate electrode portions (53, 54) provided in the insulating layer (85) and not connected to the first electrode portion (51) and the second electrode portion (52), wherein the intermediate electrode portions (53, 54) include first electrode portions (53A, 54A) and second electrode portions (53B, 54B) having different positions in a thickness direction (z direction) of the insulating layer (85), and connection portions (53C, 54C) that extend in the thickness direction (z direction) of the insulating layer (85) and connect the first electrode portions (53A, 54A) and the second electrode portions (53B, 54B), and the capacitor (40 / 40A, 40B, 40C) is configured such that the first electrode portion (51) and the second electrode portion (52) are coupled via the intermediate electrode portions (53, 54). A gate driver.

[0268] (Supplementary Note 15) The first electrode portion (51) is electrically connected to the low-voltage circuit (20), and the second electrode portion (52) is electrically connected to the high-voltage circuit (30). The gate driver according to Supplementary Note 14.

[0269] (Supplementary Note 16) The gate driver (10) is configured such that signals are transmitted bidirectionally between the low-voltage circuit (20) and the high-voltage circuit (30) via the capacitor (40 / 40A, 40B, 40C), wherein the signals include a first signal and a second signal, The capacitor (40 / 40A, 40B, 40C) includes a first signal capacitor (40A, 40B) and a second signal capacitor (40C). The first signal is transmitted from the low-voltage circuit (20) to the high-voltage circuit (30) via the first signal capacitors (40A, 40B). The second signal is transmitted from the high-voltage circuit (30) to the low-voltage circuit (20) via the second signal capacitor (40C). The gate driver described in Appendix 14.

[0270] (Note 17) The insulating layer (85) consists of at least one of an oxide film and a resin. The gate driver described in any one of the appendices 14-16.

[0271] (Note 18) The system includes an isolator (80) comprising the first signal capacitor (40A, 40B) and the second signal capacitor (40C). The gate driver described in Appendix 13.

[0272] (Note 19) The isolator is, A first capacitor chip (80T) including the first signal capacitors (40A, 40B), A second capacitor chip (80R) including the second signal capacitor (40C) is provided. The gate driver mentioned in Appendix 13.

[0273] (Note 20) The sum of the separation distance (D1) between the first intermediate layer (53A) of the first intermediate electrode portion (53) and the first electrode portion (51), the separation distance (D2) between the second intermediate layer (53B) of the first intermediate electrode portion (51) and the first intermediate layer (54A) of the second intermediate electrode portion (54), and the separation distance (D3) between the second intermediate layer (54B) of the second intermediate electrode portion (54) and the second electrode portion (52) is greater than the thickness of the insulating layer (85). The gate driver described in Appendix 7.

[0274] (Note 21) The sum of the separation distance (DA) between the first intermediate layer (59A) and the first electrode portion (51) of the intermediate electrode portion (59), and the separation distance (DB) between the second intermediate layer (59B) and the second electrode portion (52) of the intermediate electrode portion (59), (DA + DB) is greater than the thickness of the insulating layer (85). The gate driver described in Appendix 10.

[0275] (Note 22) A gate driver (10) that applies a drive voltage signal to the gate of a switching element (501), A low-voltage circuit chip (60) includes a low-voltage circuit (20) configured to operate when a first voltage (V1) is applied, A high-voltage circuit chip (70) includes a high-voltage circuit (30) configured to operate when a second voltage (V2) higher than the first voltage (V1) is applied, The low-voltage circuit chip (60) is Insulating layer (85), A first electrode portion (51) is provided within the insulating layer (85) and connected to a first pad (81) formed on the surface (85s) of the insulating layer (85), A second electrode portion (52) is provided within the insulating layer (85) and connected to a second pad (82) formed on the surface (85s) of the insulating layer (85), The device comprises intermediate electrode portions (53, 54) provided within the insulating layer (85) and not connected to the first electrode portion (51) and the second electrode portion (52), The intermediate electrode portions (53, 54) are The insulating layer (85) has first electrode portions (53A, 54A) and second electrode portions (53B, 54B) whose positions in the thickness direction (z direction) are different from each other, The insulating layer (85) extends in the thickness direction (z direction) and has connecting portions (53C, 54C) that connect the first electrode portions (53A, 54A) and the second electrode portions (53B, 54B), The capacitor (40 / 40A, 40B, 40C) is configured such that the first electrode portion (51) and the second electrode portion (52) are coupled via the intermediate electrode portions (53, 54). Gate driver.

[0276] (Note 23) A gate driver (10) that applies a drive voltage signal to the gate of a switching element (501), A low-voltage circuit chip (60) includes a low-voltage circuit (20) configured to operate when a first voltage (V1) is applied, A high-voltage circuit chip (70) includes a high-voltage circuit (30) configured to operate when a second voltage (V2) higher than the first voltage (V1) is applied, The aforementioned high-voltage circuit chip (70) is Insulating layer (85), A first electrode portion (51) is provided within the insulating layer (85) and connected to a first pad (81) formed on the surface (85s) of the insulating layer (85), A second electrode portion (52) is provided within the insulating layer (85) and connected to a second pad (82) formed on the surface (85s) of the insulating layer (85), The device comprises intermediate electrode portions (53, 54) provided within the insulating layer (85) and not connected to the first electrode portion (51) and the second electrode portion (52), The intermediate electrode portions (53, 54) are The insulating layer (85) has first electrode portions (53A, 54A) and second electrode portions (53B, 54B) whose positions in the thickness direction (z direction) are different from each other, The insulating layer (85) extends in the thickness direction (z direction) and has connecting portions (53C, 54C) that connect the first electrode portions (53A, 54A) and the second electrode portions (53B, 54B), The capacitor (40 / 40A, 40B, 40C) is configured such that the first electrode portion (51) and the second electrode portion (52) are coupled via the intermediate electrode portions (53, 54). Gate driver. [Explanation of symbols]

[0277] 10... Gate Driver 20... Low-voltage circuits 30…High-voltage circuits 40, 40A, 40B… Capacitors 43A, 43B... First capacitor (capacitor) 44A, 44B... Second capacitor (capacitor) 51...First electrode part 52…Second electrode part 53...First intermediate electrode section 53A...First upper electrode layer (first intermediate layer) 53B...First lower electrode layer (second intermediate layer) 53C...First connection point (connection point) 54…Second intermediate electrode section 54A...Second upper electrode layer (first intermediate layer) 54B...Second lower electrode layer (second intermediate layer) 54C...Second connection point (connection point) 55…Capacitor cell 55A…First capacitor cell 55B…Second capacitor cell 55C…Third capacitor cell 55D…First capacitor cell 55E…Second capacitor cell 59…Intermediate electrode part 59A...Top electrode layer (first intermediate layer) 59B...Lower electrode layer (second intermediate layer) 59C...Connection part 60... Low-voltage circuit chip 70…High-voltage circuit chip 80…Capacitor chip 80A…First capacitor chip 80B…Second capacitor chip 80R…Capacitor chip 80T…Capacitor chip 80s... Main surface of the chip 81…First electrode pad (first pad) 82...Second electrode pad (second pad) 85...Insulating layer 85s…Surface 220...Isolation module 300... Low-voltage circuit unit (isolation module) 410…High-voltage circuit unit (insulation module) 501, 502… Switching elements D1~D3, DA, DB... Separation distance

Claims

1. An isolator having an insulating layer and a capacitor embedded in the insulating layer, The aforementioned capacitor is A first electrode portion is provided within the insulating layer and connected to a first pad formed on the surface of the insulating layer, A second electrode portion is provided within the insulating layer and connected to a second pad formed on the surface of the insulating layer, An intermediate electrode portion provided within the insulating layer and not connected to the first electrode portion and the second electrode portion, Includes, The aforementioned intermediate electrode portion is The first intermediate layer and the second intermediate layer are located at different positions in the thickness direction of the insulating layer, The insulating layer extends in the thickness direction and has a connecting portion that connects the first intermediate layer and the second intermediate layer, It has, The capacitor is configured such that the first electrode portion and the second electrode portion are coupled via the intermediate electrode portion. Isolator.

2. Multiple intermediate electrode sections are provided, The first electrode portion and the second electrode portion are coupled via the plurality of intermediate electrode portions to constitute the capacitor. The plurality of intermediate electrode portions include a first intermediate electrode portion and a second intermediate electrode portion, The first capacitor cell is formed by the first intermediate layer and the first electrode portion of the first intermediate electrode portion facing each other at a distance in the thickness direction of the insulating layer. The second intermediate layer of the first intermediate electrode portion is positioned differently from the first intermediate layer of the first intermediate electrode portion when viewed from the thickness direction of the insulating layer. The second intermediate layer of the first intermediate electrode portion and the first intermediate layer of the second intermediate electrode portion are spaced apart in the thickness direction of the insulating layer and face each other, thereby forming a second capacitor cell connected in series with the first capacitor cell via the connection portion of the first intermediate electrode portion. The isolator according to claim 1.

3. The first intermediate layer of the first intermediate electrode portion is circular or polygonal when viewed from the thickness direction of the insulating layer. The second intermediate layer of the first intermediate electrode portion and the first intermediate layer of the second intermediate electrode portion are ring-shaped and formed to surround the first intermediate layer of the first intermediate electrode portion when viewed from the thickness direction of the insulating layer. The second intermediate layer of the second intermediate electrode portion is ring-shaped, as viewed from the thickness direction of the insulating layer, so as to surround the first intermediate layer of the second intermediate electrode portion. The isolator according to claim 2.

4. The second intermediate layer of the first intermediate electrode portion is arranged between the first intermediate layer of the first intermediate electrode portion and the first electrode portion in the thickness direction of the insulating layer. The first intermediate layer of the second intermediate electrode portion is positioned closer to the surface of the insulating layer than the first intermediate layer of the first intermediate electrode portion in the thickness direction of the insulating layer. The isolator according to claim 2 or 3.

5. The opposing area and separation distance between the first intermediate layer of the first intermediate electrode portion and the first electrode portion, and the opposing area and separation distance between the second intermediate layer of the first intermediate electrode portion and the first intermediate layer of the second intermediate electrode portion are set so that the capacitance of the first capacitor cell and the capacitance of the second capacitor cell are the same. The isolator according to any one of claims 2 to 4.

6. The second intermediate layer of the second intermediate electrode portion is positioned differently from the first intermediate layer of the second intermediate electrode portion when viewed from the thickness direction of the insulating layer. The second intermediate layer of the second intermediate electrode portion and the second electrode portion are spaced apart in the thickness direction of the insulating layer and face each other, thereby forming a third capacitor cell connected in series with the second capacitor cell via the connection portion of the second intermediate electrode portion. The isolator according to any one of claims 2 to 5.

7. The second intermediate layer of the second intermediate electrode portion is positioned between the second intermediate layer of the first intermediate electrode portion and the second electrode portion in the thickness direction of the insulating layer. The isolator according to claim 6.

8. The capacitance of the first capacitor cell and the capacitance of the second capacitor cell are the same. The opposing area and separation distance between the second intermediate layer and the second electrode portion of the second intermediate electrode portion are set so that the capacitance of the first capacitor cell and the second capacitor cell is the same as the capacitance of the third capacitor cell. The isolator according to claim 6 or 7.

9. The first capacitor cell is formed by the first intermediate layer and the first electrode portion facing each other at a distance in the thickness direction of the insulating layer. The second intermediate layer is provided at a different position from the first intermediate layer when viewed from the thickness direction of the insulating layer. The second intermediate layer and the second electrode portion are spaced apart in the thickness direction of the insulating layer and face each other, thereby forming a second capacitor cell connected in series with the first capacitor cell via the connection portion. The isolator according to claim 1.

10. The second intermediate layer is disposed between the first intermediate layer and the first electrode portion in the thickness direction of the insulating layer. The second electrode portion is positioned closer to the surface of the insulating layer than the first intermediate layer. The isolator according to claim 9.

11. The opposing area and separation distance between the first intermediate layer and the first electrode portion, and the opposing area and separation distance between the second intermediate layer and the second electrode portion are set so that the capacitance of the first capacitor cell and the capacitance of the second capacitor cell are the same. The isolator according to claim 9 or 10.

12. The isolator comprises the one described in any one of claims 1 to 11, The isolator is connected between a low-voltage circuit chip and a high-voltage circuit chip included in a gate driver that drives a switching element. The low-voltage circuit chip further comprises the aforementioned low-voltage circuit chip Insulation module.

13. The isolator comprises the one described in any one of claims 1 to 11, The isolator is used to isolate the low-voltage circuit chip and the high-voltage circuit chip included in the gate driver that drives the switching element. The aforementioned high-voltage circuit chip is further provided Insulation module.

14. A gate driver that applies a drive voltage signal to the gate of a switching element, A low-voltage circuit chip including a low-voltage circuit configured to operate when a first voltage is applied, A high-voltage circuit chip including a high-voltage circuit configured to operate when a second voltage higher than the first voltage is applied, An isolator connected between the low-voltage circuit chip and the high-voltage circuit chip, Equipped with, The isolator is, Insulating layer and, A first electrode portion is provided within the insulating layer and connected to a first pad formed on the surface of the insulating layer, A second electrode portion is provided within the insulating layer and connected to a second pad formed on the surface of the insulating layer, An intermediate electrode portion provided within the insulating layer and not connected to the first electrode portion and the second electrode portion, Equipped with, The aforementioned intermediate electrode portion is The first intermediate layer and the second intermediate layer are located at different positions in the thickness direction of the insulating layer, The insulating layer extends in the thickness direction and has a connecting portion that connects the first intermediate layer and the second intermediate layer, It has, The capacitor is formed by the coupling of the first electrode portion and the second electrode portion via the intermediate electrode portion. Gate driver.

15. The first electrode portion is electrically connected to the low-voltage circuit. The second electrode portion is electrically connected to the high-voltage circuit. The gate driver according to claim 14.

16. The gate driver is configured such that signals are transmitted bidirectionally between the low-voltage circuit and the high-voltage circuit via the capacitor. The aforementioned signal includes a first signal and a second signal, The capacitor includes a first signal capacitor and a second signal capacitor. The first signal is transmitted from the low-voltage circuit to the high-voltage circuit via the first signal capacitor. The second signal is transmitted from the high-voltage circuit to the low-voltage circuit via the second signal capacitor. The gate driver according to claim 14.

17. The insulating layer consists of at least one of an oxide film and a resin. A gate driver according to any one of claims 14 to 16.

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