DC / DC converter

Abstract

A driver circuit (13) operates switching elements (Q1, Q2) with a constant on-time control. A monitoring circuit generates a first control signal indicating whether a DC / DC converter (1) is in a steady state or in an abnormal state. An on-timer circuit (14) generates, on the basis of the first control signal, a second control signal for terminating an interval which is a partial interval within the switching cycle of each of the switching elements (Q1, Q2) and in which energy is stored in an inductor (L1) and sends the second control signal to the driver circuit (13). When the DC / DC converter (1) is in the steady state, the on-timer circuit (14) generates the second control signal by using a first reference voltage (Vref21) that changes in accordance with the duty ratios of the switching elements (Q1, Q2). When the DC / DC converter (1) is in the abnormal state, the on-timer circuit (14) generates the second control signal by using a fixed second reference voltage (Vref22).

Description

Technical Field

[0001] The present disclosure relates to a DC / DC converter and its control circuit.

Background Art

[0002] In recent years, with the high functionality and miniaturization of portable devices, as a power supply circuit, a switching power supply with high-frequency operation and hysteresis control that can achieve high efficiency and miniaturization has been widely used. For example, Patent Document 1 discloses controlling a DC / DC converter so as to operate to make the magnitude or frequency of the ripple component of the output voltage constant, thereby suppressing fluctuations in the output voltage.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One type of hysteresis control for DC / DC converters is known as "constant on-time control." For example, in constant on-time control of a buck converter, when the output voltage falls below a threshold during each switching cycle of the switching elements, the high-side switching element is turned on for a predetermined duration, and then turned off. In a buck converter, when the high-side switching element is turned on and the low-side switching element is turned off, energy is stored in the inductor, and when the high-side switching element is turned off and the low-side switching element is turned on, the energy stored in the inductor is released. In this specification, the time interval during which energy is stored in the inductor is called the "on-interval," and the time interval during which the energy stored in the inductor is released is called the "rectification interval." Note that if the conditions for ending the on-interval are fixed, the switching frequency of the switching elements may fluctuate when the input voltage, output voltage, or output current of the DC / DC converter fluctuates. Therefore, the conditions for ending the on-interval may be changed to prevent fluctuations in the switching frequency.

[0005] However, when the operation of the switching elements deviates from its steady state, such as immediately after the startup of a DC / DC converter or when a ground fault protection circuit is activated, it is difficult to perform constant on-time control without fluctuations in the switching frequency. Therefore, even when the operation of the switching elements deviates from its steady state, it is required to reduce fluctuations in the switching frequency compared to conventional methods, and preferably perform constant on-time control at a constant switching frequency.

[0006] One object of this disclosure is to provide a control circuit that can control a DC / DC converter to perform constant on-time control with reduced fluctuations in switching frequency compared to conventional methods, even when the operation of the switching elements deviates from its steady state. Furthermore, one object of this disclosure is to provide a DC / DC converter equipped with such a control circuit. [Means for solving the problem]

[0007] According to a control circuit for a DC / DC converter in one aspect of this disclosure, In a control circuit for controlling a DC / DC converter comprising an inductor and first and second switching elements for storing and releasing energy relative to the inductor, The aforementioned control circuit is A driver circuit that operates the first and second switching elements with constant on-time control, A monitoring circuit that generates a first control signal indicating whether the DC / DC converter is in a steady state or an abnormal state, The system includes an on-timer circuit that, based on the first control signal, generates a second control signal that terminates a portion of the switching cycle of the first and second switching elements, in which energy is stored in the inductor, and sends this signal to the driver circuit. The aforementioned ON Timer Circuit When the DC / DC converter is in a steady state, the second control signal is generated using a first reference voltage that changes according to the duty cycle of the first and second switching elements. If the DC / DC converter is in an abnormal state, the second control signal is generated using a fixed second reference voltage. [Effects of the Invention]

[0008] According to one aspect of this disclosure, even when the operation of the switching element deviates from its steady state, the DC / DC converter can be controlled to reduce fluctuations in the switching frequency compared to conventional methods and perform constant on-time control. [Brief explanation of the drawing]

[0009] [Figure 1] This is a block diagram showing the configuration of the DC / DC converter 1 according to the embodiment. [Figure 2]Figure 1 is a circuit diagram showing the configuration of the on-timer circuit 14. [Figure 3] Figure 2 is a timing chart showing the changes in each signal in the on-timer circuit 14. [Figure 4] This is a block diagram showing the configuration of the DC / DC converter 1A according to a first modified example of the embodiment. [Figure 5] This is a block diagram showing the configuration of the DC / DC converter 1B according to a second modified example of the embodiment. [Figure 6] This is a block diagram showing the configuration of the DC / DC converter 1C according to a third modified example of the embodiment. [Figure 7] This is a block diagram showing the configuration of the DC / DC converter 1D according to a fourth modified example of the embodiment. [Figure 8] This is a block diagram showing the configuration of the DC / DC converter 1E according to a fifth modified example of the embodiment. [Figure 9] This is a block diagram showing the configuration of the DC / DC converter 1F according to a sixth modified example of the embodiment. [Figure 10] This is a block diagram showing a part of the configuration of the on-timer circuit 14A according to a seventh modified example of the embodiment. [Figure 11] This is a block diagram showing the configuration of the on-timer circuit 14B according to the eighth modified example of the embodiment. [Figure 12] This is a block diagram showing the configuration of the on-timer circuit 14C according to the ninth modified example of the embodiment. [Figure 13] This is a block diagram showing the configuration of the DC / DC converter 1G according to the 10th modified example of the embodiment. [Figure 14] This is a block diagram showing the configuration of the DC / DC converter 1H according to the 11th modified example of the embodiment. [Figure 15] This is a block diagram showing the configuration of DC / DC converter 1I in a comparative example. [Figure 16] Figure 15 is a circuit diagram showing the configuration of the on-timer circuit 14I. [Figure 17]A timing chart showing the changes in each signal of the on-timer circuit 14I when the duty ratios of the switching elements Q1 and Q2 in FIG. 15 are 25%. [Figure 18] A timing chart showing the changes in each signal of the on-timer circuit 14I when the duty ratios of the switching elements Q1 and Q2 in FIG. 15 are 50%. [Figure 19] A timing chart showing the changes in each signal of the on-timer circuit 14I when the duty ratios of the switching elements Q1 and Q2 in FIG. 15 are 75%. [Figure 20] A timing chart showing the changes in each signal of the on-timer circuit 14I immediately after the start-up of the DC / DC converter 1I in FIG. 15.

Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Throughout the drawings, similar components are denoted by the same reference numerals.

[0011] [Configuration of Embodiment] Figure 1 is a block diagram showing the configuration of a DC / DC converter 1 according to an embodiment. The DC / DC converter 1 comprises switching elements Q1 and Q2, an inductor L1, a capacitor C1, and a control circuit 10. The switching elements Q1 and Q2 are connected in series with each other between the input voltage source Vdd and ground. The switching elements Q1 and Q2 are provided on the high side and low side, respectively. Switching element Q1 is, for example, a P-channel field-effect transistor, and switching element Q2 is, for example, an N-channel field-effect transistor. The inductor L1 is connected between the node between the switching elements Q1 and Q2 and the output terminal Nout of the DC / DC converter 1. The capacitor C1 is connected between the output terminal Nout of the DC / DC converter 1 and ground. The control circuit 10 generates drive signals S1 and S2 to control the on / off state of each switching element Q1 and Q2, and applies the drive signals S1 and S2 to the control electrodes (gates) of each switching element Q1 and Q2. As a result, the control circuit 10 controls the switching elements Q1 and Q2 to store and release energy in the inductor L1.

[0012] DC / DC converter 1 receives an input voltage Vin from an input voltage source Vdd, generates an output voltage Vout at its output terminal Nout, and supplies the output voltage Vout to the load device 2. DC / DC converter 1 is an example of a step-down converter that generates an output voltage Vout lower than the input voltage Vin.

[0013] The control circuit 10 comprises resistors R11, R12, a reference voltage source E11, a comparator 11, a latch circuit 12, a driver circuit 13, an on-timer circuit 14, and a soft-start circuit 31. The control circuit 10 may be configured as an integrated circuit having terminals N0 to N4.

[0014] Resistors R11 and R12 are voltage divider resistors connected in series with each other. Resistors R11 and R12 divide the output voltage Vout applied via terminal N0 at a predetermined voltage division ratio, and input the divided voltage Vdiv to the inverting input terminal of comparator 11.

[0015] The reference voltage source E11 generates a variable reference voltage Vref11 in response to the signal Sss (described later) output from the soft-start circuit 31 and inputs it to the non-inverting input terminal of the comparator 11. When the signal Sss is at a low level, the reference voltage Vref11 is set to a first value corresponding to the desired voltage to be supplied from the DC / DC converter 1 to the load device 2. On the other hand, when the signal Sss is at a high level, the reference voltage Vref11 is set to slowly increase from a second value (e.g., 0V) lower than the first value to the first value. As a result, the DC / DC converter 1 performs a soft start when it starts up, as will be described later.

[0016] The comparator 11 compares the voltage Vdiv with the reference voltage Vref11 and inputs the signal Scmp, which indicates the comparison result, to the S terminal of the latch circuit 12.

[0017] The R terminal of the latch circuit 12 receives the signal Sot (described later) output from the on-timer circuit 14. The latch circuit 12 generates a signal having a high-level or low-level value represented by a predetermined truth table, according to the signals Scmp and Sot input from the comparator 11 and on-timer circuit 14, respectively, and sends it to the driver circuit 13.

[0018] The driver circuit 13 generates drive signals S1 and S2 and applies them to the control electrodes of switching elements Q1 and Q2 via terminals N1 and N2, respectively. The driver circuit 13 operates the switching elements Q1 and Q2 with constant on-time control. In each switching cycle of switching elements Q1 and Q2, when the voltage Vdiv falls below the reference voltage Vref11, the driver circuit 13 turns on switching element Q1 and turns off switching element Q2 for a predetermined time, thereby accumulating energy in inductor L1 (on-interval). After the on-interval has elapsed, the driver circuit 13 turns off switching element Q1 and turns on switching element Q2, thereby releasing the energy accumulated in inductor L1 (rectification interval). The latch circuit 12 operates according to the signal Sot (described later) output from the on-timer circuit 14, so the driver circuit 13 operates switching elements Q1 and Q2 to terminate the on-interval according to the signal Sot.

[0019] The on-timer circuit 14 receives drive signals S1 and S2, and a signal S3 indicating the voltage at the node between switching elements Q1 and Q2 is input via terminal N3. The on-timer circuit 14 also receives a signal generated by some monitoring circuit that indicates whether the DC / DC converter 1 is in a steady state or an abnormal state. A steady state of the DC / DC converter 1 means that when the DC / DC converter 1 is operating, parameters such as the input voltage Vin, output voltage Vout, and output current Iout are within the desired range. An abnormal state of the DC / DC converter 1 means that when the DC / DC converter 1 is operating, at least one of the parameters such as the input voltage Vin, output voltage Vout, and output current Iout is outside the desired range. In the example in Figure 1, the soft-start circuit 31 is the monitoring circuit, and a signal Sss generated by the soft-start circuit 31 is input to the on-timer circuit 14 as a signal indicating whether the DC / DC converter 1 is in a steady state or an abnormal state.

[0020] The soft-start circuit 31 controls the reference voltage source E11 to ensure that the DC / DC converter 1 performs a soft start when it starts up, in response to a signal Sen input from outside the DC / DC converter 1 via terminal N4. A soft start of the DC / DC converter 1 means that, after the DC / DC converter 1 starts up, the output voltage Vout is slowly increased from 0V to the desired voltage of the load device 2 in order to prevent inrush of input current and overshoot of the output voltage. In this specification, the time period after the DC / DC converter 1 starts up, from when the output voltage Vout slowly increases from 0V to when it reaches the desired voltage of the load device 2, is called the "soft-start period". The soft-start circuit 31 generates a signal Sss indicating whether the DC / DC converter 1 is in the soft-start period and sends it to the reference voltage source E11. For example, when the signal Sss is high level, the DC / DC converter 1 is in the soft-start period, and when the signal Sss is low level, the DC / DC converter 1 is not in the soft-start period. When the DC / DC converter 1 is in the soft-start period, the output voltage Vout is less than the desired voltage of the load device 2, so the DC / DC converter 1 is in an abnormal state. On the other hand, after the soft-start period has elapsed, the output voltage Vout reaches the desired voltage of the load device 2, and it is highly likely that the DC / DC converter 1 is in a steady state. In other words, the signal Sss indicates whether the DC / DC converter 1 is in a steady state or an abnormal state. Also, as mentioned above, the soft-start circuit 31 sends the signal Sss to the on-timer circuit 14.

[0021] The on-timer circuit 14 generates a signal Sot that terminates the ON interval of each switching period of switching elements Q1 and Q2 based on signals S1, S2, S3, and Sss, and sends the signal Sot to the driver circuit 13 via the latch circuit 12. The on-timer circuit 14 generates the signal Sot using different reference voltages depending on the signal Sss, as described below.

[0022] Figure 2 is a circuit diagram showing the configuration of the on-timer circuit 14 in Figure 1. The on-timer circuit 14 comprises inverters 21, 24, 25, NOR gates 22, 23, comparator 26, capacitors C21, C22, reference voltage source E21, switching elements Q21, Q22, resistors R21 to R23, and switches SW21 to SW25.

[0023] The on-timer circuit 14 receives drive signals S1 and S2, as well as a signal S3 indicating the voltage at the node between switching elements Q1 and Q2. The on-timer circuit 14 also receives a signal Sss output from the soft-start circuit 31, which is treated as one of the signals Strg1 to StrgK.

[0024] Switching elements Q21 and Q22 are connected in series with each other between the input voltage source Vdd and ground. Switching elements Q21 and Q22 are provided on the high side and low side, respectively. Switching element Q21 is, for example, a P-channel field-effect transistor, and switching element Q22 is, for example, an N-channel field-effect transistor. Drive signals S1 and S2 are applied to the control electrodes (gates) of each switching element Q21 and Q22, respectively. Switching elements Q21 and Q22 are configured and operate in the same way as switching elements Q1 and Q2. Therefore, switching elements Q21 and Q22 generate a voltage that changes at the node between switching elements Q21 and Q22 in the same way as the voltage at the node between switching elements Q1 and Q2.

[0025] Signal S3 is applied to the node between switching elements Q21 and Q22 via switch SW21. The inverter 21 and NOR circuit 22 turn off switch SW21 when one of switching elements Q21 or Q22 is on, and turn on switch SW21 when both switching elements Q21 and Q22 are off.

[0026] Resistors R21 and R22 are voltage divider resistors connected in series with each other. Resistors R21 and R22 divide the voltage at the node between switching elements Q21 and Q22 at a predetermined voltage division ratio, and the divided voltage charges capacitor C21. When switching elements Q1 and Q2 are operating at a predetermined switching frequency, switching elements Q21 and Q22 also operate at the same switching frequency, and capacitor C21 is charged by the voltage generated by switching elements Q21 and Q22. On the other hand, when both switching elements Q1 and Q2 are turned off (for example, when pulse frequency modulation is used), both switching elements Q21 and Q22 are also turned off, and capacitor C21 is charged by the voltage of signal S3. In either case, the voltage across capacitor C21 changes according to the duty cycle of switching elements Q1 and Q2. The voltage across capacitor C21 is used as a variable reference voltage Vref21. The reference voltage Vref21 is input to the inverting input terminal of comparator 26.

[0027] Switch SW24, resistor R23, and capacitor C22 are connected in series with each other between the input voltage source Vdd and ground. Switch SW24 is turned on / off according to the inverted signal S1, which is inverted by the inverter 25. The ends of capacitor C22 are short-circuited by switch SW25, which is turned on / off according to signal S1. The voltage Vrmp across capacitor C22 gradually increases when the switching element Q1 is on and becomes zero when the switching element Q1 is off. The voltage Vrmp is input to the non-inverting input terminal of comparator 26.

[0028] The NOR circuit 23, inverter 24, reference voltage source E21, and switches SW22, SW23 send a fixed reference voltage Vref22 to the comparator 26 instead of the variable reference voltage Vref21 when the DC / DC converter 1 is in an abnormal state. The reference voltage source E21 generates the fixed reference voltage Vref22. The NOR circuit 23 takes signals Strg1 to StrgK as input from one or more monitoring circuits, indicating whether the DC / DC converter 1 is in a steady state or an abnormal state. In the example in Figure 1, the soft-start circuit 31 is the monitoring circuit, but as an alternative or addition, the NOR circuit 23 may take signals Strg1 to StrgK as input from other monitoring circuits, as described with reference to Figures 4 to 9. The NOR circuit 23 and inverter 24 control switches SW22 and SW23 to send a reference voltage Vref21 to comparator 26 when all signals Strg1 to StrgK are at a low level (i.e., no abnormal condition occurs). The NOR circuit 23 and inverter 24 control switches SW22 and SW23 to send a reference voltage Vref22 to comparator 26 when at least one of signals Strg1 to StrgK is at a high level (i.e., some abnormal condition occurs).

[0029] The comparator 26 generates a signal Sot by comparing the voltage Vrmp with a reference voltage Vref21 or Vref22 and sends it to the latch circuit 12.

[0030] As explained above, the on-timer circuit 14 generates a second control signal Sot based on the first control signal Sss, which terminates the ON interval of each switching period of the switching elements Q1 and Q2, and sends it to the driver circuit 13. When the DC / DC converter 1 is in a steady state, the on-timer circuit 14 generates the control signal Sot using a first reference voltage Vref21 that changes according to the duty cycle of the switching elements Q1 and Q2. When the DC / DC converter 1 is in an abnormal state, the on-timer circuit 14 generates the control signal Sot using a fixed second reference voltage Vref22.

[0031] According to the control circuit 10 of the DC / DC converter 1 according to this embodiment, by including the on-timer circuit 14 shown in Figure 2, even when the operation of the switching elements Q1 and Q2 deviates from their steady state, the DC / DC converter 1 can be controlled to perform constant on-time control with a reduced fluctuation in the switching frequency compared to conventional methods. The operation of the control circuit 10 of the DC / DC converter 1 according to this embodiment will be described in more detail below with reference to a DC / DC converter according to a comparative example.

[0032] [Comparative Example] Next, referring to Figures 15 to 20, the configuration and operation of a comparative example DC / DC converter that does not have the on-timer circuit 14 according to the embodiment will be described.

[0033] Figure 15 is a block diagram showing the configuration of a DC / DC converter 1I in a comparative example. The DC / DC converter 1I includes an on-timer circuit 14I instead of the on-timer circuit 14 in Figure 1. The signal Sss generated by the soft-start circuit 31 is not input to the on-timer circuit 14I.

[0034] Figure 16 is a circuit diagram showing the configuration of the on-timer circuit 14I in Figure 15. The on-timer circuit 14I has a configuration that removes the NOR circuit 23, inverter 24, reference voltage source E21, and switches SW22 and SW23 from the on-timer circuit 14 in Figure 2. The on-timer circuit 14I generates the signal Sot using only the variable reference voltage Vref21.

[0035] Figure 17 is a timing chart showing the changes in each signal of the on-timer circuit 14I when the duty cycle of switching elements Q1 and Q2 in Figure 15 is 25%. Figure 18 is a timing chart showing the changes in each signal of the on-timer circuit 14I when the duty cycle of switching elements Q1 and Q2 in Figure 15 is 50%. Figure 19 is a timing chart showing the changes in each signal of the on-timer circuit 14I when the duty cycle of switching elements Q1 and Q2 in Figure 15 is 75%. Signals S1, S2, and Sot transition between high level (H) and low level (L). Voltage Vrmp gradually increases when switching element Q1 is turned on and becomes zero when switching element Q1 is turned off. The reference voltage Vref21 changes according to the duty cycle of switching elements Q1 and Q2. When voltage Vrmp reaches the reference voltage Vref21, signal Sot transitions from low level to high level. As shown in Figures 17 to 19, when the DC / DC converter 1 is in a steady state, the ON-interval is terminated by comparing the voltage Vrmp with the variable reference voltage Vref21, and the switching elements Q1 and Q2 can be operated at a constant switching frequency.

[0036] Figure 20 is a timing chart showing the changes in each signal of the on-timer circuit 14I immediately after startup of the DC / DC converter 1I shown in Figure 15. Figure 20 shows the case immediately after startup of the DC / DC converter 1I where the output voltage Vout is near 0V, the reference voltage Vref21 is extremely low, and as a result the period for ending the ON section becomes very short. As mentioned above, the reference voltage Vref21 changes according to the duty cycle of the switching elements Q1 and Q2. Therefore, for example, immediately after startup of the DC / DC converter 1I, or when the ground fault protection circuit is operating, if the operation of the switching elements Q1 and Q2 deviates from their steady state, it is not possible to operate the switching elements Q1 and Q2 at the desired switching frequency.

[0037] [Operation of the Embodiment] Figure 3 is a timing chart showing the changes in each signal in the on-timer circuit 14 of Figure 2. According to the control circuit 10 of the DC / DC converter 1 in this embodiment, the on-timer circuit 14 of Figure 2 is provided, allowing for the selective use of a variable reference voltage Vref21 and a fixed reference voltage Vref22. When the DC / DC converter 1 is in the soft-start period, i.e., when the signal Sss is at a high level, the fixed reference voltage Vref22 is used, and when the signal Sss is at a low level, the variable reference voltage Vref21 is used. When the voltage Vrmp reaches the reference voltage Vref21 or Vref22, the signal Sot transitions from a low level to a high level. In this way, by selectively using the variable reference voltage Vref21 and the fixed reference voltage Vref22, the switching elements Q1 and Q2 operate at the desired switching frequency. According to the control circuit 10 of the DC / DC converter 1 according to the embodiment, even when the operation of switching elements Q1 and Q2 deviates from its steady state, the DC / DC converter 1 can be controlled to perform constant on-time control with a reduced fluctuation in switching frequency compared to conventional methods. According to the control circuit 10 of the DC / DC converter 1 according to the embodiment, even when the operation of switching elements Q1 and Q2 deviates from its steady state, the DC / DC converter 1 can preferably be controlled to perform constant on-time control at a constant switching frequency.

[0038] [Variations of monitoring circuits] As mentioned above, in the example in Figure 1, the soft-start circuit 31 is the monitoring circuit, but as an alternative or addition, the NOR circuit 23 in Figure 2 may take signals Strg1 to StrgK as input from other monitoring circuits, which will be explained with reference to Figures 4 to 9.

[0039] Figure 4 is a block diagram showing the configuration of a DC / DC converter 1A according to a first modification of the embodiment. The DC / DC converter 1A includes a control circuit 10A instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10A includes a voltage drop detector 32 and a delay circuit 33. In Figures 4 to 9, the soft start circuit 31 is not shown. The voltage drop detector 32 is an example of a monitoring circuit. The voltage drop detector 32 acquires the input voltage Vin of the DC / DC converter 1A via terminal N5 and detects the magnitude of the input voltage Vin. The voltage drop detector 32 generates a signal Suvin indicating whether the input voltage Vin is in a steady state (above or below a threshold) or in an abnormal state (below the threshold), and sends the signal Suvin to the on-timer circuit 14 via the delay circuit 33. For example, when the input voltage Vin is above the threshold, the signal Suvin is set to a low level, and when the input voltage Vin is below the threshold, the signal Suvin is set to a high level. The signal Suvin is treated as one of the signals Strg1 to StrgK that are input to the NOR gate 23.

[0040] Figure 5 is a block diagram showing the configuration of a DC / DC converter 1B according to a second modification of the embodiment. The DC / DC converter 1B includes a control circuit 10B instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10B includes a voltage drop detector 34. The voltage drop detector 34 is an example of a monitoring circuit. The voltage drop detector 34 generates a signal Suvout indicating whether the output voltage Vout is in a steady state (above or below a threshold) or in an abnormal state (below the threshold) and sends it to the on-timer circuit 14. For example, when the output voltage Vout is above the threshold, the signal Suvout is set to a low level, and when the output voltage Vout is below the threshold, the signal Suvout is set to a high level. The signal Suvout is treated as one of the signals Strg1 to StrgK input to the NOR circuit 23.

[0041] Figure 6 is a block diagram showing the configuration of a DC / DC converter 1C according to a third modified example of the embodiment. The DC / DC converter 1C includes a control circuit 10C instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10C includes a transient response detector 35. The transient response detector 35 is an example of a monitoring circuit. The transient response detector 35 uses the output voltage Vout to determine the DC / DC converter 1C The transient response detector 35 detects whether the DC / DC converter 1C is in a transient response state due to the load device 2. A transient response state means that the output voltage Vout fluctuates significantly over a predetermined time period due to the transient response of the load device 2 connected to the output terminal Nout of the DC / DC converter 1C. 1C It generates a signal Sus indicating whether it is in a transient response state, i.e., an abnormal state, or a steady state, and sends it to the on-timer circuit 14. For example, a DC / DC converter 1C When the system is in a transient response state, the signal Sus is set to a high level; otherwise, the signal Sus is set to a low level. The signal Sus is treated as one of the signals Strg1 to StrgK input to the NOR gate 23.

[0042] Figure 7 is a block diagram showing the configuration of a DC / DC converter 1D according to a fourth modified example of the embodiment. The DC / DC converter 1D includes a control circuit 10D instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10D includes a peak current detector 36. The peak current detector 36 is an example of a monitoring circuit. The peak current detector 36 is connected to the input voltage source Vdd via terminal N6 and to the node between switching elements Q1 and Q2 via terminal N3. The peak current detector 36 obtains the output current Iout (or current flowing through inductor L1) of the DC / DC converter 1D by monitoring the voltage across the switching element Q1 when the switching element Q1 is turned on, and detects the magnitude of the peak of the output current Iout. The peak current detector 36 generates a signal Spc indicating whether the peak of the output current Iout is above a threshold value (a steady state) or below a threshold value (an abnormal state) and sends it to the on-timer circuit 14. For example, when the peak of the output current Iout is greater than or equal to the threshold, the signal Spc is set to a low level, and when the peak of the output current Iout is less than the threshold, the signal Spc is set to a high level. The signal Spc is treated as one of the signals Strg1 to StrgK that are input to the NOR gate 23.

[0043] Figure 8 is a block diagram showing the configuration of a DC / DC converter 1E according to a fifth modified example of the embodiment. The DC / DC converter 1E includes a control circuit 10E instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10E includes a zero current detector 37. The zero current detector 37 is an example of a monitoring circuit. The zero current detector 37 is connected to the node between switching elements Q1 and Q2 via terminal N3 and grounded via terminal N7. The zero current detector 37 obtains the output current Iout of the DC / DC converter 1E by monitoring the voltage across the switching element Q2 when the switching element Q2 is turned on, and detects the direction in which the output current Iout flows. The zero current detector 37 generates a signal Szc indicating whether the output current Iout is in a steady state flowing from the switching element Q2 towards the output terminal Nout, or in an abnormal state flowing in the reverse direction, and sends it to the on-timer circuit 14. For example, when the output current Iout flows from the switching element Q2 towards the output terminal Nout, the signal Szc is set to a low level, and when the output current Iout flows in the reverse direction, the signal Szc is set to a high level. The signal Szc is treated as one of the signals Strg1 to StrgK input to the NOR circuit 23.

[0044] Figure 9 is a block diagram showing the configuration of a DC / DC converter 1F according to a sixth modified example of the embodiment. The DC / DC converter 1F includes a control circuit 10F instead of the control circuit 10 in Figure 1. In addition to the components of Figure 1, the control circuit 10F includes a reverse current detector 38. The reverse current detector 38 is an example of a monitoring circuit. The reverse current detector 38 is connected to the node between switching elements Q1 and Q2 via terminal N3 and grounded via terminal N7. The reverse current detector 38 obtains the output current Iout of the DC / DC converter 1F by monitoring the voltage across the switching element Q2 when the switching element Q2 is turned on, and detects the direction and magnitude of the output current Iout. The reverse current detector 38 generates a signal Src indicating whether the output current Iout is in a steady state flowing from the switching element Q2 towards the output terminal Nout, or in an abnormal state flowing in the reverse direction and greater than a threshold, and sends it to the on-timer circuit 14. For example, when the output current Iout flows from the switching element Q2 towards the output terminal Nout, the signal Src is set to a low level, and when the output current Iout flows in the reverse direction and is greater than the threshold, the signal Src is set to a high level. The signal Src is treated as one of the signals Strg1 to StrgK input to the NOR circuit 23.

[0045] According to the modified control circuits 10A to 10F of DC / DC converters 1A to 1F, similar to the control circuit 10 in Figure 1, a control signal Sot that terminates the ON section can be generated by selectively using a variable reference voltage Vref21 and a fixed reference voltage Vref22. As a result, even when the operation of switching elements Q1 and Q2 deviates from its steady state, the DC / DC converters 1A to 1F can be controlled to perform constant on-time control with a reduced fluctuation in switching frequency compared to conventional methods.

[0046] The configurations described with reference to Figures 1, 4 to 9 may be combined. The NOR circuit 23 in Figure 2 may acquire signals Strg1 to StrgK as input from multiple monitoring circuits. This makes it possible to detect multiple events indicating whether the DC / DC converter is in a steady state or an abnormal state.

[0047] [Differential examples of on-timer circuits] Figure 10 is a block diagram showing a part of the configuration of an on-timer circuit 14A according to a seventh modification of the embodiment. The on-timer circuit 14A may be equipped with reference voltage sources E21-1 to E21-K and switches SW23-1 to SW23-K as shown in Figure 10, instead of the inverter 24, reference voltage source E21, and switch SW23 in Figure 2. The reference voltage sources E21-1 to E21-K generate a plurality of different reference voltages Vref22-1 to Vref22-K. The on-timer circuit 14A can generate a control signal Sot using a plurality of different reference voltages Vref22-1 to Vref22-K, each corresponding to a plurality of events. This allows for the use of an appropriate reference voltage depending on the event when detecting a plurality of events that indicate whether the DC / DC converter is in a steady state or an abnormal state.

[0048] Figure 11 is a block diagram showing the configuration of an on-timer circuit 14B according to the eighth modified embodiment. The on-timer circuit 14B includes a delay circuit 27 instead of the switch S21 in Figure 2. The output signal of the NOR circuit 22 is transmitted to the NOR circuit via the delay circuit 27. 23 This is input to the on-timer circuit 14B. As a result, when the on-timer circuit 14B starts switching operation from a state where switching elements Q1 and Q2 are simultaneously turned off, it can generate a control signal Sot using a fixed reference voltage Vref22 for a certain period of time after the switching operation starts.

[0049] Figure 12 is a block diagram showing the configuration of the on-timer circuit 14C according to the ninth modified embodiment. The on-timer circuit 14C has a configuration in which the inverter 21, NOR circuit 22, switching elements Q21, Q22, and switch SW21 of Figure 2 are removed. As a result, the on-timer circuit 14C has a simpler circuit configuration than the on-timer circuit 14 of Figure 2, and its size and cost can be reduced.

[0050] [Diagram of a DC / DC converter] Figures 1 to 12 show examples of DC / DC converters, which are step-down converters. On the other hand, the control of the DC / DC converter according to the embodiment is also applicable to step-up converters or step-up / step-down converters.

[0051] Figure 13 is a block diagram showing the configuration of a DC / DC converter 1G according to a tenth modified example of the embodiment. The DC / DC converter 1G comprises switching elements Q11 and Q12, an inductor L1, a capacitor C1, and a control circuit 10G. The inductor L1 and the switching element Q11 are connected in series with each other between the input voltage source Vdd and ground. The switching element Q12 is connected between the node between the inductor L1 and the switching element Q11 and the output terminal Nout of the DC / DC converter 1G. The switching elements Q11 and Q12 are provided on the low side and high side, respectively. The switching element Q11 is, for example, an N-channel field-effect transistor, and the switching element Q12 is, for example, a P-channel field-effect transistor. The capacitor C1 is connected between the output terminal Nout of the DC / DC converter 1G and ground. The control circuit 10G generates drive signals S11 and S12 to control the on / off state of each switching element Q11 and Q12, and applies the drive signals S11 and S12 to the control electrodes (gates) of each switching element Q11 and Q12. In this way, the control circuit 10G controls the switching elements Q11 and Q12 to store and release energy relative to the inductor L1.

[0052] DC / DC converter 1G is an example of a boost converter that generates an output voltage Vout that is higher than the input voltage Vin.

[0053] The control circuit 10G includes a driver circuit 13G and an on-timer circuit 14G, instead of the driver circuit 13 and on-timer circuit 14 shown in Figure 1.

[0054] The driver circuit 13G generates drive signals S11 and S12 and applies them to the control electrodes of switching elements Q11 and Q12 via terminals N11 and N12, respectively. The driver circuit 13G operates the switching elements Q11 and Q12 with constant on-time control. In each switching cycle of switching elements Q11 and Q12, when the voltage Vdiv falls below the reference voltage Vref11, the driver circuit 13G turns on switching element Q11 and turns off switching element Q12 for a predetermined time, thereby accumulating energy in inductor L1 (on-interval). After the on-interval has elapsed, the driver circuit 13G turns off switching element Q11 and turns on switching element Q12, thereby releasing the energy accumulated in inductor L1 (rectification interval). Furthermore, since the latch circuit 12 operates in response to the signal Sot, the driver circuit 13G operates the switching elements Q11 and Q12 to terminate the ON period according to the signal Sot.

[0055] The on-timer circuit 14G receives drive signals S11 and S12, and a signal S13 indicating the output voltage Vout is input via terminal N13. The on-timer circuit 14G also receives a signal Sss generated by the soft-start circuit 31. Based on signals S11, S12, S13, and Sss, the on-timer circuit 14G generates a signal Sot and sends it to the driver circuit 13G via the latch circuit 12. Similar to the on-timer circuit 14 in Figure 1, the on-timer circuit 14G generates the signal Sot by selectively using different reference voltages, namely a variable reference voltage and a fixed reference voltage, depending on the signal Sss. Within the on-timer circuit 14G, signals S11, S12, and S13 generally correspond to signals S1, S2, and S3 in Figure 2, respectively. The on-timer circuit 14G may include two switching elements that operate in response to signals S11 and S12, respectively, to generate a variable reference voltage, similar to the on-timer circuit 14 in Figure 2, or it may use signal S3, similar to the on-timer circuit 14C in Figure 12.

[0056] According to the control circuit 10G in Figure 13, similar to the control circuit 10 in Figure 1, a control signal Sot that terminates the ON period can be generated by selectively using a variable reference voltage and a fixed reference voltage. As a result, even when the operation of switching elements Q11 and Q12 deviates from its steady state, the DC / DC converter 1G can be controlled to perform constant on-time control with a reduced fluctuation in switching frequency compared to conventional methods.

[0057] In the example shown in Figure 13, the soft-start circuit 31 is the monitoring circuit, but the DC / DC converter 1G, which is a boost converter, may be equipped with other monitoring circuits as described with reference to Figures 4 to 9, either as an alternative or addition.

[0058] Figure 14 is a block diagram showing the configuration of a DC / DC converter 1H according to an eleventh modification of the embodiment. The DC / DC converter 1H comprises switching elements Q1, Q2, Q11, Q12, an inductor L1, a capacitor C1, and a control circuit 10H. The switching elements Q1, Q2 and inductor L1 in Figure 14 operate as part of a buck converter, similar to the corresponding components in Figure 1. The switching elements Q11, Q12 and inductor L1 in Figure 14 operate as part of a boost converter, similar to the corresponding components in Figure 13. The control circuit 10H has the functions of both the control circuit 10 in Figure 1 and the control circuit 10G in Figure 13. The DC / DC converter 1H is an example of a buck-boost converter that generates both an output voltage Vout lower than the input voltage Vin and an output voltage Vout higher than the input voltage Vin. According to the control circuit 10H in Figure 14, similar to the control circuit 10 in Figure 1 and the control circuit 10G in Figure 13, even when the operation of switching elements Q1, Q2, Q11, and Q12 deviates from its steady state, the DC / DC converter 1H can be controlled to perform constant on-time control with a reduced fluctuation in switching frequency compared to conventional methods.

[0059] [Other variations] In the example shown in Figure 1, the switching elements Q1 and Q2 are located outside the integrated circuit having terminals N0 to N8, but the switching elements Q1 and Q2 may also be integrated inside the control circuit 10.

[0060] The resistor R21 may be configured to have an adjustable resistance value. The reference voltage source E21 may be configured to have an adjustable voltage value.

[0061] In Figure 1, etc., a signal S3 indicating the voltage at the node between switching elements Q1 and Q2 is used to generate a reference voltage Vref21 that changes according to the duty cycle of switching elements Q1 and Q2. However, the output voltage Vout may be used instead of signal S3.

[0062] [Summary of Embodiments] The control circuit 10 of a DC / DC converter 1 according to a first aspect of this disclosure controls a DC / DC converter 1 comprising an inductor L1 and first and second switching elements Q1 and Q2 that store and release energy relative to the inductor L1. The control circuit 10 comprises a driver circuit 13, a monitoring circuit, and an on-timer circuit 14. The driver circuit 13 operates the first and second switching elements Q1 and Q2 in constant on-time control. The monitoring circuit generates a first control signal indicating whether the DC / DC converter 1 is in a steady state or an abnormal state. Based on the first control signal, the on-timer circuit 14 generates a second control signal that terminates a portion of the switching cycle of the first and second switching elements Q1 and Q2, specifically the section in which energy is stored relative to the inductor L1, and sends it to the driver circuit 13. When the DC / DC converter 1 is in a steady state, the on-timer circuit 14 generates a second control signal using a first reference voltage that changes according to the duty cycle of the first and second switching elements Q1 and Q2. The on-timer circuit 14 generates a second control signal using a fixed second reference voltage when the DC / DC converter 1 is in an abnormal state.

[0063] According to the control circuit 10 of the DC / DC converter 1 in the second aspect of this disclosure, the control circuit in the first aspect may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the DC / DC converter 1 is in a soft-start period.

[0064] According to the control circuit 10 of the DC / DC converter 1 in the third aspect of this disclosure, the control circuit in the first or second aspect may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the input voltage of the DC / DC converter 1 is lower than a first threshold.

[0065] According to the control circuit 10 of the DC / DC converter 1 in the fourth aspect of this disclosure, the control circuit in one of the first to third aspects may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the output voltage of the DC / DC converter 1 is lower than a second threshold.

[0066] According to the control circuit 10 of the DC / DC converter 1 in the fifth aspect of this disclosure, the control circuit in one of the first to fourth aspects may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the DC / DC converter 1 is in a transient response state due to a load.

[0067] According to the control circuit 10 of the DC / DC converter 1 in the sixth aspect of this disclosure, the control circuit in one of the first to fifth aspects may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the peak of the output current of the DC / DC converter 1 is smaller than a third threshold.

[0068] According to the control circuit 10 of the DC / DC converter 1 in the seventh aspect of this disclosure, the control circuit according to one of the first to sixth aspects may be configured as follows: When the monitoring circuit detects a reverse current in the output current of the DC / DC converter 1, it generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state.

[0069] According to the control circuit 10 of the DC / DC converter 1 in the eighth aspect of this disclosure, the control circuit in one of the first to seventh aspects may be configured as follows: The monitoring circuit generates a first control signal indicating that the DC / DC converter 1 is in an abnormal state when the output current of the DC / DC converter 1 is flowing in reverse and is greater than a fourth threshold.

[0070] According to the control circuit 10 of the DC / DC converter 1 in the ninth aspect of this disclosure, the control circuit in one of the first to eighth aspects may be configured as follows: The monitoring circuit detects a plurality of events, each indicating that the DC / DC converter 1 is in an abnormal state. The on-timer circuit 14 corresponds to each of the plurality of events and generates a control signal using a plurality of second reference voltages that are different from each other.

[0071] According to the control circuit 10 of the DC / DC converter 1 according to the tenth aspect of this disclosure, the control circuit according to one of the first to ninth aspects may be configured as follows. When the on-timer circuit 14 starts switching operation from a state in which the first and second switching elements Q1 and Q2 are simultaneously turned off, it generates a control signal using a fixed second reference voltage for a certain period of time after the switching operation has started.

[0072] A DC / DC converter 1 according to the eleventh aspect of this disclosure comprises first and second switching elements Q1 and Q2 provided on the high side and low side, respectively, and a control circuit 10 according to one of the first to tenth aspects. [Explanation of symbols]

[0073] 1.1A~1I DC / DC converter 2 Load device 10, 10A~10I control circuit 11 Comparator 12. Latch Circuit 13,13G driver circuit 14, 14A~14C, 14G, 14I On-timer circuit 21, 24, 25 Inverter 22,23 Negative OR (NOR) Circuit 26 Comparator 27 Delay Circuit 31 Soft-start circuit 32 Voltage drop detector 33 Delay Circuit 34 Voltage drop detector 35 Transient Response Detector 36. Peak current detector 37. Zero-current detector 38 Reverse current detector C1, C21, C22 Capacitors E11, E21, E21-1~E21-K Reference Voltage Source L1 Inductor Q1, Q2, Q11, Q12, Q21, Q22 Switching elements R11,R12,R21~R23 Resistor SW21~SW23, SW23-1~SW23-K, SW24, SW25 switches

Claims

1. In a control circuit for controlling a DC / DC converter comprising an inductor and first and second switching elements for storing and releasing energy relative to the inductor, The aforementioned control circuit is A driver circuit that operates the first and second switching elements with constant on-time control, A monitoring circuit that generates a first control signal indicating whether the DC / DC converter is in a steady state or an abnormal state, The system includes an on-timer circuit that, based on the first control signal, generates a second control signal to terminate a portion of the switching cycle of the first and second switching elements, which is a portion of the period in which energy is stored in the inductor, and sends this signal to the driver circuit. The aforementioned ON Timer Circuit When the DC / DC converter is in a steady state, the control signal is generated using a first reference voltage that changes according to the duty cycle of the first and second switching elements. If the DC / DC converter is in an abnormal state, the control signal is generated using a fixed second reference voltage. Control circuit for a DC / DC converter.

2. The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the DC / DC converter is in a soft-start period. Control circuit for a DC / DC converter according to claim 1.

3. The monitoring circuit generates a first control signal indicating that the DC / DC converter is in an abnormal state when the input voltage of the DC / DC converter is lower than a first threshold. Control circuit for a DC / DC converter according to claim 1.

4. The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the output voltage of the DC / DC converter is lower than a second threshold. Control circuit for a DC / DC converter according to claim 1.

5. The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the DC / DC converter is in a transient response state due to the load. Control circuit for a DC / DC converter according to claim 1.

6. The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the peak output current of the DC / DC converter is less than a third threshold. Control circuit for a DC / DC converter according to claim 1.

7. The monitoring circuit, upon detecting a reverse current in the output current of the DC / DC converter, generates the first control signal indicating that the DC / DC converter is in an abnormal state. Control circuit for a DC / DC converter according to claim 1.

8. The monitoring circuit generates the first control signal indicating that the DC / DC converter is in an abnormal state when the output current of the DC / DC converter is flowing in reverse and is greater than a fourth threshold. Control circuit for a DC / DC converter according to claim 1.

9. The monitoring circuit detects a number of events, each indicating that the DC / DC converter is in an abnormal state. The on-timer circuit generates the second control signal using a plurality of second reference voltages that correspond to each of the plurality of events and are different from each other. Control circuit for a DC / DC converter according to claim 1.

10. When the on-timer circuit starts switching operation from a state in which the first and second switching elements are simultaneously turned off, it generates the second control signal using a fixed second reference voltage for a certain period of time after the switching operation has started. Control circuit for a DC / DC converter according to claim 1.

11. Inductor and First and second switching elements that store and release energy in relation to the inductor, A control circuit according to one of claims 1 to 10, DC / DC converter.

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