Evaluation method for the operation simulation of semiconductor devices

Abstract

This invention provides a method for evaluating the operation simulation of semiconductor devices, which allows for the appropriate evaluation of the accuracy and problems associated with such simulations. [Solution] A method for evaluating the operation simulation of a semiconductor element, comprising: a first determination step of determining whether the results of the operation simulation for the first element are accurate based on a comparison of the output results of an operation simulation for the first element to which the minimum dimensions of the semiconductor element are applied and the output results of actual measurements for the first element; and a second determination step of performing an operation simulation for the second element using element parameters extracted by layout parasitic extraction technology to which the actual dimensions of the semiconductor element are applied, and determining whether the results of the operation simulation for the second element are accurate based on a comparison of the output results of the operation simulation for the second element and the output results of actual measurements for the second element.

Description

Technical Field

[0001] The present invention relates to a method for evaluating the operation simulation of semiconductor devices.

Background Art

[0002] An evaluation technique for the operation simulation of semiconductor devices using a ring oscillator (ROSC) is known. A ring oscillator is an oscillation circuit configured in a ring shape by connecting an odd number of inverter circuits using PMOS transistors and NMOS transistors and feeding back the output of the last inverter to the input of the first inverter. An inverter circuit is a circuit that inverts and outputs an input signal. When the input is "1" (high potential), the output becomes "0" (low potential), and vice versa. In a ring oscillator, by setting the number of stages of the inverter circuits connected in series to an odd number, the overall output has an inversion relationship with the input, so feedback always repeats inversion and oscillation occurs.

[0003] Each inverter circuit has a slight delay (propagation delay time) due to transistor characteristics and parasitic capacitance of wiring. Due to this delay, it takes time for the output of each inverter circuit to be transmitted to the next-stage inverter circuit, and each time the signal circulates through the ring oscillator, inversion and delay by the inverter are added, resulting in continuous oscillation. The oscillation frequency f at this time is represented by f = 1 / (2Nt pd using the number of inverter stages N and the delay time t df ) of each stage. The oscillation frequency f (the reciprocal of the signal circulation speed) depends on the structure of the ring oscillator and the delay of each inverter circuit. Therefore, by inputting a pulse signal to the ring oscillator to cause oscillation and measuring the oscillation frequency with an oscilloscope or a frequency counter, it is possible to confirm the influence of the characteristics of the device and wiring delay based on the oscillation frequency.

[0004] A technique has been disclosed in which a ring oscillator is used to compare the simulation results of an element model with the test results using an actual element, and if the difference between the results does not meet a threshold, the device model is repeatedly optimized until the difference meets the threshold (Patent Document 1). Furthermore, a technique has been disclosed in which a reference ring oscillator corresponding to each critical voltage unit is determined based on the measured value of the ring oscillator and the simulated value of the ring oscillator (Patent Document 2). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Chinese Patent Application Publication No. 117910402 Specification [Patent Document 2] Chinese Patent Application Publication No. 113378501 Specification [Overview of the project] [Problems that the invention aims to solve]

[0006] Incidentally, the difference between the results of semiconductor device operation simulations and actual measurement results is often thought to be due to factors such as RC extraction technology and the layout dependency of MOS.

[0007] RC (Resistance Control) technology extracts parasitic resistance (R) and capacitance (C) from the circuit layout pattern. The values ​​of parasitic resistance (R) and capacitance (C) extracted by RC technology depend on various elements of the circuit layout, such as the length and width of the wiring, the distance between layers, and the spacing between adjacent wirings.

[0008] Furthermore, the MOS center model is a model of typical device characteristics measured on a test chip (test key) to represent the characteristics of a MOS transistor. Simulation and measurement of semiconductor device operation using the MOS center model are performed using a standard device structure with specific L (gate length) and W (gate width), such as minimum dimensions. The center model reflects ideal conditions and does not reflect the influence of actual device layout and wiring, leading to discrepancies in operation simulations and measurements due to layout dependency.

[0009] Therefore, it is necessary to improve the accuracy of semiconductor device operation simulations by appropriately evaluating the accuracy and problems associated with them. [Means for solving the problem]

[0010] One aspect of the present invention is a method for evaluating the operation simulation of a semiconductor element, comprising: a first determination step of determining whether the results of the operation simulation for a first element are accurate based on a comparison of the output results of the operation simulation for a first element to which the minimum dimensions of the semiconductor element are applied and the output results of actual measurements for the first element; and, if it is determined in the first determination step that the operation simulation for the first element is inaccurate, a second determination step of performing an operation simulation for a second element using element parameters extracted by layout parasitic extraction technology to which the actual dimensions of the semiconductor element are applied, and determining whether the results of the operation simulation for the second element are accurate based on a comparison of the output results of the operation simulation for the second element and the output results of actual measurements for the second element. This is a method for evaluating the operation simulation of a semiconductor element, characterized in that, in the first determination step, if the result of the operation simulation for the first element is determined to be accurate, it is determined that the operation simulation using the minimum dimensions of the semiconductor element is accurate; if the result of the operation simulation for the first element is determined to be inaccurate in the first determination step, and the result of the operation simulation for the second element is determined to be accurate in the second determination step, it is determined that the operation simulation using the layout parasitic extraction technique applying the actual dimensions of the semiconductor element and the extracted element parameters is accurate; and if the result of the operation simulation for the second element is determined to be inaccurate in the second determination step, it is determined that the layout parasitic extraction technique applying the actual dimensions of the semiconductor element needs to be modified.

[0011] In this case, the semiconductor element is preferably a MOSFET.

[0012] Furthermore, in the first determination step, it is preferable to perform an operation simulation and actual measurement of the first element using a ring oscillator, and to determine whether the results of the operation simulation for the first element are accurate based on the oscillation frequency of the ring oscillator.

[0013] Furthermore, in the second determination step, it is preferable to perform an operation simulation and actual measurement of the second element using a ring oscillator, and to determine whether the results of the operation simulation for the second element are accurate based on the oscillation frequency of the ring oscillator.

[0014] Furthermore, the first determination step preferably involves simulating the first element, obtaining the simulation results of the first element, performing actual measurements on the first element, obtaining the actual measurement results of the first element, and determining whether the simulation results of the first element are accurate.

[0015] Furthermore, the step of determining whether the simulation results of the first element are accurate preferably involves comparing the simulation results of the first element with the actual measurement results of the first element, determining that the simulation of the first element is accurate if the difference in the results is less than a predetermined reference value, and determining that the simulation of the first element is inaccurate if the difference in the results is equal to or greater than the reference value.

[0016] Furthermore, the first element is preferably a ring oscillator configured based on the inverter layout based on minimum dimensions.

[0017] Furthermore, the second determination step preferably involves simulating the second element, obtaining the simulation results of the second element, performing actual measurements on the second element, obtaining the actual measurement results of the second element, and determining whether the simulation results of the second element are accurate.

[0018] Furthermore, the step of determining whether the simulation results of the second element are accurate preferably involves comparing the simulation results of the second element with the actual measurement results of the second element, determining that the simulation of the second element is accurate if the difference in the results is less than a predetermined reference value, and determining that the simulation of the second element is inaccurate if the difference in the results is equal to or greater than the reference value.

[0019] Further, the second element is Actual dimensions of semiconductor devices preferably a ring oscillator configured based on the layout of an inverter based on

Advantages of the Invention

[0020] According to the present invention, it is possible to provide a method for evaluating the operation simulation of a semiconductor element that can appropriately evaluate the accuracy and problems of the operation simulation of the semiconductor element.

Brief Description of the Drawings

[0021] [Figure 1] It is a flowchart showing a method for evaluating the operation simulation of a semiconductor element in an embodiment of the present invention. [Figure 2] It is a diagram showing a configuration example of an inverter. [Figure 3] It is a diagram showing a configuration example of a ring oscillator. [Figure 4] It is a diagram showing a configuration example of the layout of an inverter based on actual dimensions.

Embodiments for Carrying Out the Invention

[0022] The method for evaluating the operation simulation of a semiconductor element in an embodiment of the present invention is executed according to the flowchart shown in FIG. 1. Hereinafter, the method for evaluating the operation simulation of a semiconductor element will be described while referring to FIG. 1.

[0023] The evaluation of the operation of the semiconductor element is performed using a ring oscillator (ROSC: Ring Oscillator). FIG. 2 shows a configuration example of an inverter 100 that constitutes the ring oscillator. FIG. 3 shows a ring oscillator 200 formed by combining the inverters 100 and a partially enlarged view thereof.

[0024] The inverter 100 is composed of a combination of PMOS and NMOS transistors. The inverter 100 includes a power line 10, a ground line 12, a signal line 14, a P source 16, a P drain 18, an N source 20, an N drain 22, and a gate 24. The P source 16 of the PMOS is connected to the power line 10. The N source 20 of the NMOS is connected to the ground line 12. The gate 24, which is common to both the PMOS and NMOS transistors, is connected to the signal line 14. The P drain 18 of the PMOS is connected to the N drain 22 of the NMOS transistor.

[0025] In inverter 100, when the signal applied to signal line 14 is low (0V), the PMOS is on and the NMOS is off, and the output is pulled up to the power supply voltage (VDD) and becomes high (VDD). When the signal applied to signal line 14 is high (VDD), the PMOS is off and the NMOS is on, and the output is grounded and becomes low (GND).

[0026] The ring oscillator 200 is constructed by combining multiple inverters 100 in an odd number of stages. The ring oscillator 200 is formed in a ring shape by feeding back the output of the last inverter 100 to the input of the first inverter 100. In the ring oscillator 200, by making the number of stages of inverters 100 connected in series odd, the overall output is inverted relative to the input, and the feedback is constantly inverted, causing oscillation.

[0027] As described above, the oscillation frequency f of the ring oscillator 200 is determined by the number of inverter stages N and the delay time t of each stage. pd Using this, f = 1 / (2Nt df This is represented as ( ). This oscillation frequency f (the reciprocal of the signal's circuit speed) depends on the structure of the ring oscillator 200 and the delay of each inverter 100. Therefore, by inputting a pulse signal to the ring oscillator 200 to cause oscillation and measuring the oscillation frequency f with an oscilloscope or frequency counter, the characteristics of the elements and the effect of wiring delay can be confirmed based on the oscillation frequency f.

[0028] When evaluating the operation simulator of a semiconductor device, the results of the operation simulation for the ring oscillator 200 are compared with the measured values ​​when the ring oscillator 200 is actually operated to confirm whether it is oscillating at the designed frequency and to check the degree of error between the simulation results and the measured results. If the error is large, the accuracy of the device model and parasitic elements in the operation simulation is re-evaluated. The criterion value for judging the magnitude of the error should be set appropriately according to the required accuracy of the operation simulation.

[0029] In step S10, the ring oscillator 200 is configured by applying the layout of the inverter 100 based on standard design rules (minimum dimensions), and an operational simulation is performed for the ring oscillator 200. That is, an operational simulation is performed for the ring oscillator 200 configured by connecting the inverter 100 to which the minimum dimensions allowed by the process are applied. For example, the operational simulation is performed for the ring oscillator 200 at an oscillation frequency f. The operational simulation can be performed using, for example, SPICE.

[0030] In step S12, the ring oscillator 200 is configured by applying the layout of the inverter 100 based on standard design rules (minimum dimensions), and the operation of the ring oscillator 200 is measured. For example, the oscillation frequency f of the ring oscillator 200 is measured.

[0031] In step S14, it is determined whether the results of the operation simulation are accurate. The results of the operation simulation performed in step S10 are compared with the results of the actual measurements performed in step S12. If the difference between the results is less than a predetermined reference value, it is determined that the operation simulation using the minimum dimensions of the semiconductor element is accurate (Determination Result 1). In other words, Determination Result 1 indicates that the operation simulation based on the standard design rules (minimum dimensions) is accurate and does not require correction. Conversely, if the difference between the results is greater than or equal to the reference value, it is determined that the operation simulation using the minimum dimensions of the semiconductor element is inaccurate, and the process proceeds to step S16.

[0032] In step S16, a ring oscillator 200 is configured by applying the layout of the inverter 100 based on actual dimensions, and an operational simulation is performed on the ring oscillator 200. That is, the ring oscillator 200, whose layout is aligned with the same parameters as the element center model (Model testkey: a model of the device characteristics of a test chip used to measure characteristics), is the subject of the operational simulation. For example, the operational simulation of the ring oscillator 200 at the oscillation frequency f is performed. The operational simulation can be performed using, for example, SPICE.

[0033] Specifically, as shown in Figure 4, the gate length (Lg), gate width (W), LOD (Length of Diffusion), WPE (Well Proximity Effect), and layout-dependent parameters such as the influence of surrounding wiring and STI (Shallow Trench Isolation) are standardized.

[0034] Layout Parasitic Extraction (LPE) technology is applied to inverter 100, which has a layout based on actual dimensions, to extract parasitic elements (mainly parasitic resistance R and parasitic capacitance C) that occur in the wiring and devices, and generate an RC netlist for the ring oscillator 200 model for accurate operation simulation. Examples of LPE technology include parasitic extraction tools such as Calibre, Assura, and StarRC.

[0035] An RC netlist is a description of circuit information that takes into account the parasitic resistance (R) and parasitic capacitance (C) contained in the wiring and components during circuit design and simulation. This makes it possible to perform simulations that reflect the actual physical effects. A netlist is a file that describes the components that make up a circuit (transistors, resistors, capacitors, inductors, etc.) and the connections between those components in text format.

[0036] In step S18, the ring oscillator 200 is configured by applying the layout of the inverter 100 based on the actual dimensions, and the operation of the ring oscillator 200 is measured. For example, the oscillation frequency f of the ring oscillator 200 is measured.

[0037] In step S20, a determination is made as to whether the results of the operation simulation are accurate. The results of the operation simulation performed in step S16 are compared with the results of the actual measurements performed in step S18. If the difference between the results is less than a predetermined standard value, it is determined that the operation simulation using the actual dimensions of the semiconductor device is accurate (Determination Result 2). In other words, Determination Result 2 indicates that the operation simulation based on the standard design rules (minimum dimensions) is not accurate, but the modification to the model based on the actual dimensions is accurate.

[0038] In contrast, if the difference in the results exceeds a certain threshold, it is determined that the operation simulation using the actual dimensions of the semiconductor device is inaccurate (Judgment Result 3). In other words, this indicates a possible problem with the extraction of parasitic resistance (R) and parasitic capacitance (C) using LPE technology, or with the device center model. Therefore, it can be determined that these corrections are necessary.

[0039] As described above, according to this embodiment, the accuracy of the operation simulation of semiconductor devices and its problems can be appropriately evaluated. [Explanation of symbols]

[0040] 10 Power line, 12 Ground line, 14 Signal line, 16 P source, 18 P drain, 20 N source, 22 N drain, 24 Gate, 100 Inverter, 200 Ring oscillator.

Claims

1. A method for evaluating the operation simulation of semiconductor devices, A first determination step involves determining whether the results of the operation simulation for the first element are accurate, based on a comparison between the output results of the operation simulation for the first element using the minimum dimensions of the semiconductor element and the output results of actual measurements for the first element. If, in the first determination step, it is determined that the operation simulation for the first element is inaccurate, the operation simulation for the second element is performed using element parameters extracted by layout parasitic extraction technology for the second element, which has the actual dimensions of the semiconductor element applied, and a second determination step is performed to determine whether the results of the operation simulation for the second element are accurate or not based on a comparison of the output results of the operation simulation for the second element and the output results of the actual measurement for the second element. Equipped with, If the results of the operation simulation for the first element are determined to be accurate in the first determination step, then it is determined that the operation simulation using the minimum dimensions of the semiconductor element is accurate. If, in the first determination step, the result of the operation simulation for the first element is determined to be inaccurate, and in the second determination step, the result of the operation simulation for the second element is determined to be accurate, then the operation simulation using the layout parasitic extraction technique that applies the actual dimensions of the semiconductor element and the extracted element parameters is determined to be accurate. If, in the second determination step, it is determined that the results of the operation simulation for the second element are inaccurate, it is determined that the layout parasitic extraction technique needs to be modified to apply the actual dimensions of the semiconductor element. A method for evaluating the operation simulation of a semiconductor device, characterized by the following features.

2. A method for evaluating the operation simulation of a semiconductor device according to claim 1, A method for evaluating the operation simulation of a semiconductor device, characterized in that the semiconductor device is a MOSFET.

3. A method for evaluating the operation simulation of a semiconductor device according to claim 2, A method for evaluating the operation simulation of a semiconductor element, characterized in that, in the first determination step, the operation simulation and actual measurement of the first element using a ring oscillator are performed, and the result of the operation simulation for the first element is determined to be accurate based on the oscillation frequency of the ring oscillator.

4. A method for evaluating the operation simulation of a semiconductor device according to claim 2 or 3, A method for evaluating the operation simulation of a semiconductor element, characterized in that the second determination step involves performing an operation simulation and actual measurement of the second element using a ring oscillator, and determining whether the results of the operation simulation for the second element are accurate based on the oscillation frequency of the ring oscillator.

5. A method for evaluating the operation simulation of a semiconductor device according to claim 1, The first determination step is, The first element is simulated, and the simulation results of the first element are obtained. Actual measurements are performed on the first element, and the actual measurement results of the first element are obtained. Determine whether the simulation results for the first element are accurate. A method for evaluating the operation simulation of a semiconductor device, characterized by the following features.

6. A method for evaluating the operation simulation of a semiconductor device according to claim 5, The step of determining whether the simulation results of the first element are accurate is: A method for evaluating the operation simulation of a semiconductor element, characterized by comparing the simulation results of the first element with the actual measurement results of the first element, determining that the simulation of the first element is accurate if the difference in the results is less than a predetermined reference value, and determining that the simulation of the first element is inaccurate if the difference in the results is greater than or equal to the reference value.

7. A method for evaluating the operation simulation of a semiconductor device according to claim 5, A method for evaluating the operation simulation of a semiconductor element, characterized in that the first element is a ring oscillator configured based on an inverter layout based on minimum dimensions.

8. A method for evaluating the operation simulation of a semiconductor device according to claim 1, The second determination step described above is: The second element is simulated, and the simulation results of the second element are obtained. Actual measurements are performed on the second element, and the actual measurement results of the second element are obtained. Determine whether the simulation results for the second element are accurate. A method for evaluating the operation simulation of a semiconductor device, characterized by the following features.

9. A method for evaluating the operation simulation of a semiconductor device according to claim 8, The step of determining whether the simulation results for the second element are accurate is: By comparing the simulation results of the second element with the actual measurement results of the second element, A method for evaluating the operation simulation of a semiconductor element, characterized in that the simulation of the second element is determined to be accurate if the difference in the results is less than a predetermined reference value, and the simulation of the second element is determined to be inaccurate if the difference in the results is equal to or greater than the reference value.

10. A method for evaluating the operation simulation of a semiconductor device according to claim 1 or 8, A method for evaluating the operation simulation of a semiconductor element, characterized in that the second element is a ring oscillator configured based on the layout of an inverter based on the actual dimensions of the semiconductor element.

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