An improved architecture for storing and retrieving system data in a non-volatile memory system.

Abstract

To provide an improved architecture for storing and retrieving system data in a non-volatile memory system.SOLUTION: In a system data architecture, during a read operation, both word lines 601 and 603 are selected. Read currents from non-volatile memory (NVM) cells 801 and 802 are combined at a common bit line 604. The summed current is sensed by a sense amplifier 104 based on a reference current to determine its logic state.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] (Claim of Priority) This application claims priority to U.S. Provisional Patent Application No. 63 / 131,624, filed Dec. 29, 2020, entitled “Architectures for Storing and Retrieving System Data in a Non-Volatile Memory System,” and U.S. Patent Application No. 17 / 199,383, filed Mar. 11, 2021, entitled “Architectures for Storing and Retrieving System Data in a Non-Volatile Memory System.”

[0002] (Field of the Invention) Numerous embodiments of improved architectures for storing and retrieving system data in a non-volatile memory system are disclosed.

Background Art

[0003] Non-volatile memory systems are well known in the prior art. Figure 1 shows a prior art non-volatile memory system 100. The non-volatile memory system 100 comprises an array 101, a row decoder 102, a column decoder 103, and a sense amplifier 104. The array 101 comprises an array of non-volatile memory cells arranged in rows and columns. The row decoder 102 is coupled to each row of non-volatile memory cells in the array 101 and typically enables one or more rows for read, erase, or program operations in response to a received row address. The column decoder 103 is coupled to each column of non-volatile memory cells in the array 101 and typically enables one or more columns for read, erase, or program operations in response to a received column address. If the non-volatile memory cells are flash memory cells, the row decoder 102 is typically coupled to the word line of each row of a cell, and the column decoder 103 is typically coupled to the bit line of each column of a cell. The sense amplifier 104 is used during a read operation to sense the values ​​stored in one or more selected cells.

[0004] Various designs of non-volatile memory cells are known in the prior art. For example, U.S. Patent No. 5,029,130 ​​("130"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in Figure 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed insulated above a first portion of the channel region 18 (and controlling the conductivity of the first portion of the channel region 18) and extends above a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed insulated above a second portion of the channel region 18 (and controlling the conductivity of the second portion of the channel region 18) and a second portion extending upward above the floating gate 20. The floating gate 20 and word line terminal 22 are insulated from the substrate 12 by the gate oxide. The bit line 24 is coupled to the drain region 16.

[0005] The memory cell 210 is erased by applying a high positive voltage to the word line terminal 22 relative to the substrate region 12 (in this case, electrons are removed from the floating gate), thereby tunneling electrons on the floating gate 20 through the intermediate insulator from the floating gate 20 to the word line terminal 22 via Fowler-Nordheim tunneling.

[0006] The memory cell 210 is programmed by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14 (electrons are supplied to the floating gate). Electrons flow from the drain region 16 towards the source region 14. The electrons are accelerated and heated as they move through the channel region 18 below the gap between the word line terminal 22 and the floating gate 20, and the channel region 18 below the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to the electrostatic attraction from the floating gate 20 and the resulting reduction in the oxide energy barrier.

[0007] The memory cell 210 is read by applying a positive read voltage to the source area 14 by applying a drain area 16 and the word line terminal 22 (turning on the portion of the channel area 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., electrons are erased), the portion of the channel area 18 below the floating gate 20 is also turned on, and current flows across the channel area 18 to the source area 14, which is detected as the erased state, i.e., the "1" state. When the floating gate 20 is negatively charged (i.e., electrons are programmed), the portion of the channel area below the floating gate 20 is almost or completely off, and no (or very little) current flows through the channel area 18 to the source area 14, which is detected as the programmed state, i.e., the "0" state.

[0008] Table 1 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 in Figure 3 [Table 1]

[0009] Other types of flash memory cells are also known, including other split-gate memory cell configurations. For example, Figure 3 shows a four-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of the channel region 18, a selection gate 22 (typically coupled to a word line, WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent No. 7,868,375, which is incorporated herein by reference for all purposes. Here, all gates are non-floating gates, except for the floating gate 20; that is, they are electrically connected to or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0010] Table 2 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 in Figure 3 [Table 2]

[0011] Figure 4 shows a different type of flash memory cell, a 3-gate memory cell 410. Memory cell 410 is identical to memory cell 310 in Figure 3, except that memory cell 410 does not have a separate control gate. The erase operation (where erasure occurs through the use of the erase gate) and read operation are the same as those in Figure 3, except that no control gate bias is applied. The programming operation is also performed without a control gate bias; therefore, during the programming operation, a higher voltage must be applied to the source line to compensate for the lack of control gate bias.

[0012] Table 3 shows typical voltage / current ranges that can be applied to the terminals of the memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 in Figure 4 [Table 3]

[0013] The methods and means described herein may be applied to other non-volatile memory technologies such as FINFET split-gate flash or stack-gate flash memory, NAND flash, SONOS (silicon oxide-nitride-oxide-silicon, charge trap in nitride), MONOS (metal oxide-nitride-oxide-silicon, metal charge trap in nitride), ReRAM (resistive random-access memory), PCM (phase-change memory), MRAM (magnetoresistive random-access memory), FeRAM (ferroelectric random-access memory), CT (charge trap) memory, CN (carbon nanotube) memory, OTP (bilevel or multilevel one-time programmable), and CeRAM (strongly correlated electron memory).

[0014] Referring to Figure 5, the prior art non-volatile memory system 100 may create and maintain a protected area 501 within the array 101. The protected area 501 can then be used to store configuration data, trim data, fuses, and other types of data essential to the operation of the non-volatile memory system 100, which are referred to herein as “system data” or “system bits.” User data is not stored in the protected area 501, and optionally, the protected area 501 is not accessible for read, erase, and program operations initiated from an external source to the non-volatile memory system 100.

[0015] Since the data stored in the protected area 501 is critical to the precise functioning of the non-volatile memory system 100, the data stored in the protected area 501 requires additional protection from low-probability data loss events such as charge loss, charge transfer, read disturbances, radiation-induced soft errors, and other mechanisms that cause slight changes in read current / voltage of a small portion of the cell.

[0016] One prior art approach involves redundantly storing each system bit within the protected area 501 in two non-volatile memory cells. In this approach, the read currents from the two cells can be summed and compared to a reference value to determine the stored value.

[0017] However, even with redundancy, in some non-volatile memory cell designs, charge loss, charge redistribution, disturbance, or other physical changes in the non-volatile memory cell will, depending on the architecture of the non-volatile memory cell, primarily cause the cell to flip from a "1" state to a "0" state, or from a "0" state to a "1" state.

[0018] This can corrupt system bits. For example, if one of two non-volatile memory cells flips from a "0" state to a "1" state, the total read current will exceed the reference current, and the detected data will flip from "0" to "1".

[0019] What is needed is an embodiment for storing critical system data in a non-volatile memory array, thereby reducing the likelihood of the system data being corrupted by charge loss, charge redistribution, disturbance effects, or other physical changes in the non-volatile memory cell that cause changes in read current or voltage, but are not limited to. [Overview of the project]

[0020] A number of embodiments of an improved architecture for storing and retrieving system data in a non-volatile memory system are disclosed. Using these embodiments, system data is much less likely to be corrupted due to charge loss, charge redistribution, disturbance effects, and other phenomena that caused data corruption in prior art non-volatile memory systems.

[0021] In one embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, a sense amplifier configured to receive a current from a first non-volatile memory cell in a first column of the array during a read operation to indicate a first value stored in the first non-volatile memory cell and receive a current from a second non-volatile memory cell in a second column of the array to indicate a second value stored in the second non-volatile memory cell, and logic circuitry configured to receive the first value and the second value from the sense amplifier and generate a data bit output based on the first value and the second value.

[0022] In another embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, and a sense amplifier configured to receive a combined current from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array during a read operation and generate a data bit output indicating a value based on the combined current.

[0023] In another embodiment, a non-volatile memory system includes an array of non-volatile memory cells arranged in a plurality of rows and a plurality of columns, where each row includes a word of non-volatile memory cells and error correction code data calculated from the word. The non-volatile memory system further includes a sense amplifier configured to receive a current from the array during a read operation and output the word and the error correction code data of the word, and an error correction code engine configured to use the error correction code data of the word to correct one or more errors in the word.

[0024]

[0025] ]>

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033] [Brief explanation of the drawing]

[0034] [Figure 1] This shows a prior art non-volatile memory system. [Figure 2] This shows a prior art split-gate flash memory cell. [Figure 3] This shows another prior art split-gate flash memory cell. [Figure 4] This shows another prior art split-gate flash memory cell. [Figure 5] This shows a prior art non-volatile memory system with a protected area. [Figure 6] Another embodiment of the system data architecture is shown. [Figure 7] Another embodiment of the system data architecture is shown. [Figure 8] Another embodiment of the system data architecture is shown. [Figure 9] Another embodiment of the system data architecture is shown. [Figure 10] Another embodiment of the system data architecture is shown. [Figure 11] Another embodiment of the system data architecture is shown. [Modes for carrying out the invention]

[0035] Figures 6-8 show embodiments particularly suitable for non-volatile memory (NVM) cell design, in which charge loss, charge redistribution, disturbance, or other physical or electrical changes in the NVM cell can pull the cell to a "1" state, inverting stored "0s" to "1s" but without affecting stored "1s".

[0036] Figure 6 shows the system data architecture 600. Each bit of the system data is written to two redundant NVM cells, such as cells 601 and 602, located in the same row accessible by the same word line, such as word line 601, and in different columns accessible by different bit lines, such as bit lines 604 and 605.

[0037] During the read operation, the currents from NVM cells 601 and 602 are simultaneously but independently detected by the sense amplifier 104 relative to a reference current in order to determine their respective logic states. The data read from the two cells as an output by the sense amplifier 104 (representing a first value stored in one of the two NVM cells 601 and 602, and a second value stored in the other of the two NVM cells 601 and 602) is routed through the AND device 603 (a logic device that performs an AND function, which may be implemented using hardware logic or by firmware running on the controller or processor) to generate the final system data (indicated by "Output").

[0038] If NVM cells 601 and 602 initially store "0" and neither cell has inverted, the output will be "0". If NVM cells 601 and 602 initially store "0", and one of the two NVM cells 601 or 602 inverts from "0" to "1", the output of AND device 603 will be "0", so the output will still be "0". The probability of both NVM cells inverting from "0" to "1" is extremely low.

[0039] If NVM cells 601 and 602 initially store 1, it is expected that both NVM cells 601 and 602 will still store 1, since the underlying NVM cell architecture is assumed to be of the type where leakage or disturbance inverts "0" to "1" but not "1" to "0". Bit line 606 and word line 603 are shown for completeness.

[0040] Figure 7 shows the system data architecture 700. Each bit of the system data is written to two redundant NVM cells. Each redundant NVM cell can be located in any row and any column. That is, there are no restrictions on where redundant NVM cells can be placed, and redundant NVM cells do not need to be located in the same row or column or adjacent rows or columns. In this embodiment, a pair of redundant bits are accessed by word line 601 and bit line 604 in NVM cell 701, and by word line 603 and bit line 604. 7 It is stored in NVM cell 702, which is accessible by 06. word Line 602 and bit Line 605 is shown for completeness.

[0041] During the read operation, the currents from NVM cells 701 and 702 are independently detected by the sense amplifier 104 relative to a reference current to determine their respective logic states. The read data from the two NVM cells output by the sense amplifier 104 (representing a first value stored in one of the two NVM cells 701 and 702, and a second value stored in the other of the two NVM cells 701 and 702) is processed by the AND device 603 (a logic device that performs an AND function, which may be implemented using hardware logic or by firmware running on a controller or processor) to generate the final system data (indicated by "Output").

[0042] If NVM cells 701 and 702 initially store "0" and neither cell is inverted, the output will be "0". If NVM cells 701 and 702 initially store "0", and one of the two NVM cells 701 or 702 inverts from "0" to "1", the output of the AND operation is "0", so the final data will still be "0". The probability that both NVM cells 701 and 702 invert from "0" to "1" is extremely low.

[0043] If NVM cells 701 and 702 initially store "1", then it is expected that both will still store "1", as the underlying NVM cell architecture is assumed to be of the type where leakage, disturbance, or other changes will invert "0" to "1" but not "1" to "0".

[0044] Figure 8 shows the system data architecture 800. Each bit of the system data is written to two redundant NVM cells, such as NVM cells 801 and 802, which are located in the same column accessible by the same bit line, such as bit line 604, but in different rows accessible by different word lines, such as word lines 601 and 603. Bit lines 605, 606 and word line 602 are shown for completeness.

[0045] During a read operation, both word lines 601 and 603 are selected. The read currents from NVM cells 801 and 802 are coupled on a common bit line 604. The summed current is sensed by a sense amplifier 104 against a reference current to determine its logic state. The reference current is set to a level within a range that is higher than the sum of the typical zero-state read current of the NVM cell and the upper limit of the neutral floating gate (FG) read current (for NVM cells using charge storage in polysilicon FG, the upper limit refers to the upper limit of the range of neutral FG read currents for NVM cells in the array), or higher than the sum of the typical zero-state read current and the saturation point of the zero-state read current shift (for NVM cells using other storage mechanisms). The reference level is also lower than twice the lower limit of the read current of a one-state cell read immediately after being set to one state.

[0046] During production test screening of devices conforming to the system data architecture 800, readouts using a reference current within the range described above are performed on the protection area 501 to ensure that the two NVM cells 801 and 802 can be sufficiently erased under worst-case erase and read conditions to ensure that the combined read current exceeds the reference level, where “worst-case” refers to the weakest erase and read conditions over a specific process / temperature / voltage range, which may vary from technology to technology. These conditions are typically captured during testing.

[0047] If the data stored in the selected NVM cells 801 and 802 is "0" and neither NVM cell inverts, the final data output by the sense amplifier 104 (indicated by "Output") is still "0". If the data stored in the selected NVM cells 801 and 802 is "0" and one of the two NVM cells 801 or 802 inverts from "0" to "1", the combined read current of the two NVM cells saturates before exceeding the reference current, and the final data is still "0" by the sense amplifier 104. The probability that both NVM cells 801 and 802 invert from "0" to "1" is extremely low.

[0048] If NVM cells 801 and 802 initially store "1", then it is assumed that the underlying NVM cell architecture is of the type where leakage, disturbance, or other changes will invert "0" to "1" but not "1" to "0", so it is expected that both NVM cells 801 and 802 will still store "1".

[0049] Figures 9-10 show embodiments particularly suitable for NVM cell designs in which charge loss, charge redistribution, or disturbance can pull the cell toward a "0" state, inverting stored "1s" to "0s," but without affecting the stored "0s."

[0050] Figure 9 shows the system data architecture 900. Each bit of the system data is written to two redundant NVM cells, such as cells 901 and 902, which are located in the same row accessible by the same word line, such as word line 601, but in different columns accessible by different bit lines, such as bit lines 604 and 605. Bit line 606 and word lines 602 and 603 are shown for completeness.

[0051] During the read operation, the currents from NVM cells 901 and 902 are simultaneously but independently detected by the sense amplifier 104 relative to a reference current in order to determine the first value stored in NVM cell 901 and the second value stored in NVM cell 902. The read data from the two NVM cells output by the sense amplifier 104 is processed by the OR device 903 (a logic device that performs OR functions, which may be implemented using hardware logic or by firmware running on a controller or processor) to generate the final system data (indicated by "Output").

[0052] If NVM cells 901 and 902 initially store "1" and neither cell has been inverted, the output will be "1". If NVM cells 901 and 902 initially store "1" and one of the two NVM cells inverts from "1" to "0", the output of OR device 903 will be "0", so the final data will still be "1". The probability of both NVM cells 901 and 902 inverting from "1" to "0" is extremely low.

[0053] If NVM cells 901 and 902 initially store "0", this scheme is only used in NVM cell architectures where leakage, disturbance, or other changes would invert "1"s to "0"s but not "0"s, so it is expected that both NVM cells 901 and 902 will still store "0".

[0054] Figure 10 shows the system data architecture 1000. Each bit of the system data is written to two redundant NVM cells. Each redundant NVM cell can be located in any row and column. That is, there are no restrictions on where NVM cells can be placed, and NVM cells do not need to be located in the same row or column or adjacent rows or columns.

[0055] In this embodiment, a pair of redundant bits are stored in NVM cell 1001, accessible by word line 601 and bit line 604, and in NVM cell 1002, accessible by word line 603 and bit line 606. Bit line 605 and word line 602 are shown for completeness.

[0056] During the read operation, the currents from NVM cells 1001 and 1002 are detected independently of a reference current by the sense amplifier 104 to determine the first value stored in NVM cell 1001 and the second value stored in NVM cell 1002. The read data from the two NVM cells output by the sense amplifier 104 is processed by the OR device 903 (a logic device that performs OR functions, which may be implemented using hardware logic or by firmware running on a controller or processor) to generate the final system data (indicated by "Output").

[0057] If NVM cells 1001 and 1002 initially store "1" and neither NVM cell has inverted, the output will be "1". If NVM cells 1001 and 1002 initially store "1" and one of the two NVM cells inverts from "1" to "0", the output of OR device 903 will be "0", so the final data will still be "1". The probability that both NVM cells 1001 and 1002 invert from "1" to "0" is extremely low.

[0058] If NVM cells 1001 and 1002 initially store "0", this scheme is only used in NVM cell architectures where leakage, disturbance, or other changes would invert "1"s to "0"s but not "0"s, so it is expected that both NVM cells 1001 and 1002 will still store "0".

[0059] Figure 11 shows a suitable embodiment for any of the following: (1) an NVM cell design in which charge loss, charge redistribution, disturbance, or other physical change to the cell can pull the cell toward a "0" state and reverse stored "1"s to "0", but without affecting stored "0"s; (2) an NVM cell design in which the aforementioned change can pull the cell toward a "1" state and reverse stored "0"s to "1", but without affecting stored "1"s; and (3) an NVM cell design in which the aforementioned change can pull the NVM cell toward any state, which can reverse some stored "0"s to "1", but can also reverse some stored "1"s to "0".

[0060] Figure 11 shows the system data architecture 1100. Here, each word of system data, such as word 1101, is stored in a row along with associated error correction code data, such as error correction code (ECC) data 1102. Each system bit is stored in a word and is stored without redundancy. Multiple words can be stored in a single row without exceeding the range, and each word has associated error correction code data.

[0061] Here, ECC data 1102 is generated for word 1101 using ECC such as Hamming codes or codes generated by a majority voting algorithm (where data is stored in N redundant physical cells, and the value of the stored data is considered to be the value indicated by a majority of the N cells) to perform error detection and error correction, such as a 2-bit error detection and 1-bit error correction scheme. Instead of ECC data 1102, a parity bit scheme can also be used to indicate error detection without correction. When bit 1101 is read, the entire word 1101 and the ECC data 1102 are read by the sense amplifier 104 and sent to the ECC engine 1103. That is, the sense amplifier 104 receives current from the array and outputs the word and the error correction code data for that word to the ECC engine 1103. If any single bit in word 1101 flips in either direction, the error is successfully detected and / or corrected by the ECC engine 1103. The probability of two or more bits flipping is extremely low.

[0062] In one embodiment, the system data architecture 1100 is further implemented with redundancy, such as using multiple cells for each system bit, to further enhance reliability, including functional safety for automotive applications. For example, each system bit can be stored in two cells in two rows or two columns, as described in the previous embodiment.

[0063] In one embodiment, the ECC engine 1103 is implemented using an external controller or firmware.

[0064] It should be noted that, as used herein, the terms “over” and “on” both encompass “directly” (without intermediate material, element, or gap between them) and “indirectly to” (with intermediate material, element, or gap between them). Similarly, the term “adjacent” includes “directly adjacent” (without intermediate material, element, or gap between them) and “indirectly adjacent” (with intermediate material, element, or gap between them); “attached” includes “directly attached” (without intermediate material, element, or gap between them) and “indirectly attached to” (with intermediate material, element, or gap between them); and “electrically coupled” includes “directly electrically coupled” (without intermediate material or element between them electrically connecting the elements together) and “indirectly electrically coupled to” (with intermediate material or element between them electrically connecting the elements together). For example, forming an element "on top of a substrate" may include forming the element directly on the substrate without any intermediate materials / elements between them, and forming the element indirectly on the substrate with one or more intermediate materials / elements between them.

Claims

[Claim 1] A non-volatile memory system, An array of non-volatile memory cells arranged in multiple rows and multiple columns, A sense amplifier configured to receive a combined current from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array during a read operation, and to generate a data bit output indicating a value based on a comparison of the combined current and a reference current, wherein the first non-volatile memory cell and the second non-volatile memory cell are programmed with the same value, and the reference current is set to be greater than the combined current of the current stored as a value of "1" and the current stored as a value of "0".

Images