Fault-tolerant quantum error correction using physical transport of qubits

Abstract

The quantum computing system includes a classical computing entity, a controller, and a quantum processor. The controller is configured to control operation of the quantum processor and communicate with the computing entity. The controller causes the execution of a syndrome circuit segment to generate a syndrome of the logical qubit. The syndrome circuit segment is implemented, at least in part, by causing the execution of a series of transport operations and interactions of at least two physical qubits. Each transport operation in the series of transport operations causes physical transport of at least one of a respective data qubit or a respective ancillary qubit of the logical qubit to a respective interaction zone defined by the quantum processor. Each interaction of the at least two physical qubits is performed within the respective interaction zone. At least one quantum error correction is determined using the syndrome, and the controller causes a classical memory to be updated based on the syndrome and / or the quantum error correction.

Description

Technical Field

[0001] Cross - reference to Related Applications This application claims the priority of U.S. Application No. 18 / 347,054, filed on July 5, 2023, which claims the priority of U.S. Application No. 63 / 368,421, filed on July 14, 2022, the contents of which are hereby incorporated by reference in their entirety.

[0002] Various embodiments relate to fault - tolerant quantum error correction using physical transport of one or more qubits. Various embodiments relate to fault - tolerant quantum error correction corresponding to a quantum processor in which nearest - neighbor qubits are not defined, where qubit connectivity is high and / or the relative qubit positions are variable.

Background Art

[0003] Complex quantum computations require a level of precision that is not possible with conventional quantum computers due to, for example, imperfect control and noise in gate operations between data qubits. Through dedicated effort, ingenuity, and technological innovation, many of the drawbacks of previous systems have been addressed by developing solutions constructed in accordance with embodiments of the present invention, many examples of which are detailed herein.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Means for Solving the Problems

[0005] Exemplary embodiments provide methods, systems, apparatus, computer program products, controllers configured to control the operation of a quantum processor, etc., for performing fault-tolerant quantum computation and / or fault-tolerant quantum error correction, wherein the implementation of a syndrome circuit segment and / or application of physical quantum error correction includes the physical transport of one or more qubits (e.g., data qubits and / or auxiliary qubits of a logic qubit).

[0006] According to a first embodiment, a method is provided for performing fault-tolerant quantum error correction using physical transport of qubits. In an exemplary embodiment, the method is performed by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicates with the classical computing entity. In an exemplary embodiment, the method comprises the step of causing the controller to cause the implementation of at least one syndrome circuit segment to generate a syndrome of logical qubits. The at least one syndrome circuit segment is implemented by causing at least part of a series of transport operations and an interaction of at least two physical qubits (e.g., an interaction between two or more physical qubits such as a 2(physical) qubit gate). Each transport operation in the series of transport operations and the interaction of at least two physical qubits causes a physical transport of at least one of (a) the respective data qubit of the logical qubit or (b) the respective auxiliary qubit to each interaction zone defined by the quantum processor, such that at least one of (a) the respective data qubit of the logical qubit or (b) the respective auxiliary qubit is located within each interaction zone defined by the quantum processor, and the interaction of at least two physical qubits is performed there. The method further comprises the steps of determining at least one quantum error correction by a classical computing entity based at least in part on a logical qubit syndrome, and causing a controller to update at least one classical memory of the controller or classical computing entity based on the syndrome or at least one of the quantum error corrections.

[0007] In one exemplary embodiment, the method further comprises the step of having a controller apply at least one quantum error correction to a logical qubit.

[0008] In one exemplary embodiment, the step of ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following steps: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0009] In one exemplary embodiment, the step of causing a physical correction of a logic qubit to one or more data qubits comprises the step of performing one or more transport operations on one or more data qubits so that the one or more data qubits are transported to at least one of (a) inside or (b) outside one or more interaction zones defined by the quantum processor.

[0010] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0011] In one exemplary embodiment, the step of causing the implementation of at least one syndrome circuit segment comprises: causing the implementation of a first plurality of syndrome circuit segments, wherein the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining, at least in part, based on the results of each of the first plurality of syndrome circuit segments, whether to cause the implementation of a second plurality of syndrome circuit segments, wherein the second plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments; causing the implementation of the second plurality of syndrome circuit segments in response to the decision to cause the implementation of the second plurality of syndrome circuit segments; and determining at least one quantum error correction in response to the decision not to cause the implementation of the second plurality of syndrome circuit segments, at least in part, based on the results of each of the first plurality of syndrome circuit segments.

[0012] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and the auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0013] In one exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, where the first of two or more auxiliary qubits used to implement at least one syndrome circuit segment is used as the flag qubit.

[0014] In one exemplary embodiment, the method further comprises the steps of tracking the value of a flag qubit using at least a classical qubit registry, and, in response to a determination that the value of the flag qubit has changed, triggering the execution of an unflaged syndrome circuit segment.

[0015] In one exemplary embodiment, the step of updating a classical memory based on a syndrome or at least one of at least one quantum error correction comprises the step of tracking the syndrome of logical qubits in the classical memory.

[0016] In one exemplary embodiment, the coherence of each data qubit of the logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0017] In one exemplary embodiment, the method further comprises the steps of causing the execution of a state preparation circuit segment to prepare the state of each auxiliary qubit before causing the execution of at least one syndrome circuit segment, and causing each auxiliary qubit to be read after the execution of a series of transport operations and interactions of at least two physical qubits, wherein the logic qubit syndrome is generated on at least part of the result of the reading of each auxiliary qubit.

[0018] In another embodiment, a quantum computing system is provided configured to perform fault-tolerant quantum error correction using the physical transport of qubits. In one exemplary embodiment, the quantum computing system comprises a classical computing entity, a controller, and a quantum processor. The controller is configured to control the operation of the quantum processor and communicates with the classical computing entity. In one exemplary embodiment, the controller is configured to trigger the implementation of at least one syndrome circuit segment to generate a syndrome of logic qubits. The at least one syndrome circuit segment is implemented by triggering the implementation of a series of transport operations and the interaction of at least two physical qubits, at least in part. Each transport operation in the series of transport operations and the interaction of at least two physical qubits triggers the physical transport of at least one of (a) the respective data qubit of the logic qubit or (b) the respective auxiliary qubit to each interaction zone defined by the quantum processor, such that at least one of (a) the respective data qubit of the logic qubit or (b) the respective auxiliary qubit is located within each interaction zone defined by the quantum processor, and the interaction of at least two physical qubits is performed there. A classical computation entity is configured to determine at least one quantum error correction based at least in part on a logical qubit syndrome. The controller is further configured so that the classical memory of at least one of the controller or classical computation entities is updated based on the syndrome or at least one of the at least one quantum error corrections.

[0019] In one exemplary embodiment, the controller is further configured to apply at least one quantum error correction to a logical qubit.

[0020] In one exemplary embodiment, ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0021] In one exemplary embodiment, causing a physical correction of one or more data qubits to a logical qubit comprises performing one or more transport operations on one or more data qubits so that the one or more data qubits are transported to at least one of (a) inside or (b) outside one or more interaction zones defined by the quantum processor.

[0022] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0023] In one exemplary embodiment, causing the implementation of at least one syndrome circuit segment comprises causing the implementation of a first plurality of syndrome circuit segments, where the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments using a probabilistic selection process, and determining whether to cause the implementation of a second plurality of syndrome circuit segments based at least in part on the result of each of the first plurality of syndrome circuit segments, where the second plurality of syndrome circuit segments are selected from the defined set of syndrome circuit segments, causing the implementation of the second plurality of syndrome circuit segments in response to a determination to cause the implementation of the second plurality of syndrome circuit segments, and determining at least one quantum error correction based at least in part on the result of each of the first plurality of syndrome circuit segments in response to a determination not to cause the implementation of the second plurality of syndrome circuit segments.

[0024] In one exemplary embodiment, a logical qubit is one of a plurality of logical qubits, and an ancillary qubit is used to perform a syndrome circuit segment for two or more of the plurality of logical qubits.

[0025] In one exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, and a first ancillary qubit of two or more ancillary qubits used to perform at least one syndrome circuit segment is used as a flag qubit.

[0026] In one exemplary embodiment, the controller is further configured to track the value of the flag qubit using at least a classical qubit register and cause the implementation of an unflagged syndrome circuit segment in response to a determination that the value of the flag qubit has changed.

[0027] In one exemplary embodiment, updating classical memory based on at least one of a syndrome or at least one quantum error correction comprises tracking the syndrome of logical qubits in the classical memory.

[0028] In one exemplary embodiment, during the implementation of at least one syndrome circuit segment, the coherence of each data qubit of the logical qubits is maintained.

[0029] In one exemplary embodiment, the controller further causes the implementation of a state preparation circuit segment to prepare the state of each ancillary qubit before causing the implementation of at least one syndrome circuit segment, and causes each ancillary qubit to be read after a series of transport operations and the implementation of at least two physical qubit interactions, and the syndrome of the logical qubits is generated based at least in part on the result of the reading of each ancillary qubit.

[0030] In another embodiment, a controller is provided which is configured to control the operation of a quantum processor and to trigger the implementation of fault-tolerant quantum error correction using physical transport of qubits. In one exemplary embodiment, the controller is configured to communicate with a classical computing entity. In one exemplary embodiment, the controller is configured (and / or programmed) to trigger the implementation of at least one syndrome circuit segment to generate a syndrome of logic qubits. The at least one syndrome circuit segment is implemented by triggering at least part of a series of transport operations and the interaction of at least two physical qubits. Each transport operation in the series of transport operations and the interaction of at least two physical qubits triggers the physical transport of at least one of (a) the respective data qubit of the logic qubit or (b) the respective auxiliary qubit to each interaction zone defined by the quantum processor, such that at least one of (a) the respective data qubit of the logic qubit or (b) the respective auxiliary qubit is located within each interaction zone defined by the quantum processor, and the interaction of at least two physical qubits is implemented therein. The controller is further configured to cause the classical computing entity to determine at least one quantum error correction based at least part of the syndrome of logic qubits. The controller is further configured to ensure that at least one quantum error correction is applied to a logical qubit.

[0031] In one exemplary embodiment, ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0032] In one exemplary embodiment, causing a physical correction of one or more data qubits to a logical qubit comprises performing one or more transport operations on one or more data qubits so that the one or more data qubits are transported to at least one of (a) inside or (b) outside one or more interaction zones defined by the quantum processor.

[0033] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0034] In one exemplary embodiment, triggering the implementation of at least one syndrome circuit segment comprises triggering the implementation of a first plurality of syndrome circuit segments, wherein the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining, at least in part, based on the outcome of each of the first plurality of syndrome circuit segments, whether to trigger the implementation of a second plurality of syndrome circuit segments, wherein the second plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments; triggering the implementation of the second plurality of syndrome circuit segments in response to the decision to trigger the implementation of the second plurality of syndrome circuit segments; and determining at least one quantum error correction in response to the decision not to trigger the implementation of the second plurality of syndrome circuit segments, at least in part, based on the outcome of each of the first plurality of syndrome circuit segments.

[0035] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and the auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0036] In one exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, where the first of two or more auxiliary qubits used to implement at least one syndrome circuit segment is used as the flag qubit.

[0037] In one exemplary embodiment, the controller is further configured to track the value of a flag qubit using at least a classical qubit registry and, in response to a determination that the value of the flag qubit has changed, trigger the execution of an unflaged syndrome circuit segment.

[0038] In one exemplary embodiment, updating a classical memory based on a syndrome or at least one of at least one quantum error correction comprises tracking a syndrome of logical qubits in the classical memory.

[0039] In one exemplary embodiment, the coherence of each data qubit of the logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0040] In one exemplary embodiment, the controller is further configured to trigger the execution of a state preparation circuit segment to prepare the state of each auxiliary qubit before triggering the execution of at least one syndrome circuit segment, so that each auxiliary qubit is read after a series of transport operations and the interaction of at least two physical qubits, and the logic qubit syndrome is generated based at least in part on the results of the reading of each auxiliary qubit.

[0041] In another embodiment, a computer program product is provided comprising at least one non-temporary computer-readable medium. At least one computer-readable memory stores a computer-executable instruction, which, when executed by a controller processing element, causes the controller to control the operation of a quantum processor and trigger the implementation of fault-tolerant quantum error correction using the physical transport of qubits. In one exemplary embodiment, the computer-executable instruction, when executed by a controller processing element, is configured to cause the controller to trigger the implementation of at least one syndrome circuit segment to generate a syndrome of logical qubits. The at least one syndrome circuit segment is implemented, at least in part, by triggering the implementation of a series of transport operations and the interaction of at least two physical qubits. Each transport operation in the series of transport operations and the interaction of at least two physical qubits triggers the physical transport of at least one of the data qubits or the auxiliary qubits of the logical qubit to each of those interaction zones, such that (a) each data qubit of the logical qubit and (b) each auxiliary qubit are located within each interaction zone defined by the quantum processor, and the interaction of at least two physical qubits is performed there. The computer executable instructions, when executed by the controller's processing element, are configured to cause the controller to cause a classical computing entity communicating with the controller to determine at least one quantum error correction based at least part on a logical qubit syndrome, and to cause at least one classical memory of the controller or the classical computing entity to be updated based on the syndrome or at least one of the quantum error corrections.

[0042] In one exemplary embodiment, a computer executable instruction is further configured, when executed by a controller processing element, to cause the controller to perform at least one quantum error correction on a logical qubit.

[0043] In one exemplary embodiment, ensuring that at least one quantum error correction is applied to a logical qubit comprises at least one of the following: (a) updating a classical qubit registry corresponding to the logical qubit based on at least one quantum error correction; (b) causing the implementation of a physical correction to one or more data qubits of the logical qubit; or (c) ensuring that a logical operation which will be implemented at least in part on one or more data qubits of the logical qubit is modified at least in part based on at least one quantum error correction.

[0044] In one exemplary embodiment, causing a physical correction of one or more data qubits to a logical qubit comprises performing one or more transport operations on one or more data qubits so that the one or more data qubits are transported to at least one of (a) inside or (b) outside one or more interaction zones defined by the quantum processor.

[0045] In one exemplary embodiment, the implementation of at least one syndrome circuit segment comprises the implementation of multiple syndrome circuit segments.

[0046] In one exemplary embodiment, triggering the implementation of at least one syndrome circuit segment comprises triggering the implementation of a first plurality of syndrome circuit segments, wherein the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments using a probabilistic selection process; determining, at least in part, based on the outcome of each of the first plurality of syndrome circuit segments, whether to trigger the implementation of a second plurality of syndrome circuit segments, wherein the second plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments; triggering the implementation of the second plurality of syndrome circuit segments in response to the decision to trigger the implementation of the second plurality of syndrome circuit segments; and determining at least one quantum error correction in response to the decision not to trigger the implementation of the second plurality of syndrome circuit segments, at least in part, based on the outcome of each of the first plurality of syndrome circuit segments.

[0047] In one exemplary embodiment, the logic qubit is one of a plurality of logic qubits, and the auxiliary qubit is used to implement a syndrome circuit segment for two or more of the plurality of logic qubits.

[0048] In one exemplary embodiment, at least one syndrome circuit segment comprises a flagged syndrome circuit segment, where the first of two or more auxiliary qubits used to implement at least one syndrome circuit segment is used as the flag qubit.

[0049] In one exemplary embodiment, the computer executable instruction, when executed by the controller's processing element, is further configured to cause the controller to track the value of a flag qubit using at least one classical qubit registry and, in response to a determination that the value of the flag qubit has changed, trigger the execution of an unflagged syndrome circuit segment.

[0050] In one exemplary embodiment, a computer executable instruction, when executed by a controller processing element, is configured to cause the controller to (a) track a syndrome of logical qubits in the controller's memory, or (b) cause a classical computation entity to track a syndrome of logical qubits in the classical computation entity's memory.

[0051] In one exemplary embodiment, the coherence of each data qubit of the logic qubit is maintained during the implementation of at least one syndrome circuit segment.

[0052] In one exemplary embodiment, a computer executable instruction, when executed by a controller processing element, is configured to cause the controller to perform a state preparation circuit segment to prepare the state of each auxiliary qubit before causing the execution of at least one syndrome circuit segment, so that each auxiliary qubit can be read after a series of transport operations and the interaction of at least two physical qubits, and the logic qubit syndrome is generated based at least in part on the results of the reading of each auxiliary qubit.

[0053] In another embodiment, a method is provided for implementing a logic multi-qubit gate (a logic gate between two or more logic qubits). In one exemplary embodiment, the method comprises the step of causing a quantum processor to implement a first part of a logic multi-qubit gate by causing a first group implementation of at least two physical qubit interactions for a first subset of at least physical qubits from a set of physical qubits. The set of physical qubits comprises a data qubit of the first logic qubit, a data qubit of the second physical qubit, and one or more auxiliary qubits. The logic multi-qubit gate is implemented for at least the first logic qubit and the second logic qubit. The method further comprises the step of causing the quantum processor to implement a multi-qubit quantum error correction cycle by the controller, which comprises an implementation of at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction; and the step of causing the quantum processor to implement a second part of a logic multi-qubit gate by causing a second group implementation of at least two physical qubit interactions for a second subset of at least physical qubits from a set of physical qubits.

[0054] In one exemplary embodiment, at least one interaction of at least two physical qubits from a second group of interactions of at least two physical qubits is modified at least in part based on at least one quantum error correction.

[0055] In one exemplary embodiment, the method further comprises at least one of the following steps: (a) causing the performance of a physical correction on at least one of the first or second logic qubits after the completion of a logic multi-qubit gate based on at least one quantum error correction; or (b) causing the performance of an operation on at least one of the first or second logic qubits after the completion of the logic multi-qubit gate has been corrected at least in part based on at least one quantum error correction.

[0056] In one exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit before the implementation of a second group of interactions of at least two physical qubits.

[0057] In one exemplary embodiment, the method further comprises the step of causing a trace of at least one of at least one syndrome or at least one quantum error correction in classical memory.

[0058] In one exemplary embodiment, the step of performing at least one of a first group of interactions of at least two physical qubits, at least one syndrome circuit segment, or a second group of interactions of at least two physical qubits comprises the step of causing the transport of one or more physical qubits from a set of physical qubits into or out of one or more interaction zones defined by a quantum processor.

[0059] In another embodiment, a controller is provided which controls the operation of a quantum processor and is configured to trigger the implementation of fault-tolerant quantum error correction using the physical transport of qubits. In one exemplary embodiment, the controller is configured (and / or programmed) to cause the quantum processor to implement a first portion of a logic multi-qubit gate by causing the implementation of a first group of interactions of at least two physical qubits on a first subset of at least physical qubits from a set of physical qubits. The set of physical qubits comprises a data qubit of the first logic qubit, a data qubit of the second logic qubit, and one or more auxiliary qubits. The logic multi-qubit gate is implemented on at least the first logic qubit and the second logic qubit. The controller is further configured to cause the quantum processor to implement a multi-qubit quantum error correction cycle comprising the implementation of at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction, and to cause the quantum processor to implement a second portion of a logic multi-qubit gate by causing the implementation of a second group of interactions of at least two physical qubits on a second subset of at least physical qubits from a set of physical qubits.

[0060] In one exemplary embodiment, at least one interaction of at least two physical qubits from a second group of interactions of at least two physical qubits is modified at least in part based on at least one quantum error correction.

[0061] In one exemplary embodiment, the controller is further configured to (a) cause the implementation of a physical correction on at least one of the first or second logic qubits after the completion of a logic multi-qubit gate based on at least one quantum error correction, or (b) cause the implementation of an operation on at least one of the first or second logic qubits after the completion of the logic multi-qubit gate has been corrected at least in part based on at least one quantum error correction.

[0062] In one exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit before the implementation of a second group of interactions of at least two physical qubits.

[0063] In one exemplary embodiment, the controller is further configured to induce at least one tracking of at least one syndrome or at least one quantum error correction in classical memory.

[0064] In one exemplary embodiment, performing at least one of a first group of interactions of at least two physical qubits, at least one syndrome circuit segment, or a second group of interactions of at least two physical qubits comprises causing the transport of one or more physical qubits from a set of physical qubits into or out of one or more interaction zones defined by a quantum processor.

[0065] In another embodiment, a computer program product is provided comprising at least one non-temporary computer-readable medium. The at least one computer-readable memory stores computer-executable instructions, which, when executed by a controller processing element, are configured to cause the controller to control the operation of a quantum processor and trigger the execution of fault-tolerant quantum logic operations using the physical transport of qubits. In one exemplary embodiment, the computer-executable instructions, when executed by a controller processing element, are configured to cause the quantum processor to execute a first portion of a logic multi-qubit gate by triggering the execution of a first group of interactions of at least two physical qubits on a first subset of at least physical qubits from a set of physical qubits. The set of physical qubits comprises a data qubit of a first logic qubit, a data qubit of a second logic qubit, and one or more auxiliary qubits. The logic multi-qubit gate is executed on at least a first logic qubit and a second logic qubit. The controller is further configured to cause the quantum processor to perform a multi-qubit quantum error correction cycle comprising the implementation of at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction, and to cause the quantum processor to perform a second part of a logic multi-qubit gate by causing the implementation of a second group of at least two physical qubit interactions for a second subset of at least physical qubits from a set of physical qubits.

[0066] In one exemplary embodiment, at least one interaction of at least two physical qubits from a second group of interactions of at least two physical qubits is modified at least in part based on at least one quantum error correction.

[0067] In one exemplary embodiment, a computer executable instruction, when executed by a controller processing element, is configured to cause the controller to perform at least one of the following: (a) to cause the implementation of a physical correction on at least one of the first or second logic qubits after the completion of a logic multi-qubit gate based on at least one quantum error correction; or (b) to cause the implementation of an operation on at least one of the first or second logic qubits after the completion of the logic multi-qubit gate has been corrected at least in part based on at least one quantum error correction.

[0068] In one exemplary embodiment, a physical correction is performed on at least one of the first logical qubit or the second logical qubit before the implementation of a second group of interactions of at least two physical qubits.

[0069] In one exemplary embodiment, the computer executable instruction is further configured, when executed by the controller's processing element, to cause the controller to trigger at least one of at least one syndrome or at least one quantum error correction tracking in classical memory.

[0070] In one exemplary embodiment, performing at least one of a first group of interactions of at least two physical qubits, at least one syndrome circuit segment, or a second group of interactions of at least two physical qubits comprises causing the transport of one or more physical qubits from a set of physical qubits into or out of one or more interaction zones defined by a quantum processor.

[0071] The present invention has been described in general terms as described above, and the attached drawings are referenced here, which are not necessarily drawn to scale. [Brief explanation of the drawing]

[0072] [Figure 1] This is a schematic diagram illustrating an exemplary quantum computing system according to one exemplary embodiment. [Figure 2A] This is a top view of a portion of an exemplary confinement device for an exemplary quantum processor at different time points, according to an exemplary embodiment. [Figure 2B] This is a top view of a portion of an exemplary confinement device for an exemplary quantum processor at different time points, according to an exemplary embodiment. [Figure 3] This flowchart shows various processes, operations, and / or procedures performed by a quantum computing system, such as the quantum computing system in Figure 1, to implement a quantum circuit, according to various embodiments. [Figure 4] This is a schematic diagram of an exemplary controller configured to control the operation of a confinement device according to one exemplary embodiment. [Figure 5] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 4, to implement a quantum error correction cycle, according to various embodiments. [Figure 6] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 4, to determine the syndrome of logical qubits, according to various embodiments. [Figure 7] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 4, in conjunction with a classical computation entity in Figure 9, in order to determine a syndrome for one or more logical qubits, according to various embodiments. [Figure 8] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 4, to determine the syndrome of logical qubits, according to various embodiments. [Figure 9]This is a schematic diagram of an exemplary computational entity that may be used according to an exemplary embodiment. [Figure 10] This flowchart shows various processes, operations, and / or procedures performed by a controller, such as the controller in Figure 4, to implement fault-tolerant logic multi-qubit gates in various embodiments. [Modes for carrying out the invention]

[0073] The present invention will be described more fully later with respect to the accompanying drawings, which illustrate some, but not all, embodiments of the invention. In fact, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments specified herein. Rather, these embodiments are provided to satisfy the legal requirements to which this disclosure is applicable. The term "or" (also written as " / ") is used herein in both an alternative and conjunctive sense unless otherwise indicated. The terms "illustrative" and "exemplary" are used as examples without indicating a level of quality. The terms "generally," "substantially," and "approximately" mean within processing and / or manufacturing tolerances and / or within the user's measurement capabilities, unless otherwise indicated. Similar numbers refer to similar elements as a whole.

[0074] Exemplary embodiments provide methods, systems, apparatus, computer program products, and controllers configured to control the operation of a quantum processor or the like for performing fault-tolerant quantum computation and / or fault-tolerant quantum error correction, wherein the implementation of a syndrome circuit segment and / or the application of physical quantum error correction involves the physical transport of one or more qubits (e.g., data qubits and / or auxiliary qubits of a logic qubit). For example, in various embodiments, the implementation of a quantum program, algorithm, or circuit (referred to herein as a quantum circuit) comprises the implementation of one or more quantum error correction cycles. For example, quantum error correction cycles may be implemented at various points in time during the implementation of a quantum circuit.

[0075] During a quantum error correction cycle, one or more syndrome circuit segments are implemented to generate, determine, and / or extract syndromes from one or more logic qubits used in the implementation of the quantum circuit. In various embodiments, the logic qubit comprises multiple data qubits and forms the binary logic element of the quantum processor. In various embodiments, the quantum error correction cycle may further include determining one or more quantum error corrections based on the generated, determined, and / or extracted syndromes, and applying one or more quantum error corrections to each logic qubit.

[0076] In various embodiments, at least one syndrome circuit segment is implemented to generate a syndrome for each logic qubit. The at least one syndrome circuit segment is implemented, at least in part, by causing the implementation of a series of transport operations and interactions of at least two physical qubits. Each transport operation in the series of transport operations and the interactions of at least two physical qubits causes a physical transport of at least one of the data qubits or auxiliary qubits of the logic qubit to each of those interaction zones, such that (a) each data qubit of the logic qubit and (b) each auxiliary qubit are arranged within respective interaction zones defined by the quantum processor, and the interactions of at least two physical qubits are performed therein. Based at least in part on the syndrome of the logic qubit, at least one quantum error correction is determined and applied to the logic qubit.

[0077] In various embodiments, quantum error correction comprises software correction, which is applied by tracking quantum errors experienced by logical qubits in a classical qubit registry corresponding to logical qubits, physically applying corrections to one or more data qubits of a logical qubit, and / or modifying logical operations performed on one or more data qubits of a logical qubit based at least in part on the determined quantum error correction.

[0078] Exemplary quantum computing systems Figure 1 shows an exemplary quantum computing system configured to perform fault-tolerant quantum error correction using data qubit transport. As is to be understood, various embodiments relate to various types of quantum computing systems in which the physical positions of the qubits are not fixed (for example, the physical qubit register is reconfigurable). For example, various embodiments relate to quantum computing systems that use ions, neutral atoms, quantum dots, quantum particles, etc., as qubits.

[0079] For example, Figure 1 shows a quantum computing system 100 based on an exemplary quantum charge-coupled device (QCCD). The quantum computing system 100 comprises a classical computing entity 10, a controller 30, and a quantum processor 115. The controller 30 is configured to control the operation of the quantum processor 115. The controller 30 and the classical computing entity 10 communicate with each other via direct wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0080] In the embodiments shown, the quantum processor 115 includes a confinement device 120 used to confine an operable object so that various functions can be performed on the operable object. For example, in various embodiments, the confinement device 120 is an ion trap. For example, in various embodiments, the operable object is an ion, a multipolar molecule, and / or a charged molecule, a charged particle, etc. Various functions can be performed on the operable object, such as state preparation, execution of logic gates, state reading / determination, cooling, and transport between different locations of the confinement device 120. In various embodiments, the logic gates performed on the operable object include transversal gates. A transversal gate is a gate on which an error correction code can achieve a conversion to a logic qubit by applying the gate to each of the data qubits of that logic qubit. For example, in a 5-qubit code, a Hadamard gate is a transversal gate if a logic Hadamard can be achieved on a logic qubit by applying Hadamard to each of the five data qubits of the logic qubit. In various embodiments, logic gates that are not transversal gates are used.

[0081] In various embodiments, the manipulable object comprises an auxiliary qubit and a plurality of data qubits, which are organized into one or more logic qubits. In various embodiments, the auxiliary qubits are used to examine the data qubits and / or logic qubits to determine one or more syndromes of them. For example, the auxiliary qubits are used to examine the data qubits and / or logic qubits such that the coherence of each data qubit of each logic qubit is maintained during the implementation of the syndrome circuit segment. This allows for the generation, determination, and / or tracking of logic qubit syndromes without breaking the coherence of each data qubit of the logic qubit.

[0082] In various embodiments, the quantum system controller 30 is configured to control the quantum processor 115, including programming, etc. For example, the quantum processor 115 includes a confinement device 120 configured to confine a plurality of manipulable objects. The quantum system controller 30 is configured to control the operation of the confinement device 20. In one exemplary embodiment, the quantum processor 115 includes a plurality of qubits (e.g., physical data qubits organized into logical qubits, auxiliary qubits, etc.). In various embodiments, the data qubits and auxiliary qubits are each embodied by the respective manipulable objects of the plurality of manipulable objects confined by the confinement device 120. In various embodiments, the quantum computer 110 includes, or communicates with, a database and / or programs (not shown) of quantum error decoders and / or quantum error correction decision applications, programs, etc. (e.g., stored by and / or running on the classical computing entity 10). For example, the database may be stored by one or more classical computing entities 10 communicating with the controller 30 via one or more wired and / or wireless networks 20, and / or in memory local to the controller 30.

[0083] In various embodiments, the quantum processor 115 includes means for controlling the development of quantum states of qubits. For example, in one exemplary embodiment, the quantum processor 115 comprises a cryostat and / or vacuum chamber 40 surrounding a confinement device 120 (e.g., an ion trap), one or more manipulators 60, one or more voltage sources 50, and / or one or more optical collection systems 70. For example, the cryostat and / or vacuum chamber 40 may be a chamber whose temperature and / or pressure are controlled. In one exemplary embodiment, one or more manipulators 60 may comprise one or more lasers (e.g., optical lasers, microwave sources, etc.). In various embodiments, one or more manipulators 60 are configured to manipulate and / or induce the development of controlled quantum states of one or more manipulable objects within the confinement device 120. In various embodiments, the manipulable objects within the confinement device 120 (e.g., ions trapped in an ion trap) behave as data qubits and / or auxiliary qubits of the quantum processor 115 of the quantum computer 110. For example, in an exemplary embodiment in which one or more manipulators 60 comprises one or more lasers, the lasers may provide one or more laser beams to a manipulable object trapped in a confinement device 120 within a cryostat and / or vacuum chamber 40. For example, the manipulators 60 may generate and / or provide laser beams configured to ionize the manipulable object, initialize the manipulable object in a defined two-state qubit space of a quantum processor, perform gates on one or more qubits of the quantum processor (e.g., logic gates on logic qubits and / or physical gates on physical qubits), read the quantum states of one or more qubits of the quantum processor, and so on.

[0084] In various embodiments, the quantum computer 110 includes an optical collection system 70 configured to collect and / or detect photons generated by qubits (for example, during a read procedure). The optical collection system 70 may comprise one or more optical elements (e.g., lenses, mirrors, waveguides, optical fiber cables, etc.) and one or more photodetectors. In various embodiments, the photodetectors may be photodiodes, photomultiplier tubes, charge-coupled device (CCD) sensors, complementary metal-oxide-semiconductor (CMOS) sensors, micro-electromechanical system (MEMS) sensors, and / or other photodetectors that sense light of the expected fluorescence wavelengths of the data qubits and / or auxiliary qubits of the quantum computer 110. In various embodiments, the detectors may be in electronic communication with the quantum system controller 30 via one or more A / D converters 425 (see Figure 4), etc.

[0085] In various embodiments, the quantum computer 110 comprises one or more voltage sources 50. For example, the voltage source 50 may comprise a plurality of voltage drivers and / or voltage sources, and / or at least one RF driver and / or voltage source. For example, in various embodiments, the voltage source 50 includes a plurality of arbitrary waveform generators (AWGs). In one exemplary embodiment, the voltage source 50 may be electrically coupled to a corresponding potential generating element (e.g., an electrode) of the confinement device 120.

[0086] In various embodiments, the classical computing entity 10 is configured to allow a user to provide input to the quantum computer 110 (for example, through the user interface of the computing entity 10) and to receive, view, and so on, outputs from the quantum computer 110. In various embodiments, the classical computing entity 10 is configured to perform one or more classical computations in real time or near real time in conjunction with the implementation of a quantum circuit by the quantum computer 10. For example, during the implementation of the quantum circuit, the controller 30 may provide one or more syndromes of one or more logic qubits, and the classical computing entity 10 determines and provides one or more corresponding quantum error corrections so that the controller 30 can perform quantum error correction in real time while the quantum circuit is being implemented.

[0087] The classical computing entity 10 performs classical computing operations using semiconductor-based hardware and is therefore referred to herein as “classical.” The classical computing entity 10 may communicate with the quantum system controller 30 of the quantum computer 110 via one or more wired or wireless networks 20, and / or via direct wired and / or direct wireless communications. In one exemplary embodiment, the classical computing entity 10 may perform conversions, configurations, and formats of information / data, quantum computing algorithms and / or circuits, etc., into a computational language, executable instructions, command sets, etc., that the quantum system controller 30 can understand and / or implement. For example, the controller 30 is configured to generate machine code-level commands that, when executed by the appropriate components of the quantum computer 110, are configured to trigger the implementation of quantum circuits by the quantum computer 110. In various embodiments, the classical computing entity 10 may provide quantum computing algorithms and / or circuits in a computational language that the quantum system controller 30 resolves into individual or set operations and / or machine code-level commands.

[0088] In various embodiments, the classical computing entity 10 and the controller 30 are coupled in a low-latency manner for communication. For example, the controller 30 may be configured to invoke classical operations, programs, modules, functions, etc., operating on the classical computing entity 10 (e.g., using a Foreign Function Interface (FFI), an Application Programming Interface (API), or other suitable interface). The results of these exchanges between the controller 30 and the classical computing entity 10 may be used to dynamically modify and / or act upon quantum circuits implemented by the quantum processor 115, in real time, in the circuit, etc. Thus, in one exemplary embodiment, the latency of communication between the classical computing entity 10 and the controller 30 is minimized.

[0089] In various embodiments, the quantum system controller 30 is configured to control a voltage source 50, a cryostat system and / or vacuum system that controls the temperature and pressure within the cryostat and / or vacuum chamber 40, an operating source 60, and / or other systems that control various environmental conditions (e.g., temperature, pressure, etc.) located within the cryostat and / or vacuum chamber 40 and / or configured to operate and / or induce a controlled deployment of the quantum state of one or more operable objects within the confinement device 120. For example, the quantum system controller 30 may induce a controlled deployment of the quantum state of one or more operable objects within the confinement device 120 in order to execute a quantum circuit and / or algorithm. For example, the quantum system controller 30 may, in some cases, induce the execution of a read procedure with coherent shelving as part of executing a quantum circuit and / or algorithm. In addition, the quantum system controller 30 is configured to communicate and / or receive input data from the optical collection system 70 corresponding to the reading of the quantum state of the physical data qubits and / or auxiliary qubits of the quantum computer 110. In various embodiments, the manipulable objects confined within the confinement device 120 are used as data qubits and / or auxiliary qubits of the quantum computer 110. In various embodiments, the data qubits are organized into logic qubits, and the auxiliary qubits are used to non-invasively examine the data qubits and / or logic qubits.

[0090] In various embodiments, the implementation of a quantum circuit comprises the implementation of one or more quantum error correction cycles. During a quantum error correction cycle, one or more syndrome circuit segments are implemented to generate and / or extract syndromes from one or more logic qubits used in the implementation of the quantum circuit. The syndrome circuit segments are implemented, at least in part, by inducing the implementation of a series of transport operations and the interaction of at least two physical qubits. Each transport operation in the series of transport operations and the interaction of at least two physical qubits causes a physical transport of at least one of the data qubits of the logic qubit or each of the auxiliary qubits to each of those interaction zones, such that (a) each data qubit of the logic qubit and (b) each auxiliary qubit are located within respective interaction zones defined by the quantum processor, and the interaction of each at least two physical qubits is performed therein. The interaction between each auxiliary qubit and one or more data qubits of the logic qubit causes information about one or more data qubits of the logic qubit to be encoded by the auxiliary qubit in a non-invasive manner (e.g., without breaking the coherence of one or more data qubits). Therefore, the state of the auxiliary qubit can be used to determine and / or extract the syndrome of the logic qubit.

[0091] Figure 2A shows a top view of a portion of the confinement device 120 at a first time t1 during the implementation of the syndrome circuit segment. The shown portion of the confinement device 120 includes radio frequency (RF) rails 122A, 122B, and three sets of control electrodes 124A, 124B, and 124C. Each set of control electrodes 124 comprises a plurality of control electrodes 126.

[0092] In various embodiments, the RF voltage source of the voltage source 50 generates and provides RF voltage signals applied to the RF rails 122A, 122B to generate pseudopotentials that define one or more linear confinement regions (e.g., a two-dimensional or three-dimensional array of one-dimensional confinement regions). The operable object confined by the confinement device 120 is confined within one or more linear confinement regions.

[0093] Manipulable objects can be transported between different locations in the confinement device 120 through the application of a set of voltage signal sequences to the control electrode 126. For example, at time t1, manipulable objects used as the first data qubit 5A and manipulable objects used as the auxiliary qubit 8 are located within the interaction zone 128 of the confinement device 120. The first data qubit 5A is part of a logic qubit, and the interaction of at least two physical qubits may be performed on the first data qubit 5A and the auxiliary qubit 8 as part of a syndrome circuit segment to generate, determine, and / or extract a logic qubit syndrome.

[0094] At the first time t1, the second data qubit 5B is located outside the interaction zone 128. After performing at least two physical qubit interactions with the first data qubit 5A and auxiliary qubit 8, the first data qubit 5A is transported outside the interaction zone 128 and the second data qubit 5B is transported inside the interaction zone 128. For example, as shown in Figure 2B, at the second time t2, the second data qubit 5B and auxiliary qubit 8 are located inside the interaction zone 128, and the first data qubit is located outside the interaction zone 128. Then, at least two physical qubit interactions may be performed on the second data qubit 5B and auxiliary qubit 8 as part of the implementation of the syndrome circuit segment.

[0095] Exemplary Operation of a Quantum Computing System Figure 3 is a flowchart illustrating various processes, operations, and / or procedures performed by a quantum computing system, such as the quantum computing system 100, to implement a quantum circuit according to various embodiments. For example, the quantum circuit may be acquired by the controller 30 (e.g., accessed from memory 410, received via communication interface 420, etc. (see Figure 4)), compiled, etc. The controller 30 can then cause the quantum computing system 100 to start executing the quantum circuit (optionally via user input received via classical computing entity 10 and / or via the user interface of the controller 30).

[0096] Starting in block 302, the state of the physical qubits is prepared. In this specification, the term "physical qubit" refers to a qubit embodied by each manipulable object. Each physical qubit is either a data qubit or an auxiliary qubit. For example, data qubits and auxiliary qubits are examples of physical qubits. One or more logical qubits each comprise multiple data qubits, each forming a binary logical element of the quantum processor.

[0097] In various embodiments, the controller 30 controls the operation of the voltage source 50 to generate and provide voltage signals that transport physical qubits into and out of respective interaction zones defined by the quantum processor 115 (for example, locations in the confinement device 120 configured to intersect the physical qubits with the respective operation signals so that the physical qubits located in the interaction zones are affected by the respective operation signals). The controller 30 further controls the operation of one or more operation sources 60 so that the respective operation signals are provided to the respective interaction zones defined by the quantum processor to prepare the respective quantum states of each physical qubit. For example, in various embodiments, state preparation comprises bringing the quantum states of one or more physical qubits to known states in a defined two-state qubit space of the energy structure of each manipulable object.

[0098] In one exemplary embodiment, the state-preparation operation is not fault-tolerant. However, since the quantum information has not yet been encoded into data qubits at this point when the quantum circuit is being implemented (e.g., before the implementation of logic gates on the physical and / or logic qubits on which state-preparation is being performed has begun), the state-preparation operation may be implemented as a circuit segment that iterates until successful, ensuring in real time that the state of each qubit is fault-tolerantly prepared. For example, the execution of a syndrome circuit segment may be used to determine whether the state-preparation operation has been performed successfully.

[0099] In step / operation 304, one or more logic operations are performed on the logic qubits according to at least a portion of the quantum circuit. For example, the controller 30 may cause the quantum processor 115 to perform one or more logic operations on the logic qubits of the quantum processor 115 according to the quantum circuit. For example, performing one or more logic operations on logic qubits may include, according to the quantum circuit, transporting one or more data qubits of the logic qubit into and / or out of their respective interaction zones, causing interactions between each data qubit of the logic qubit, or performing a single and / or at least two physical qubit gate (e.g., a gate that causes interactions between two or more physical qubits) on each data qubit of the logic qubit. In various embodiments, the physical qubits (data qubits and auxiliary qubits) of the quantum computing system 100 may be physically transportable within the confinement device 120 so that any selected pair of physical qubits can be transported to the same interaction zone and interact with each other (e.g., so that two-qubit gates are performed on them). For example, the quantum circuit indicates which gates should be performed on which logic qubits and in what order.

[0100] In various embodiments, the gates implemented are transversal gates. For example, a single-qubit gate is implemented on a logic qubit by implementing a single qubit gate corresponding to each of the multiple data qubits of the logic qubit in series, in parallel, and / or a combination thereof. In various embodiments, a two-qubit gate is implemented on a first logic qubit and a second logic qubit by implementing a two-qubit gate corresponding to each pair of the first data qubit of the first logic qubit and the second data qubit of the second logic qubit.

[0101] In various embodiments, at least one non-transversal gate is used. For example, in one exemplary embodiment, the logic gates of a quantum circuit (e.g., a single logic gate and / or at least two logic qubit gates) and / or one or more gates of a syndrome circuit segment are non-transversal gates. For example, at least one gate (e.g., in a quantum circuit and / or syndrome circuit segment) may be used, in which case a first set of operators is applied to a first subset of the data qubits of the logic qubits and a second (different) set of operators is applied to a second subset of the data qubits of the logic qubits in order to perform the gate. For example, in one exemplary embodiment, a set of physical gates that result in the performance of each logic operation on one or more logic qubits is used to perform the logic operation.

[0102] At various points in time during the implementation of the quantum circuit, syndromes of one or more logic qubits are generated, determined, and / or extracted. Specifically, in step / operation 306, auxiliary qubits are used to perform syndrome extraction. For example, one or more auxiliary qubits are used to non-invasively examine data qubits and / or logic qubits. For example, the interaction between each auxiliary qubit and one or more data qubits of a logic qubit ensures that information about one or more data qubits of a logic qubit is encoded by the auxiliary qubit non-invasively (e.g., without breaking the coherence of one or more data qubits).

[0103] In various embodiments, syndrome extraction is performed through the implementation of a syndrome circuit segment. The implementation of a syndrome circuit segment comprises the implementation of a series of transport operations and the interaction of at least two physical qubits. Each transport operation in the series of transport operations and the interaction of at least two physical qubits causes a physical transport of at least one of the data qubits or auxiliary qubits of a logic qubit to each of those interaction zones, such that (a) each data qubit of the logic qubit and (b) each auxiliary qubit are located within the respective interaction zones defined by the quantum processor 115. The interaction of at least two physical qubits is then performed on the data qubit and auxiliary qubit in the interaction zones, such that information about the data qubit is encoded into the quantum state of the auxiliary qubit without disturbing the quantum state of the data qubit. In various embodiments, the implementation of a syndrome circuit segment may include the implementation of various forms of lattice surgery and / or interaction between two or more auxiliary qubits.

[0104] In various embodiments, a syndrome circuit segment is implemented using one or more auxiliary qubits and one or more data qubits of a logic qubit to generate, determine, and / or extract a syndrome of a logic qubit. A syndrome circuit is a relatively short circuit (compared to a quantum circuit) configured to encode information about one or more data qubits of a logic qubit into the quantum states of one or more auxiliary qubits, such that the auxiliary qubits can be read to determine a syndrome of a logic qubit having one or more data qubits without destroying the coherence and / or quantum information stored in one or more data qubits of the logic qubit. For example, a syndrome of a logic qubit is configured to provide information about the occurrence, location, and / or type of errors that the logic qubit experiences.

[0105] For example, one or more quantum error correction cycles may be performed to generate, determine, and / or extract a syndrome of one or more logic qubits in a fault-tolerant manner. Fault tolerance, as used herein, refers to a design principle that ensures that a fault does not spread too quickly within the quantum circuit to become an uncorrectable logic error. For example, each quantum error correction cycle includes the implementation of one or more syndrome circuit segments. In various embodiments, generating, determining, and / or extracting a syndrome of one or more logic qubits in a fault-tolerant manner comprises performing multiple syndrome extraction cycles for each logic qubit and comparing the results of the multiple syndrome extraction cycles. For example, the fault tolerance of quantum error correction may be a probability-based fault tolerance.

[0106] In various embodiments, one or more quantum error correction cycles include the implementation of one or more flagged syndrome circuit segments. In one exemplary embodiment, when it is determined that the current value (e.g., quantum state) of an auxiliary qubit used as a flag in the implementation of a flagged syndrome circuit for a logic qubit is different from the previous value (e.g., quantum state) of an auxiliary qubit used as a flag in a previous implementation of the flagged syndrome circuit for the logic qubit, an unflagged syndrome circuit segment is implemented to gather additional information about one or more errors experienced by the logic qubit. For example, in one exemplary embodiment, a quantum error decoder (e.g., operating on classical computation entity 10 and / or controller 30) is invoked to determine one or more quantum error corrections only when the implementation of an unflagged syndrome circuit is triggered. For example, the quantum error decoder is configured to receive syndromes for logic qubits that are generated, determined, and / or extracted using the unflagged syndrome circuit segments in order to determine one or more quantum error corrections for the logic qubit.

[0107] Continuing with Figure 3, in step / operation 308, one or more quantum error corrections for one or more logic qubits are determined based on the respective syndromes generated, determined, and / or extracted from them. For example, one or more syndromes generated, determined, and / or extracted from logic qubits during a syndrome extraction step (e.g., step / operation 306) are provided to a quantum error decoder operating on the classical computation entity 10 and / or controller 30. The quantum error decoder is a program, application, etc., configured to determine one or more quantum error corrections for logic qubits based on one or more syndromes for the logic qubits. In one exemplary embodiment, the quantum error decoder is embodied as one or more lookup tables. In various embodiments, the quantum error decoder is configured to determine one or more quantum error corrections based on one or more syndromes with respect to receiving one or more syndromes as input.

[0108] In various embodiments and scenarios, the determined quantum error correction is the identity operation. For example, when no error is detected and / or when one or more syndromes for a logical qubit do not indicate the presence of an error, the determined quantum error correction is to make no adjustments or modifications to the qubit. For example, the determined quantum error correction may be to apply a software correction equivalent to applying the identity operator to the classical qubit registry corresponding to the logical qubit.

[0109] In step / operation 310, the classical qubit registry (for example, stored in memory 410 and / or memories 922, 924) is updated based on the extracted syndrome and / or determined quantum error correction. For example, the controller 30 may ensure that the extracted syndrome and / or determined quantum error correction are tracked (for example, in classical memory). In an exemplary embodiment, the syndrome value (and flag, if important) and / or determined quantum error correction are stored for the entire implementation of the quantum circuit. In an exemplary embodiment, the syndrome value and / or determined quantum error correction are tracked for a time frame (for example, for a time frame of a set length of time, or for a time frame of a number of logic gates, until a trigger event is identified and the corresponding error correction is applied, etc.).

[0110] In step / operation 312, one or more quantum error corrections for a logical qubit are applied to the logical qubit. For example, the controller 30 controls the operation of various components of the quantum processor 115 (e.g., voltage source 50, operation source 60, etc.) so that one or more quantum error corrections are applied to the logical qubit. In various embodiments, the quantum error correction includes a software correction applied by tracking quantum errors experienced by the logical qubit in a classical qubit registry corresponding to the logical qubit (stored, for example, in the memory of the controller 30 and / or the memory of the classical computation entity 10), physically applying the correction to one or more data qubits of the logical qubit (e.g., through one or more single-qubit gates and / or two-qubit gates applied to various data qubits of the logical qubit), and / or modifying a logical operation performed on one or more data qubits of the logical qubit based at least in part on the determined quantum error correction.

[0111] In various embodiments, quantum error correction is not applied immediately after it is determined. For example, in various embodiments, the syndrome and quantum error correction are tracked (e.g., in memory 410 and / or memories 922, 924) for a period of time and / or until a triggering event is identified. For example, in one exemplary embodiment, the syndrome and / or quantum error correction are tracked in a classical qubit registry.

[0112] In one exemplary embodiment, a trigger event corresponds to a decision that a logic gate that does not commute with one or more quantum error corrections (e.g., a non-Clifford gate in one exemplary embodiment) will be performed on a logic qubit. For example, it may be decided that a controller is scheduled and / or a quantum circuit is instructed to perform a future execution of a logic gate that does not commute with one or more quantum error corrections (e.g., a non-Clifford gate in one exemplary embodiment) on a logic qubit. Once a trigger event is identified, any necessary physical corrections may be scheduled (before the execution of one or more gates that do not commute with quantum error corrections), and / or the execution of one or more gates that do not commute with quantum error corrections may be scheduled in a modified manner such that the execution of the gates is modified to consider and / or include one or more quantum error corrections.

[0113] As is understood, some quantum error correction involves updating the classical representation of the qubit's Pauli frame and applying it to logical qubits through updates to a classical qubit registry (e.g., software quantum error correction).

[0114] In various embodiments, the process of performing one or more logical operations on one or more logical qubits, performing syndrome generation / determination / extraction, determining quantum error correction, and applying quantum error correction is repeated multiple times until the logical operations of the quantum circuit are complete. For example, completing a quantum circuit may include preparing the physical qubits, performing logical operations, performing quantum error correction cycles, performing logical operations, performing quantum error correction cycles, performing logical operations, performing quantum error correction cycles, ..., and reading the logical qubits after all the logical operations of the quantum circuit have been performed. As is understood, in various embodiments, in an exemplary embodiment, the state preparation of auxiliary qubits is performed between each quantum error correction cycle and / or between the performance of quantum error correction cycles on different logical qubits.

[0115] Therefore, once it is determined that all logical operations of the quantum circuit have been performed, the process proceeds to step / operation 314. In step / operation 314, one or more logic qubits are read according to the quantum circuit. For example, the data qubits of the logic qubits may be transported (in series and / or parallel) to their respective read zones (which may or may not be physical parts of the same confinement device 120 as the interaction zone 128). According to the quantum circuit and the read, each data qubit may be rotated to a desired read frame.

[0116] For example, a read operation may involve an operation signal being incident on a physical qubit (e.g., a data qubit). Depending on which state the physical qubit is in in the two-state qubit space, the physical qubit either fluoresces or does not fluoresce in response to the operation signal incident on it. Based on the fluorescence observed (or not observed) by the optical collection system 70, the quantum state of the physical qubit is determined. Based on the quantum state of the data qubit of the logic qubit, the state of the logic qubit is determined. The state of the logic qubit is then used to determine the result of the quantum circuit.

[0117] In step / operation 316, in various embodiments, the last syndrome is extracted, the last correction is determined, and the last correction is applied. For example, the last syndrome of a logical qubit is determined based on the result of reading the data qubit of the logical qubit. For example, the distribution of the quantum states of the data qubit of the logical qubit provides an indication of the error the logical qubit will experience. The last syndrome of the logical qubit is then used (for example, by a quantum error decoder) to determine the last correction. In various embodiments, the last correction is a software quantum error correction. For example, since the data qubit has been read, the quantum information stored by the data qubit is corrupted. Therefore, a physical correction cannot be applied. For example, in one exemplary embodiment, the last correction is a software correction such as a Pauli frame rotation. The last correction is applied by updating the classical qubit registry corresponding to the logical qubit based on the last correction.

[0118] In step / operation 318, the output of the quantum circuit is provided after each of the last corrections has been applied to each of the logic qubits. For example, the controller 30 may provide the output of the quantum circuit to the classical computing entity 10. In another example, the classical computing entity 10 may provide an indication of the output of the quantum circuit via its user interface (e.g., display 916) and / or transmit an indication of the output of the quantum circuit to another computing entity (e.g., via transmitter 904 and / or network interface 920).

[0119] An exemplary controller for a quantum computing system In various embodiments, the quantum computer 110 comprises a quantum system controller 30 and a quantum processor 115. The quantum system controller 30 is configured to control various components of the quantum processor 115. For example, the controller 30 is configured to control the operation of components of the quantum processor 115 to trigger the implementation of a quantum circuit that includes multiple quantum error correction cycles. For example, various embodiments are configured to perform one or more quantum error corrections on one or more data qubits in real time and / or near real time in response to the occurrence of one or more quantum errors experienced by one or more data qubits, which can be evaluated as a conditional block.

[0120] In various embodiments, the quantum system controller 30 communicates with the optical collection system 70 so as to be configured to receive input data captured and / or generated by the optical collection system 70. The quantum system controller 30 is further configured to perform quantum error correction via software-based correction and / or via the physical application of quantum error correction to one or more qubits (for example, by controlling one or more voltage sources 50 and / or manipulator sources 60). In various embodiments, the quantum system controller 30 is further configured to control the cryostat system and / or vacuum system, controlling the temperature and pressure in the cryostat and / or vacuum chamber 40, the cooling system, and / or other systems that control environmental conditions (e.g., temperature, humidity, pressure, etc.) within the cryostat and / or vacuum chamber 40.

[0121] As shown in Figure 4, in various embodiments, the quantum system controller 30 may comprise various quantum system controller elements, including a processing element 405, a memory 410, a driver controller element 415, a communication interface 420, and an analog-to-digital (A / D) converter 425. In various embodiments, the quantum system controller 30 is configured to receive input data generated by the optical collection system via the A / D converter 425. In various embodiments, the processing element 405 is configured to operate as described herein. In various embodiments, the quantum system controller 30 may include additional quantum system controller elements configured to perform various functions described herein. In one exemplary embodiment, the controller 30 is similar to the controller described in U.S. Patent Application No. 63 / 235,022 filed August 19, 2021, the entirety of which is incorporated herein by reference.

[0122] In various embodiments, the processing element 405 comprises one or more processing devices, such as a processor, a programmable logic device (CPLD), a microprocessor, a coprocessing entity, an application-specific instruction set processor (ASIP), an integrated circuit, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a programmable logic array (PLA), a hardware accelerator, and other processing elements and / or circuits. The term "circuit" may refer to an entirely hardware embodiment or a combination of hardware and computer program products. In one exemplary embodiment, the processing element 405 of the quantum system controller 30 comprises and / or communicates with a clock.

[0123] In various embodiments, the memory 410 includes non-temporary memory such as volatile and / or non-volatile memory storage, such as one or more of the following: hard disk, ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. In various embodiments, the memory 410 may store a queue of commands to be executed to cause quantum algorithms and / or circuits to be executed (e.g., executable queues), qubit records corresponding to qubits of a quantum computer (e.g., in a qubit record datastore, qubit record database, qubit record table, etc.), calibration tables, computer program code (e.g., code in one or more computer languages, special quantum system controller languages, etc.). In one exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 410 (for example, by processing element 405) causes the quantum system controller 30 to perform one or more steps, actions, processes, procedures, etc., for generating one or more sets of commands configured to cause the quantum processor 115 to perform at least a portion of a quantum circuit, update one or more qubit registries, etc. In one exemplary embodiment, the execution of at least a portion of the computer program code stored in memory 410 causes the quantum system controller 30 to perform one or more commands. In various embodiments, the computation program code stored in memory 410 comprises quantum assembly (QASM) and / or quantum intermediate representation (QIR) code, and / or binary and / or machine code generated by compiling the QASM and / or QIR code.

[0124] In various embodiments, the driver controller element 415 includes one or more drivers and / or quantum system controller elements, each configured to control one or more drivers. In various embodiments, the driver quantum system controller element 415 may comprise drivers and / or driver controllers. For example, a driver controller may be configured to operate one or more corresponding drivers according to executable instructions, commands, etc., generated, scheduled, and executed by the quantum system controller 30. For example, a processing element 405 may generate one or more commands that will be executed by a first driver.

[0125] In various embodiments, the driver controller element 415 enables the quantum system controller 30 to operate a voltage source 50, an operating source 60, a cooling system, a vacuum system, and the like. In various embodiments, the drivers may be a laser driver (for example, configured to operate and / or control one or more operating sources 60), a vacuum component driver, a driver for controlling the flow of current and / or voltage applied to electrodes used to maintain and / or control the trap potential of the confinement device 120 (for example, configured to operate and / or control one or more voltage sources 50) (and / or other devices for providing a sequence of driver activity to the potential generating elements of the confinement device), a cryostat and / or a vacuum system component driver, a cooling system driver, and the like.

[0126] Each driver controller element 415 corresponds to an endpoint in the system (e.g., a component of the operating source 60, a component of the voltage source 50 (radio frequency voltage source, arbitrary waveform generator (AWG), direct digital synthesizer (DDS), and / or other waveform generators), a component of the cooling and / or vacuum system, a component of the optical collection system 70, etc.). Each endpoint in the quantum computer 110 represents an individual hardware control device. In various embodiments, each endpoint has a unique set of accepted microcommands. Examples, but not limited to, include a voltage source 50 such as a direct digital synthesizer (DDS), a component of the optical collection system 70 such as a photomultiplier tube (PMT), a component of the operating source 60 such as a laser driver and / or optical modulator switch, and / or a general-purpose output (GPO). Individual commands for the DDS allow setting the power level, frequency, and phase of the control signals it generates. In various embodiments, commands for the PMT interface include starting / stopping photon counting and resetting the count. Commands for GPO endpoints include setting and / or clearing one or more output lines. These output lines can be used to control external hardware in a manner synchronized with quantum circuit execution.

[0127] In various embodiments, the quantum system controller 30 includes means for communicating and / or receiving signals from one or more optical receiver components (e.g., of the optical collection system 70). For example, the quantum system controller 30 may include one or more analog-to-digital (A / D) converters 425 configured to receive signals from one or more optical receiver components (e.g., photodetectors of the optical collection system 70), calibration sensors, etc. In various embodiments, the A / D converters 425 are configured to write input data generated by converting the received signals generated by one or more optical receiver components of the optical collection system 70 to a memory 410.

[0128] In various embodiments, the quantum system controller 30 may include a communication interface 420 for, for example, interface with and / or communicate with a classical computing entity 10. For example, the quantum system controller 30 may include a communication interface 420 for receiving executable instructions, command sets, etc., from the computing entity 10 and providing the computing entity 10 with outputs received from the quantum computer 110 (for example, from the optical collection system 70) and / or the results of processing those outputs. In various embodiments, the computing entity 10 and the quantum system controller 30 may communicate directly via wired and / or wireless connections, and / or via one or more wired and / or wireless networks 20.

[0129] Exemplary operation of a controller in a quantum computing system Figure 5 is a flowchart illustrating various processes, operations, and / or procedures performed by the controller 30 to implement, for example, a quantum error correction cycle, according to various embodiments. For example, in various embodiments, the processes, operations, and / or procedures shown in Figure 5 are performed at various times during the implementation of the quantum circuit.

[0130] Initiating step / operation 502, the controller 30 triggers the execution of one or more syndrome circuit segments to determine one or more syndromes for one or more logic qubits. For example, the controller 30 includes means such as a processing element 405, a memory 410, a driver controller element 415, and an A / D converter 425 for triggering the execution of one or more syndrome circuit segments to determine one or more syndromes for one or more logic qubits.

[0131] For example, the quantum computing system 100 may implement a quantum circuit comprising 100 to several hundred, or even 1,000 to several thousand logic qubits. Each logic qubit comprises a plurality of data qubits, each embodied as a manipulable object that is physically transportable within the confinement device 120. For example, the physical qubits (data qubits and auxiliary qubits) of the quantum computing system 100 may be physically transportable within the confinement device 120 so that any selected pair of physical qubits can be transported to the same interaction zone and interact with each other (for example, so that a two-qubit gate is implemented on them). In other words, the quantum processor 115 has a reconfigurable physical qubit register. This feature of the quantum computing system 100 is referred to herein as all-to-all connectivity. In various embodiments, the controller 30 causes at least part of the syndrome circuit segment to be implemented by triggering a series of transport operations and the implementation of interactions of at least two physical qubits. Each transport operation in a series of transport operations and the interaction of at least two physical qubits causes a physical transport of at least one of the data qubits or auxiliary qubits of the logic qubit to each of those interaction zones, such that (a) each data qubit of the logic qubit and (b) each auxiliary qubit are placed within respective interaction zones defined by the quantum processor 115, and the interaction of at least two physical qubits takes place there (for example, by causing appropriate operational signals to be incident on the data qubit and / or auxiliary qubit in the interaction zone).

[0132] Specifically, the interaction between the data qubit and the auxiliary qubit is configured such that it does not destroy the quantum information stored by the data qubit, and encodes the information corresponding to the data qubit (and / or the data qubit of the logic qubit as a whole) into the quantum state of the auxiliary qubit. For example, a syndrome circuit segment may include the implementation of one or more two-qubit gates called controlled NOT (CNOT) gates for each data qubit and auxiliary qubit.

[0133] In various embodiments, a syndrome circuit segment ends with a read of one or more auxiliary qubits used in the syndrome circuit segment. For example, the quantum states of one or more auxiliary qubits used to implement the syndrome circuit segment may be read and / or determined. Controller 30 receives a signal from the optical acquisition system 70 indicating the result of reading one or more auxiliary qubits used to implement the syndrome circuit segment. Based on the received signal, in one exemplary embodiment, Controller 30 determines one or more syndromes for each logic qubit. In another embodiment, Controller 30 provides a classical computation entity 10 with something indicating the quantum state of one or more auxiliary qubits used to implement the syndrome circuit segment, and the classical computation entity 10 determines one or more syndromes for each logic qubit. In one exemplary embodiment, a syndrome is a set of binary values ​​(e.g., binary values ​​read from one or more auxiliary qubits), a function of the values ​​read from one or more auxiliary qubits, etc.

[0134] In various embodiments, the syndrome determined for each logic qubit by the implementation of the syndrome circuit segment is compared to a previously known value of the syndrome. For example, the syndrome determined for each logic qubit may be compared to the initial value (e.g., prepared state) of the auxiliary qubit for the first quantum error correction cycle of the quantum circuit. For example, the syndrome determined for each logic qubit may be compared to the value determined immediately before the syndrome for that logic qubit. For example, it may be determined whether the value of the syndrome has changed since the last time it was determined.

[0135] For example, in one exemplary embodiment, in step / operation 504, the controller 30 determines whether the syndrome value determined for each logic qubit through the execution of the syndrome circuit segment in step / operation 502 has changed (for example, from a previously known value). In one exemplary embodiment, the controller 30 may cause the classical computation entity 10 to determine whether the syndrome value determined for each logic qubit through the execution of the syndrome circuit segment has changed. For example, providing the classical computation entity 10 with information from which the syndrome can be determined may inspire the classical computation entity 10 to determine whether the syndrome value for each logic qubit has changed.

[0136] For example, the controller 30 and / or the classical computation entity 10 store a classical qubit registry in (e.g., memory 410 and / or memory 922, 924) containing information corresponding to each logical qubit. The classical qubit registry is a data structure stored by classical (e.g., semiconductor-based) memory, and is referred to herein as "classical" to distinguish it from physical qubit registers. For example, the classical qubit registry corresponding to each logical qubit may include information identifying the data qubits constituting each logical qubit, the organization of the data qubits constituting each logical qubit, one or more previously determined syndrome values ​​for each logical qubit, one or more software corrections applied to each logical qubit (e.g., Pauli frame rotations), a track of quantum error corrections to be physically performed on each logical qubit at some future point in time, and so on. The controller 30 and / or classical computation entity 10 compare the determined syndrome for each logical qubit with the syndrome value for each logical qubit stored in the classical qubit registry corresponding to each logical qubit in order to determine whether the syndrome value has changed.

[0137] In various embodiments, the controller 30 includes means such as a processing element 405, a memory 410, and a communication interface 420 for determining whether the syndrome for each logical qubit has changed, and / or for triggering a determination that the syndrome for each logical qubit has changed.

[0138] In one exemplary embodiment, if it is determined in step / operation 504 that the syndrome for each logic qubit has not changed (and / or in response to the determination made in step / operation 504), then it is determined that the quantum error correction cycle for each logic qubit is complete. For example, in one exemplary embodiment, when it is determined that the syndrome for each logic qubit has not changed, it is determined that quantum error correction for each logic qubit does not need to be determined and / or applied.

[0139] In one exemplary embodiment, when it is determined in step / operation 504 that the syndrome for each logic qubit has changed (and / or in response to the determination made in step / operation 504), the process proceeds to step / operation 506.

[0140] In step / operation 506, the controller 30 determines and / or triggers the determination of one or more quantum error corrections for each logical qubit, based at least in part on the syndromes for each logical qubit generated, determined, and / or extracted in step / operation 502. For example, the controller 30 may operate a quantum error decoder, or have the classical computation entity 10 operate a quantum error decoder, to determine one or more quantum error corrections for each logical qubit. The one or more quantum error corrections may be determined based on the value of the syndrome for each logical qubit, a change to the syndrome for each logical qubit, and so on. In various embodiments, the quantum error decoder is configured to determine one or more quantum error corrections based on one or more syndromes in real time or near real time with respect to receiving one or more syndromes as input. In one exemplary embodiment, the quantum error decoder is embodied as one or more lookup tables.

[0141] For example, the controller 30 includes means such as a processing element 405, a memory 410, and a communication interface 420 for determining one or more quantum error corrections for each logical qubit, and / or for triggering such determinations, based at least in part on the syndrome for each logical qubit.

[0142] In various embodiments, the controller 30 is configured to invoke one or more classical programs, modules, operations, functions, etc. (for example, operating on the classical computation entity 10). For example, the controller 30 may use a Foreign Function Interface (FFI) for invoking a quantum error decoder (for example, operating on the classical computation entity 10), and one or more syndromes for each logical qubit to the quantum error decoder. In response, the controller may receive one or more quantum error corrections for each logical qubit (for example, via an FFI response or FFI call).

[0143] In step / operation 508, the controller 30 ensures that one or more quantum error corrections are applied to a logic qubit. For example, the controller 30 includes means such as a processing element 405, a memory 410, a driver controller element 415, and a communication interface 420 for ensuring that one or more quantum error corrections are applied to a logic qubit. In various embodiments, the quantum error corrections are appropriately applied to the quantum error correction and / or quantum circuit before further implementation of the quantum circuit and / or tracked to be applied at a later point in time during the implementation of the quantum circuit. In various embodiments, one or more quantum error corrections to be applied to a logic qubit include a first quantum error correction to be performed on a first subset of the data qubits of the logic qubit, a second quantum error correction to be performed on a second subset of the data qubits of the logic qubit, and so on. In one exemplary embodiment, the first subset of data qubits and the second subset of data qubits do not overlap (for example, these two subsets have an empty intersection), and the first quantum error correction is different from the second quantum error correction.

[0144] For example, in step / operation 508A, the controller 30 applies and / or triggers software quantum error correction. For example, the classical qubit registry corresponding to each logical qubit (stored in memory 410 and / or memories 922, 924) may be updated. For example, one or more Pauli frame rotations may be added to and / or applied to the classical qubit registry corresponding to each logical qubit and / or its elements.

[0145] For example, in step / operation 508B, the controller 30 physically applies one or more quantum error corrections to one or more data qubits of each logic qubit. For example, one or more single-qubit gates or two-qubit gates may be performed on one or more data qubits of each logic qubit. For example, one or more data qubits may be transported to their respective interaction zones and interact with themselves (e.g., through the application of appropriate operational signals) so that one or more quantum error corrections are applied to one or more data qubits. In various embodiments, the transport and interaction operations of physically applying quantum error corrections to one or more data qubits are performed in parallel, in series, and / or a combination thereof. For example, the physical application of quantum error corrections may cause rotation of one or more data qubits of each logic qubit, a phase correction of each quantum state of one or more data qubits of each logic qubit, and so on.

[0146] For example, in step / operation 508C, the controller 30 modifies one or more logical operations to be performed on each logical qubit, based at least in part on the determined quantum error correction. For example, the controller 30 may ensure that the single-qubit gate or two-qubit gate to be performed on each logical qubit (and / or one or more data qubits thereof) is rotated with respect to the reference frame of each logical qubit (and / or one or more data qubits thereof).

[0147] Figure 6 is a flowchart illustrating various processes, operations, and / or procedures performed by the controller 30 to determine, for example, the syndrome of a logical qubit, according to various embodiments. For example, in one exemplary embodiment, the processes, operations, and / or procedures in Figure 6 may be performed as part of step / operation 502.

[0148] Initiating step / operation 602, the controller 30 triggers the performance of a state-preparation operation on one or more auxiliary qubits. For example, performing a state-preparation operation on an auxiliary qubit sets the quantum state of the auxiliary qubit to a known state (e.g., a specific state in a two-state qubit space). For example, the controller 30 may control the operation of one or more voltage sources 50, manipulators 60, etc., to position one or more auxiliary qubits in the appropriate location in the confinement device 120 so that one or more manipulator signals are incident on each of the auxiliary qubits so that each of the quantum states of the one or more auxiliary qubits is in a known state.

[0149] In various embodiments, one or more auxiliary qubits may be used to generate, determine, and / or extract syndromes from a plurality of logic qubits. For example, in one exemplary embodiment, auxiliary qubits are used to implement a syndrome circuit segment for two or more logic qubits of a plurality of logic qubits. In such embodiments, previous syndrome values ​​are stored in a classical qubit registry (stored in memory 410 or memory 922, 924), and the auxiliary qubits can be reinitialized and reused through the implementation of a state-prepared operation. This reduces the overall number of physical qubits required to implement a quantum circuit, since each logic qubit does not need to have its own dedicated auxiliary qubit. In various embodiments, this technical improvement is enabled, at least in part, by the all-to-all connectivity of physical qubits.

[0150] In step / operation 604, the controller 30 triggers the execution of a series of transport operations and interactions of at least two physical qubits according to the syndrome circuit segment. In various embodiments, a particular series of transport operations and interactions of at least two physical qubits are controlled by the position of each physical qubit of the quantum processor 115 at the time the syndrome circuit segment is initiated, and the specific interactions required by the syndrome circuit segment. In various embodiments, the interactions of at least two physical qubits may be interactions of two or more auxiliary qubits, interactions of two or more data qubits, interactions of at least one auxiliary qubit and at least one data qubit, etc., according to the quantum circuit and / or syndrome circuit segment.

[0151] Each transport operation in the series of transport operations and the interaction of at least two physical qubits causes a physical transport of at least one of the data qubits or auxiliary qubits of the logic qubit to the respective interaction zones defined by the quantum processor, such that (a) each data qubit of the logic qubit and (b) each auxiliary qubit are located within those respective interaction zones. Each interaction of at least two physical qubits in the series of transport operations and the interaction of at least two physical qubits causes a non-invasive transfer of information about the quantum state of the data qubit to the auxiliary qubit (for example, such that the quantum information stored by the data qubit is not corrupted).

[0152] In one exemplary embodiment, auxiliary qubits are maintained within their respective interaction zones, and data qubits are transported in and out of the interaction zones to enable interaction between at least two physical qubits of the syndrome circuit segment.

[0153] In step / operation 606, one or more auxiliary qubits are read. For example, the data qubit of a logic qubit may be transported outside the interaction zone containing the auxiliary qubit, and / or the auxiliary qubit may be moved to a read zone defined by the quantum processor 115. The controller 30 then controls the operation of one or more operation sources 60 so that one or more appropriate operation signals are incident on each of the auxiliary qubits. The controller 30 then controls the operation of the optical collection system 70 to observe any fluorescence emitted by the auxiliary qubit so that the quantum state of each of the auxiliary qubits can be determined.

[0154] In step / operation 608, the syndrome of each logic qubit is determined based on the quantum state determined for the auxiliary qubit through the read operation. For example, the controller 30 determines the quantum state of each auxiliary qubit based on the signal received from the element of the optical collection system 70 corresponding to the location of each auxiliary qubit. For example, if a photodetector configured to fix the location of the first auxiliary qubit observes significant fluorescence during the read operation of the first auxiliary qubit, the first auxiliary qubit is determined to be in the first state of the two-state qubit space. If a photodetector configured to fix the location of the second auxiliary qubit does not observe significant fluorescence during the read operation of the second auxiliary qubit, the second auxiliary qubit is determined to be in the second state of the two-state qubit space. In one exemplary embodiment, the syndrome of each logic qubit depends on one or more quantum states of the auxiliary qubit. Thus, the controller 30 determines the syndrome for each logic qubit based on the respective determined quantum states of the auxiliary qubits.

[0155] In one exemplary embodiment, a syndrome circuit segment is performed more than once to determine whether the syndromes generated, determined, and / or extracted through multiple entities of the syndrome circuit segment are the same, and / or to determine a representative syndrome based on multiple entities of performing the syndrome circuit segment. For example, in one exemplary embodiment, steps / operations 602-606 are performed multiple times, and step / operation 608 includes processing and / or analyzing the distribution of syndromes generated, determined, and / or extracted through multiple entities of performing steps / operations 602-606 to determine the respective syndrome for each logic qubit. For example, a first syndrome circuit segment may be performed multiple times, and the distribution of syndromes generated, determined, and / or extracted may be analyzed and / or processed to determine a representative syndrome corresponding to the first syndrome circuit segment, such as one that will be used to determine quantum error correction for each logic qubit, or one that will be used to update the classical qubit registry for each logic qubit. For example, by repeating the first syndrome circuit segment multiple times, uncertainties in measurements, interactions of at least two physical qubits, and read operations can be "averaged."

[0156] In one exemplary embodiment, one or more syndromes generated, determined, and / or extracted from each logic qubit through the implementation of a syndrome circuit segment are stored in a classical qubit registry corresponding to each logic qubit (for example, stored in memory 410 and / or memories 922, 924), unlike the corresponding one or more syndromes stored in the classical qubit registry corresponding to each logic qubit, which is updated to reflect and / or include the most recently determined (representative) syndrome.

[0157] In various embodiments, several syndrome circuit segments are implemented to generate, determine, and / or extract multiple syndromes for each logic qubit. For example, different syndrome circuit segments are configured to identify and / or characterize different quantum errors that each logic qubit may experience. In various embodiments, the controller 30 is programmed to implement each of a defined set of syndrome circuit segments. In one exemplary embodiment, each of the syndrome circuit segments from the defined set of syndrome circuit segments is implemented during each quantum error correction cycle. In one exemplary embodiment, a first set of syndrome circuit segments is implemented, and based on the results, the controller 30 determines whether (and possibly which syndrome circuit segments) additional syndrome circuit segments from the defined set of syndrome circuit segments need to be implemented.

[0158] Figure 7 is a flowchart illustrating various processes, operations, and / or procedures performed by the controller 30, possibly in conjunction with a classical computation entity 10, to determine, for example, a syndrome for one or more logic qubits, where the result of a first plurality of syndrome circuit segments is used to determine whether a second plurality of syndrome circuit segments should be performed and / or which second plurality of syndrome circuit segments should be performed. In one exemplary embodiment, the processes, operations, and / or procedures in Figure 7 are performed as part of step / operation 502.

[0159] Initiating step / operation 702, the first plurality of syndrome circuit segments are selected from a defined set of syndrome circuit segments. In one exemplary embodiment, the controller 30 and / or classical computation entity 10 select the first plurality of syndrome circuit segments randomly and / or based on a probabilistic process from a defined set of syndrome circuit segments. In one exemplary embodiment, the controller 30 and / or classical computation entity 10 select the first plurality of syndrome circuit segments from a defined set of syndrome circuit segments based at least in part on one or more syndromes previously generated, determined, and / or extracted from each or another logic qubit used in the implementation of the quantum circuit. For example, the controller 30 and / or classical computation entity 10 select the first plurality of syndrome circuit segments from a defined set of syndrome circuit segments based at least in part on errors that have already been observed and / or are expected to exist in the implementation of the quantum circuit. In one exemplary embodiment, a first set of syndrome circuit segments are selected from a defined set of syndrome circuit segments before the start of the quantum circuit implementation, based on quantum errors identified in a previous implementation of the quantum circuit, user inputs, and the like.

[0160] In step / operation 704, the controller 30 triggers the implementation of the first set of syndrome circuit segments. For example, the controller 30 controls the operation of various elements of the quantum processor 115 so that each syndrome is generated, determined, and / or extracted from its respective logic qubit, so that the first set of syndrome circuit segments are implemented. For example, a process similar to that described with respect to Figure 6 may be performed for each syndrome circuit segment of the first set of syndrome circuit segments.

[0161] In step / operation 706, the results of the first multiple syndrome circuit segments are processed and / or analyzed by the controller 30 and / or the classical computation entity 10. For example, the distribution of syndromes, the distribution of changes in syndromes, etc., may be determined and processed. For example, in one exemplary embodiment, the results of the first multiple syndrome circuit segments are processed using probabilistic techniques to determine and / or predict whether all, most, and / or dominant errors experienced by each logic qubit are captured and / or characterized through the implementation of the first multiple syndrome circuit segments.

[0162] In step / operation 708, based on the results of processing and / or analyzing the results of the first multiple syndrome circuit segments, the controller 30 and / or classical computation entity 10 determine whether the quantum error cycle syndrome extraction process is complete. For example, if the results of processing and / or analyzing the results of the first multiple syndrome circuit segments indicate that all, most, and / or dominant errors experienced by each logic qubit have been captured and / or characterized through the implementation of the first multiple syndrome circuit segments, then the quantum error cycle syndrome extraction process is determined to be complete. For example, if the results of processing and / or analyzing the results of the first multiple syndrome circuit segments indicate that some, most, and / or dominant errors experienced by each logic qubit have not been captured and / or characterized through the implementation of the first multiple syndrome circuit segments, then the quantum error cycle syndrome extraction process is determined to be incomplete, and the process proceeds to step / operation 710.

[0163] In another example, the quantum error cycle syndrome extraction process is determined to be complete when it is determined that a sufficient amount of information has been extracted from one or more logical qubits so that a quantum error decoder operating on the classical computation entity 10 can determine an appropriate quantum error correction for the logical qubits. For example, if it is determined that there is not enough information for the quantum error decoder operating on the classical computation entity 10 to confidently determine an appropriate quantum error correction for the logical qubits, the quantum error cycle syndrome extraction process is determined to be incomplete, and the process proceeds to step / operation 710.

[0164] In step / operation 710, a second set of syndrome circuit segments is selected from a defined set of syndrome circuit segments. In one exemplary embodiment, the controller 30 and / or the classical computation entity 10 selects the second set of syndrome circuit segments randomly and / or based on a probabilistic process from a defined set of syndrome circuit segments. In one exemplary embodiment, the controller 30 and / or the classical computation entity 10 selects the second set of syndrome circuit segments from a defined set of syndrome circuit segments based at least in part on the results of performing the first set of syndrome circuit segments. For example, the controller 30 and / or the classical computation entity 10 selects the second set of syndrome circuit segments from a defined set of syndrome circuit segments based at least in part on errors already observed and / or expected to exist in the implementation of the quantum circuit, additional information required for the quantum error decoder to confidently determine appropriate quantum error correction, etc. In one exemplary embodiment, the second set of syndrome circuit segments are selected from a defined set of syndrome circuit segments before the start of the quantum circuit implementation, based on quantum errors identified in a previous implementation of the quantum circuit, user inputs, etc. In various embodiments, there may be overlap between the first set of syndrome circuit segments and the second set of syndrome circuit segments. In one exemplary embodiment, the first set of syndrome circuit segments do not overlap with the second set of syndrome circuit segments.

[0165] In step / operation 712, the controller 30 triggers the implementation of the second set of syndrome circuit segments. For example, the controller 30 controls the operation of various elements of the quantum processor 115 so that each syndrome is generated, determined, and / or extracted from its respective logic qubit, so that the second set of syndrome circuit segments are implemented. For example, a process similar to that described with respect to Figure 6 may be implemented for each syndrome circuit segment of the second set of syndrome circuit segments.

[0166] In step / operation 714, the results of the second plurality of syndrome circuit segments are processed and / or analyzed by the controller 30 and / or the classical computation entity 10. For example, the distribution of syndromes, the distribution of syndrome changes, etc., may be determined and processed. For example, in one exemplary embodiment, the results of the second plurality of syndrome circuit segments are processed using probabilistic techniques to determine and / or predict whether all, most, and / or dominant errors experienced by each logic qubit have been captured and / or characterized through the implementation of the first plurality of syndrome circuit segments and the second plurality of syndrome circuit segments. In one exemplary embodiment, the controller 30 and / or the classical computation entity 10 may determine whether a third plurality of syndrome circuit segment should be implemented. In one exemplary embodiment, once the implementation of the second plurality of syndrome circuit segments is complete, it is determined that syndrome extraction of the quantum error correction cycle is complete.

[0167] In various embodiments, a defined set of syndrome circuit segments includes flagged and unflagged syndrome circuit segments. A flagged syndrome circuit segment uses an auxiliary qubit as a flag qubit (or one or more auxiliary qubits as a flag qubit). The value of the flag qubit is configured to indicate the presence or absence of one or more specific types of errors in the quantum circuit and / or each logic qubit. In various embodiments, a flagged syndrome circuit segment is configured to determine the specific syndrome of each logic qubit using fewer auxiliary qubits than the corresponding conventional and / or unflagged syndrome circuit segment. In one exemplary embodiment, the flag qubit is configured to indicate when an error occurred while the syndrome circuit segment was being implemented.

[0168] Figure 8 is a flowchart illustrating various processes, operations, and / or procedures performed by the controller 30 to determine the syndrome of a logic qubit using, for example, a combination of flagged and unflagged syndrome circuit segments, according to various embodiments. For example, a flagged syndrome circuit segment may be used to identify the presence (and / or absence) of a Hook error, where the interaction between the auxiliary qubit and the data qubit causes the diffusion of a logic error. For example, in one exemplary embodiment, the processes, operations, and / or procedures in Figure 8 may be performed as part of step / operation 502.

[0169] Initiating step / operation 802, the controller 30 triggers the implementation of the first flagged syndrome circuit segment. For example, the controller 30 controls the operation of various elements of the quantum processor 115 so that the first flagged syndrome is generated, determined, and / or extracted from each logic qubit so that the first flagged syndrome circuit segment is implemented. For example, a first set of flag qubit values ​​is determined through the implementation of the first flagged syndrome circuit segment. For example, a process similar to that described with respect to Figure 6 may be implemented to trigger the implementation of the first flagged syndrome circuit segment.

[0170] In various embodiments, a first flagged syndrome circuit segment examines a first set of embodiments of each logic qubit. For example, a first flagged syndrome circuit segment examines a first set of ballasts. For example, when a ballast code is used to perform fault-tolerant quantum error correction, a set of commutative operators called ballasts is measured and / or used to detect the errors experienced by each logic qubit. The measurement results of the ballasts form an error syndrome which can be processed using a quantum error decoder to determine one or more quantum error corrections. Thus, in an exemplary embodiment, a first flagged syndrome circuit segment is configured to examine a first set of these ballasts.

[0171] In step / operation 804, a first set of flag qubit values ​​(for example, a set of values ​​representing the quantum state of each auxiliary qubit used as a flag qubit in a first flagged syndrome circuit segment) is compared with a previous first set of flag qubit values ​​stored in the classical qubit registry corresponding to each logical qubit. For example, the controller 30 and / or the classical computation entity 10 compare the determined first set of flag qubit values ​​with the first set of flag qubit values ​​stored in the classical qubit registry to determine whether the first set of flag qubit values ​​has changed from the (immediately) previously determined first set of flag qubit values.

[0172] When the first set of determined flag qubit values ​​is the same as the first set of flag qubit values ​​stored in the classical qubit registry, the corresponding syndrome remains unchanged. When the first set of determined flag qubit values ​​is not the same as the first set of flag qubit values ​​stored in the classical qubit registry, the corresponding syndrome has changed.

[0173] (Direct) If the first set of flag qubit values ​​has changed from the first set of flag qubit values ​​determined previously, as determined in step / operation 804 (and / or in response to that determination), the process proceeds to step / operation 810. (Direct) If the first set of flag qubit values ​​has not changed from the first set of flag qubit values ​​determined previously, as determined in step / operation 804 (and / or in response to that determination), the process proceeds to step / operation 806.

[0174] In step / operation 806, the controller 30 triggers the implementation of a second flagged syndrome circuit segment. For example, the controller 30 controls the operation of various elements of the quantum processor 115 so that a second flagged syndrome is generated, determined, and / or extracted from each logic qubit so that the second flagged syndrome circuit segment is implemented. For example, a second set of flag qubit values ​​is determined through the implementation of the second flagged syndrome circuit segment. For example, a process similar to that described with respect to Figure 6 may be implemented to trigger the implementation of the second flagged syndrome circuit segment.

[0175] In various embodiments, a second flagged syndrome circuit segment examines a second set of embodiments of each logic qubit. For example, a second flagged syndrome circuit segment examines a second set of ballasts. For example, in one exemplary embodiment, a second flagged syndrome circuit segment is configured to examine a second set of ballasts. In various embodiments, the first set of ballasts and the second set of ballasts do not overlap. In one exemplary embodiment, the first set of ballasts and the second set of ballasts are orthogonal to each other and / or examine orthogonal frames of each logic qubit.

[0176] In step / operation 808, a second set of flag qubit values ​​(for example, values ​​indicating the quantum state of an auxiliary qubit used as a flag qubit in a second flagged syndrome circuit segment) is compared to a previous second set of flag qubit values ​​stored in the classical qubit registry corresponding to each logical qubit. For example, the controller 30 and / or the classical computation entity 10 compare the determined second set of flag qubit values ​​to a second set of flag qubit values ​​stored in the classical qubit registry to determine whether the second set of flag qubit values ​​has changed from the second set of flag qubit values ​​determined (immediately) earlier.

[0177] When the second set of determined flag qubit values ​​is the same as the second set of flag qubit values ​​stored in the classical qubit registry, the corresponding syndrome remains unchanged. When the second set of determined flag qubit values ​​is not the same as the second set of flag qubit values ​​stored in the classical qubit registry, the corresponding syndrome has changed.

[0178] (Directly) If the second set of flag qubit values ​​has changed from the second set of flag qubit values ​​determined previously, when it is determined in step / operation 808 (and / or in response to that determination), the process proceeds to step / operation 810. (Directly) If the second set of flag qubit values ​​has not changed from the second set of flag qubit values ​​determined previously, when it is determined in step / operation 808 (and / or in response to that determination), it is determined that the quantum error correction cycle for each qubit is complete. For example, from each previously determined value stored in the classical qubit registry, it may be determined that the first set of flag qubit values ​​has not changed and the second set of flag qubit values ​​has not changed, so no new quantum error correction needs to be determined and applied.

[0179] In step / operation 810, the controller 30 triggers the execution of an unflagged syndrome circuit segment. In one exemplary embodiment, the unflagged syndrome circuit segment measures and / or determines a value corresponding to each ballast in the set of ballasts. For example, the result of the unflagged syndrome circuit segment is a set of syndromes, each containing a syndrome for each ballast in the set of ballasts. For example, a process similar to that described with respect to Figure 6 may be performed to trigger the execution of an unflagged syndrome circuit segment.

[0180] In step / operation 812, the classical qubit registry for each logical qubit (for example, stored in memory 410 and / or memories 922, 924) is updated using a first and / or second set of determined flag qubit values ​​and the determined syndromes. For example, the classical qubit registry for each logical qubit is updated based on the results of performing a first flagged syndrome circuit segment, a second flagged syndrome circuit segment, and / or an unflaged syndrome circuit segment. For example, the controller 30 and / or the classical computation entity 10 update the classical qubit registry for each logical qubit based on the results of performing a first flagged syndrome circuit segment, a second flagged syndrome circuit segment, and / or an unflaged syndrome circuit segment.

[0181] Exemplary Computational Entity Figure 9 provides a schematic diagram for illustrative purposes representing an exemplary classical computing entity 10 (also referred to herein as the computing entity) that may be used in conjunction with embodiments of the present disclosure. In various embodiments, the classical computing entity 10 is a classical (e.g., semiconductor-based) computer configured to allow a user to provide inputs to a quantum computer 110 (e.g., through the user interface of the computing entity 10) and to receive, display, analyze, etc., outputs from the quantum computer 110. In one exemplary embodiment, the classical computing entity 10 is part of a controller 30.

[0182] As shown in Figure 9, the classical computing entity 10 may include an antenna 912, a transmitter 904 (e.g., wireless), a receiver 906 (e.g., wireless), and a processing element 908 that provides signals to the transmitter 904 and receives signals from the receiver 906. The signals provided to the transmitter 904 and received from the receiver 906 may include information / data signaling in accordance with applicable wireless system air interface standards for communication with various entities such as the quantum system controller 30 and other computing entities 10. The computing entity 10 may also include a network interface 920 that can provide and receive signals in accordance with applicable network system interface standards for communication with various entities such as the quantum system controller 30 and other computing entities 10.

[0183] In this regard, the computing entity 10 may be capable of operating with one or more air interface standards, communication protocols, modulation types, and access types. For example, the computing entity 10 may be configured to receive and / or provide communications using wired data transmission protocols such as Fiber Distributed Data Interface (FDDI), Digital Subscriber Line (DSL), Ethernet, Asynchronous Transfer Mode (ATM), Frame Relay, Data Over Cable Service Interface Specification (DOCSIS), or any other wired transmission protocol.Similarly, computation entity 10 handles general packet radio service (GPRS), Universal Mobile Telecommunications System (UMTS), Code Division Multiple Access 2000 (CDMA2000), CDMA2000 1X (1xRTT), Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Time Division Synchronous Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), Evolved Universal Terrestrial Radio Access Network (E-UTRAN), Evolution-Data Optimized (EVDO), High Speed ​​Packet Access (HSPA), High-Speed ​​Downlink Packet Access (HSDPA), IEEE 802.11 (Wi-Fi), Wi-Fi Direct, 802.16 (WiMAX), and ultra-wideband It may be configured to communicate over a wireless external communication network using any of the following protocols: UWB (Ultra-Wide Blocking), infrared (IR) protocol, near-field communication (NFC) protocol, Wibree, Bluetooth protocol, wireless universal serial bus (USB) protocol, and / or any other wireless protocol.Computational entity 10 may use protocols and standards such as Border Gateway Protocol (BGP), Dynamic Host Configuration Protocol (DHCP), Domain Name System (DNS), File Transfer Protocol (FTP), Hypertext Transfer Protocol (HTTP), HTTP over TLS / SSL / Secure, Internet Message Access Protocol (IMAP), Network Time Protocol (NTP), Simple Mail Transfer Protocol (SMTP), Telnet, Transport Layer Security (TLS), Secure Sockets Layer (SSL), Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Datagram Congestion Control Protocol (DCCP), Stream Control Transmission Protocol (SCTP), and HyperText Markup Language (HTML) to communicate.

[0184] Through these communication standards and protocols, the computing entity 10 can communicate with various other entities using concepts such as Unstructured Supplementary Service information / data (USSD), Short Message Service (SMS), Multimedia Messaging Service (MMS), Dual-Tone Multi-Frequency Signaling (DTMF), and / or Subscriber Identification Module Dialer (SIM Dialer). The computing entity 10 can also download changes, add-ons, and updates to its firmware, software (including, for example, executable instructions, applications, and program modules), and operating system.

[0185] The computational entity 10 may also include a user interface device comprising one or more user input / output interfaces (e.g., a display 916 and / or speaker / speaker driver coupled to the processing element 908, a touchscreen, keyboard, mouse, and / or microphone coupled to the processing element 908). For example, a user output interface may be configured to provide applications, browsers, user interfaces, interfaces, dashboards, screens, web pages, pages, and / or similar words used interchangeably herein, which run on and / or are accessible through the computational entity 10, in order to trigger the display or audible presentation of information / data, and for interaction with them via one or more user input interfaces. A user input interface may comprise any of several devices that enable the computational entity 10 to receive data, such as a keypad 918 (hard or soft), a touch display, a voice / speech or motion interface, a scanner, a reader, or other input device. In embodiments including a keypad 918, the keypad 918 may include (or trigger the display of) conventional numeric keys (0-9) and associated keys (#, *), as well as other keys used to operate the computational entity 10, and may include a complete set of alphanumeric keys, or a set of keys that can be activated to provide a complete set of alphanumeric keys. In addition to providing input, the user input interface may be used to enable or disable several functions, such as a screen saver and / or sleep mode. Through such input, the computational entity 10 can collect information / data, user interaction / input, etc.

[0186] The computation entity 10 may also include volatile storage or memory 922 and / or non-volatile storage or memory 924, which may be embedded and / or removable. For example, non-volatile memory may be ROM, PROM, EPROM, EEPROM, flash memory, MMC, SD memory card, memory stick, CBRAM, PRAM, FeRAM, RRAM, SONOS, racetrack memory, etc. Volatile memory may be RAM, DRAM, SRAM, FPM DRAM, EDO DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RDRAM, RIMM, DIMM, SIMM, VRAM, cache memory, register memory, etc. The volatile and non-volatile storage or memory may store databases, database instances, database management system entities, data, applications, programs, program modules, scripts, source code, object code, bytecode, compiled code, interpreted code, machine code, executable instructions, etc., in order to implement the functions of the computation entity 10.

[0187] In various embodiments, the classical computation entity 10 is configured to receive information from the controller 30 (e.g., auxiliary qubit values, data qubits and / or logical qubit values, syndromes corresponding to each logical qubit, etc.) and perform various operations based on it. For example, the classical computation entity 10 may receive auxiliary qubit values ​​and determine one or more syndromes for one or more logical qubits. For example, the classical computation entity 10 may be configured to operate a quantum error decoder and / or otherwise determine one or more quantum error corrections for one or more logical qubits based on one or more syndromes for each of the one or more logical qubits. For example, the classical computation entity 10 may determine one or more quantum error corrections for each logical qubit and provide (e.g., transmit) the quantum error corrections so that the controller 30 can receive the quantum error corrections and trigger their implementation. In one exemplary embodiment, the classical computation entity 10 stores and / or updates one or more qubit registries (e.g., in memories 922, 924) based on one or more quantum error corrections.

[0188] Exemplary operation of a controller in a quantum computing system for implementing fault-tolerant logic multi-qubit gates In various embodiments, the quantum computer 110 is configured to implement fault-tolerant logic multi-qubit gates. For example, the controller 30 is configured to control the quantum processor 115 to implement fault-tolerant logic multi-qubit gates (e.g., logic gates implemented in a fault-tolerant manner for two or more logic qubits).

[0189] In various embodiments, the implementation of a logical multi-qubit gate comprises the implementation of a series of at least two physical qubit interactions between each physical qubit of a set of physical qubits comprising the data qubit of the logical qubit on which the gate is implemented and one or more auxiliary qubits. In various embodiments, the series of at least two physical qubit interactions is divided into two or more groups such that the logical multi-qubit gate is partially implemented. Between consecutive parts, a multi-qubit quantum error correction cycle may be implemented. In various embodiments, the multi-qubit quantum error correction cycle is similar to the quantum error correction cycles described elsewhere in this specification.

[0190] In various embodiments, as a result of performing a multi-qubit quantum error correction cycle, the interaction of one or more or at least two physical qubits in a contiguous portion of a logical multi-qubit gate may be corrected based on the determined quantum error correction. In various embodiments, one or more quantum error corrections are performed between and / or after the performance of the contiguous portion of the logical multi-qubit gate.

[0191] In various embodiments, the controller induces a syndrome and / or quantum error correction tracking determined during a multi-qubit quantum error correction cycle in classical memory.

[0192] In various embodiments, the implementation of at least one of the group of interactions of at least two physical qubits and / or at least one syndrome circuit segment of a multi-qubit quantum error correction cycle includes causing the transport of one or more physical qubits into or out of one or more interaction zones defined by the quantum processor.

[0193] Figure 10 provides a flowchart illustrating various processes, procedures, and operations performed by the controller 30 to cause the quantum processor 115 to implement a fault-tolerant logic multi-qubit gate for at least a first logic qubit and a second logic qubit.

[0194] Initiating step / operation 1002, the controller causes the quantum processor to implement a first part of a logic multi-qubit gate. In various embodiments, causing the implementation of the first part of a logic multi-qubit gate comprises causing the implementation of a first group of interactions of at least two physical qubits for a first subset of physical qubits of a set of physical qubits. The set of physical qubits comprises a data qubit of the first logic qubit, a data qubit of the second logic qubit, and one or more auxiliary qubits. The logic multi-qubit gate is implemented for at least the first logic qubit and the second logic qubit.

[0195] In step / operation 1004, the controller causes the quantum processor to perform a multi-qubit quantum error correction cycle. In various embodiments, performing a multi-qubit quantum error correction cycle comprises performing at least one syndrome circuit segment to determine at least one syndrome and at least one quantum error correction. For example, the syndrome circuit segment may be performed as described elsewhere herein to determine each syndrome, and the quantum error correction may be determined based on the determined syndrome (for example, using a quantum error decoder operating on a classical computation entity 10).

[0196] In various embodiments, a multi-qubit quantum error correction cycle may result in the determination of one or more syndromes for a first logic qubit and / or one or more syndromes for a second logic qubit. In various embodiments, a multi-qubit quantum error correction cycle may result in the determination of one or more syndromes describing the combination of errors present in the first logic qubit and the second logic qubit and the corresponding quantum error corrections. For example, the first logic qubit and the second logic qubit may be treated separately and / or independently during the multi-qubit quantum error correction cycle, or they may be treated as a combined set of physical qubits during the multi-qubit quantum error correction cycle.

[0197] In step / operation 1006, the controller may ensure that the syndrome and / or quantum error correction determined through a multi-qubit quantum error correction cycle is tracked in classical memory (e.g., memory 410 and / or memory 922, 924). As understood, the syndrome tracking and / or quantum error correction may include the application of software corrections to a classical qubit registry stored in classical memory (e.g., memory 410 and / or memory 922, 924).

[0198] In step / operation 1008, the controller causes the implementation of one or more physical corrections to one or more data qubits of the first logic qubit and / or the second logic qubit, and / or causes the modification of the interaction of one or more at least two physical qubits of the second part (or third part or other consecutive part) of the logic multi-qubit gate based on the determined quantum error correction. For example, in one exemplary embodiment, the interaction of at least one at least two physical qubits from the second group of at least two physical qubit interactions is modified at least in part based on at least one quantum error correction. For example, in one exemplary embodiment, a physical correction is implemented on at least one of the first logic qubit or the second logic qubit before the implementation of the second group of at least two physical qubit interactions.

[0199] In step / operation 1010, the controller causes the quantum processor to perform a second part of a logical multi-qubit gate. For example, the controller causes the quantum processor to perform a second group of interactions of at least two physical qubits on a second subset of at least two physical qubits of a set of physical qubits.

[0200] In step / operation 1012, the controller triggers the implementation of quantum error correction on the first and / or second logic qubit (e.g., determined during a multi-qubit quantum error correction cycle). For example, in one exemplary embodiment, the controller triggers (a) a physical correction being implemented on at least one of the first or second logic qubit after the completion of the logic multi-qubit gate based on at least one quantum error correction, or (b) at least one of an operation being performed on at least one of the first or second logic qubit after the completion of the logic multi-qubit gate has been corrected, based at least in part on at least one quantum error correction.

[0201] In various embodiments, implementing at least one of a first group of interactions of at least two physical qubits, at least one syndrome circuit segment, or a second group of interactions of at least two physical qubits comprises causing the transport of one or more physical qubits into or out of one or more interaction zones defined by a quantum processor, in order to enable the implementation of each at least two physical qubit interaction within one or more interaction zones.

[0202] Technical advantages Complex quantum computations require levels of precision unattainable by conventional quantum computers, for example, due to imperfect control and noise in gate operations between data qubits. Proposed methods for quantum error correction involve syndrome extraction, which generally includes the interaction of auxiliary qubits with data qubits. However, if not implemented carefully, such interactions between auxiliary and data qubits can catastrophically propagate errors, leading to logic errors that would otherwise be correctable considering the initial weights. Thus, there are technical problems regarding how to perform quantum computations with a level of precision sufficient to perform complex calculations. Furthermore, there are technical problems regarding how to extract the information needed to diagnose and correct errors from logic qubits without causing further error propagation.

[0203] Various embodiments provide technical solutions to such technical problems. For example, various embodiments realize the implementation of fault-tolerant quantum computation and / or fault-tolerant quantum error correction using physical transport of physical qubits. For example, syndromes can be generated, determined, and / or extracted from logic qubits through the interaction of data qubits of logic qubits with auxiliary qubits. Data qubits and / or auxiliary qubits can be physically transported in and out of interaction zones so that the auxiliary qubits can interact with multiple data qubits of logic qubits. In addition, auxiliary qubits can be used to implement syndrome circuit segments for multiple logic qubits (sequentially). Thus, various embodiments realize fault-tolerant quantum error correction with a minimum and / or fewer auxiliary qubits. By minimizing and / or reducing the number of auxiliary qubits required, the number of physical qubits used can be reduced and / or, more physical qubits of the quantum processor 115 can be available as data qubits, allowing a larger number of logic qubits to be used. In addition, in various embodiments, using flagged syndrome circuit segments to determine when or whether the implementation of unflashed syndrome circuit segments is guaranteed allows for the identification of when additional error diffusion is occurring and its mitigation. Thus, various embodiments result in improvements over conventional quantum error correction methods.

[0204] conclusion Many modifications and other embodiments of the invention as defined herein will be recalled by those skilled in the art to which the invention relates, who benefit from the teachings presented in the above description and the accompanying drawings. It should be understood that the invention is not to be limited to any particular embodiment disclosed, and that modifications and other embodiments are intended to be included within the scope of the appended claims. Certain terms are used herein, but they are used comprehensively and not restrictively. [Explanation of Symbols]

[0205] 10 Classical Computation Entities 20 Wired / Wireless Networks 30 controllers 40 Cryostat / Vacuum Chamber 50 Voltage source 60 Operation source 70 Light Collection System 100 Quantum Computing Systems 110 Quantum Computers 115 Quantum Processors 120 Confinement device 122 RF Rail 124 Control electrodes 126 Control electrodes 128 Interaction Zones 405 Processing element 410 memory 415 Driver Controller Elements 420 Communication Interfaces 425 A / D converter 904 Transmitter 906 Receiver 908 Processing elements 912 Antenna 916 displays 918 Keypad 920 Network Interfaces 922 Volatile memory 924 Non-volatile memory

Claims

1. A method carried out by a quantum computing system comprising a classical computing entity, a controller, and a quantum processor, wherein the controller is configured to (a) control the operation of the quantum processor and (b) communicate with the classical computing entity, and the method The steps include: causing the controller to perform the implementation of at least one syndrome circuit segment to generate a logic qubit syndrome, wherein the at least one syndrome circuit segment is performed at least partially by causing the implementation of a series of transport operations and interactions of at least two physical qubits, each of the transport operations and interactions of at least two physical qubits causing the physical transport of at least one of (a) the data qubit of the logic qubit or (b) the auxiliary qubit of the logic qubit to each interaction zone, such that at least one of the data qubit of the logic qubit or (b) the auxiliary qubit of the logic qubit is located in each interaction zone defined by the quantum processor, and the interactions of at least two physical qubits of the logic qubit are performed therein; The steps include determining at least one quantum error correction by the classical computation entity based at least partially on the syndrome of the logical qubit, A method comprising the step of causing the controller to update a classical memory of at least one of the controller or the classical computation entity based on the syndrome or at least one of the at least one quantum error correction.

2. The controller further comprises the step of applying the at least one quantum error correction to the logical qubit, the step of applying the at least one quantum error correction to the logical qubit, A step of updating a classical qubit registry corresponding to a logical qubit based on at least one quantum error correction, A step that causes a physical correction to one or more data qubits of the logical qubit, or A step to ensure that a logical operation performed at least partially on one or more data qubits of the logical qubit is modified at least partially based on the at least one quantum error correction. The method according to claim 1, comprising at least one of the following.

3. The steps include: causing the execution of a state preparation circuit segment to prepare the state of each of the auxiliary qubits before causing the execution of the at least one syndrome circuit segment; The method according to claim 1, further comprising the step of reading each of the auxiliary qubits after the execution of the series of transport operations and the interaction of at least two physical qubits, wherein the syndrome of the logical qubit is generated at least in part on the result of the reading of each of the auxiliary qubits.

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