Methods for operating information technology systems, information technology systems, and vehicles

Abstract

The present invention relates to a method for operating an information technology system, in which a program code usable by a processor for processing at least one task (1.1, 1.2) is divided by a compiler into at least two functional blocks (2) during a compilation step, which are arranged in a data flow graph (3), and the compiler analyzes the data flow graph (3) to determine the execution order of each functional block (2) by the processor. The method according to the present invention is characterized in that, when processing the at least one task (1.1, 1.2), the compiler identifies functional blocks (2) that can be executed in parallel by the processor, checks for each group (4) of functional blocks (2) that can be executed in parallel whether at least program code portions of at least two functional blocks (2) require the execution of the same instruction (5) by the processor, and assigns these program code portions to the same execution unit of the processor for simultaneous processing according to a single instruction, multiple data approach.

Description

Technical Field

[0001] The present invention relates to a method of operating an information technology system of the type defined in detail in the preamble of claim 1, a corresponding information technology system, and a vehicle equipped with such an information technology system.

Background Art

[0002] Information technology systems such as computers, embedded systems, or similar computing devices have become indispensable in daily life in order to solve various problems. In this case, the development goal is to improve the performance of hardware components while miniaturizing them. This makes it possible to solve complex tasks even in the context of automotive applications.

[0003] For example, with the progress of digitization, the importance of computer systems in vehicles is also increasing. Modern vehicles are equipped with various control devices for, for example, power train control, navigation route calculation, or communication connection between the vehicle and the Internet. In this case, in order to maintain the user experience, for example, by processing user input fast enough and outputting corresponding responses fast enough, high-performance hardware components are indispensable so that, for example, control signals with time constraints can be calculated fast enough. Furthermore, in a vehicle, the mounting space for incorporating computing components is limited. In addition to this, incorporating such a computing device must not significantly increase the manufacturing cost of the vehicle. These factors make the development of computer systems provided in the automotive field particularly difficult. In short, there is a need to constantly improve the performance and efficiency of computing components.

[0004] A well-known approach for accelerating computer-aided problem solving is parallelization. Modern processors are equipped with a plurality of execution units such as, for example, arithmetic cores, which makes it possible to perform so-called multithreading, that is, to process different tasks simultaneously by one and the same processor.

[0005] A further method for improving computational efficiency is the Single Instruction, Multiple Data (SIMD) method. SIMD allows a computer system to apply the same arithmetic operation to multiple data points simultaneously. For example, in a PC, this can reduce the number of write and read accesses required to main memory, as well as the number of operations performed by the processor (CPU). Accordingly, the time required for a program to solve a task can be reduced. For example, D. Nuzman et al., "Vapor SIMD: Auto-vectorize once, run everywhere," International Symposium on Code Generation and Optimization (CGO 2011), 2011, pp.151-160, doi:10.1109 / CGO.2011.5764683, describes how compilers transform loops and encode multiple iterations of the same loop in parallel using SIMD instructions.

[0006] Furthermore, International Publication No. 2007 / 113369 discloses a method for generating programs that can be executed in parallel. This method describes compiling a computer program from source code into executable code, during which a dataflow graph is generated from the corresponding source code and checked to verify data dependencies. The thus generated executable program is distributed into individual packages, and these packages are distributed to individual execution units of the processor of the arithmetic unit being used. The determination of the execution order is made as late as possible to suit the arithmetic architecture of the arithmetic unit currently being used. This enables particularly efficient load balancing to individual execution units of the processor, regardless of the variety of arithmetic units available for program execution. Here again, the improvement in computational speed is based on distributing individual program parts to multiple execution units of one or more processors and parallelizing the program sequence. [Overview of the project] [Problems that the invention aims to solve]

[0007] The object of the present invention is to provide an improved method for operating information technology systems, and by using this method, the performance of information technology systems will be further improved. [Means for solving the problem]

[0008] According to the present invention, this objective is achieved by a method of operating an information technology system having the features of claim 1. Advantageous configurations and developments, as well as corresponding information technology systems and vehicles equipped with such information technology systems suitable for carrying out the method according to the present invention, will become apparent from the claims dependent on claim 1.

[0009] The standard operating method of an information technology system is that, in order to process at least one task, the program code available to the processor is divided into at least two functional blocks by the compiler during the compilation process, these are placed in a data flow graph, and the compiler analyzes this data flow graph to determine the execution order of each functional block by the processor. This standard operating method is further improved in the present invention, characterized in that the compiler identifies functional blocks that can be executed in parallel when the processor processes at least one task, and for each group of functional blocks that can be executed in parallel, it checks whether at least two program code portions of the functional blocks require the execution of the same instruction by the processor, and assigns these program code portions to the same execution unit of the processor for simultaneous processing according to a single-instruction multiple data scheme.

[0010] By using the method based on the present invention, the degree of program parallelization can be further improved. For example, not only can a processor with multiple execution units process different programs simultaneously, but a single, identical execution unit of the processor can also process different parts of the same program simultaneously in a single computation cycle. By executing partial functions of a single identical task simultaneously, cycle time in the processor is saved, thereby enabling faster resolution of the underlying task and thus faster processing of the corresponding program.

[0011] Here, the processor may have multiple execution units, such as processor cores. However, the processor does not necessarily have multiple physical execution units. Furthermore, the processor may be implemented to perform multithreading. The processor may be a central processing unit (CPU), a graphics processor (GPU), or other dedicated programmable arithmetic units, such as those integrated on a system-on-a-chip (SoC).

[0012] To identify functional blocks that can be executed in parallel, the compiler checks the interdependencies of individual functional blocks in the dataflow graph. Functional blocks typically have an input interface and an output interface. The input interface provides the functional block with the data it needs, and the output interface provides the results generated by each functional block. If one functional block requires a specific result from another functional block, or if a functional block passes its computation results to another functional block, these functional blocks cannot be executed in parallel. However, if two functional blocks do not have dependencies on their respective input and output data, they can generally be executed in parallel.

[0013] A particularly efficient application of the method according to the present invention is possible in functional blocks including loops, where these functional blocks or each of the loops have the same depth and, more preferably, the same upper limit.

[0014] In an advantageous development of this method, the compiler identifies the number of instructions to be processed by the processor for each function block that can be executed in parallel, and for each group of function blocks that can be executed in parallel, a placeholder instruction is inserted into each function block that contains fewer instructions than the function block with the largest number of instructions in that group, so that all function blocks in each group contain the same number of instructions. When the function blocks in a group of function blocks that can be executed in parallel contain the same number of instructions to be executed by the processor, it is particularly easy and efficient to assign the program code portion to the same execution unit of the processor according to the single-instruction multiple data scheme. Here, "instruction" means that the same instruction exists in all function blocks included in a group of function blocks that can be executed in parallel. For example, this instruction may be an "addition" or "multiplication" command. If an individual program code portion deviates from or is missing this instruction, for example, if a "multiplication" instruction is used instead of an "addition" instruction, or if the instruction line (command line) is completely missing, it is necessary to insert a spaceholder instruction at the corresponding location in each function block in order to perform the assignment of the program code portion according to the single-instruction multiple data scheme.

[0015] Furthermore, in a further advantageous embodiment of the method according to the present invention, if a portion of the program code included in a functional block within a group of functional blocks that can be executed in parallel contains a loop, the following processing is performed: - The compiler determines the number of iterations for each loop, - The compiler checks whether loops in a functional block containing program code that can be assigned to the same execution unit of the processor according to the single-instruction multiple-data scheme have different numbers of iterations. If this is the case (they have different numbers of iterations), The compiler processes each program code portion of a functional block simultaneously by the same execution unit of the processor according to the fewest number of iterations, and processes the program code portions of functional blocks with more iterations sequentially by the processor according to the remaining iterations.

[0016] The method according to the present invention is particularly simple and efficient to execute when the program code portions allocated to the same execution unit of the processor according to the single-instruction multiple data scheme consist only of instructions of the same type. However, the program code portions of a functional block may also include loops. In this case, if multiple functional blocks have different numbers of iterations in their corresponding loops, only the program code portions consisting of identical instructions in a group of functional blocks that can be executed in parallel can be parallelized according to the single-instruction multiple data scheme, and this follows the number of iterations of the loop with the fewest iterations. In other words, for program code portions of functional blocks with many iterations, the corresponding instructions from the remaining functional blocks cannot be used for simultaneous distribution to the processor's execution units. Therefore, the corresponding surplus is processed sequentially by the processor.

[0017] Preferably, in the case of a multithreaded processor, at least two different tasks are processed in parallel on at least two different execution units of the processor. This can further improve the degree of parallelism. In this case, it is also conceivable to use the method according to the present invention for allocating program code portions according to a single-instruction multiple-data scheme individually for each task on each execution unit of the processor. In other words, multiple tasks can be processed simultaneously on multiple execution units, and in this case, parallelism can be performed on each individual execution unit according to the method according to the present invention.

[0018] An information technology system is provided to carry out the method described above in accordance with the present invention. This information technology system may be a well-known computing device such as a PC, an embedded system, or a SoC. The method according to the present invention can be particularly useful in relation to embedded systems, because relatively low-performance hardware components are installed there, and other measures are needed to improve computing efficiency.

[0019] Such information technology systems are particularly preferably incorporated into vehicles according to the present invention. The vehicle may be any vehicle, such as a passenger car, truck, transporter, or bus. This information technology system can form a central onboard computer, a control device for a vehicle subsystem, and so on. Multiple such information technology systems may also be incorporated into the vehicle. As already mentioned at the beginning, there are limitations to incorporating high-performance computing components into vehicles. By using the method according to the present invention and incorporating such an information technology system according to the present invention, the computing efficiency of the computing device installed in the vehicle is improved, thereby improving its performance. In doing so, existing mounting space can be used in a space-saving manner, and low-cost vehicle manufacturing is guaranteed.

[0020] Further advantageous embodiments of the method for operating an information technology system based on the present invention are also evident from the embodiments described below in detail with reference to the figures. [Brief explanation of the drawing]

[0021] [Figure 1] This diagram shows program code divided into individual functional blocks, represented as a data flow graph. [Figure 2] Figure 1 shows the pseudocode for functional blocks C and D, and the assignment of instructions included in the pseudocode to the same execution unit of the processor according to the method of the present invention. [Modes for carrying out the invention]

[0022] FIG. 1 shows, in a diagram abstracted as a data flow graph 3, that program code executed on an information technology system to solve one or more tasks 1.1, 1.2 is divided into individual functional blocks 2. At this time, the functional blocks 2 correspond to sub - problems of the respective tasks 1.1, 1.2 that can be calculated independently. The processor of this information technology system can be set to execute multi - threads, whereby parallel processing of a plurality of tasks 1.1, 1.2, that is, a plurality of execution threads is possible. These execution threads can have the same execution frequency or different execution frequencies. At this time, each task 1.1, 1.2 is assigned to an individual execution unit of the processor, that is, for example, to separate arithmetic cores. This is the first possibility of program parallelization. To ensure readability, reference numerals are only attached to a part of the same type of reference objects in each figure.

[0023] The individual functional blocks 2 are provided with an input interface 2.E for reading input data and an output interface 2.A for outputting arithmetic results. Considering the corresponding data dependency relationships, the execution order of the functional blocks 2 can be derived. In information technology systems known from the prior art, the individual functional blocks 2 of each task 1.1 and 1.2 are executed sequentially. However, this wastes computing capacity. Because usually, the individual functional blocks 2, or also the program code portions included in each functional block 2, can also be executed in parallel.

[0024] For further improving the calculation efficiency, the method according to the present invention is used, by which the instructions in each individual functional block 2 including instruction 5 shown in detail in FIG. 2 can be distributed to the processor, and a part of a single task 1.1 can also be parallelized in the same way. At this time, in the method according to the present invention, the same type of instructions 5 from the functional blocks 2 that can be executed in parallel are allocated to the same execution unit of the processor according to the single instruction multiple data (SIMD) method. Therefore, in one calculation cycle, the same instruction is applied to different register areas of the same register respectively. Here, "the same type of" means the same kind of instructions, for example, when all the code lines to be parallelized contain "addition" commands, etc., which is a basic prerequisite of the SIMD method.

[0025] In addition to this, in the method according to the present invention, the corresponding compiler analyzes the data flow graph 3 shown in FIG. 1, and at this time, determines the execution order of each functional block 2. The functional block 2 can be executed in parallel when there is no dependency relationship between the data exchanged through the input interface 2.E and the output interface 2.A. This is applicable to, for example, functional blocks C and D, and C and B in FIG. 1. Furthermore, functional blocks A and H can also be parallelized. For functional blocks E and F, and functional blocks M, N, O, Q of task 1.2, parallelization is impossible because there are dependency relationships.

[0026] Hereinafter, it is assumed that functional blocks C and D can be executed in parallel. Depending on the complexity of the program code forming the group 4 of the functional blocks 2 that can be executed in parallel shown in FIG. 2, such a group 4 may include three, four, or more functional blocks 2 that can be executed in parallel.

[0027] In this case, Figure 2 abstractly shows the program code portion, including functional blocks C and D, as pseudocode. Depending on the specifications of the information technology system and the problem to be processed, any programming language that is generally conceivable can be used to implement the method according to the present invention.

[0028] The command "Mov" represents moving data from one register to another, or from memory to a register. Accordingly, register r0 is assigned the numerical value 42 or 30.

[0029] ":Loop" indicates the start of a loop, and "Bnz loop" indicates the end of a loop. It is assumed that r0=0 has been reached.

[0030] The commands "Mov" and "Add" are instructions 5 executed by the information technology system's processor. Instead of addition, multiplication or similar operations can also be requested. The command "Add r1,[r2],+r0" means, for example, that the sum of the contents of register r2 and the value of r0 is allocated to register r1. In this case, the loop shown in functional block C counts backward from 42 to 0. This backward counting operation is performed by the code line "Add r0,r0,-1".

[0031] The two lines of code, "Add r1,[r2],+r0" in functional block C and "Add r1,[r2],0" in functional block D, correspond to the same instruction 5 to the processor and access the same register area. Therefore, these are suitable for applying the assignment of instruction 5 to the same execution unit of the processor of an information technology system according to the single instruction multiple data scheme, as described by the present invention.

[0032] However, the loops contained in functional blocks C and D have different iteration counts and instruction 5s. To address this, a so-called space holder instruction 6 is initially inserted into functional block C. This ensures that functional blocks C and D have the same number of instruction 5s. For example, using the symbol "nop" as the space holder instruction 6 prevents the processor from performing any arithmetic operations when it reads the space holder instruction 6.

[0033] Because the loops in functional blocks C and D have different iteration counts, the program code portion of functional block C is executed sequentially on the processor first, followed by the execution of the program code portions of functional blocks C and D in parallel. For example, the loop in functional block C has 42 iterations, and the loop in functional block D has 30 iterations. Therefore, the loop in functional block C is executed sequentially 12 times first, and then the program code of functional blocks C and D is executed 30 times in parallel on the same execution unit of the processor. Depending on the design of the program code and the underlying programming language, it is also possible that execution occurs in parallel first, followed by sequential execution.

[0034] In Figure 2, the program code "Add r1a,[r2a],0&r1b,[r2b],+r0" shown in the dashed box represents the parallelized portion of the program code that leads to actual improvements in computational efficiency. Furthermore, the portion "Add r0,r0,-1" is also executed in fewer iterations. In other words, while the conventional technique executes 42 times sequentially and 30 times sequentially (a total of 72 iterations), this method executes 12 times in a sequential loop and 30 times in a parallelized loop (a total of 42 iterations).

[0035] In this case, registers r1 and r2 are divided into register area a and register area b, respectively. That is, in this program code, access to register area b of the first and second registers is performed according to function block C, and access to register area a of the first and second registers is performed according to the program code of function block D. [Prior art documents] [Patent Documents]

[0036] [Patent Document 1] German Patent No. 102019206584 Specification [Non-patent literature]

[0037] [Non-Patent Document 1] D. Nuzman et al. ;Vapor SIMD: Auto-vectorize once, run everywhere; International Symposium on Code Generation and Optimization (CGO 2011), 2011, pp. 151-160, doi: 10.1109 / CGO.2011.5764683

Claims

1. A method for operating an information technology system, wherein, in order to process at least one task (1.1, 1.2), program code usable by a processor is divided by a compiler in the compilation process into at least two functional blocks (2), which are arranged in a data flow graph (3), and the compiler analyzes the data flow graph (3) to determine the execution order of each of the functional blocks (2) by the processor, A method characterized in that, when processing at least one of the tasks (1.1, 1.2), the compiler identifies functional blocks (2) that can be executed in parallel by the processor, and for each group (4) of the functional blocks (2) that can be executed in parallel, it checks whether at least two functional blocks (2) have program code portions that require the execution of the same instruction (5) by the processor, and assigns these program code portions to the same execution unit of the processor for simultaneous processing in accordance with a single instruction multiple data scheme.

2. The method according to claim 1, characterized in that the compiler specifies the number of instructions (5) to be processed by the processor for each of the parallel executable functional blocks (2), and for each group (4) of the parallel executable functional blocks (2), a placeholder instruction (6) is incorporated into each functional block (C) that contains fewer instructions (5) than the functional block (D) with the maximum number of instructions in each group (4), so that all of the functional blocks (2) in each group (4) contain the same number of instructions (5).

3. If the program code portion included in the functional block (2) within the group (4) of the parallel executable functional block (2) includes a loop, - The compiler determines the number of iterations of each loop, - The compiler checks whether the loops in the functional block (2) that include the program code portion that can be assigned to the same execution unit of the processor according to the single instruction multiple data scheme have different iteration counts, and if they do have different iteration counts, - The compiler causes each program code portion of the functional blocks (C, D) to be processed simultaneously by the same execution unit of the processor according to the fewest number of iterations, and the program code portion of the functional block (C) with a larger number of iterations to be processed sequentially by the processor according to the remaining iterations. The method according to claim 1, characterized in that

4. The method according to claim 1, characterized in that, in the case of a multithreaded processor, at least two different tasks (1.1, 1.2) are processed in parallel on at least two different execution units of the processor.

5. An information technology system characterized by comprising an apparatus for performing the method described in any one of claims 1 to 4.

6. A vehicle characterized by comprising the information technology system described in claim 5.

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