Semiconductor equipment

Abstract

A first block (11) is operated by receiving a first power supply voltage (VDD1) and a reference voltage (VSS). A second block (12) is operated by receiving a second power supply voltage (VDD2) and the reference voltage. When starting a semiconductor device (1a), the timing for changing the voltage of a first power supply line (PL1) from the reference voltage (VSS) to the first power supply voltage (VDD1) is earlier than the timing for changing the voltage of a second power supply line (PL2) from the reference voltage (VSS) to the second power supply voltage (VDD2). A first switch (SW1) is connected between a node (Ni) that transfers signals processed by the first block (11) or the second block (12), and the second power supply line (PL2). The first switch (SW1) turns ON when the voltage of the second power supply line (PL2) is the reference voltage (VSS), and turns OFF in response to the voltage of the second power supply line (PL2) approaching the second power supply voltage (VDD2).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In recent years, semiconductor devices that operate receiving supplies of a plurality of power supply voltages, such as a mixed mounting of analog circuits and digital circuits, have been used. For example, International Publication No. 2007 / 004294 (Patent Document 1) discloses a level converter circuit (generally also referred to as a level shift circuit) that receives supplies of voltages Vd1 and Vd2 (Vd2>Vd1) and converts a signal with an amplitude of voltage Vd1 into a signal with an amplitude of voltage Vd2.

[0003] In such a configuration using a plurality of power supplies, at the time of startup of the semiconductor device, since the supply start timings of the plurality of power supply voltages are different, there is a possibility that only some of the power supply voltages are supplied. For example, in a configuration in which some power supply voltages are supplied from the outside of the semiconductor device and other power supply voltages are generated inside the semiconductor device using the some power supply voltages, inevitably, a state in which only some power supply voltages are supplied will occur. Alternatively, even in a configuration in which all of the plurality of power supply voltages are supplied from the outside of the semiconductor device, there is a case where a fixed order is provided for the input of the plurality of power supply voltages.

[0004] In a state where only some power supply voltages are supplied, there is a concern that a through current may occur in the device because some nodes become high impedance (Hi-Z) states due to the influence of the power supply voltage with a late supply start.

[0005] Patent Document 1 discloses a level converter circuit in which a switch is placed to fix the potential of the input nodes to circuit elements such as inverters when the supply of voltages Vd1 and Vd2 begins. Specifically, a P-type field-effect transistor is used as the switch, with its source connected to the supply node of voltage Vd2, its drain connected to the input node, and its gate connected to the supply node of voltage Vd1. Hereafter, P-type and N-type field-effect transistors will also be simply referred to as P-type transistors and N-type transistors.

[0006] As a result, in Patent Document 1, it becomes possible to fix the potential of the input node when voltages Vd1 and Vd2 are generated, thereby preventing the generation of the aforementioned through-current. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] International Publication No. 2007 / 004294 [Overview of the Initiative] [Problems that the invention aims to solve]

[0008] However, in the configuration of Patent Document 1, in the P-type transistor that acts as a potential-fixing switch when voltages Vd1 and Vd2 are first supplied, a voltage difference of (Vd1-Vd2) is continuously generated between the gate and source after the supply of voltages Vd1 and Vd2. As a result, an unnecessary leakage current dependent on the on-resistance corresponding to this voltage difference is continuously generated in the P-type transistor, raising concerns that the power consumption of the semiconductor device after startup (during steady-state operation) will increase.

[0009] This disclosure was made to solve these problems, and the purpose of this disclosure is to achieve both the prevention of through-current during startup and the reduction of power consumption after startup in a semiconductor device that operates under multiple power supply voltages with different supply start timings. [Means for solving the problem]

[0010] In certain aspects of this disclosure, a semiconductor device is provided. The semiconductor device comprises a first power supply line receiving a first power supply voltage, a second power supply line receiving a second power supply voltage, a reference voltage line transmitting a reference voltage, a first block, a second block, and a first switch. When the semiconductor device is started up, the timing at which the voltage of the first power supply line changes from the reference voltage to the first power supply voltage is earlier than the timing at which the voltage of the second power supply line changes from the reference voltage to the second power supply voltage. The first block operates by receiving the first power supply voltage and the reference voltage from the first power supply line and the reference voltage line. The second block operates by receiving the second power supply voltage and the reference voltage from the second power supply line and the reference voltage line. The first switch is connected between a node transmitting a signal to be processed in the first or second block and the second power supply line. The first switch turns on when the voltage of the second power supply line is the reference voltage, and turns off as the voltage of the second power supply line approaches the second power supply voltage. [Effects of the Invention]

[0011] According to this disclosure, in a semiconductor device that operates on multiple power supply voltages with different start timings, the arrangement of the first switch makes it possible to prevent through-current during startup and reduce power consumption after startup. [Brief explanation of the drawing]

[0012] [Figure 1] This is a block diagram illustrating the configuration of a semiconductor device according to Embodiment 1. [Figure 2] This is a circuit diagram showing an example configuration of a pull-down switch. [Figure 3] This is a conceptual waveform diagram illustrating the startup operation of the semiconductor device according to Embodiment 1. [Figure 4] This is a block diagram illustrating the configuration of a semiconductor device according to a modified example 1 of Embodiment 1. [Figure 5]It is a block diagram for explaining the configuration of a semiconductor device according to Modification Example 2 of Embodiment 1. [Figure 6] It is a conceptual waveform diagram for explaining the operation at startup of a semiconductor device according to Modification Example 2 of Embodiment 1. [Figure 7] It is a chart for explaining a configuration example of the first block and the second block. [Figure 8] It is a conceptual waveform diagram for explaining the operation at startup of a semiconductor device according to Modification Example 3 of Embodiment 1. [Figure 9] It is a circuit diagram showing a configuration example of a pull-down switch in a semiconductor device according to Modification Example 3 of Embodiment 1. [Figure 10] It is a schematic diagram for explaining the configuration of a level shift circuit according to the first example of Embodiment 2. [Figure 11] It is a schematic diagram for explaining the configuration of a level shift circuit according to the second example of Embodiment 2. [Figure 12] It is a circuit diagram showing a configuration example of the pull-down switch shown in FIGS. 10 and 11. [Figure 13] It is a circuit diagram for explaining the configuration of a level shift circuit according to the third example of Embodiment 2. [Figure 14] It is a circuit diagram showing a configuration example of the pull-down switch shown in FIG. 13. [Figure 15] It is a circuit diagram for explaining the configuration of a level shift circuit according to the fourth example of Embodiment 2. [Figure 16] It is a schematic diagram for explaining the configuration of a level shift circuit according to Modification Example 1 of Embodiment 2. [Figure 17] It is a circuit diagram showing a configuration example of the pull-down switch shown in FIG. 16. [Figure 18] It is a schematic diagram for explaining the configuration of a level shift circuit according to Modification Example 2 of Embodiment 2. [Figure 19] It is a circuit diagram showing a configuration example of the pull-down switch shown in FIG. 18.

Embodiments of the Invention

[0013] Embodiments of this disclosure will be described in detail below with reference to the drawings. In the following, the same or corresponding parts in the drawings will be denoted by the same reference numerals, and their descriptions will not be repeated in principle.

[0014] Embodiment 1. Figure 1 is a block diagram illustrating the configuration of the semiconductor device 1a according to Embodiment 1.

[0015] As shown in Figure 1, the semiconductor device 1a according to Embodiment 1 includes power supply wiring PL1 and PL2, a reference voltage wiring SL for transmitting a reference voltage VSS, a first block 11, a second block 12, and a switch SW1.

[0016] The reference voltage VSS is typically the ground voltage; therefore, below, the reference voltage VSS will be referred to as the ground voltage VSS, and the reference voltage wiring SL will also be referred to as the ground wiring SL. Power supply wiring PL1 receives power supply voltage VDD1. Power supply wiring PL2 receives power supply voltage VDD2. In the example in Figure 1, power supply voltages VDD1 and VDD2 are supplied from outside the semiconductor device 1a.

[0017] When semiconductor device 1a is started up, upon receiving the power supply voltage VDD1, the voltage V(PL1) of the power supply wiring PL1 changes from the ground voltage VSS to the power supply voltage VDD1. Similarly, upon receiving the power supply voltage VDD2, the voltage V(PL2) of the power supply wiring PL2 changes from the ground voltage VSS to the power supply voltage VDD2.

[0018] In this embodiment, the power supply voltage VDD1 is supplied before the power supply voltage VDD2; that is, the start of supply of power supply voltage VDD1 is earlier than the start of supply of power supply voltage VDD2. In other words, the timing at which voltage V(PL1) changes from the ground voltage VSS to the power supply voltage VDD1 is earlier than the timing at which voltage V(PL2) changes from the ground voltage VSS to the power supply voltage VDD2. Each embodiment will be described under these conditions.

[0019] The first block 11 and the second block 12 are composed of transistors (typically field-effect transistors) not shown. The first block 11 processes the input signal VIN1 to generate the output signal VO1.

[0020] The second block 12 operates when the enable signal EN is at a logical high level (hereinafter simply referred to as "H level"), and stops operating when the enable signal EN is at a logical low level (hereinafter simply referred to as "L level"). When operating, the second block 12 processes the input signal VIN2 of node Ni to generate the output signal VO2. The output signal VO1 of the first block 11 may be transmitted to node Ni as the input signal VIN2. Alternatively, the output signal VO2 of the second block 12 may be processed by the first block 11 as the input signal VIN1.

[0021] Switch SW1 is connected between power supply wiring PL2, which supplies the power supply voltage VDD2 (the voltage that starts later), and node Ni, and switches on and off according to the voltage difference ΔV across power supply wiring PL2 to ground wiring SL. Specifically, it remains on when the voltage difference ΔV is small, i.e., when the voltage of power supply wiring PL2 is V(PL2) = VSS, while it turns off when the voltage of power supply wiring PL2 approaches the power supply voltage VDD2 and the voltage difference ΔV becomes large. When the voltage of power supply wiring PL2 is V(PL2) = VDD2, switch SW1 remains off.

[0022] In the example shown in Figure 1, node Ni, where switch SW1 is located, is the node that transmits the input signal VIN2 processed in the second block 12. However, it is also possible to use node Ni as the node that transmits the input signal VIN1 processed in the first block 11, and place switch SW1 between it and the power supply wiring PL2. Furthermore, it is also possible to place switch SW1 at both the node that transmits the input signal VIN1 (first block 11) and the node that transmits the input signal VIN2 (second block 12). In addition, node Ni may be an internal node (not shown) of the first block 11 or the second block 12, and can be any node that transmits the signals processed in the first block 11 or the second block 12. For example, switch SW1 can be placed at any node inside the first block 11 or the second block 12 where the generation of through-current is a concern due to the Hi-Z state, typically a node connected to the gate of a field-effect transistor.

[0023] Next, an example of the configuration of switch SW1 will be explained using Figure 2. As shown in Figure 2, for example, switch SW1 can be constructed using an N-type native transistor NN0. A native transistor is a field-effect transistor, such as a MOS (Metal Oxide Semiconductor) transistor, which is a field-effect transistor with a threshold voltage Vt near 0[V]. In contrast, the threshold voltage Vt of an enhancement-type field-effect transistor is about 0.8[V].

[0024] The native transistor NN0 is connected between node Ni and power supply wiring PL2, with its gate (control electrode) connected to the ground wiring SL. Therefore, when the voltage across power supply wiring PL2 is the ground voltage VSS, the gate-source voltage of the native transistor NN0 is 0[V], and thus it turns on. On the other hand, when the voltage across power supply wiring PL2 changes from the ground voltage VSS to the power supply voltage VDD2, the gate (G) becomes low relative to the source (S), and the native transistor NN0 turns off. As a result, the function of the switch SW1 shown in Figure 1 is realized by the N-type native transistor NN0 illustrated in Figure 2.

[0025] Figure 3 shows a conceptual waveform diagram illustrating the startup operation of the semiconductor device 1a shown in Figures 1 and 2.

[0026] Referring to Figure 3, at time t0, when the supply of power voltage VDD1 to power wiring PL1 begins, the voltage V(PL1) across power wiring PL1 rises from the ground voltage VSS. At time t1, the voltage V(PL1) reaches the power voltage VDD1.

[0027] At time t2, which is after time t0, when the supply of power voltage VDD2 to power wiring PL2 begins, the voltage V(PL2) across power wiring PL2 rises from the ground voltage VSS. At time t3, which is after time t1, the voltage V(PL2) reaches the power voltage VDD1.

[0028] The enable signal EN is set to a high level corresponding to the operating period of the second block 12. Therefore, the supply period of the power supply voltage VDD2 can also be set to correspond to the high-level period of the enable signal EN. In the example in Figure 3, the enable signal EN is set to a high level during the period from time t2 to t4.

[0029] Therefore, at time t4, the supply of the power supply voltage VDD2 to the power supply wiring PL2 is stopped. After time t4, the voltage V(PL2) of the power supply wiring PL2 changes toward the ground voltage VSS due to discharge. As will be explained in the modified example below, a pull-down switch may be provided to connect the power supply wiring PL2 to the ground wiring SL and discharge it during the L level period of the enable signal EN.

[0030] The operation of switch SW1 in response to the voltage changes in the power supply wirings PL1 and PL2 described above will now be explained. Since the grounding wiring SL is fixed to the grounding voltage VSS, the voltage difference ΔV shown in Figures 1 and 2 corresponds to the voltage V(PL2) of the power supply wiring PL2.

[0031] During the period up to time t2, before the voltage of the power supply wiring PL2 changes (V(PL2)=VSS), the gate-source voltage of the native transistor NN0 shown in Figure 2 is 0[V], corresponding to the voltage difference ΔV=0, so switch SW1 (native transistor NN0) is in the ON state. As a result, node Ni in Figure 1 is fixed at the ground voltage VSS without entering a Hi-Z state. This prevents the generation of through-current within the second block 12.

[0032] In contrast, from time t2 onward, the voltage difference ΔV increases as the voltage V(PL2) changes toward the power supply voltage VDD2. As a result, the native transistor NN0 shown in Figure 2 turns off when the voltage difference ΔV between the gate and source becomes greater than the voltage Vc, that is, when the voltage V(PL2) of the power supply wiring PL2 becomes higher than the voltage Vc. While the voltage V(PL2) > Vc, the switch SW1 (native transistor NN0) is in the off state. Note that the above voltage Vc is a constant voltage determined by the physical properties of the native transistor NN0, and is, for example, about 0.5[V].

[0033] As a result, during the period when the second block operates with the supply of the power supply voltage VDD2, the node Ni is electrically disconnected from the ground voltage VSS and transmits the input signal VIN2 to the second block 12. Further, during the period when V(PL2)>Vc, the switch SW1 (native transistor NN0) is turned off, and no useless leakage current as in Patent Document 1 occurs.

[0034] In this way, in the semiconductor device according to Embodiment 1, under the configuration that operates receiving the power supply voltages VDD1 and VDD2 with different supply start timings, between the power supply wiring PL2 that supplies the power supply voltage VDD2 with a later supply start and the node Ni, an active switch SW1 for pull-down that is turned on and off according to the voltage of the power supply wiring PL2 is provided.

[0035] As a result, during the period before the supply of the power supply voltage (V(PL2)<Vc), by turning on the switch SW1 and fixing (pulling down) the node Ni to the ground voltage VSS without putting the node Ni in the Hi-Z state, the generation of the through-current inside the second block 12 that processes the signal of the node Ni can be prevented.

[0036] Further, during the operation period of the second block 12 after the supply of the power supply voltage VDD2 (V(PL2)>Vc), by maintaining the switch SW1 off, the generation of useless power consumption current during the steady state due to the mechanism for preventing the through-current at startup is avoided. As a result, it becomes possible to achieve both the prevention of the through-current at startup and the reduction of power consumption after startup.

[0037] Modification Example of Embodiment 1. FIG. 4 is a block diagram for explaining the configuration of a semiconductor device 1b according to Modification Example 1 of Embodiment 1.

[0038] Referring to Figure 4, the semiconductor device 1b according to the modification 1 of Embodiment 1 differs from the semiconductor device 1a (Figure 1) according to Embodiment 1 in that it further includes a voltage conversion circuit 15. The voltage conversion circuit 15 generates a power supply voltage VDD2 by DC-DC conversion using the power supply voltage VDD1 on the power supply wiring PL1, and outputs the power supply voltage VDD2 to the power supply wiring PL2.

[0039] For example, the voltage conversion circuit 15 is configured to operate in response to the enable signal EN. It is understood that, by controlling the output of the power supply voltage VDD2 to the power supply wiring PL2 by the voltage conversion circuit 15 in accordance with the enable signal EN, the behavior of the voltage V(PL2) at the power supply wiring PL2 becomes the same as shown in Figure 3.

[0040] The configuration and operation of the other parts of semiconductor device 1b are the same as those of semiconductor device 1a, so a detailed explanation will not be repeated. Also, in the configuration shown in Figure 1, the voltage conversion circuit 15 may be located outside of semiconductor device 1a.

[0041] As a result, the semiconductor device according to the modified example 1 of Embodiment 1 is also provided with an active pull-down switch SW1, so it is possible to enjoy the same effects as in Embodiment 1, and to achieve both the prevention of through-current during startup and low power consumption after startup.

[0042] Figure 5 is a block diagram illustrating the configuration of the semiconductor device 1c according to a modified example 2 of Embodiment 1.

[0043] Referring to Figure 5, the semiconductor device 1c according to the modified example 2 of Embodiment 1 differs from the semiconductor device 1a (Figure 1) according to Embodiment 1 in that it further includes a switch SW2. The switch SW2 is positioned to ensure that the switch SW1 is reliably turned on during periods when the power supply voltage VDD2 is not supplied, by pulling down the power supply wiring PL2 that supplies the power supply voltage VDD2 which has a later start-up date.

[0044] Therefore, switch SW2 is connected between the ground wire SL and the power supply wire PL2 and is configured to turn on and off in response to the inverted signal of the enable signal EN. Specifically, switch SW2 is turned on during the low level period of the enable signal EN, while switch SW2 is turned off during the high level period of the enable signal EN. For example, switch SW2 can be configured as an enhancement-type N-type transistor to which the inverted signal of the enable signal EN is input to the gate.

[0045] Figure 6 shows a conceptual waveform diagram illustrating the startup operation of semiconductor device 1c shown in Figure 5. In Figure 6, a waveform indicating the on / off state of switch SW2 is added to the waveform diagram in Figure 3. That is, in Figure 6 as well, the voltages of power supply wiring PL1 and PL2, the enable signal EN, and the waveforms related to the on / off state of switch SW1 are the same as in Figure 3.

[0046] As shown in Figure 6, switch SW2 is turned off during the high-level period of the enable signal EN, i.e., when the second block 12 is operating and the power supply voltage VDD2 is supplied to the power supply wiring PL2, while it is turned on during the low-level period of the enable signal EN, i.e., when the second block 12 is not operating.

[0047] As a result, during periods when the power supply voltage VDD2 is not supplied to the power supply wiring PL2, for example, before time t2 and after time t4 in Figure 6, the power supply wiring PL2 is pulled down by being electrically connected to the ground wiring SL. This ensures that the voltage difference ΔV between the power supply wiring PL2 and the ground wiring SL during that period is 0, and that the pull-down switch SW1 located at node Ni to prevent through-current is reliably turned on.

[0048] Therefore, according to the semiconductor device of modified embodiment 2 of embodiment 1, in addition to the same effects as in embodiment 1 due to the arrangement of switch SW1, it is possible to enhance the effect of preventing through-current during startup.

[0049] Figure 7 shows examples of the configurations of the first block 11 and the second block 12 in a semiconductor device according to Embodiment 1 and its modified versions 1 and 2.

[0050] In recent years, semiconductor devices such as ASICs (Application Specific Integrated Circuits) that integrate digital and analog circuits have become widely used. It is known that the power consumption of digital circuits depends on the charging and discharging of parasitic capacitance and is proportional to the product of the operating frequency (clock frequency) and the square of the voltage amplitude of the digital signal, while the power consumption of analog circuits is proportional to the product of the power supply voltage and the bias current. For this reason, lowering the power supply voltage is highly effective in reducing the power consumption of digital circuits. In contrast, the power consumption reduction effect of lowering the power supply voltage is not as significant for analog circuits as it is for digital circuits. Therefore, considering dynamic range, distortion, noise effects, etc., lowering the power supply voltage is not always desirable.

[0051] Given this situation, there is a growing trend to adopt applications where the power supply voltages for analog and digital circuits are set to different levels. For example, the power supply voltage for digital circuits may be set to around 1.5V, while the power supply voltage for analog circuits may be 3.3V or 5V.

[0052] Therefore, as shown in the first and second examples of Figure 7, the first block 11 and the second block 12, which operate under different power supply voltages VDD1 and VDD2, can be composed of either digital or analog circuits. For example, the digital circuit may be a large-scale circuit for calculating control logic, while the analog circuit may be a small-scale circuit focused solely on signal input and output functions.

[0053] In the first example of FIG. 7, the first block 11 that operates receiving the power supply voltage VDD1 with an earlier supply start is constituted by a digital circuit, while the second block 12 that operates receiving the power supply voltage VDD2 with a later supply start is constituted by an analog circuit. In this case, since VDD1 < VDD2, the voltage conversion circuit 15 shown in FIG. 4 can be constituted by a boosting circuit such as a boost chopper or a charge pump circuit.

[0054] In the second example of FIG. 7, conversely, the first block 11 that operates receiving the power supply voltage VDD1 is constituted by an analog circuit, while the second block 12 that operates receiving the power supply voltage VDD2 is constituted by a digital circuit. In this case, since VDD2 < VDD1, the voltage conversion circuit 15 shown in FIG. 4 can be constituted by a bucking circuit such as a buck chopper or a VDC (Voltage Down Converter).

[0055] Alternatively, as shown in the third example of FIG. 7, both the first block 11 and the second block 12 may be constituted by analog circuits. Similarly, as shown in the fourth example of FIG. 7, both the first block 11 and the second block 12 may be constituted by digital circuits.

[0056] In these third and fourth examples, since the power supply voltages of the input circuit and the output circuit are to be matched to the voltage levels of the circuits connected in the previous stage or the subsequent stage, the relationship between the power supply voltages VDD1 and VDD2 may be either VDD1 > VDD2 or VDD1 < VDD2. Usually, regarding the control logic operation between the input and the output, the power supply voltage can be freely set, so it is preferable in terms of power consumption to perform it in the block with the lower power supply voltage. Therefore, in the third and fourth examples of FIG. 7 where the control logic is calculated in the first block 11, it is preferable to set VDD1 < VDD2.

[0057] As understood from FIG. 7, regardless of the levels of the power supply voltage VDD1 with an earlier supply start and the power supply voltage VDD2 with a later supply start, the semiconductor device according to the present embodiment can be applied.

[0058] Alternatively, the semiconductor device according to this embodiment can be applied even if the power supply voltage VDD2 is a negative voltage. In this case, for example, the voltage conversion circuit 15 can be configured as a charge pump circuit for generating a negative voltage.

[0059] Therefore, a configuration example in which the power supply voltage VDD2 is a negative voltage (VDD2 < 0) in the semiconductor device 1a of Figure 1 will be described below as a modification 3 of Embodiment 1.

[0060] Figure 8 shows a conceptual waveform diagram illustrating the startup operation of a semiconductor device according to Modification 3 of Embodiment 1. In Figure 8, the difference from the waveform diagram in Figure 3 is that the power supply voltage VDD2 supplied to the power supply wiring PL2 is a negative voltage (VDD2 < 0). That is, in Figure 8 as well, the voltage of the power supply wiring PL1 and the waveform of the enable signal EN are the same as in Figure 3.

[0061] As shown in Figure 9, when the power supply voltage VDD2 is a negative voltage, the switch SW1 in Figure 1 can be configured with a P-type native transistor NP0 whose threshold voltage Vt is near 0[V].

[0062] The native transistor NP0, like the native transistor NN0 in Figure 2, is connected between node Ni and power supply wiring PL2, and its gate (control electrode) is connected to the ground wiring SL.

[0063] The native transistor NP0 turns on when the voltage across the power supply line PL2 is the ground voltage VSS, because the gate-source voltage is 0[V]. On the other hand, when the voltage across the power supply line PL2 changes from the ground voltage VSS to the power supply voltage VDD2 (negative voltage), and the gate (G) becomes higher relative to the source (S), the native transistor NP0 turns off.

[0064] Referring again to Figure 8, during the period up to time t2, before the voltage of the power supply wiring PL2 changes (V(PL2)=VSS), the gate-source voltage of the native transistor NP0 shown in Figure 9 is 0[V], corresponding to the voltage difference ΔV=0, so switch SW1 (native transistor NP0) is in the ON state. As a result, node Ni in Figure 1 is fixed at the ground voltage VSS without entering a Hi-Z state. This prevents the generation of through-current inside the second block 12.

[0065] In contrast, from time t2 onward, as the voltage V(PL2) changes toward the power supply voltage VDD2 (negative voltage), the voltage difference ΔV increases. The native transistor NP0 shown in Figure 9 is turned off when the voltage difference ΔV between the gate (G) and the source (S) becomes smaller than the voltage -Vc, that is, when the voltage V(PL2) of the power supply wiring PL2 becomes lower than the voltage -Vc. While the voltage V(PL2) < -Vc, the switch SW1 (native transistor NP0) is in the off state. Note that the above voltage -Vc is a constant voltage determined by the physical properties of the native transistor NP0, and is, for example, about -0.5[V].

[0066] In summary, Figures 2 and 9 show that the switch SW1 (native transistors NN0, NP0) can operate as an active pull-down switch, as described in Embodiment 1, by turning on when the absolute value |ΔV| of the voltage difference between the power supply wiring PL2 and the ground wiring SL is less than a predetermined voltage Vc, and turning off when |ΔV| > Vc.

[0067] Thus, in the semiconductor device according to Modification 3 of Embodiment 1, even when the power supply voltage VDD2 supplied to the power supply wiring PL2 on which the switch SW1 is located is a negative voltage, it is possible to achieve both the prevention of through-current during startup and low power consumption after startup, similar to Embodiment 1.

[0068] Furthermore, in the third modification of Embodiment 1, the power supply voltage VDD1 may be a negative voltage, and a switch SW2 similar to the second modification of Embodiment 1 may be added. Also, the power supply voltage VDD2 may be configured by a voltage conversion circuit 15 located inside or outside the semiconductor device 1c. In this way, Embodiment 1 and its modifications can be combined as appropriate, within a range that does not result in technical inconsistencies or contradictions.

[0069] In the above-described embodiment 1 and its modifications, power wiring PL1 corresponds to a "first power wiring," power wiring PL2 corresponds to a "second power wiring," power voltage VDD1 corresponds to a "first power voltage," and power voltage VDD2 corresponds to a "second power voltage" embodiment. Furthermore, switch SW1 corresponds to a "first switch," and switch SW2 corresponds to a "second switch" embodiment.

[0070] Embodiment 2. Embodiment 2 will primarily describe an example of a level shift circuit configuration as a specific example of the semiconductor device described in Embodiment 1 and its variations.

[0071] Figure 10 is a schematic diagram illustrating the configuration of a level shift circuit 100 according to the first example of Embodiment 2.

[0072] Referring to Figure 10, the level shift circuit 100 includes an input section 111 that receives an input signal VIN with an amplitude equal to the power supply voltage VDD2, and an output section 121 that generates an output signal VOUT with an amplitude equal to the power supply voltage VDD1.

[0073] In Embodiment 2, as shown in Figure 3, the power supply voltage VDD1 is supplied before the power supply voltage VDD2. In addition, the level shift circuit in Embodiment 2 generates an output signal with a voltage amplitude larger than that of the input signal. That is, the power supply voltage VDD1 is higher than the power supply voltage VDD2 (VDD1 > VDD2). Also, both the power supply voltage VDD1 and the power supply voltage VDD2 are positive voltages.

[0074] The level shift circuit 100 shown in Figure 10, as a simplified configuration example, has an input section 111 and an output section 121, each composed of a single inverter. Specifically, the input section 111 has an inverter 110 that operates by receiving voltage from the power supply wiring PL2 (power supply voltage VDD2) and the grounding wiring SL (ground voltage VSS). Similarly, the output section 121 has an inverter 120 that operates by receiving voltage from the power supply wiring PL1 (power supply voltage VDD1) and the grounding wiring SL (ground voltage VSS). Each of the inverters 110 and 120 is composed of a CMOS (Complementary MOS) inverter in which a P-type transistor and an N-type transistor (not shown) are connected in series. That is, the input section 111 that operates by receiving the power supply voltage VDD2 corresponds to a specific example of the second block 12 in Embodiment 1, and the output section 121 that operates by receiving the power supply voltage VDD1 corresponds to a specific example of the first block 11 in Embodiment 1.

[0075] As a result, the level shift circuit 100 can implement a level conversion function that converts an input signal VIN, whose amplitude is equal to the power supply voltage VDD2, into an output signal VOUT, whose amplitude is equal to the power supply voltage VDD1 (VDD1 > VDD2). This makes it possible to supply a digital signal (output signal VOUT) with the amplitude of the power supply voltage VDD1 to a subsequent block or circuit that operates on the power supply voltage VDD1, thereby ensuring that the subsequent circuit or block operates reliably without leakage current.

[0076] In the level shift circuit 100, during the operation between times t0 and t2 in Figure 3, that is, during the period when the supply of power voltage VDD1 is started but before the supply of power voltage VDD2 is started, if node Ni, which is the output node of inverter 110 and the input node of inverter 120, enters a Hi-Z state, there is a risk that a shoot-through current will occur in inverter 120, which is receiving the power voltage VDD1.

[0077] Therefore, in the level shift circuit 100, the switch SW1 described in Embodiment 1 is placed between node Ni and power supply wiring PL2. In Figure 10, since the power supply voltage VDD2 is a positive voltage, the switch SW1 can be constructed using an N-type native transistor NN0, similar to Figure 2.

[0078] As shown in Figure 12, switch SW1 is composed of an N-type native transistor NN0, which is connected between node Ni in Figure 10 and power supply wiring PL2, and whose gate (control electrode) is connected to the ground wiring SL.

[0079] The native transistor NN0, which constitutes the switch SW1, turns on when the voltage difference ΔV across the power supply wiring PL2 to the ground wiring SL is less than the voltage Vc, as in Embodiment 1, and turns off when ΔV > Vc.

[0080] As a result, in the level shift circuit 100, the node Ni can be pulled down and fixed to the ground voltage VSS by turning on switch SW1 during the period before the power supply voltage VDD2 is supplied. As a result, in the inverter 120, the N-type transistor (not shown) that constitutes the CMOS inverter is fixed to the OFF position, so that no shoot-through current occurs.

[0081] Furthermore, since switch SW1 is turned off during the period when the power supply voltage VDD2 is supplied, the level shift circuit 100 can operate without generating any extra leakage current at node Ni.

[0082] As a result, the level shift circuit 100, in the circuit that realizes the level conversion function described above, can achieve both prevention of through-current during startup and low power consumption after startup, similar to the effect in Embodiment 1.

[0083] Figure 11 is a schematic diagram illustrating the configuration of a level shift circuit 101 according to a second example of Embodiment 2.

[0084] Referring to Figure 11, the level shift circuit 101 differs from the level shift circuit 100 in Figure 10 in that the input section 111 outputs complementary differential signals to nodes Nip and Nin, with the power supply voltage VDD2 as the amplitude. Therefore, the output section 121 is configured to generate an output signal VOUT with the power supply voltage VDD1 as the amplitude, based on the differential signals of nodes Nip and Nin. In the level shift circuit 101 as well, the power supply voltages VDD1 and VDD2 are supplied in the same way as in the level shift circuit 100 in Figure 10. By using differential signals, noise immunity can be improved in addition to the effects described for the level shift circuit 100.

[0085] In the level shift circuit 101, at least one of the following is provided: a switch SW1p connected between node Nip and power supply wiring PL2, and a switch SW1n connected between node Nin and power supply wiring PL2. That is, both switches SW1p and SW1n may be provided, or only one of them may be provided. Since the power supply voltage VDD2 is a positive voltage, each of switches SW1p and SW1n can be configured with an N-type native transistor NN0 similar to that in Figure 2.

[0086] Figure 12 further shows an example configuration of switches SW1p and SW1n shown in Figure 11. Referring to Figure 12, switch SW1p is composed of an N-type native transistor NN0, connected between node Nip and power supply wiring PL2 in Figure 11, with its gate (control electrode) connected to the ground wiring SL. Similarly, switch SW1n is composed of an N-type native transistor NN0, connected between node Nin and power supply wiring PL2 in Figure 11, with its gate (control electrode) connected to the ground wiring SL.

[0087] The native transistors NN0 that make up switches SW1p and SW1n turn on when the voltage difference ΔV of the power supply wiring PL2 relative to the ground wiring SL is less than the voltage Vc, and turn off when ΔV > Vc, similar to Embodiment 1.

[0088] As a result, in the level shift circuit 101, during the period before the power supply voltage VDD2 is supplied, the nodes Nip and Nin can be pulled down and fixed to the ground voltage VSS by turning on switches SW1p and SW1n. This prevents the generation of through-currents inside the output section 121.

[0089] Furthermore, during the period when the power supply voltage VDD2 is supplied, switches SW1p and SW1n are turned off in accordance with the expansion of the voltage difference ΔV, so the level shift circuit 101 can operate without generating excess leakage current at nodes Nip and Nin.

[0090] As a result, by arranging at least one of the switches SW1p and SW1n in the level shift circuit 101, it is possible to achieve both the prevention of shoot-through current during startup and low power consumption after startup, similar to the effect in Embodiment 1.

[0091] Figure 13 shows a circuit diagram illustrating the configuration of a level shift circuit 102 according to a third example of Embodiment 2. The level shift circuit 102 corresponds to the specific configuration example of the input section 111 and output section 121 shown in the level shift circuit 101 of Figure 11.

[0092] Referring to Figure 13, the level shift circuit 102 includes series-connected input stage inverters INV11 and INV12, a cross-coupled circuit 115 composed of N-type transistors MN11 and MN12 and P-type transistors MP11 and MP21, and series-connected output stage inverters INV13 and INV14.

[0093] Inverters INV11 and INV12 operate by receiving voltage from the power supply wiring PL2 (power supply voltage VDD2) and the grounding wiring SL (grounding voltage VSS). Inverter INV11 outputs a signal to node Nin that is the inverted version of the input signal VIN. Inverter INV12 inverts the signal from node Nin and outputs it to node Nip. As a result, node Nip outputs a signal that is in phase with the input signal VIN, and node Nin outputs a signal that is out of phase with the input signal VIN. The amplitude of the signal between the input signal VIN and the signals at nodes Nip and Nin is the power supply voltage VDD2.

[0094] In the cross-coupled circuit 115, the P-type transistors MP11 and MP21 are connected between the power supply wiring PL1 (power supply voltage VDD1) and nodes N1 and N2, respectively. The gate of transistor MP11 is connected to node N2, and the gate of transistor MP21 is connected to node N1.

[0095] Furthermore, the N-type transistors MN11 and MN12 are connected to nodes N1 and N2 and to the ground wire SL, respectively. The gate of transistor MN11 is connected to node Nip, and the gate of transistor MN12 is connected to node Nin.

[0096] As a result, in the cross-coupled circuit 115, the voltage difference between nodes Nip and Nin (VDD2 / VSS) is amplified to the voltage difference between nodes N1 and N2 (VDD1 / VSS), and the voltage levels of nodes N1 and N2 are latched by transistors MP11 and MP21.

[0097] Inverters INV13 and INV14 operate by receiving voltage from the power supply wiring PL1 (power supply voltage VDD1) and the ground wiring SL (ground voltage VSS). Inverter INV13 inverts the signal from node N2 and outputs it to node N3. Inverter INV14 inverts the signal from node N3 and generates the output signal VOUT.

[0098] In the level shift circuit 102, the input section 111 in Figure 11 can be configured by inverters INV11 and INV12, and the output section 121 in Figure 11 can be configured by the cross-coupled circuit 115 and inverters INV13 and INV14.

[0099] As a result, the level shift circuit 102 can convert an input signal VIN, whose amplitude is equal to the power supply voltage VDD2, into an output signal VOUT, whose amplitude is equal to the power supply voltage VDD1 (VDD1 > VDD2). In particular, the level shift circuit 102 generates the output signal VOUT by amplifying the voltage difference between differential signals based on the input signal VIN, thereby improving noise immunity in addition to the effects described for the level shift circuit 100.

[0100] In the level shift circuit 102, during the period from time t0 to t2 in Figure 3, that is, while power supply voltage VDD1 is supplied, before the supply of power supply voltage VDD2 begins, if nodes Nip, Nin, and N2 enter a Hi-Z state, there is a risk of shoot-through current occurring in the cross-coupled circuit 115 and inverters INV13 and INV14, which are receiving power supply voltage VDD1.

[0101] Therefore, the level shift circuit 102 includes at least one of the following switches: SW1x connected between node Nin and power supply wiring PL2, SW1y connected between node Nip and power supply wiring PL2, and SW1z connected between node N2 and power supply wiring PL2. In Figure 13, since the power supply voltage VDD2 is a positive voltage, each of the switches SW1x, SW1y, and SW1z can be constructed using an N-type native transistor NN0, similar to Figure 2.

[0102] Figure 14 is a circuit diagram showing an example configuration of the switches SW1x, SW1y, and SW1z shown in Figure 13.

[0103] As shown in Figure 14, switch SW1x is composed of an N-type native transistor NN0, connected between node Nin and power supply wiring PL2 in Figure 13, with its gate (control electrode) connected to the ground wiring SL. Similarly, switch SW1y is composed of an N-type native transistor NN0, connected between node Nip and power supply wiring PL2 in Figure 13, with its gate (control electrode) connected to the ground wiring SL. Furthermore, switch SW1z is composed of an N-type native transistor NN0, connected between node N2 and power supply wiring PL2 in Figure 13, with its gate (control electrode) connected to the ground wiring SL.

[0104] The native transistor NN0, which constitutes switches SW1x to SW1z, turns on when the absolute value of the voltage difference |ΔV| between the ground wire SL and the power supply wire PL2 is less than the voltage Vc, similar to Embodiment 1, and turns off when |ΔV| > Vc.

[0105] As a result, in the level shift circuit 102, during the period before the power supply voltage VDD2 is supplied, at least one of nodes Nin, Nip, and N2 can be pulled down and fixed to the ground voltage VSS by turning on switches SW1x to SW1z. This prevents through-current from occurring in the cross-coupled circuit 115 and inverters INV13 and INV14.

[0106] Furthermore, during the period when the power supply voltage VDD2 is supplied, switches SW1x to SW1z are turned off in accordance with the expansion of the voltage difference ΔV, so the level shift circuit 102 can operate without generating excess leakage current at nodes Nin, Nip, and N2.

[0107] As a result, in the level shift circuit 102, by arranging at least one of the switches SW1x to SW1z, it is possible to achieve both the prevention of shoot-through current during startup and the reduction of power consumption after startup, similar to the effect in Embodiment 1.

[0108] Figure 15 shows a circuit diagram illustrating the configuration of a level shift circuit 103 according to a fourth example of Embodiment 2.

[0109] Referring to Figure 15, the level shift circuit 103 differs from the level shift circuit 102 shown in Figure 13 in that it includes a cross-coupler circuit 115# instead of the cross-coupler circuit 115. The configuration of the other parts of the level shift circuit 103 is the same as that of the level shift circuit 102. That is, in the level shift circuit 103 as well, the input section 111 in Figure 11 can be configured by inverters INV11 and INV12, and the output section 121 in Figure 11 can be configured by the cross-coupler circuit 115# and inverters INV13 and INV14.

[0110] Cross-coupled circuit 115# differs from cross-coupled circuit 115 (Figure 13) in that multiple transistors are connected in series between nodes N1 and N2 and the power supply wiring PL1.

[0111] Specifically, between node N1 and power supply wiring PL1, N (N: natural number) P-type transistors MP11~MP1N and M (M: natural number) P-type transistors MP31~MP3M are connected in series. Each gate of transistors MP11~MP1N is connected to node N2, and each gate of transistors MP31~MP3M is connected to transistor MN 11 Similarly, it connects to node Nip.

[0112] Similarly, between node N2 and power supply wiring PL1, N P-type transistors MP21-MP2N and M P-type transistors MP41-MP4M are connected in series. Each gate of transistors MP21-MP2N is connected to node N1, and each gate of transistors MP41-MP4M is connected to transistor MN 12 Similarly, it connects to node Nin.

[0113] Since the cross-coupled circuit 115# is composed of a larger number of transistors compared to the cross-coupled circuit 115, the level-shifting circuit 103 can shorten the time required from the input of the input signal VIN to the output of the output signal VOUT compared to the level-shifting circuit 102, thereby enabling faster operation.

[0114] In the level shift circuit 103, when the supply of power voltage VDD1 is started but before the supply of power voltage VDD2 is started, if nodes Nip, Nin, and N2 are in a Hi-Z state, there is a risk of shoot-through current occurring in the cross-coupled circuit 115# and inverters INV13 and INV14, which are receiving power voltage VDD1.

[0115] Therefore, in the level shift circuit 103, similar to the level shift circuit 102, at least one of the pull-down switches SW1x, SW1y, SW1z (Figure 14) corresponding to nodes Nip, Nin, and N2 can be placed.

[0116] As a result, by arranging at least one of the switches SW1x to SW1z in the level shift circuit 103, it is possible to achieve both the prevention of shoot-through current during startup and low power consumption after startup, similar to the effect in Embodiment 1.

[0117] A modified example of Embodiment 2. In a modified example of Embodiment 2, an example of a level shift circuit configuration that operates using a negative voltage as the power supply voltage is described.

[0118] Figure 16 is a schematic diagram illustrating the configuration of a level shift circuit 100U according to a modification 1 of Embodiment 2. The level shift circuit 100U is an example of a configuration in which both power supply voltages VDD1 and VDD2 are negative voltages, as in the level shift circuit 100 shown in Figure 10. Thus, the power supply voltage VDD1 can be either a positive or negative voltage, and this embodiment can be applied to any combination of polarities (positive / negative voltage) of power supply voltages VDD1 and VDD2.

[0119] Referring to FIG. 16, the level shift circuit 100U includes an input section 111U that receives an input signal VIN having an amplitude of a power supply voltage VDD2 (VDD2 < 0), and an output section 121U that generates an output signal VOUT having an amplitude of a power supply voltage VDD1 (VDD1 < 0). That is, the input section 111U corresponds to a specific example of the second block 12 in the first embodiment, and the output section 121U corresponds to a specific example of the first block 11 in the first embodiment.

[0120] Also in the level shift circuit according to the first modification of the second embodiment, the power supply voltage VDD1 is supplied prior to the power supply voltage VDD2, and an output signal having a larger voltage amplitude than the input signal is generated. That is, the relationship VDD1 < VDD2 < 0 (VSS) holds for the power supply voltages VDD1 and VDD2.

[0121] The input section 111U can be configured, for example, by an inverter (not shown) that operates by receiving voltages from a power supply wiring PL2 (power supply voltage VDD2 < 0) and a ground wiring SL. Similarly, the output section 121U can be configured, for example, by an inverter (not shown) that operates by receiving voltages from a power supply wiring PL1 (power supply voltage VDD1 < 0) and a ground wiring SL.

[0122] In the level shift circuit 100U, during a period in which the supply of the power supply voltage VDD1 is started while the supply of the power supply voltage VDD2 has not yet been started, if a node NUi, which is the output node of the input section 111U and also the input node of the output section 121U, enters the Hi-Z state, a through-current may occur inside the output section 121U that is receiving the supply of the power supply voltage VDD1.

[0123] Therefore, in the level shift circuit 100U, a switch SW1U similar to the switch SW1 in the first embodiment is disposed between the node NUi and the power supply wiring PL2 of the power supply voltage VDD2 that is supplied later. In FIG. 16, since the power supply voltage VDD2 is a negative voltage, the switch SW1U can be configured by a P-type native transistor NP0, similar to FIG. 9.

[0124] As shown in Figure 17, switch SW1U is connected between node NUi and power supply wiring PL2 in Figure 16, and consists of a P-type native transistor NP0 whose gate (control electrode) is connected to the ground wiring SL.

[0125] As explained in Modification 3 of Embodiment 1, the native transistor NP0 that constitutes the switch SW1U turns on when the voltage of the power supply wiring PL2 is the ground voltage VSS, because the gate-source voltage is 0[V]. Conversely, when the voltage of the power supply wiring PL2 changes from the ground voltage VSS to the power supply voltage VDD2 (negative voltage), and the gate (G) becomes at a higher potential than the source (S), the native transistor NP0 turns off. That is, for the switch SW1U as well, it turns on when the absolute value of the voltage difference between the ground supply wiring SL and the power supply wiring PL2, |ΔV|, is less than the voltage Vc, while it turns off when |ΔV| > Vc.

[0126] As a result, the level shift circuit 100U can fix node NUi to the ground voltage VSS by turning on switch SW1U during the period before the power supply voltage VDD2 is supplied. This prevents the generation of through-currents inside the output unit 121U.

[0127] Furthermore, during the period when power supply voltage VDD2 is supplied, switch SW1U is voltage difference (Absolute value) Because it is turned off in response to the expansion of |ΔV|, the level shift circuit 100U can operate without generating any extra leakage current at node NUi.

[0128] As a result, by arranging the switch SW1U in the level shift circuit 100U, it is possible to achieve both the prevention of shoot-through current during startup and the reduction of power consumption after startup, similar to the effect in Embodiment 1.

[0129] FIG. 18 shows a circuit diagram for explaining the configuration of the level shift circuit 102U according to Modification 2 of Embodiment 2. The level shift circuit 102U corresponds to a configuration example in which both the power supply voltages VDD1 and VDD2 are negative voltages in the level shift circuit 102 (FIG. 13) that operates using differential signals. Also in FIG. 18, it is assumed that VDD1 < VDD2 < 0 (VSS) holds for the power supply voltages VDD1 and VDD2, and the supply of the power supply voltage VDD1 starts earlier than the supply of the power supply voltage VDD2.

[0130] Referring to FIG. 18, the level shift circuit 102U includes inverters INVU11 and INVU12 in the input stage connected in series, a cross-coupled circuit 115U constituted by N-type transistors MNU11, MNU12 and P-type transistors MPU11, MPU21, and inverters INVU13 and INVU14 in the output stage connected in series.

[0131] The inverters INVU11 and INVU12 operate by receiving voltages from the ground wiring SL (ground voltage VSS) and the power supply wiring PL2 (power supply voltage VDD2 < 0). The inverter INVU11 outputs a signal obtained by inverting the input signal VIN to the node NUin. The inverter INVU12 inverts the signal at the node NUin and outputs it to the node NUip. As a result, a signal having the same phase as the input signal VIN is output to the node NUip, and a signal having a phase opposite to the input signal VIN is output to the node NUin. The amplitudes of the input signal VIN and the signals at the nodes NUip and NUin correspond to the power supply voltage VDD2.

[0132] In the cross-coupled circuit 115U, the P-type transistors MPU11 and MPU21 are respectively connected between the ground wiring SL (ground voltage VSS) and the nodes NU1 and NU2. The gate of the transistor MPU11 is connected to the node NUip, and the gate of the transistor MPU21 is connected to the node NUin.

[0133] Furthermore, the N-type transistors MNU11 and MNU12 are connected to nodes NU1 and NU2 and to the power supply wiring PL1 (power supply voltage VDD1 < 0), respectively. The gate of transistor MNU11 is connected to node NU2, and the gate of transistor MNU12 is connected to node NU1.

[0134] As a result, in the cross-coupled circuit 115U, the voltage difference between nodes NUip and NUin (VSS / VDD2) is amplified to the voltage difference between nodes NU1 and NU2 (VSS / VDD1), and the voltage levels of nodes NU1 and NU2 are latched by transistors MNU11 and MNU12.

[0135] Inverters INVU13 and INVU14 operate by receiving voltage from the grounding wire SL (grounding voltage VSS) and the power supply wire PL1 (power supply voltage VDD1<0). Inverter INVU13 inverts the signal from node NU2 and outputs it to node NU3. Inverter INVU14 inverts the signal from node NU3 and generates the output signal VOUT.

[0136] In the level shift circuit 102U, the input section 111U in Figure 16 can be configured to output a differential signal using inverters INVU11 and INVU12. Furthermore, the output section 121U in Figure 16 can be configured to operate by receiving a differential signal using the cross-coupler circuit 115U and inverters INVU13 and INVU14.

[0137] As a result, the level shift circuit 102U can convert an input signal VIN, whose amplitude is the negative power supply voltage VDD2, into an output signal VOUT, whose amplitude is the negative power supply voltage VDD1 (|VDD1|>|VDD2|). The level shift circuit 102U can also improve its noise immunity by amplifying the voltage difference between differential signals based on the input signal VIN to generate the output signal VOUT.

[0138] In the level shift circuit 102U, when the supply of power voltage VDD1 is initiated but before the supply of power voltage VDD2 is initiated, if nodes NUip, NUin, and NU2 are in a Hi-Z state, there is a risk of shoot-through current occurring in the cross-coupled circuit 115U and inverters INVU13 and INVU14, which are receiving power voltage VDD1.

[0139] Therefore, in the level shift circuit 102U, at least one of the following is provided: switch SW1Ux connected between node NUin and power supply wiring PL2 to which the later-starting power supply voltage VDD2 is supplied; switch SW1Uy connected between node NUip and power supply wiring PL2; and switch SW1Uz connected between node NU2 and power supply wiring PL2. In Figure 18, since the power supply voltage VDD2 is a negative voltage, each of the switches SW1Ux, SW1Uy, and SW1Uz can be configured with a P-type native transistor NP0, as in Figure 9.

[0140] Figure 19 is a circuit diagram showing an example configuration of the switches SW1Ux, SW1Uy, and SW1Uz shown in Figure 18.

[0141] As shown in Figure 19, switch SW1Ux is composed of a P-type native transistor NP0, connected between node NUin and power supply wiring PL2 in Figure 18, with its gate (control electrode) connected to the ground wiring SL. Similarly, switch SW1Uy is composed of a P-type native transistor NP0, connected between node NUip and power supply wiring PL2 in Figure 18, with its gate (control electrode) connected to the ground wiring SL. Furthermore, switch SW1Uz is composed of a P-type native transistor NP0, connected between node NU2 and power supply wiring PL2 in Figure 18, with its gate (control electrode) connected to the ground wiring SL.

[0142] The native transistor NP0 that constitutes the switches SW1Ux~SW1Uz is the same as in the modified example 3 of Embodiment 1, which is the voltage difference between the ground wire SL and the power wire PL2. (Absolute value)The device turns on when |ΔV| is less than the voltage Vc, and turns off when |ΔV| > Vc.

[0143] As a result, in the level shift circuit 102U, during the period before the power supply voltage VDD2 is supplied, turning on switches SW1Ux to SW1Uz allows at least one of nodes NUin, NUip, and NU2 to be pulled down and fixed to the ground voltage VSS. This prevents through-current from occurring in the cross-coupled circuit 115U and inverters INVU13 and INVU14.

[0144] Furthermore, during the period when the power supply voltage VDD2 is supplied, switches SW1Ux~SW1Uz are at the voltage difference. (Absolute value) Because it is switched off in response to the expansion of |ΔV|, the level shift circuit 102U can operate without generating excess leakage current at nodes NUin, NUip, and NU2.

[0145] As a result, in the level shift circuit 102U, by arranging at least one of the switches SW1Ux to SW1Uz, it is possible to achieve both prevention of shoot-through current during startup and low power consumption after startup, similar to the modification 3 of Embodiment 1.

[0146] Furthermore, in the cross-coupled circuit 115U shown in Figure 18, it is also possible to increase the number of N-type transistors connected between nodes NU1 and NU2 and the power supply wiring PL1 to (M+N), similar to Figure 15, in order to achieve higher speed operation.

[0147] Furthermore, in each configuration example described in Embodiment 2 and its modified examples, the delayed-supplied power supply voltage VDD2 may be generated by converting the power supply voltage VDD1 using the voltage conversion circuit 15 (Figure 4). Alternatively, the switch SW2 shown in Figure 5 may be further arranged to reliably fix the power supply wiring PL2 to the ground voltage VSS during periods when the power supply voltage VDD2 is not supplied.

[0148] Although a level shift circuit was exemplified in Embodiment 2 and its modified form, this embodiment can be applied to any semiconductor device, including a DAC (Digital to Analog Converter) or ADC (Analog to Digital Converter), as long as it has a first block 11 and a second block 12 that operate under the same power supply voltages VDD1 and VDD2 as in this embodiment.

[0149] Furthermore, regarding the multiple embodiments and their variations described above, it is intended from the outset that the configurations described in each embodiment and its variations will be appropriately combined, including combinations not mentioned in the specification, to the extent that no inconsistencies or contradictions arise.

[0150] In this embodiment, an example was described in which the switch SW1 corresponding to the "first switch" is configured with an N-type or P-type native transistor. However, it is also possible to configure the switch using a depletion-type transistor instead of a native transistor. As is well known, an N-type depletion-type transistor has a threshold voltage of a negative voltage (for example, around -0.5[V]).

[0151] Therefore, using a depletion-type transistor is advantageous because the on-resistance when the gate-source voltage is 0[V], i.e., when the voltage difference ΔV=0, is smaller than that of a native transistor. On the other hand, when the difference between the power supply voltage VDD2 and the ground voltage VSS is small, it may not be possible to turn off the "first switch" even if the power supply voltage VDD2 is supplied, which is disadvantageous because it narrows the range of compatible power supply voltages VDD2. In other words, it is preferable to configure the "first switch" of this disclosure by selectively applying a depletion-type transistor or a native transistor, taking into account the level of the power supply voltage VDD2.

[0152] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this disclosure is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended. [Explanation of Symbols]

[0153] 1a, 1b, 1c Semiconductor device, 11 First block, 12 Second block, 15 Voltage conversion circuit, 100, 100U, 101, 102, 102U, 103 Level shift circuit, 110, 120, INV11~INV14, INVU11~INVU13, INVU14 Inverter, 111, 111U Input section, 115, 115U, 115# Cross-coupled circuit, 121, 121U Output section, EN Enable signal, NN0, NP0 Native transistor, PL1, PL2 Power supply wiring, SL Reference voltage wiring (ground wiring), SW1, SW1n, SW1p, SW1x, SW1y, SW1z, SW1U, SW1Ux, SW1Uy, SW1Uz, SW2 Switch, VDD1, VDD2 Power supply voltage, VSS Reference voltage (ground voltage).

Claims

1. A semiconductor device, A first power supply wiring that receives the first power supply voltage, A second power supply wiring that receives the second power supply voltage, Reference voltage wiring that transmits the reference voltage, A first block that operates by receiving the first power supply voltage and the reference voltage from the first power supply wiring and the reference voltage wiring, A second block that operates by receiving the second power supply voltage and the reference voltage from the second power supply wiring and the reference voltage wiring, The system comprises a node that transmits signals processed in the first block or the second block, and a first switch connected between the node and the second power supply wiring, When the semiconductor device is started up, the timing at which the voltage of the first power supply wiring changes from the reference voltage to the first power supply voltage is earlier than the timing at which the voltage of the second power supply wiring changes from the reference voltage to the second power supply voltage. The semiconductor device comprises a first switch which turns on when the voltage of the second power supply wiring is equal to the reference voltage, and turns off as the voltage of the second power supply wiring approaches the second power supply voltage.

2. The semiconductor device according to claim 1, wherein the first switch is configured to turn on when the absolute value of the voltage difference between the second power supply wiring and the reference voltage wiring is less than a predetermined voltage, and to turn off when the absolute value of the voltage difference is greater than the predetermined voltage.

3. The semiconductor device according to claim 2, wherein the first switch is composed of a native transistor or a depletion-type transistor whose control electrode is connected to the reference voltage wiring.

4. The aforementioned second power supply voltage is a positive voltage, The semiconductor device according to claim 3, wherein the first switch is composed of an N-type native transistor or a depletion-type transistor.

5. The aforementioned second power supply voltage is a negative voltage, The semiconductor device according to claim 3, wherein the first switch is composed of a P-type native transistor or a depletion-type transistor.

6. The aforementioned semiconductor device is The system further includes a second switch connected between the second power supply wiring and the reference voltage wiring, The semiconductor device according to any one of claims 1 to 5, wherein the second switch is turned off when the second block is operating and turned on when the second block is not operating.

7. The semiconductor device is a level shift circuit, The second block is a signal input section that receives an input signal having the amplitude of the second power supply voltage, The first block is a signal output unit that outputs an output signal obtained by converting the input signal so that it has the amplitude of the first power supply voltage. The semiconductor device according to any one of claims 1 to 6, wherein the first switch is located at least between a node that transmits the input signal or an inverted signal of the input signal and the second power supply wiring.

8. The first block is an analog circuit that uses the first power supply voltage as its power source, The semiconductor device according to any one of claims 1 to 6, wherein the second block is a digital circuit powered by the second power supply voltage.

9. The first block is a digital circuit that uses the first power supply voltage as its power source, The semiconductor device according to any one of claims 1 to 6, wherein the second block is an analog circuit that uses the second power supply voltage as a power source.

10. The first power supply wiring is supplied with the first power supply voltage from outside the semiconductor device. The aforementioned semiconductor device is The system further comprises a voltage conversion circuit positioned between the first power supply wiring and the second power supply wiring, The semiconductor device according to any one of claims 1 to 9, wherein the voltage conversion circuit converts the first power supply voltage supplied to the first power supply wiring into the second power supply voltage and outputs the converted second power supply voltage to the second power supply wiring.

11. The semiconductor device according to any one of claims 1 to 9, wherein the second power supply voltage is output to the second power supply wiring from a voltage conversion circuit that converts the first power supply voltage to the second power supply voltage.

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