Power converter

Abstract

This power conversion apparatus comprises: a semiconductor element (1); a voltage detector (13) that detects voltage between two terminals of the semiconductor element (1); a current detector (14) that detects current flowing between the two terminals of the semiconductor element (1); and a control device (200) that, when the values of the current detected by the current detector (14) are substantially equal to each other, determines the deterioration of the power conversion apparatus on the basis of the change amount of the voltage detected by the voltage detector (13) at a plurality of timings. The control device (200) sets a detection frequency of the voltage in a first time period subsequent to when the change amount of the voltage detected by the voltage detector (13) has exceeded a threshold, higher than a detection frequency of the voltage in a time period preceding the first time period.

Description

Technical Field

[0001] The present disclosure relates to a power conversion device.

Background Art

[0002] In a power module that constitutes a power conversion device, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is mounted as a power semiconductor element inside. These power semiconductor elements have metal wires joined to the metal electrodes on their surfaces. Therefore, while the power conversion device is operating, heat generation and cooling are repeated in the power semiconductor elements, so at the joint between the metal electrode and the metal wire, cutting and peeling of the metal wire occur due to the difference in the linear expansion coefficients of the two.

[0003] For example, the power conversion device described in Patent Document 1 obtains the output characteristics of an IGBT generally described in a data sheet by projecting a set of the collector-emitter voltage detection value and the collector current detection value onto the V-I plane and deriving a distribution. This power conversion device estimates the degree of deterioration of the power conversion device by comparing the state based on the distribution with the initial state.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] To detect the collector-emitter voltage and determine the degradation state of a power converter, it is necessary to measure and evaluate the collector-emitter voltage for multiple current values. Measuring and evaluating the collector-emitter voltage at a constant frequency (time interval) is inefficient and results in low evaluation accuracy. A high frequency of measurement and evaluation during periods when degradation is not progressing is wasteful. Conversely, a low frequency of measurement and evaluation during periods of progressing degradation leads to poor accuracy in determining the degradation.

[0006] Therefore, the purpose of this disclosure is to provide a power converter that can efficiently and accurately determine the deterioration of the power converter. [Means for solving the problem]

[0007] The power conversion device of this disclosure comprises a semiconductor element, a voltage detector for detecting the voltage between two terminals of the semiconductor element, a current detector for detecting the current flowing between the two terminals of the semiconductor element, and a control device for determining the degradation of the power conversion device based on the change in voltage detected by the voltage detector at multiple timings when the currents detected by the current detector are substantially the same. The control device sets the voltage detection frequency in a first period after the change in voltage detected by the voltage detector exceeds a threshold to be higher than the voltage detection frequency in the period prior to the first period. [Effects of the Invention]

[0008] According to the power conversion device of this disclosure, the voltage detection frequency in the first period after the amount of change in voltage detected by the voltage detector exceeds a threshold is set higher than the voltage detection frequency in the period prior to the first period, so that the deterioration of the power conversion device can be determined efficiently and with high accuracy. [Brief explanation of the drawing]

[0009] [Figure 1] This diagram shows the configuration of the power semiconductor element 1 inside the power module that constitutes the power conversion device, and the surrounding area of ​​the power semiconductor element 1. [Figure 2] This figure shows the degradation of bonding wires 12 around the power semiconductor element 1 inside the power module that constitutes a power conversion device. [Figure 3] This figure shows an example of the implementation of the voltage detector 13 and the current detector 14 in the power conversion device according to Embodiment 1. [Figure 4] This figure shows the voltage detector 13, current detector 14, control device 200, and storage device 18 included in the power conversion device in Embodiment 1. [Figure 5] This is a diagram showing a typical failure rate curve. [Figure 6] This figure shows the change over time in the cumulative number of detections of the collector-emitter voltage Vce, which is used to estimate the degradation state of the power converter in Embodiment 1. [Figure 7] This figure shows the relationship between the detected voltage and the warning output of the power converter in Embodiment 1. [Figure 8] This figure shows an example of the implementation of the voltage detector 13b and the current detector 14 in the power conversion device according to Embodiment 2. [Figure 9] This figure shows the insertion location of the current detector 14a in the power converter in Embodiment 3. [Figure 10] This figure shows the detection timing in the power converter in Embodiment 3. [Figure 11] This figure shows the insertion location of the current detector 14b in the power converter in Embodiment 4. [Figure 12] This figure shows the detection timing in the power converter in Embodiment 4. [Figure 13] This figure illustrates the correction of the detected voltage in the power converter in Embodiment 5. [Figure 14] This figure illustrates the correction of the detected voltage in the power converter in Embodiment 6. [Figure 15] This figure illustrates the correction of the detected voltage in the power converter in Embodiment 7. [Figure 16]It is a diagram showing the correction of the detected voltage in the power conversion device in the modification of Embodiment 7.

Mode for Carrying Out the Invention

[0010] Embodiment 1. The power conversion device of this embodiment performs power conversion between three-phase alternating current and direct current. The power conversion device has upper and lower arms for three phases and includes an inverter that is PWM-controlled. Each arm has a power semiconductor element 1. The power semiconductor element 1 is, for example, an IGBT or a MOSFET. Hereinafter, the IGBT will be described as an example of the power semiconductor element 1.

[0011] FIG. 1 is a diagram showing the power semiconductor element 1 inside the power module constituting the power conversion device and the configuration of the peripheral portion of the power semiconductor element 1.

[0012] Bonding wires 9, 10, 12a, 12b, 12c are joined to the metal electrode 2 on the surface of the power semiconductor element 1. The bonding wire 9 connects the metal electrode 2 and the gate terminal 3. The bonding wire 10 connects the metal electrode 2 and the reference emitter terminal 4. The bonding wires 12a, 12b, 12c connect the metal electrode 2 and the emitter terminal 5. The bonding wires 12a, 12b, 12c may also be collectively referred to as the bonding wire 12.

[0013] In the power conversion device, since the power semiconductor element 1 repeats the on-state and the off-state, heat generation and cooling are repeated in the power semiconductor element 1.

[0014] When power semiconductor element 1 is ON, current flows from collector terminal 6 → bonding wire 11 → collector substrate 7 → solder joint 8 → metal electrode 2 → bonding wires 12a, 12b, 12c → emitter terminal 5. Therefore, as the switching operation of power semiconductor element 1 is repeated, cracks may form in the bonding wires 12a, 12b, 12c at the junctions between the metal electrode 2 and the bonding wires 12a, 12b, 12c due to the difference in their coefficients of thermal expansion, causing the bonding wires 12a, 12b, 12c to deteriorate. Ultimately, this can lead to the bonding wires 12a, 12b, 12c breaking or delaminating.

[0015] Figure 2 shows the degradation of bonding wires 12 around the power semiconductor element 1 inside the power module that constitutes the power conversion device.

[0016] Bonding wires 12a, 12b, and 12c are connected between the metal electrode 2 and the emitter terminal 5. Assume that one bonding wire 12a has a crack due to deterioration. When a crack occurs in bonding wire 12a, one of the bonding wires 12a, 12b, and 12c connected in parallel, the overall resistance of bonding wires 12a, 12b, and 12c increases. As the crack gradually propagates due to the subsequent switching operation of the power semiconductor element 1, the overall resistance of bonding wires 12a, 12b, and 12c also gradually increases. When the crack gradually propagates and bonding wire 12a delaminates, the overall resistance of bonding wires 12a, 12b, and 12c increases sharply. Therefore, when a predetermined current flows through the power semiconductor element 1, measuring the collector-emitter voltage including the bonding wires 12a, 12b, and 12c will show a larger collector-emitter voltage compared to the initial state, due to the increased overall resistance of the bonding wires 12a, 12b, and 12c. This indicates that the bonding wires 12a, 12b, and 12b as a whole have deteriorated.

[0017] Figure 3 shows an example of the implementation of the voltage detector 13 and current detector 14 in the power converter according to Embodiment 1. Figure 4 shows the voltage detector 13, current detector 14, control device 200, and storage device 18 included in the power converter according to Embodiment 1. The control device 200 may be a processor that executes a program. The storage device 18 may store a program that the processor executes.

[0018] The current detector 14 detects the current I0 flowing through the power semiconductor element 1. For example, the current detector 14 detects the collector current Ic flowing from the collector terminal 6 to the emitter terminal 5 of the power semiconductor element 1 as the current I0 flowing through the power semiconductor element 1. Examples of the current detector 14 include a CT (Current Transducer) or a shunt resistor. The current detector 14 detects the collector current Ic at a constant sampling interval and transmits it to the control device 200.

[0019] The voltage detector 13 detects the voltage between the two main terminals of the power semiconductor element 1. Specifically, the voltage detector 13 detects the collector-emitter voltage Vce of the power semiconductor element 1. The path between the collector terminal 6 and the emitter terminal 5 includes a bonding wire 12. The voltage detector 13 may detect the collector-emitter voltage Vce at the same timing as the current detector 14 and transmit it to the control device 200, which may then store only the necessary values ​​of the received collector-emitter voltage Vce in the storage device 18. Alternatively, the voltage detector 13 may detect the collector-emitter voltage Vce at a timing specified by the control device 200 and transmit it to the control device 200.

[0020] The memory device 18 can store the voltage Vce detected by the voltage detector 13 and the current I0 detected by the current detector 14.

[0021] The control device 200 determines the deterioration of the power converter based on the change in voltage detected by the voltage detector 13 at multiple timings when the current detected by the current detector 14 is approximately the same. Here, "approximately the same" means substantially identical. The range of "approximately the same" is the range in which the accuracy of deterioration determination and period transition determination does not change from when they are identical. The range of "approximately the same" also includes identical values. The reason for using "approximately the same" is that since the current changes continuously, if the voltage is detected after detecting that the current is a predetermined value, a time difference occurs, and the current value at the time of voltage detection may differ from the predetermined value.

[0022] In order to estimate the degradation of the bonding wires 12 of the power semiconductor module over time due to the operation of the power converter, it is necessary to detect and evaluate the current I0 and collector-emitter voltage Vce flowing through the power semiconductor element 1 while the power converter is operating. However, if the current I0 and collector-emitter voltage Vce flowing through the power semiconductor element 1 are detected and evaluated at a constant frequency, it is inefficient and inaccurate.

[0023] Figure 5 shows a typical failure rate curve. The failure rate curve shows how the failure rate of a device changes over time. The timing of failures can be divided into three stages: the initial failure stage, the random failure stage, and the wear-out failure stage. In terms of estimating the remaining lifespan of a power converter, it is sufficient to evaluate the degradation state of the bonding wire 12 during the wear-out failure stage, but it is also necessary to consider initial failures and random failures.

[0024] The control device 200 sets the detection frequency of voltage Vce in the first period (wear-out failure period) after the amount of change in voltage Vce detected by the voltage detector 13 exceeds a threshold to be higher than the detection frequency of voltage Vce in the period prior to the first period. Furthermore, in the period prior to the first period, the control device 200 sets the detection frequency of voltage Vce in the predetermined second period (initial failure period) after the installation of the power converter and the start of operation to be higher than the detection frequency of voltage Vce in the third period (random failure period) after the second period. The detection frequency in the first period > the detection frequency in the second period > the detection frequency in the third period.

[0025] Figure 6 shows the change over time in the cumulative number of detections of the collector-emitter voltage Vce, which is used to estimate the degradation state of the power converter in Embodiment 1.

[0026] During the initial period of operation of the power converter corresponding to the initial failure phase, the voltage detector 13 detects Vce at a high frequency. Subsequently, during the period corresponding to random faults, the voltage detector 13 detects Vce at a low frequency. After that, the voltage value detected by the voltage detector 13 begins to show signs of rising. This indicates that the bonding wire 12 is deteriorating and that the end of its life corresponding to the wear failure phase is approaching. Therefore, the voltage detector 13 detects Vce at the highest frequency. This allows for efficient and highly accurate data acquisition.

[0027] Figure 7 shows the relationship between the detected voltage and the warning output of the power converter in Embodiment 1. After the bonding wire 12 begins to show signs of deterioration, the collector-emitter voltage Vce rises rapidly as the crack in the bonding wire 12 progresses. The control device 200 outputs a warning to the outside when the amount of change in the collector-emitter voltage Vce becomes greater than a threshold during the first period (wear failure period).

[0028] The control device 200 may set a detection frequency of K times per cycle for every L1 cycle of the current (output current) output from the power converter during the first period (wear-out failure period). The control device 200 may set a detection frequency of K times per cycle for every L2 cycle of the current (output current) output from the power converter during the second period (initial failure period). The control device 200 may set a detection frequency of K times per cycle for every L3 cycle of the current (output current) output from the power converter during the third period (random failure period). However, K, L1, L2, and L3 are natural numbers, and L1 > L2 > L3.

[0029] Modification 1 of Embodiment 1. Consider detecting the current I0 and collector-emitter voltage Vce flowing through the power semiconductor element 1 over K and T cycles per cycle of the output current from the power converter. The T cycles are every L1 cycle of the output current in the first period (wear-out failure period), every L2 cycle of the output current in the second period (initial failure period), and every L3 cycle of the output current in the third period (random failure period). If we store the detection data as a data pair (i, v) with i as the current value and v as the voltage value, we will store (T × K) data pairs. Alternatively, we could store the data with r as the value obtained by dividing the voltage value by the current value, but in either case, random storage would result in complicated data. Therefore, the memory device 18 stores the data for the p-th cycle as a K-dimensional vector V(p, K), and all the data as a matrix M(T, K). When the voltage detector 13 measures K times per period of the output current, the output current is a sine wave and, due to its symmetry, it detects the collector-emitter voltage Vce for K1 = (K / 2) current values ​​when K is even, and for K1 = ((K+1) / 2) current values ​​when K is odd. Therefore, the memory device 18 stores the data from the p-th period as a K1-dimensional vector V1(p, K1) and all the data as a matrix M1(T, K1), making it easy to compare detected voltage values ​​at approximately the same current value. For example, if vector V1(p, K1) is a row vector, then matrix M1(T1, K1) is a T1 row, K1 column matrix, so the detected voltage values ​​in each column can be compared. Alternatively, if V1(p, K1) is a column vector, the detected voltage values ​​in each row can be compared.

[0030] Modification 2 of Embodiment 1. When storing pairs of (i, v), the elements of V(p, K), M(T, K), V1(p, K1), and M1(T, K1) are defined as pairs of (i, v), but this is not the only way to do so. Separate vectors and matrices may be provided for i and for v.

[0031] Modification 3 of Embodiment 1. In the third period (random failure period), the value of the current I0 at the j-th timing of the i-th period (i≧1) of each L3 period of the current output from the power converter is a predetermined I3(j) (j=1~K), and the value of the voltage Vce at the j-th timing of the i-th period is V3(i,j) (j=1~K). The value of the current I0 at the j-th timing is the same for all i. These data are obtained, for example, by having the current detector 14 detect the current I0 and the voltage detector 13 detect the voltage Vce at a constant sampling interval, and by the control device 200 setting the detected Vce at the timing when the value of the current I0 becomes I3(j) as V3(i,j). Thus, for each j, the comparison between V3(m,j) and V3(n,j) can be made as a comparison at approximately the same current I0.

[0032] The memory device 18 stores at least V3(i,j). The control device 200 controls the transition from the third period (random failure period) to the first period (wear-out failure period) based on a comparison between V3(p,j) in the p-th period (p≧1) and V3(p+1,j) in the (p+1)-th period during the third period (random failure period). For example, the control device 200 may transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to the detection frequency of the first period if, at least one j, the value obtained by subtracting V3(p,j) from V3(p+1,j) exceeds the threshold THV3(j). Alternatively, the control device 200 may, for all j, transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to that of the first period if the value obtained by subtracting V3(p,j) from V3(p+1,j) exceeds the threshold THV3(j). Alternatively, the control device 200 may, when the average value obtained by subtracting V3(p,j) from V3(p+1,j) exceeds the threshold THV3A, transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to that of the first period.

[0033] Modification 4 of Embodiment 1. In the third period (random failure period), the value of the resistance obtained by dividing the voltage Vce at the j-th timing of the i-th period (i≧1) of the current output from the power converter by the value of the current I0 at the j-th timing of the i-th period is R3(i,j) (j=1~K). In this modified example, unlike Modified Example 3, the value of the current I0 at the j-th timing does not need to be the same for all i.

[0034] The memory device 18 stores at least R3(i,j). The control device 200 controls the transition from the third period (random failure period) to the first period (wear-out failure period) based on a comparison between R3(p,1)~R3(p,K) in the p-th period (p≧1) and R3(p+1,1)~R3(p+1,K) in the (p+1)th period during the third period (random failure period). For example, the control device 200 may transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to the detection frequency of the first period if the value obtained by subtracting the average value of R3(p,1)~R3(p+1,K) from the average value of R3(p+1,1)~R3(p+1,K) exceeds the threshold THR3.

[0035] Modification 5 of Embodiment 1. Considering that measurement errors (variations) always occur in detection data, the variability in the data is corrected by obtaining statistical data such as the mean value μ and standard deviation σ of the detection data by taking measurements at a high frequency during the initial operation of the power converter. This makes it possible to improve the accuracy of detection data when the power converter is not degraded.

[0036] The control device 200 calculates the mean value μ and standard deviation σ for the detected data values, matrix M(T, K), stored in the memory device 18. Regarding the variability and degree of the detected data, approximately 95.5% of the detected data is included within μ±2σ, and approximately 99.7% of the detected data is included within μ±3σ. In other words, if the bonding wire (emitter) 12 has not deteriorated much, almost all of the voltage detected by the voltage detector 13 will fall within the range of μ±3σ. If the bonding wire (emitter) 12 deteriorates and delaminates, the resistance will rise sharply at that time, that is, the detected voltage value will rise sharply, causing it to deviate from the range of μ±3σ.

[0037] If the output current of the power converter is detected K times in one cycle, the data detected up to the pth cycle is stored as a matrix M(p, K).

[0038] The control device 200 calculates the mean value μ and standard deviation σ for each column of matrix M. This allows the matrix M(p, K) to be represented as a K-dimensional vector V1(μ, K) with the mean value μ as an element, and a K-dimensional vector V2(σ, K) with the standard deviation σ as an element. Therefore, after performing statistical processing, only vectors V1(μ, K) and V2(σ, K) may be stored, and the data used for statistical processing may be erased. In this way, the K-dimensional vector V1(μ, K) obtained by statistical processing can be represented as V1(K)_μ, and the K-dimensional vector V2(σ, K) can be represented as V2(K)_σ.

[0039] The control device 200 can determine that the remaining lifespan of the bonding wire 12 is approaching due to deterioration when each element of V(p+1, K) detected in the (p+1)th period is greater than each element of V1(K)_μ + 3 × V2(K)_σ calculated from the values ​​detected up to the pth period.

[0040] Modification 6 of Embodiment 1. During the first period (wear-out failure period), the value of the current output from the power converter at the j-th timing of the i-th period (i≧1) of each L1 period is a predetermined I1(j) (j=1~K), and the value of the voltage at the j-th timing of the i-th period is V1(i,j) (j=1~K). The average value of V1(s,j) (s=1~p) up to the p-th period is μ(j), and the standard deviation is σ(j).

[0041] The memory device 18 stores at least μ(j) and σ(j). The control device 200 determines whether the power converter is degraded during the first period based on a comparison between V1(p+1,j) of the (p+1)th period and μ(j) + 3σ(j). For example, if V1(p+1,j) exceeds {μ(j) + 3σ(j)} at at least one j, the control device 200 may transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to the detection frequency of the first period.

[0042] Alternatively, the control device 200 may, in all j, transition from the third period (random failure period) to the first period (wear-out failure period) and change the detection frequency to the detection frequency of the first period if V1(p+1,j) exceeds {μ(j)+3σ(j)}.

[0043] Modification 7 of Embodiment 1. The power converter in this embodiment operates using PWM. In this power converter, a PWM signal is generally generated using a triangular wave of the order of kHz. Therefore, the control device 200 may set K detection points in one period to any of the timings of the centers of multiple pulses of the PWM signal. The IGBT turns on and collector current flows according to the pulse width of the PWM signal. The timing of the center of the pulse is the timing of the center of the on period. While the collector current may change depending on the timing difference of the detection at the rising or falling edge of the pulse, a stable current can be detected at the timing of the center of the pulse. Because the frequency of the PWM signal is constant, the period from the on state of one pulse to the on state of the next pulse is the same, but the pulse widths are different, so the centers of the pulse widths are not equally spaced. In order to ensure that the detection points are equally spaced and approximately the center of the on-pulse signal of the PWM signal that turns on the IGBT, the control device 200 may set the timings of multiple peaks of a triangular wave called the carrier wave as K detection points in one period.

[0044] The control device 200 may set the K detection points for the upper arm power semiconductor element 1 to one of the timings of a plurality of triangular waves that are the center of the pulses of the PWM signal during the period when the output current (current flowing through the load) is positive. The control device 200 may set the K detection points for the lower arm power semiconductor element 1 to one of the timings of a plurality of triangular waves that are the center of the pulses of the PWM signal during the period when the output current (current flowing through the load) is negative.

[0045] Modification 8 of Embodiment 1. When x (x≧2) bonding wires 12 are connected to a single power semiconductor element 1, the maximum number of times the detected voltage Vce rises sharply due to the delamination of the bonding wires 12 is (x-1). The control device 200 may output a warning when the number of times the change in the detected voltage Vce exceeds the threshold reaches (x-1). Alternatively, the control device 200 may output a warning each time the change in the detected voltage Vce exceeds the threshold. Furthermore, the control device 200 may output different warnings depending on the number of times the detected voltage Vce rises sharply, i.e., the number of times the change in the detected voltage Vce exceeds the threshold (number of warnings).

[0046] Modification 9 of Embodiment 1. The control device 200 may compare the collector-emitter voltage Vce from the time the power converter is installed until it starts operation (initial state) when approximately the same current flows through the power semiconductor element 1 with the collector-emitter voltage Vce at each point in time.

[0047] The control device 200 may compare the resistance obtained by dividing the collector-emitter voltage Vce by the current I0 flowing through the power semiconductor element 1 when approximately the same current flows through the power semiconductor element 1, from the time the power converter is installed until it starts operation (initial state), with the resistance obtained by dividing the collector-emitter voltage Vce by the current I0 flowing through the power semiconductor element 1 at each point in time.

[0048] Modification 10 of Embodiment 1. In this embodiment, the control device 200 sets the detection frequency of voltage Vce during the first period (wear-out failure period) after the change in voltage Vce detected by the voltage detector 13 exceeds a threshold to be higher than the detection frequency of voltage Vce during the period prior to the first period, but it is not limited to this. The control device 200 may also set the detection frequency of voltage Vce during the first period (wear-out failure period) after the value of voltage Vce detected by the voltage detector 13 exceeds a threshold to be higher than the detection frequency of voltage Vce during the period prior to the first period.

[0049] In this embodiment, the control device 200 outputs a warning to the outside when the change in the collector-emitter voltage Vce becomes greater than a threshold during the first period (wear-out failure period), but it is not limited to this. The control device 200 may also output a warning to the outside when the value of the collector-emitter voltage Vce becomes greater than a threshold during the first period (wear-out failure period).

[0050] Embodiment 2. Figure 8 shows an example of the implementation of the voltage detector 13b and the current detector 14 in the power conversion device according to Embodiment 2.

[0051] The voltage detector 13b detects the voltage between the reference terminal and the reference reference terminal of the power semiconductor element 1. Specifically, the voltage detector 13b detects the reference emitter terminal-emitter terminal voltage Vee of the power semiconductor element 1. Even when measuring the voltage between the reference emitter terminal 4 and the emitter terminal 5, the path between the reference emitter terminal 4 and the emitter terminal 5 includes the bonding wire 12. Therefore, degradation of the bonding wire 12 can also be detected by detecting the current I0 flowing through the power semiconductor element 1 and the reference emitter terminal-emitter terminal voltage Vee.

[0052] The current detector 14 is the same as the one described in Embodiment 1. The operation of the control device 200 is the same as the operation described in Embodiment 1 and its modified versions.

[0053] When detecting the collector-emitter voltage Vce, the characteristics of the power semiconductor element 1 are included in the detected value. However, when detecting the reference emitter terminal-emitter terminal voltage Vee, the power semiconductor element 1 is not included in the path between the reference emitter terminal and the emitter terminal. Therefore, it is possible to more directly detect the increase in voltage or resistance due to the deterioration of the bonding wire 12.

[0054] Embodiment 3. Figure 9 shows the insertion location of the current detector 14a in the power converter in Embodiment 3. Figure 9 shows an example where the power semiconductor element 1 to be measured is the upper arm power semiconductor element 1 of the U phase. The current detector 14a for detecting the current I0 flowing through the upper arm power semiconductor element 1 of the U phase is placed on the emitter side of the upper arm power semiconductor element 1 of the U phase. The current detector 14a detects the collector current of the upper arm power semiconductor element 1 of the U phase.

[0055] Figure 10 shows the detection timing in the power converter in Embodiment 3. In the region where the output current of the U-phase is positive, the power semiconductor element on the upper arm of the U-phase and the diode on the lower arm of the U-phase conduct. Therefore, the control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 on the upper arm of the U-phase at the timing indicated by the upward arrow representing the positive region of the output current of the U-phase, and the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the power semiconductor element 1 on the upper arm of the U-phase. This timing can be determined based on a triangular wave as described in Embodiment 1.

[0056] In Figure 9, the current detector 14a is shown to be located at the point where it detects the current flowing through the power semiconductor element 1 on the upper arm of the U-phase. However, it is not limited to the U-phase, nor is it limited to the upper arm. That is, it may be in the V-phase or the W-phase, or it may be mounted on all three phase arms (U, V, and W), both upper and lower.

[0057] The control device 200, at the timing of the negative region of the U-phase output current, causes the current detector 14a to detect the collector current of the power semiconductor element 1 on the lower arm of the U-phase, and causes the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the power semiconductor element 1 on the lower arm of the U-phase.

[0058] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 on the upper arm of the V phase, and the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the power semiconductor element 1 on the upper arm of the V phase, during the timing of the positive region of the output current of the V phase.

[0059] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 on the lower arm of the V phase, and the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the power semiconductor element 1 on the lower arm of the V phase, at the timing of the negative region of the V phase output current.

[0060] The control device 200 causes the current detector 14a to detect the collector current of the power semiconductor element 1 on the upper arm of the W phase, and the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the power semiconductor element 1 on the upper arm of the W phase, during the timing of the positive region of the output current of the W phase.

[0061] The control device 200, at the timing of the negative region of the W-phase output current, causes the current detector 14a to detect the collector current of the W-phase lower arm power semiconductor element 1, and causes the voltage detector 13 to detect the collector-emitter terminal voltage Vce of the W-phase lower arm power semiconductor element 1.

[0062] Embodiment 4. Figure 11 shows the insertion location of the current detector 14b in the power converter in Embodiment 4. Figure 11 shows an example where the power semiconductor element 1 to be measured is the upper arm or lower arm power semiconductor element 1 of the U phase. The current detector 14b for detecting the current I0 flowing through the upper arm or lower arm power semiconductor element 1 of the U phase is installed between the load M and the node NU between the upper arm and lower arm of the U phase. The current detector 14b detects the output current of the U phase.

[0063] If the power semiconductor element 1 to be measured is the upper arm of the U phase, the control device 200 may set the detection timing to the period when the current flowing through the U phase is positive, as in Embodiment 3. If the power semiconductor element 1 to be measured is the lower arm of the U phase, the control device 200 may set the detection timing to the period when the current flowing through the U phase is negative, as in Embodiment 3. Alternatively, the control device 200 may set the detection timing as follows.

[0064] Figure 12 shows the detection timing in the power converter in Embodiment 4. As shown in Figure 12, there is a period in which only the output current of the U phase is positive, and the output currents of the V phase and W phase are both negative (the timing period indicated by the upward arrow). This is because each phase is out of phase by 120°. During this period, the magnitude of the current flowing through the U phase increases, so the current I0 flowing through the power semiconductor element 1 on the upper arm of the U phase can be detected with high accuracy. Therefore, the control device 200 may set the detection timing period for the current detector 14b and the voltage detector 13 to the period in which only the output current of the U phase is positive, and the output currents of the V phase and W phase are both negative. This period can be determined based on the triangular wave generated when PWM control is performed.

[0065] There are times when only the output current of the U phase is negative, while the output currents of the V phase and W phase are positive. The control device 200 may use the period during which only the output current of the U phase is negative, while the output currents of the V phase and W phase are both positive, as the detection timing period for the current detector 14b and the voltage detector 13.

[0066] Similarly, if the power semiconductor element 1 to be measured is a V-phase power semiconductor element 1, a current detector 14b for detecting the current I0 flowing through the power semiconductor element 1 is installed between the load and node NV between the upper arm of the V-phase and the lower arm of the V-phase. The current detector 14b detects the output current of the V-phase. The control device 200 may set the detection timing period for the current detector 14b and the voltage detector 13 to a period during which only the output current of the V-phase is positive and the output currents of the U-phase and W-phase are both negative for the power semiconductor element 1 of the upper arm of the V-phase. The control device 200 may set the detection timing period for the current detector 14b and the voltage detector 13 to a period during which only the output current of the V-phase is negative and the output currents of the U-phase and W-phase are both positive for the power semiconductor element 1 of the lower arm of the V-phase.

[0067] Similarly, if the power semiconductor element 1 to be measured is a W-phase power semiconductor element 1, a current detector 14b for detecting the current I0 flowing through the power semiconductor element 1 is installed between the load and node NW between the upper arm of the W-phase and the lower arm of the W-phase. The control device 200 may set the detection timing period for the current detector 14b and the voltage detector 13 to a period during which only the output current of the W-phase is positive and the output currents of the U-phase and V-phase are both negative for the power semiconductor element 1 of the upper arm of the W-phase. The control device 200 may also set the detection timing period for the current detector 14b and the voltage detector 13 to a period during which only the output current of the W-phase is negative and the output currents of the U-phase and V-phase are both positive for the power semiconductor element 1 of the lower arm of the W-phase.

[0068] Embodiment 5. Figure 13 shows the voltages of each part detected by the voltage detector 13 of the power converter in Embodiment 5. A parasitic inductance Lsc exists between the collector electrode and collector terminal 6 of the power semiconductor element 1, and a parasitic inductance Lse exists between the emitter electrode and emitter terminal 5 of the power semiconductor element 1. Therefore, when the current flowing through the power semiconductor element 1 during the operation of the power converter is I, and its change per unit time is dI / dt, the voltage detected by the voltage detector 13 includes an induced voltage Vs1 = {(Lsc + Lse) × dI / dt}, and the voltage detected by the voltage detector 13b includes an induced voltage Vs2 = (Lse × dI / dt). By subtracting these induced voltages from the detected voltage, a more accurate voltage value can be detected.

[0069] In this embodiment, the control device 200 subtracts the induced voltage Vs1 from the voltage value detected by the voltage detector 13. Alternatively, the control device 200 subtracts the induced voltage Vs2 from the voltage value detected by the voltage detector 13b.

[0070] The control device 200 uses the subtracted voltage instead of the voltage detected by the voltage detector 13 or 13b to perform the calculations and control described in the above embodiment.

[0071] A modified example of Embodiment 5. As described in Modification 10 of Embodiment 1, if the control device 200 sets the detection frequency of voltage Vce in the first period (wear-out failure period) after the voltage Vce value detected by the voltage detector 13 exceeds a threshold value to be higher than the detection frequency of voltage Vce in the period prior to the first period, the control device 200 may increase this threshold value by the induced voltage Vs1 or Vs2.

[0072] As described in Modification 10 of Embodiment 1, if the control device 200 outputs a warning to the outside when the collector-emitter voltage Vce value becomes greater than a threshold value during the first period (wear-out failure period), the control device 200 may increase this threshold value by the induced voltage Vs1 or Vs2.

[0073] Embodiment 6. Figure 14 is a diagram illustrating the correction of the detected voltage in the power converter in Embodiment 6. dI / dt can be determined from the current value between two points detected by the current detector 14 and the detection timing difference. Figure 14 shows an example using two detection points (t1,v2) and (t2,v2) at a certain period of the power converter. Parasitic inductances Lsc and Lse can be calculated in advance by electromagnetic field analysis and stored.

[0074] In this embodiment, the control device 200 calculates dI / dt using two detection points (t1,v2) and (t2,v2) at a certain period of the power converter. The control device 200 can calculate the induced voltage Vs1 using dI / dt and the stored parasitic inductances Lsc and Lse. Alternatively, the control device 200 can calculate the induced voltage Vs2 using dI / dt and the stored parasitic inductance Lse.

[0075] Embodiment 7. Figure 15 is a diagram illustrating the correction of the detection voltage in the power converter in Embodiment 7. The relationship between the collector-emitter voltage Vce and the collector current Ic flowing through the power semiconductor element 1 is nonlinear. The control device 200 uses three or more (Vce, Ic) points to obtain a regression curve that calculates Vce from Ic. The regression curve is a quadratic equation (y=ax 2Functions such as (+bx+c), linear equations (y=ax+b), exponential functions, trigonometric functions, or hyperbolic functions can be used. In the regression curve, the value of the collector-emitter voltage Vce when the collector current Ic is 0 (i.e., the x-intercept of the regression curve from the origin) is the induced voltage Vs1 included in the detection voltage of the voltage detector 13. The control device 200 determines the x-intercept of the regression curve from the origin as the induced voltage Vs1.

[0076] A modified example of Embodiment 7. Figure 16 is a diagram illustrating the correction of the detected voltage in the power converter in a modified example of Embodiment 7. The relationship between the reference emitter terminal-emitter terminal voltage Vee and the current I0 flowing through the power semiconductor element 1 is approximately linear. The control device 200 uses two or more points (Vee, Ic) to find a regression line from Ic to Vee. In the regression line, the reference emitter terminal-emitter terminal voltage Vee when the collector current Ic is 0 (i.e., the deviation x (intercept) from the origin of the regression line) is the induced voltage Vs2 included in the detected voltage of the voltage detector 13b. The control device 200 determines the deviation x from the origin of the regression line as the induced voltage Vs2.

[0077] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of the invention is indicated by the claims rather than the foregoing description, and all modifications within the meaning and scope of equivalents of the claims are intended. [Explanation of Symbols]

[0078] 1 Power semiconductor element, 2 Metal electrode, 3 Gate terminal, 4 Reference emitter terminal, 5 Emitter terminal, 6 Collector terminal, 7 Collector substrate, 8 Solder joint, 9, 10, 11, 12, 12a, 12b, 12c, 12b Bonding wires, 13, 13b Voltage detector, 14, 14a, 14b Current detector, 18 Memory device, 200 Control device, M Load, NU, NV, NW Node.

Claims

1. A power conversion device, Semiconductor elements and A voltage detector for detecting the voltage between two terminals of the semiconductor element, A current detector for detecting the current flowing between the two terminals of the semiconductor element, The power converter is equipped with a control device that determines the deterioration of the power converter based on the amount of change in voltage detected by the voltage detector at multiple timings when the current detected by the current detector is substantially the same. The control device sets the frequency of voltage detection in the first period after the amount of change in voltage detected by the voltage detector exceeds a threshold to be higher than the frequency of voltage detection in the period prior to the first period. In the period prior to the first period, the voltage detection frequency in a predetermined second period after the installation of the power converter and the start of operation is set higher than the voltage detection frequency in a third period after the second period. A power converter in which the detection frequency is set to K times per cycle for every L1 cycle of the current output from the power converter during the first period, K times per cycle for every L2 cycle of the current output from the power converter during the second period, and K times per cycle for every L3 cycle of the current output from the power converter during the third period, wherein K, L1, L2, and L3 are natural numbers and L1 > L2 > L3.

2. In the third period, the value of the current output from the power converter at the j-th timing of the i-th period (i≧1) of each L3 period is a predetermined I3(j) (j=1 to K), and the value of the voltage at the j-th timing of the i-th period is V3(i,j) (j=1 to K), A memory device that stores at least V3(i,j), The power conversion device according to claim 1, wherein the control device controls the transition from the third period to the first period in the third period based on a comparison between V3(p,j) of the p-th period (p≧1) and V3(p+1,j) of the (p+1)-th period.

3. During the third period, the resistance value obtained by dividing the voltage value at the j-th timing of the i-th period (i≧1) of each L3 cycle of the current output from the power converter by the current value at the j-th timing of the i-th period is R3(i,j) (j=1 to K). A memory device that stores at least R3(i,j), The power conversion device according to claim 1, wherein the control device controls the transition from the third period to the first period in the third period based on a comparison between R3(p,1) to R3(p,K) of the p-th period (p≧1) and R3(p+1,1) to R3(p+1,K) of the (p+1)th period.

4. In the first period, the value of the current output from the power converter at the j-th timing of the i-th period (i≧1) of each L1 period is a predetermined I1(j) (j=1 to K), the value of the voltage at the j-th timing of the i-th period is V1(i,j) (j=1 to K), the average value of V1(s,j) (s=1 to p) up to the p-th period (p≧1) is μ(j), and the standard deviation is σ(j). A memory device that stores at least μ(j) and σ(j), The power converter according to claim 1, wherein the control device determines whether the power converter is degraded in the first period based on a comparison between V1(p+1, j) of the (p+1)th period and μ(j) + 3σ(j).

5. The power converter according to claim 4, wherein the control device outputs a warning when it determines that the power converter is degraded.

6. The power converter according to claim 5, wherein the control device outputs different warnings depending on the number of warnings.

7. The power conversion device according to claim 1, wherein the control device causes the voltage detector to detect the voltage for the semiconductor element in the upper arm of each phase during a period when the output current of each phase is positive and the output currents of the other two phases are negative, and causes the voltage detector to detect the voltage for the semiconductor element in the lower arm of each phase during a period when the output current of each phase is negative and the output currents of the other two phases are positive.

8. The power converter according to claim 1, wherein the control device subtracts an induced voltage caused by the parasitic inductance between the two terminals of the semiconductor element from the voltage detected by the voltage detector, and uses the voltage after the subtraction to determine the deterioration of the power converter and set the frequency of voltage detection.

9. The power conversion device according to claim 8, wherein the control device calculates the induced voltage as the product of the parasitic inductance between the two terminals of the semiconductor element and the time derivative of the current detected by the current detector.

10. The power conversion device according to claim 8, wherein the control device uses a plurality of sample data consisting of voltages detected by the voltage detector and currents detected by the current detector, which are detected at substantially the same timing, to calculate a regression line or regression curve for determining the current from the voltage, and calculates the value of the current when the voltage is 0 in the regression line or regression curve as the induced voltage.

11. The power conversion device according to any one of claims 1 to 10, wherein the two terminals of the semiconductor element are the two main terminals of the semiconductor element.

12. The power conversion device according to any one of claims 1 to 10, wherein the two terminals of the semiconductor element are a reference terminal and a reference reference terminal of the semiconductor element.

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