Liquid crystal display device

Abstract

To solve the problem of a display defect or a production decrease that occurs because, in a case where TFTs that control subpixels are formed in matrix at certain intervals in a display part, it is difficult to arrange all the TFTs while avoiding the joint between adjacent SOI layers formed when a large SOI substrate is manufactured.SOLUTION: A plurality of TFTs that control subpixels are arranged collectively so as to surround an intersecting part between scan lines and signal lines. Thus, a gap between regions where the TFTs exist is expanded. Compared to a conventional arrangement in which the TFTs are disposed at certain intervals in a display part, it is possible to avoid the TFTs overlapping with the joint between SOI layers because a gap between the regions where the TFTs exist is expanded.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a display device having a so-called SOI (Silicon on Ins ulator) structure in which a semiconductor layer is provided on an insulating surface.

Background Art

[0002] Instead of a silicon wafer manufactured by slicing a single crystal semiconductor ingot thinly, an integrated circuit using a semiconductor substrate called silicon-on-insulator (hereinafter also referred to as "SOI") in which a thin single crystal semiconductor layer is provided on an insulating surface has been developed. The integrated circuit using an SOI substrate has attracted attention as a means for reducing the parasitic capacitance between the drain of a transistor and the substrate and improving the performance of a semiconductor integrated circuit. There are various manufacturing methods for SOI substrates, and a method called Smart Cut (registered trademark) is known as a method that achieves both the quality of the SOI layer and ease of production (high throughput). In this SOI substrate, hydrogen ions are implanted into a base wafer serving as a base of a silicon layer, and it is bonded to another wafer (bond wafer) at room temperature. Van der Waals force acts on the bonding between the base wafer and the bond wafer, and a strong bond can be formed even at room temperature. The silicon layer bonded to the bond wafer is heat-treated at a temperature of about 500°C, and is peeled off from the base wafer with the layer implanted with hydrogen ions as a boundary. There is known a method by the present applicant as a method of forming a single crystal silicon thin film obtained by using the Smart Cut method on crystallized glass which is high heat-resistant glass (see Patent Document 1).

[0003] <000002l> ​​​​​​​​​​​​​​​​

[0005] Furthermore, thin-film transistors that constitute the driving and control circuits of displays such as liquid crystal and organic EL displays The st is formed by an amorphous silicon film, a polycrystalline silicon film, etc., deposited on a glass substrate. It is formed. In recent years, there has been a growing demand for even higher resolution and faster drive speeds for the aforementioned displays. Therefore, an attempt is being made to form a single-crystal silicon film with higher carrier mobility on a glass substrate. This is being done extensively.

[0006] In recent years, with the increasing screen size and the resulting increase in productivity due to the increased number of components per board, Mother glass is constantly getting larger. For example, it has not yet been put into practical use. However, the largest ones are motherboards with a board size of 2850mm x 3050mm (so-called 10th generation). Glass is known.

[0007] On the other hand, even the largest silicon wafers are only 300 mm in diameter, and on a large glass substrate... To form an SOI layer, it is necessary to bond multiple silicon wafers together. On a large glass substrate, a large S without creating seams (gaps) between adjacent SOI layers Fabricating OI substrates is not easy. [Prior art documents] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 11-163363 [Overview of the project] [Problems that the invention aims to solve]

[0009] Hereafter, in this specification, one of the points that emits light or transmits light is defined as a subpixel, and each other A sub-pixel group composed of a plurality of sub-pixels showing different colors is defined as a pixel. For example, each of R (red), G (green), and B (blue) can be used as a sub-pixel, and these sub-pixel groups can be used as pixels. This is possible.

[0010] As a conventional example, one pixel is composed of three sub-pixels, a (also referred to as the first sub-pixel), b (also referred to as the second sub-pixel ), and c (also referred to as the third sub-pixel), and a thin film transistor (hereinafter referred to as TFT), which is a switching element, is provided for each sub-pixel. An example of the pixel configuration of an active matrix type display device is shown in FIG. 2. As shown in FIG. 2, the pixel arrangement of the simplest display section is a pixel arrangement in which three sub-pixels are arranged in a stripe pattern. The periphery of each sub-pixel is surrounded by wiring composed of a scanning line and a signal line, and the layout of the TFT and the pixel electrode is the same layout for all sub-pixels (the holding capacitance is not shown for the sake of simplicity of the drawing). Thus, the interval between adjacent TFTs is equal to the pitch of the sub-pixels. In many active matrix type display devices, the interval between adjacent TFTs is narrow. Therefore when manufacturing a display device using a large SOI substrate formed by bonding a plurality of single crystal semiconductor substrates to a large glass substrate, it is difficult to arrange all the TFTs in the display section

[0011] while avoiding the joints between adjacent SOI layers. For this reason, in a certain sub-pixel, it may happen that a TFT cannot be formed, or even if it is formed, it may not operate normally, and there is a problem that display defects such as dot defects and line defects are likely to occur. Therefore when manufacturing a display device using a large SOI substrate formed by bonding a plurality of single crystal semiconductor substrates to a large glass substrate, it is difficult to arrange all the TFTs in the display section while avoiding the joints between adjacent SOI layers. For this reason, in a certain sub-pixel, it may happen that a TFT cannot be formed, or even if it is formed, it may not operate normally, and there is a problem that display defects such as dot defects and line defects are likely to occur. Therefore it is less likely to occur, and there is a problem that display defects such as dot defects and line defects are likely to occur. Therefore the margin for alignment during SOI layer formation is small, and high accuracy is required for the alignment of the SOI layer. This is possible.

[0012] In addition, in many liquid crystal display devices, for the purpose of improving contrast and preventing the generation of leakage current due to light irradiation, a substrate provided with TFTs (hereinafter referred to as a TFT substrate) has a substrate facing it (hereinafter referred to as a counter substrate) on which a black matrix (hereinafter referred to as BM) is provided. Normally, the BM is formed wide to provide a margin for misalignment that occurs when the TFT substrate and the counter substrate are bonded together. Therefore, when the misalignment of the BM becomes large, the pixel area shielded by the BM becomes large, and the aperture ratio decreases. (Hereinafter, the aperture ratio refers to the ratio of the pixel area to the entire display area.) The present invention has been made in view of such problems, and proposes a TFT arrangement in which the margin for alignment during SOI layer formation is wide, or the decrease in the aperture ratio during misalignment when the TFT substrate and the counter substrate are bonded together is suppressed. Further, a display device to which the TFT arrangement is applied is provided.

[0013]

Means for Solving the Problems

Means for Solving the Problems

[0014] The present invention relates to a display device, having a display unit including a plurality of pixels arranged in a matrix, the pixels having a plurality of sub-pixels, and a plurality of scanning lines or a plurality of signal lines being installed between adjacent pixels or a plurality of scanning lines and a plurality of signal lines being installed between adjacent pixels, and the TFTs provided for each of the plurality of sub-pixels being arranged in plurality in proximity to the intersection of the scanning line and the signal line. Alternatively, a plurality of scanning lines and a plurality of signal lines are installed between adjacent pixels, and the TFTs provided for each of the plurality of sub-pixels are arranged in plurality in proximity to the intersection of the scanning line and the signal line. The gist is that the TFTs are arranged in plurality in proximity to the intersection of the scanning line and the signal line and are provided for each of the plurality of sub-pixels. That is the gist.

[0015] In addition, as the arrangement of the plurality of TFTs at this time, an arrangement in which adjacent TFTs are arranged facing each other with a scanning line or a signal line interposed therebetween can be applied. That is, an arrangement in which adjacent TFTs are arranged facing each other with a scanning line or a signal line interposed therebetween, etc. can be applied.

[0016] In other words, the present invention provides a TFT that controls subpixels, arranged to surround the intersection of scan lines and signal lines. By arranging several together, the spacing between areas where multiple TFTs are located can be expanded, thus addressing the above issue. This solves the problem. Compared to the case where TFTs are arranged at regular intervals within the display unit, multiple TFTs Because the gap between the regions where the FTs are located is large, the TFTs overlap the seams between the SOI layers. This can be avoided. Also, the margin of the BM that is provided so as to overlap with scan lines and signal lines By reducing the area, the decrease in aperture ratio when the TFT substrate and the opposing substrate are misaligned is suppressed. It is possible to do so. [Effects of the Invention]

[0017] According to the present invention, the alignment margin during SOI layer formation is increased, or T The reduction in aperture ratio due to misalignment during the bonding of the FT substrate and the opposing substrate is suppressed. This will improve productivity and reduce display defects. [Brief explanation of the drawing]

[0018] [Figure 1] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 2] A schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 3] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 4] A schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 5] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 6] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 7] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 8] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 9] A schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 10] A schematic diagram showing an example of the pixel arrangement of a display unit according to the present invention. [Figure 11] A schematic diagram showing an example of a conventional pixel arrangement in a display unit. [Figure 12] A schematic diagram showing an example of the arrangement relationship between conventional pixels and BMs in a display unit. [Figure 13] A schematic diagram showing an example of the arrangement relationship between pixels and BM in the display unit according to the present invention. [Figure 14] A cross-sectional view showing an example of the manufacturing process for a display device according to the present invention. [Figure 15] A diagram showing an example of the cross-sectional structure of a display device according to the present invention. [Figure 16] A diagram showing the configuration of an example of a display device according to the present invention. [Modes for carrying out the invention]

[0019] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention will not be described below. The present invention is not limited to, and its form and details may vary without departing from the spirit and scope of the present invention. Those skilled in the art will readily understand that it can be modified in various ways. Therefore, the present invention is as follows: The present invention is not limited to the descriptions of the embodiments. In this configuration, symbols that refer to the same or corresponding elements are used commonly across different drawings. Let's assume that.

[0020] (Embodiment 1) Figure 1 is a schematic diagram showing an example configuration of an active matrix display device according to one embodiment of the present invention. This is a diagram. In this embodiment, the pixels are a (also called the first sub-pixel) and b (the second sub-pixel). (also called sub-pixels), c (also called the third sub-pixel), three rectangles or sub-pixels of a rectangle-like shape The pixels are arranged in a stripe pattern with their longer sides parallel to the signal lines, and between adjacent pixels It consists of three signal lines joined together.

[0021] Note that the specific configuration of subpixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three subpixels.

[0022] Scan lines G(i), G(i+1) and signal lines S(j+3)~S(j+5), S(j+6)~ A TFT is provided in the first subpixel of the first pixel located in the region enclosed by S(j+8). Let this be Tr1 (also called the first thin-film transistor), and scan lines G(i+1), G(i+2) And in the region enclosed by signal lines S(j+3)~S(j+5) and S(j+6)~S(j+8) The TFT installed in the second sub-pixel of the second pixel is Tr2 (second thin film transient (Also called a st), and scan lines G(i+1), G(i+2) and signal lines S(j)~S(j+ 3) The third sub-image of the third pixel located in the region enclosed by S(j+4) to S(j+5) Let's call the TFT provided on the base Tr3 (also called the third thin-film transistor). Tr1 is running It is connected to scan line G(i+1) and signal line S(j+5), and Tr2 is connected to scan line G(i+1) and It is connected to signal line S(j+4), and Tr3 is connected to scan line G(i+1) and signal line S(j+3). They are connected. The same is true for other pixels, close to the intersection of the scan line and the three signal lines. Arrange a group consisting of three TFTs in this manner.

[0023] The configuration of this embodiment can be described in a different way, as shown below. The pixels shown in the diagram have first to third subpixels arranged parallel to each other, and the third subpixels are arranged parallel to each other. Signal lines 1 to 3 (for example, S(j+1) to S(j+3)) and the first and third parallel lines It has two scan lines (e.g., G(i) and G(i+1)). The second subpixel is the first and third It is provided between the subpixels, and the first to third signal lines are orthogonal to the first and second scan lines. The second signal line is provided between the first and third signal lines, and the first to third sub-pixels are connected to the second signal line. It is located in the area enclosed by the signal line and the third signal line, as well as the first scan line and the second scan line. Each sub-pixel has a TFT, and the TFT of the first sub-pixel has a second scan line and a second signal. Driven by lines, the second sub-pixel TFT is driven by the first scan line and the first signal line. The third sub-pixel TFT is driven by the first scan line and the third signal line. The first sub-pixel TFT is positioned closer to the second signal line than to the third signal line, and the It is positioned closer to the second scan line than to the first scan line. Also, the TFT of the second sub-pixel is It is positioned closer to the second signal line than the third signal line, and closer to the first scan line than the second scan line. It is positioned closer to the line. Also, the TFT of the third sub-pixel is closer to the third signal than the second signal line. It is positioned closer to the line, and closer to the first scan line than to the second scan line. According to this embodiment, unlike the conventional arrangement in which all TFTs are arranged at equal intervals, The three TFTs contained within the pixel are positioned near the intersection of three signal lines and one scan line. A single TFT group is formed. In this TFT group, as shown in Figure 1, each TF By arranging T so that they face each other directly across the scan line or signal line, the conventional configuration shown in Figure 2 is achieved. Compared to the previous TFT arrangement, the spacing between the regions where the TFTs are located can be expanded by approximately double. That is, as shown in Figures 1 and 2, a group of TFTs containing three TFTs located in different pixels. The distance X1 between them is greater than the distance X2 between adjacent TFTs in the conventional TFT arrangement shown in Figure 2. Therefore, the alignment margin during SOI layer formation is increased.

[0024] Next, the arrangement of pixels and BMs will be explained using Figures 12 and 13. Figure 12 is a conventional table. Figure 13 shows the arrangement relationship between the BM and pixels of the display device, and the display device formed using this embodiment. This shows the relationship between the BM and the pixel arrangement. In other words, Figure 12 corresponds to a part of Figure 2. 13 corresponds to a part of Figure 1.

[0025] In Figure 12, since BM10 is provided on each signal line, a large number of relatively narrow BM10 are provided. In contrast to this, in Figure 13, BM11 is provided on the three collected signal lines. A small number of relatively wide BM11s will be provided. The same number of signal lines will be provided on the circuit board. If this is the case, Figure 13 shows that the margin provided for each signal line can be shared, so BM The area formed can be made smaller than that shown in Figure 12.

[0026] In other words, in a pixel where multiple signal lines are gathered as in this embodiment, scan lines and signal lines When forming overlapping BMs, a merge is provided that takes into account the misalignment between the TFT substrate and the opposing substrate. The total area of ​​the elements becomes smaller. Therefore, it is possible to suppress the decrease in the aperture ratio when the element is misaligned. come.

[0027] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0028] (Embodiment 2) Figure 3 is a schematic diagram showing an example configuration of an active matrix display device according to one embodiment of the present invention. This is a diagram. In this embodiment, the pixels are a (also called the first sub-pixel) and b (the second sub-pixel). (also called sub-pixels), c (also called the third sub-pixel), three rectangles or sub-pixels of a rectangle-like shape The pixels are arranged in a stripe pattern such that the longer side is parallel to the scan line, and between adjacent pixels It consists of three scan lines joined together.

[0029] Note that the specific configuration of subpixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three subpixels.

[0030] Scan lines G(i) to G(i+2), G(i+3) to G(i+5) and signal line S(j+1), A TFT is provided in the first subpixel of the first pixel located in the region enclosed by S(j+2). Let this be Tr1 (also called the first thin-film transistor), and scan lines G(i+3) to G(i+5) In the region enclosed by G(i+6) to G(i+8) and signal lines S(j+1) and S(j+2) The TFT installed in the second sub-pixel of the second pixel is Tr2 (second thin film transient (Also called a st), and scan lines G(i+3)~G(i+5), G(i+6)~G(i+8) and the third sub-image of the third pixel located in the region enclosed by signal lines S(j) and S(j+1) Let's call the TFT provided on the base Tr3 (also called the third thin-film transistor). Tr1 is running It is connected to scan line G(i+3) and signal line S(j+1), and Tr2 is connected to scan line G(i+5) and It is connected to signal line S(j+1), and Tr3 is connected to scan line G(i+4) and signal line S(j+1). They are connected. The same is true for other pixels, close to the intersection of the three scan lines and signal lines. Arrange a group consisting of three TFTs in this manner.

[0031] The configuration of this embodiment can be described in a different way, as shown below. The pixels shown in the diagram have first to third subpixels arranged parallel to each other, and the third subpixels are arranged parallel to each other. Signal lines 1 and 2 (for example, S(j) and S(j+1)) and the first to third lines parallel to each other It has a crosshair (for example, from G(i+1) to G(i+3)). The third subpixel is the first and second It is provided between the subpixels, and the first and second signal lines are orthogonal to the first to third scan lines. The second scan line is placed between the first and third scan lines, and the first to third subpixels are connected to the first scan line. It is located in the area enclosed by the signal line and the second signal line, as well as the second scan line and the third scan line. Each sub-pixel has a TFT, and the TFT of the first sub-pixel has a third scan line and a first signal. Driven by lines, the TFT of the second sub-pixel is driven by the second scan line and the first signal line. Furthermore, the TFT of the third sub-pixel is driven by the first scan line and the second signal line. The TFT of the first sub-pixel is positioned closer to the first signal line than the second signal line, and the It is positioned closer to the third scan line than to the second scan line. Also, the TFT of the second sub-pixel is It is positioned closer to the first signal line than the second signal line, and closer to the second scan line than the third scan line. It is positioned closer to the line. Also, the TFT of the third sub-pixel is closer to the second signal than the first signal line. It is positioned closer to the line, and closer to the second scan line than to the third scan line. According to this embodiment, unlike the conventional arrangement in which all TFTs are arranged at equal intervals, The three TFTs contained within the pixel are positioned near the intersection of one signal line and three scan lines. A single TFT group is formed. In this TFT group, as shown in Figure 3, each TF By arranging T so that they face each other directly across the scan line or signal line, the conventional configuration shown in Figure 4 is achieved. Compared to the previous TFT arrangement, the spacing between the regions where the TFTs are located can be expanded by approximately double. That is, as shown in Figures 3 and 4, a group of TFTs containing three TFTs located in different pixels. The distance X1 between them is greater than the distance X2 between TFTs in the conventional TFT arrangement shown in Figure 2. Therefore, the alignment margin during SOI layer formation is increased.

[0032] Furthermore, in a pixel where multiple scan lines are gathered as in the present invention, the scan lines and signal lines overlap When forming a BM, the total margin is set considering the misalignment between the TFT substrate and the opposing substrate. The area can be reduced. Therefore, the decrease in the aperture ratio when there is a misalignment can be suppressed.

[0033] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0034] (Embodiment 3) Figure 5 shows an active matrix display device with 4 around the intersection of scan lines and signal lines. This figure shows an example configuration in which TFTs are arranged. In this embodiment, the pixels are a (first sub (Also called a pixel), b (Also called the second subpixel), c (Also called the third subpixel), three lengths Subpixels with a shape similar to a square or rectangle are arranged in a stripe pattern so that the longer side is parallel to the signal line. The configuration consists of four signal lines arranged in a row.

[0035] Furthermore, the pixels in this embodiment are a (also called the first sub-pixel) and b (also called the second sub-pixel). (also called), c (also called the third subpixel), α (also called the fourth subpixel (α=a, b, c)) ), four rectangular or rectangle-like subpixels are arranged such that their longer sides are parallel to the signal lines. The pixels are arranged in a stripe pattern, and four signal lines are gathered between adjacent pixels. This can be rephrased as, "to do."

[0036] Note that the specific configuration of subpixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three subpixels.

[0037] Four subpixels are arranged inside the grid formed by scan lines and signal lines. Taking any row (row i) as an example, using three grids arranged consecutively in the row direction as a unit, 4 strokes This will result in the placement of 12 subpixels (12 subpixels) corresponding to the prime number of pixels.

[0038] Scan lines G(i), G(i+1) and signal lines S(j)~S(j+3), S(j+4)~S( The TFT provided on the first subpixel of the first pixel located in the region enclosed by j+7) is T Let r1 be the first thin-film transistor, and scan lines G(i+1), G(i+2), and It is installed in the area enclosed by signal lines S(j) to S(j+3) and S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is called Tr2 (also known as the second thin-film transistor). Let (i) be the scan lines G(i), G(i+1) and signal lines S(j+4)~S(j+7), S The third subpixel of the third pixel located in the region enclosed by (j+8)~S(j+11) is set Let the selected TFT be Tr3 (also called the third thin-film transistor), and scan line G(i+1) , G(i+2) and signal lines S(j+4)~S(j+7), S(j+8)~S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel located in the region enclosed by the symbols is Tr4 (the fourth Let 4 be thin-film transistors. Tr1 is the scan line G(i+1) and the signal line S(j Tr2 is connected to scan line G(i+1) and signal line S(j+5), T r3 is connected to scan line G(i+1) and signal line S(j+7), and Tr4 is connected to scan line G(i+ 1) and connected to signal line S(j+6). The same applies to other pixels, and scan lines A group consisting of four TFTs is positioned close to the intersection of the four signal lines. .

[0039] In this embodiment, the sub-pixels are arranged in a stripe pattern such that the longer side of the sub-pixel is parallel to the signal line. Furthermore, a configuration in which four signal lines are gathered is shown, but the longer side of the sub-pixel is made parallel to the scan line. Even in a configuration where the TFTs are arranged in stripes and four scan lines are gathered together, the four TFTs are configured The resulting groups can be placed at the intersections of scan lines and signal lines (not shown).

[0040] The configuration of this embodiment can be described in a different way, as shown below. The pixels shown in the diagram have first to fourth subpixels arranged parallel to each other, and the second to fourth subpixels are also parallel to each other. Signal lines 1 through 4 (for example, S(j+2) through S(j+5)) and the first and second parallel lines It has two scan lines (e.g., G(i) and G(i+1)). The first and third subpixels are second It is located between the fourth subpixel and the third subpixel, and the third subpixel is closer to the second subpixel than the fourth subpixel. The first subpixel is closer to the fourth subpixel than to the second subpixel. The signal lines from the first to the fourth are the first The second scan line is perpendicular to the first and third signal lines, and the second and third signal lines are located between the first and fourth signal lines. Therefore, the second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first signal line. It is closer to the fourth signal line than the main line. The first to fourth subpixels are the second and third signal lines. Furthermore, it is located in the region enclosed by the first scan line and the second scan line. Each subpixel is a TFT The first sub-pixel TFT is driven by a second scan line and a third signal line. The TFT of the second sub-pixel is driven by the second scan line and the second signal line, and the third sub-pixel The TFT is driven by the first scan line and the first signal line, and the TFT of the fourth subpixel is driven by the first It is driven by scan lines and a fourth signal line. Furthermore, the TFT of the first subpixel is driven by the second signal It is positioned closer to the third signal line than the line, and closer to the second scan line than the first scan line. They are positioned close together. Also, the TFT of the second sub-pixel is located closer to the second signal line than to the third signal line. They are positioned close together, and are positioned closer to the second scan line than to the first scan line. Also, the third The sub-pixel TFT is positioned closer to the second signal line than to the third signal line, and the second signal line The fourth sub-pixel TFT is positioned closer to the first scan line than the scan line, and is closer to the second signal line than the second signal line. It is positioned closer to the third signal line, and closer to the first scan line than the second scan line. They are placed. According to this embodiment, the conventional arrangement in which all TFTs are arranged at equal intervals is different from the conventional arrangement in which all TFTs are arranged at equal intervals. Four different TFTs, each containing a different pixel, near the intersection of four signal lines and one scan line. They are installed to form a single TFT group. In this TFT group, as shown in Figure 5, Each TFT is arranged so that it faces the other directly across the scan line or signal line, as shown in the figure. Compared to the conventional TFT arrangement shown in 2, the spacing between the regions where the TFTs are located is expanded by approximately three times. This is possible. That is, as shown in Figure 5, it includes four TFTs contained in different pixels. The distance X1 between TFT groups is larger than the distance between TFTs in a conventional TFT configuration. This increases the alignment margin during SOI layer formation.

[0041] Furthermore, in a pixel where multiple scan lines or signal lines are gathered together as in the present invention, scan lines and signals When forming a BM that overlaps with the line, the mark is provided taking into account the positional misalignment between the TFT substrate and the opposing substrate. This allows for a reduction in the total surface area of ​​the gin. Therefore, it suppresses the decrease in the aperture ratio when there is misalignment. It can be controlled.

[0042] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0043] (Embodiment 4) Figure 6 shows an active matrix display device with 4 around the intersection of scan lines and signal lines. This figure shows an example configuration in which TFTs are arranged. In this embodiment, the pixels are a (first sub (Also called a pixel), b (Also called the second subpixel), c (Also called the third subpixel), d (Fourth subpixel) (Also called subpixels), four rectangular or rectangle-like subpixels, with the longer side being the signal line and The pixels are arranged in parallel stripes, and four signal lines are connected between adjacent pixels. It has that configuration.

[0044] The specific configuration of subpixels a, b, c, and d is not limited. For example, R (red), G (green) ), B (blue), and W (white) can be applied to the four subpixels.

[0045] Scan lines G(i), G(i+1) and signal lines S(j)~S(j+3), S(j+4)~S( The TFT provided on the first subpixel of the first pixel located in the region enclosed by j+7) is T Let r1 be the first thin-film transistor, and scan lines G(i+1), G(i+2), and It is installed in the area enclosed by signal lines S(j) to S(j+3) and S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is called Tr2 (also known as the second thin-film transistor). Let (i) be the scan lines G(i), G(i+1) and signal lines S(j+4)~S(j+7), S The third subpixel of the third pixel located in the region enclosed by (j+8)~S(j+11) is set Let the selected TFT be Tr3 (also called the third thin-film transistor), and scan line G(i+1) , G(i+2) and signal lines S(j+4)~S(j+7), S(j+8)~S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel located in the region enclosed by the symbols is Tr4 (the fourth Let 4 be thin-film transistors. Tr1 is the scan line G(i+1) and the signal line S(j Tr2 is connected to scan line G(i+1) and signal line S(j+5), T r3 is connected to scan line G(i+1) and signal line S(j+7), and Tr4 is connected to scan line G(i+ 1) and connected to signal line S(j+6). The same applies to other pixels, and scan lines A group consisting of four TFTs is positioned close to the intersection of the signal lines.

[0046] In this embodiment, the sub-pixels are arranged in a stripe pattern such that the longer side of the sub-pixel is parallel to the signal line. Furthermore, a configuration in which four signal lines are gathered is shown, but the longer side of the sub-pixel is made parallel to the scan line. Even in a configuration where the TFTs are arranged in stripes and four scan lines are gathered together, the four TFTs are configured The resulting groups can be placed at the intersections of scan lines and signal lines (not shown).

[0047] The configuration of this embodiment can be described in a different way, as shown below. The pixels shown in the diagram have first to fourth subpixels arranged parallel to each other, and the second to fourth subpixels are also parallel to each other. Signal lines 1 through 4 (for example, S(j+2) through S(j+5)) and the first and second parallel lines It has two scan lines (e.g., G(i) and G(i+1)). The first and fourth subpixels are second It is located between the first and third subpixels, and the first subpixel is closer to the second subpixel than the third subpixel. The fourth subpixel is closer to the third subpixel than to the second subpixel. The first to fourth signal lines are the first The second scan line is perpendicular to the first and third signal lines, and the second and third signal lines are located between the first and fourth signal lines. Therefore, the second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first signal line. It is closer to the fourth signal line than the main line. The first to fourth subpixels are the second and third signal lines. Furthermore, it is located in the region enclosed by the first scan line and the second scan line. Each subpixel is a TFT It has the following: The TFT of the first subpixel is driven by the second scan line and the third signal line. The second sub-pixel TFT is driven by the first scan line and the fourth signal line, and the third sub-pixel The TFT is driven by a second scan line and a second signal line, and the TFT of the fourth subpixel is driven by the first It is driven by scan lines and a first signal line. Furthermore, the TFT of the first subpixel is driven by a second signal It is positioned closer to the third signal line than the line, and closer to the second scan line than the first scan line. They are positioned close together. Also, the TFT of the second sub-pixel is closer to the third signal line than to the second signal line. They are positioned close together, and are positioned closer to the first scan line than to the second scan line. Also, the third The sub-pixel TFT is positioned closer to the second signal line than to the third signal line, and the first signal line The fourth sub-pixel TFT is positioned closer to the second scan line than the scan line, and is located closer to the third signal line. It is positioned closer to the second signal line, and closer to the first scan line than the second scan line. They are placed. According to this embodiment, the conventional arrangement in which all TFTs are arranged at equal intervals is different from the conventional arrangement in which all TFTs are arranged at equal intervals. Four different TFTs, each containing a different pixel, near the intersection of four signal lines and one scan line. They are installed to form a single TFT group. In this TFT group, as shown in Figure 6, Each TFT is arranged so that it faces each other directly across the scan line or signal line, Compared to conventional TFT configurations, the spacing between the regions where the TFTs are located can be expanded by approximately three times. That is, as shown in Figure 6, between TFT groups containing four TFTs in different pixels The distance X1 is greater than the distance between TFTs in a conventional TFT configuration. Therefore, SO The alignment margin during the formation of layer I increases.

[0048] Furthermore, as in the present invention, a picture in which a scan line or signal line, or a plurality of scan lines and signal lines are gathered together. In this example, when a BM is formed that overlaps with the scan lines and signal lines, the position of the TFT substrate and the opposing substrate The total area of ​​the margin provided to account for misalignment becomes smaller. Therefore, when misalignment occurs... This can suppress the decrease in the aperture ratio.

[0049] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0050] (Embodiment 5) Figure 7 shows that in an active matrix display device, four lines are located around the intersection of the scan lines and signal lines. This figure shows an example configuration in which TFTs are arranged. In this embodiment, the pixels are a (first sub (Also called a pixel), b (Also called the second subpixel), c (Also called the third subpixel), d (Fourth subpixel) (Also called subpixels), four square or square-shaped subpixels are arranged in a mosaic pattern. Furthermore, it has a configuration in which four signal lines are gathered between adjacent pixels.

[0051] The specific configuration of subpixels a, b, c, and d is not limited. For example, R (red), G (green) ), B (blue), and W (white) can be applied to the four subpixels.

[0052] Scan lines G(i), G(i+1) and signal lines S(j)~S(j+3), S(j+4)~S( The TFT provided on the first subpixel of the first pixel located in the region enclosed by j+7) is T Let r1 be the first thin-film transistor, and scan lines G(i+1), G(i+2), and It is installed in the area enclosed by signal lines S(j) to S(j+3) and S(j+4) to S(j+7). The TFT provided in the second sub-pixel of the second pixel is called Tr2 (also known as the second thin-film transistor). Let (i) be the scan lines G(i), G(i+1) and signal lines S(j+4)~S(j+7), S The third subpixel of the third pixel located in the region enclosed by (j+8)~S(j+11) is set Let the selected TFT be Tr3 (also called the third thin-film transistor), and scan line G(i+1) , G(i+2) and signal lines S(j+4)~S(j+7), S(j+8)~S(j+11) The TFT provided in the fourth sub-pixel of the fourth pixel located in the region enclosed by the symbols is Tr4 (the fourth Let 4 be thin-film transistors. Tr1 is the scan line G(i+1) and the signal line S(j Tr2 is connected to scan line G(i+1) and signal line S(j+5), T r3 is connected to scan line G(i+1) and signal line S(j+7), and Tr4 is connected to scan line G(i+ 1) and connected to signal line S(j+6). The same applies to other pixels, and scan lines A group consisting of four TFTs is positioned close to the intersection of the four signal lines. .

[0053] In this embodiment, a configuration in which four signal lines are combined is shown, but what if four scan lines are combined? Even in the configuration described, the group consisting of four TFTs is crossed by scan lines and signal lines. It can be placed in the section (not shown). Also, as shown in Figure 8, scan lines and signal lines A similar TFT arrangement can also be achieved by gathering two of each of these elements.

[0054] As shown below, the configuration of this embodiment shown in Figure 7 can be described in a different way. The pixels shown in this embodiment of Figure 7 have first to fourth subpixels arranged in a mosaic pattern. , the first to fourth signal lines (for example, S(j+2) to S(j+5) are arranged parallel to each other. ) and have a first and second scan line that is parallel to each other (e.g., G(i) and G(i+1)). The first sub-pixel is closer to the second scan line than to the first scan line, and closer to the third signal line than to the second signal line. It is close to the signal line. The second subpixel is closer to the first scan line than the second scan line, and the second signal line It is closer to the third signal line than the main line. The third sub-pixel is closer to the second scan line than the first scan line. Furthermore, the fourth subpixel is closer to the second signal line than the third signal line. It is close to the scan line and closer to the second signal line than to the third signal line. The first to fourth signal lines are The first and second scan lines are orthogonal, and the second and third signal lines are located between the first and fourth signal lines. Furthermore, the second signal line is closer to the first signal line than the fourth signal line, and the third signal line is closer to the first It is closer to the fourth signal line than the signal line. The first to fourth subpixels are connected to the second signal line and the third signal line. It is located in the region enclosed by the line and the first and second scan lines. Each subpixel is T It has a FT. The TFT of the first subpixel is driven by the second scan line and the third signal line. The second sub-pixel TFT is driven by the first scan line and the fourth signal line, and the third sub-pixel The primary TFT is driven by a second scan line and a second signal line, and the fourth sub-pixel TFT is driven by a second scan line and a second signal line. It is driven by one scan line and one signal line. Furthermore, the TFT of the first subpixel is second It is positioned closer to the third signal line than the signal line, and closer to the second scan line than the first scan line. They are positioned closer together. Also, the TFT of the second sub-pixel is closer to the third signal line than the second signal line. It is positioned closer, and is positioned closer to the first scan line than to the second scan line. Also, The TFT of the third sub-pixel is positioned closer to the second signal line than to the third signal line, and the first The fourth sub-pixel TFT is positioned closer to the second scan line than the first scan line, and the third signal line It is positioned closer to the second signal line than the first scan line, and closer to the first scan line than the second scan line. They are arranged in a similar manner. Similarly, the configuration of this embodiment shown in Figure 8 is shown in another table as follows. It can be described in the present. Each pixel has a mosaic arrangement of first to fourth subpixels. The first and second signal lines (for example, S(j+1) and S(j+2)) are arranged parallel to each other, It has two parallel scan lines, a first and a second (e.g., G(i+1) and G(i+2)). The first subpixel is closer to the first scan line than the second scan line, and also closer to the first signal line than the second signal line. It is close to the signal line. The second subpixel is closer to the first scan line than the second scan line, and the first signal It is closer to the second signal line than the line. The third sub-pixel is closer to the second scan line than the first scan line. Furthermore, it is closer to the first signal line than the second signal line. The fourth sub-pixel is closer to the second scan line than the first scan line. It is close to the scan line and closer to the second signal line than to the first signal line. The first and second signal lines are the first The first to fourth subpixels are orthogonal to the first signal line and the second signal line. Furthermore, it is located in the region enclosed by the first scan line and the second scan line. Each subpixel is TF It has T. The TFT of the first subpixel is driven by the first scan line and the first signal line. The second sub-pixel TFT is driven by the first scan line and the second signal line, and the third sub-pixel The TFT is driven by the second scan line and the first signal line, and the TFT of the fourth subpixel is driven by the second It is driven by the scan line and the second signal line. Furthermore, the TFT of the first subpixel is driven by the second signal It is positioned closer to the first signal line than the line number, and closer to the first scan line than the second scan line. They are positioned closer together. Also, the TFT of the second sub-pixel is closer to the second signal line than to the first signal line. It is positioned closer to the first scan line than to the second scan line. The TFT of the third subpixel is positioned closer to the first signal line than to the second signal line, and the first The fourth sub-pixel TFT is positioned closer to the second scan line than the scan line, and is located closer to the first signal line. It is positioned closer to the second signal line, and closer to the second scan line than the first scan line. Arranged. According to this embodiment, the conventional arrangement in which all TFTs are arranged at equal intervals Unlike the previous example, four TFTs contained within different pixels are located near the intersection of four signal lines and one scan line. They are installed alongside, or near the intersection of two signal lines and two scan lines, forming a single group of TFTs. This is achieved. In this group of TFTs, as shown in Figures 7 and 8, each TFT is a scan line or By arranging them so that they face each other directly with the signal line in between, the conventional TFT arrangement shown in Figure 9 is different from the conventional TFT arrangement shown in Figure 9. In comparison, the spacing between the regions where the TFTs are located can be expanded by approximately double. That is, Figure As shown in 7 and 8, the distance X1 between groups of TFTs, including four TFTs contained in different pixels, is The inter-TFT distance X2 in the TFT arrangement shown in Figure 9 is larger. Therefore, it is an SOI layer type. The alignment margin during development increases. Also, the sub-pixels are as shown in Figures 7 and 8. By using a mosaic arrangement, a secondary effect of improved visibility can also be obtained.

[0055] Furthermore, in Figure 8, the TFT wiring and the scan lines and signal lines do not overlap in the top view. i. In the normal manufacturing process, an insulating layer is formed to avoid connection with scan lines or signal lines. By forming contact holes and a conductive layer, the TFT and the desired scanning To electrically connect a wire or signal line. However, in the configuration shown in Figure 8, The process becomes unnecessary.

[0056] Furthermore, as in the present invention, a picture in which a scan line or signal line, or a plurality of scan lines and signal lines are gathered together. In this example, when a BM is formed that overlaps with the scan lines and signal lines, the position of the TFT substrate and the opposing substrate The total area of ​​the margin provided to account for misalignment becomes smaller. Therefore, when misalignment occurs... This can suppress the decrease in the aperture ratio.

[0057] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0058] (Embodiment 6) Figure 10 shows the area around the intersection of scan lines and signal lines in an active matrix display device. This figure shows an example configuration in which two TFTs are arranged. In this embodiment, the pixels are a (the first b (also called a subpixel), b (also called the second subpixel), c (also called the third subpixel), three Rectangular or rectangular-shaped subpixels are arranged in a delta array, and between adjacent pixels It consists of two scan lines joined together.

[0059] Note that the specific configuration of subpixels a, b, and c is not limited. For example, R (red), G (green), B (blue) can be applied to three subpixels.

[0060] Scan lines G(i) and G(i+1), G(i+2) and G(i+3), and signal line S(j +1), provided in the first subpixel of the first pixel located in the region enclosed by S(j+2). Let the TFT be called Tr1 (also called the first thin-film transistor), and scan lines G(i+2) and G (i+3), G(i+4) and G(i+5), and signal lines S(j) and S(j+1) enclose the area. The TFT provided in the second subpixel of the second pixel located in the specified region is Tr2 (second Let Tr1 be a thin-film transistor (also called a thin-film transistor). Tr1 is the scan line G(i+2) and the signal line S(j+1). ) is connected, and Tr2 is connected to scan line G(i+3) and signal line S(j+1). The same applies to other pixels, with two scan lines and signal lines positioned close to the intersection. Place a group composed of TFTs.

[0061] In this embodiment, a configuration in which two scan lines are combined is shown, but two signal lines are combined Even in the configuration described above, the two TFTs are positioned near the intersection of the scan lines and signal lines. This can be done (not shown in the diagram). Also, by combining two scan lines and two signal lines, Therefore, the configuration involves arranging four TFTs near the intersections of scan lines and signal lines. It is also possible (not shown in the diagram).

[0062] According to this embodiment, the arrangement of the TFTs constituting the subpixels of the display unit is as shown in Figure 10. By doing so, as shown in Figure 11, all TFTs are arranged at regular intervals, unlike conventional TFTs. Compared to a FT (Full-Tone) configuration, the spacing between regions where TFTs are located can be expanded by approximately double. That is, as shown in Figure 10, the distance between groups of TFTs containing two TFTs that are located in different pixels. The distance X1 is greater than the distance X2 between TFTs in the TFT configuration shown in Figure 11. Therefore, This increases the alignment margin during SOI layer formation.

[0063] Furthermore, as in the present invention, a picture in which a scan line or signal line, or a plurality of scan lines and signal lines are gathered together. In this example, when a BM is formed that overlaps with the scan lines and signal lines, the position of the TFT substrate and the opposing substrate The total area of ​​the margin provided to account for misalignment becomes smaller. Therefore, when misalignment occurs... This can suppress the decrease in the aperture ratio.

[0064] Furthermore, in Figure 10, the TFT wiring and the scan lines and signal lines overlap in the top view. No. In the normal manufacturing process, in order to avoid connection with scan lines or signal lines, insulation is used. By forming layers, contact holes, and conductive layers, the TFT and the place To electrically connect the desired scan line or signal line. However, in this embodiment, This eliminates the need for such processes.

[0065] By applying the above-described TFT arrangement, the thin-film transistors provided in each subpixel Each of these can be placed in close proximity to the intersection of the scan line and the signal line. Therefore, SO Increasing the alignment margin during I-layer formation, or bonding the TFT substrate and the opposing substrate This can suppress the decrease in the aperture ratio when there is a misalignment in the position.

[0066] (Embodiment 7) In this embodiment, a transmissive liquid crystal display having a TFT arrangement as shown in Embodiments 1 to 6 is used. The method for manufacturing the device will be explained.

[0067] First, the process of forming a single-crystal semiconductor thin film on a base substrate will be explained using Figure 14. A silicon oxide film or silicon oxide nitride film is formed on a rectangularly shaped single-crystal semiconductor substrate 100. This is done, and a silicon nitride film or silicon oxide nitride film is formed on top of it. Here, silicon oxide nitride film 1 01. A silicon nitride film 102 will be formed sequentially. At that time, the silicon oxide film is a film It is preferable to form the film with a thickness of approximately 10 nm to 150 nm. Furthermore, the silicon nitride film is It is preferable to form the film with a thickness of approximately 10 nm to 200 nm.

[0068] Furthermore, silicon oxide nitride film 101 and silicon oxide nitride film 102 are made from sodium oxide from the base substrate 106. This is provided to prevent impurities such as mu ions from diffusing and contaminating the single-crystal semiconductor layer. In this context, silicon nitride oxide film is a material whose composition contains more nitrogen than oxygen. The concentration range is 15-30 atomic percent for oxygen, 20-35 atomic percent for nitrogen, and 25-3 atomic percent for Si. Each element is divided into 5 atomic percent and hydrogen in the range of 15-25 atomic percent, so that the total is 100 atomic percent. It refers to a substance containing an element at any concentration. Furthermore, a silicon oxide nitride film, in terms of its composition, contains nitrogen at any concentration. It has a higher oxygen content, with a concentration range of 55-65 atomic percent oxygen and nitrogen. Within the range of 1-20 atomic%, Si at 25-35 atomic%, and hydrogen at 0.1-10 atomic%, This refers to a material containing each element at any concentration such that the total percentage is 100 atomic percent. Note that aluminum nitride is an example of this. Aluminum oxide, nitrogen oxide, etc. may also be used. Note that silicon oxide nitride film 101 or nitrogen The silicon oxide film 102 is not necessarily required; it can be ion-injected into the single-crystal semiconductor substrate as described later. A substrate in which only the ion implantation layer has been formed may be used.

[0069] Next, hydrogen ions 103 are implanted into the single-crystal semiconductor substrate 100 to form an ion-implanted layer 104. (Figure 14(A)). Here, hydrogen ions are implanted into a single-crystal semiconductor that is transposed onto a base substrate. This is done considering the thickness of the layer. The thickness of the single-crystal semiconductor layer is preferably 10 nm to 200 nm. The thickness should be between 10 nm and 50 nm. The accelerating voltage when implanting hydrogen ions is this The thickness is set considering such a thickness. This process removes from the surface of the single-crystal semiconductor substrate 100. An ion implantation layer 104 is formed in a region of a certain depth. It is also possible to use noble gases instead of just the element, or to use a mixture of both.

[0070] Next, a mixture of TEOS gas and oxygen gas is used to chemically aerate the silicon nitride film 102. Phase growth method (CVD method: Chemical Vapor Deposition method) or A silicon oxide film 105 was formed by plasma chemical vapor deposition (CVD). (Figure 14(B)). The silicon oxide film 105 is ion-injected onto the single-crystal semiconductor substrate 100. It may be formed before input. Furthermore, a mixed gas of TEOS gas and oxygen gas can be used for CV. When forming a silicon oxide film by the D method or plasma CVD method, the minimum size is 10 nm. It is preferable to form it with a film thickness of 800 nm or less.

[0071] Note that TEOS gas here refers to Tetra Ethyl Ortho Silicat This refers to e gas. In CVD or plasma CVD methods using TEOS gas and oxygen gas. Therefore, the formed silicon oxide film is provided at the bonding interface between the single-crystal semiconductor substrate and the support substrate. This allows for further improvement of the substrate's adhesion.

[0072] If the silicon oxide nitride film 101 or the silicon oxide nitride film 102 is not formed, a single crystal semiconductor is formed. On the surface of the substrate 100, a native oxide film, a chemically formed oxide film, or an oxygen-containing atmosphere is formed. It is preferable to form an ultrathin oxide film by irradiating with UV light. Before forming the silicon oxide nitride film 101 or the silicon oxide nitride film 102 on the single crystal semiconductor substrate... It is preferable to form the above-mentioned ultrathin oxide film on the surface of the single-crystal semiconductor substrate 100. Here, the chemically formed oxide film is bonded to an oxidizing agent such as ozonated water, hydrogen peroxide, or sulfuric acid. It can be formed by treating the surface of a crystalline semiconductor substrate.

[0073] Next, multiple single-crystal semiconductor substrates 100 that have gone through the processes shown in Figure 14(A) and (B) are prepared, and Figure 1 As shown in 4(C), the silicon oxide film 105 formed on the single crystal semiconductor substrate 100 and the base The substrate 106 is joined to it. For the sake of simplifying the drawing, two single-crystal semiconductor substrates 10 are shown here. This diagram shows the process of bonding the 0s together. Note that the surface of the base substrate 106 is A base layer 107 is formed. A mixed gas of TEOS gas and oxygen gas is used as the base layer. Examples include silicon oxide films formed by CVD or plasma CVD, and silicon oxide By bonding the film 105 and the underlayer film 107, the single crystal semiconductor substrate 100 and the base substrate are bonded together. 106 can be bonded together. Note that the undercoat 107, such as a silicon oxide film, is not necessarily required. While not strictly necessary, it is preferable to provide them to improve the adhesion of the substrate.

[0074] Here, the base substrate 106 can be any substrate that is transparent, such as glass or quartz. Insulating substrates such as , can be applied. In this embodiment, a glass substrate is used. Let's assume that.

[0075] In this embodiment, the bonding is between the silicon oxide film 105 on the single crystal semiconductor substrate 100 and the base group It is formed by close contact with the underlayer film 107 on the plate side. The bonding can be performed at room temperature. It is possible. This junction occurs at the atomic level, and van der Waals forces act at room temperature. A strong bond is formed.

[0076] After forming a bond between the single-crystal semiconductor substrate 100 and the base substrate 106, heat treatment is performed, and the single-crystal semiconductor substrate 106 is bonded to the base substrate 106. A portion of the crystalline semiconductor substrate 100 (i.e., the single-crystal semiconductor layer 108) is peeled off (Figure 14(D)). ). Heating causes a volume change in the minute cavities formed in the ion implantation layer 104. A fracture surface is generated along the ion-implanted layer 104, and the single-crystal semiconductor layer 108 is formed along the fracture surface. It can be separated (cut). Then, in order to further strengthen the joint, 400 It is preferable to perform heat treatment at °C to 700. In this way, a thin layer is formed on the base substrate 106. A single-crystal semiconductor layer 109 of the film is formed. Subsequently, to planarize its surface, a chemical process is performed. Chemical Mechanical Polishing (CMP) It is preferable to do so.

[0077] As shown in Figure 14(D), a plurality of single-crystal semiconductor layers 10 are formed on the base substrate 106. In 9, a seam 110 (gap) is formed between adjacent single-crystal semiconductor layers. For example, see Figure 2. When using the conventional TFT arrangement shown in Figures 4, 9, and 11, the spacing between each TFT is narrow. Therefore, it is extremely difficult to form all TFTs while avoiding the seam 110. Furthermore, by using the TFT arrangement shown in Embodiments 1 to 6, the seams 110 can be avoided and efficient It becomes possible to place a TFT there.

[0078] Next, a resist is selectively formed on the single-crystal semiconductor layer 109, and the resist is used as a mask. By etching the crystalline semiconductor layer 109, island-shaped single-crystal semiconductor layers 201 are formed. (Figure 14(E)).

[0079] The following describes the TFT formation and liquid crystal display device manufacturing processes using Figure 15.

[0080] A first insulating layer 202 is formed to cover the island-shaped single-crystal semiconductor layer 201. This involves using plasma CVD or sputtering to create silicon with a thickness of 10-150 nm. It is formed with an insulating film containing silicon nitride, silicon oxide, and silicon oxide nitride. The first insulating layer 202 may be silicon nitride, silicon oxide, or silicon oxide nitride. It can be formed from materials such as silicon oxides or nitrides, represented by silicon nitride or silicon oxide, and laminated However, a single layer is also acceptable. Furthermore, the insulating layer is a three-layer laminate consisting of a silicon nitride film, a silicon oxide film, and another silicon nitride film. A single layer or two layers of silicon oxide nitride film may also be used. Preferably, a nitride having a dense film quality is used. A silicon film is preferable. Furthermore, between the island-shaped single-crystal semiconductor layer 201 and the first insulating layer 202 The film has a thickness of 1 to 100 nm, preferably 1 to 10 nm, and more preferably 2 to 5 nm. A thin silicon oxide film may be formed. A method for forming a thin silicon oxide film is the GRTA method. One example is a method that uses the LRTA method or similar to oxidize the surface of a semiconductor region and form a thermal oxide film. A thin silicon oxide film can be formed. Furthermore, the gate leakage current can be reduced at low deposition temperatures. To form a dense insulating film with few particles, a noble gas element such as argon is included in the reaction gas. It is preferable to mix it into the insulating film that is formed. Here, the first insulating layer 202 is the gate insulating layer It functions in this way.

[0081] Next, a first conductive layer 2, which functions as a gate electrode layer or connecting electrode, is placed on the first insulating layer 202. Form 03. Here, an example is shown in which the first conductive layer 203 is formed as a single layer, The structure may consist of two or more layers of electrically conductive material. 3 selectively etches the conductive layer formed covering the first insulating layer 202. It is formed from.

[0082] The first conductive layer 203 is composed of tantalum (Ta), tungsten (W), titanium (Ti), and molybdenum. Butene (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb) Formed from elements selected from the above, or alloys or compounds mainly composed of these elements. It is possible. Also, semiconductors represented by polycrystalline silicon doped with impurity elements such as phosphorus. It can also be formed from a solid material. For example, when the first conductive layer 203 has a laminated structure. It is preferable to use tantalum nitride as the first layer and tungsten as the second layer for formation. Furthermore, the combination is not limited to this one; the above materials can be freely combined to create the desired configuration. .

[0083] Next, using the first conductive layer 203 as a mask, impurity elements are introduced into the island-shaped single-crystal semiconductor layer 201. By introducing this, impurity regions 201b, 201c and This forms a channel region 201a in which no impurity elements are introduced. After forming the conductive layer 203 across the island-shaped single-crystal semiconductor layer 201, impurity elements are added. To introduce impurities, the impurities are introduced into the region not covered by the first conductive layer 203, and the impurity region Regions 201b and 201c are formed, and impurity elements are present in the region covered by the first conductive layer 203. A channel region 201a that is not introduced is formed.

[0084] Here, the impurity elements are impurity elements that confer n-type or impurity elements that confer p-type. It can be used. Examples of impurity elements that exhibit the n-type include phosphorus (P) and arsenic (As). It can be used. Examples of impurity elements that exhibit p-type include boron (B) and aluminum (A). l) and gallium (Ga), etc., can be used. For example, phosphorus (P) can be used as an impurity element. ) 1 × 10 18 ~1 × 10 21 atoms / cm 3 Island-shaped single condensation so that it is contained at this concentration. It is sufficient to introduce it into the crystalline semiconductor layer 201 to form impurity regions 201b and 201c that exhibit n-type properties. Furthermore, there is a low concentration of impurities between the channel region 201a and the source region or drain region. A low-concentration impurity region (LDD region) may be formed by the addition of [unspecified substance].

[0085] Next, a second insulating layer 204 is formed to cover the first conductive layer 203 and the first insulating layer 202. This is achieved. Here, the second insulating layer 204 is formed by CVD or sputtering, etc. Silicon oxide, silicon oxide nitride (SiOxNy) (x>y>0), silicon nitride oxide (S The formula iNxOy)(x>y>0) can be used. Also, polyimides and polyamides can be used. Organic materials such as polyvinylphenol, benzocyclobutene resins, acrylics, and epoxy. , or a single layer made of siloxane material such as siloxane resin, oxazole resin, etc. It can be provided in a layered structure. Note that siloxane material contains Si-O-Si bonds. It corresponds to a material. Siloxanes have a skeletal structure formed by the bonding of silicon (Si) and oxygen (O). This is achieved. Substituents include organic groups (e.g., alkyl groups, aromatic hydrocarbons) and fluoro groups. It may be used. The organic group may also contain a fluoro group. The oxazole resin is, for example, photosensitive. These include photosensitive polybenzoxazoles. Photosensitive polybenzoxazoles have a low dielectric constant. (Relative permittivity of 2.9 at room temperature and 1MHz), high heat resistance (Differential thermal gravimetric simultaneous measurement (TG / DT)) A:Thermogravimetry-Differential Thermal Analysis) showed that the thermal decomposition temperature was 550°C when the temperature was increased by 5°C / min, and the water absorption rate was low (at room temperature 2 It is a material with a dielectric constant of 0.3% in 4 hours. Oxazole resin is a material with a dielectric constant of (3.2) compared to polyimide, etc. Compared to a relative permittivity of approximately 3.4, the lower dielectric constant (approximately 2.9) suppresses the generation of parasitic capacitance. This allows for high-speed operation. Here, the second insulating layer 204 is made by the CVD method. The formed silicon oxide, silicon oxide nitride (SiOxNy) (x>y>0), or silicon nitride It is formed by forming a single layer or multiple layers of silicon (SiNxOy) (x>y>0). Furthermore, Polyimide, polyamide, polyvinylphenol, benzocyclobutene resin, acrylic , organic materials such as epoxy, siloxane materials such as siloxane resin, or oxazole resin They may be formed by lamination. Next, a resist is selectively formed on the second insulating layer 204. For the resist, select a positive-type photoresist or a negative-type photoresist as appropriate. It can be used.

[0086] Next, using the resist as a mask, the second insulating layer 204 and the first insulating layer 202 are dry-coated. Etching is performed to form contact holes that reach the island-shaped single-crystal semiconductor layer 201. Oh, as an etching gas during dry etching, the semiconductor layer will not be etched. As long as a selectivity ratio can be obtained between the second insulating layer 204 and the first insulating layer 202, there is no particular limitation. Although not specified, for example, fluorine-based gases such as CF4, NF3, SF6, CHF3, and CF4, Alternatively, a mixture of the fluorine-based gas with appropriate additions of O2 gas, H2 gas, He, Ar, and other inert gases. Gases can be used. Preferably, a mixed gas of CHF3 and He, or CF4 and H2 A mixed gas of [substance name], or a mixed gas of CHF3, He, and H2, is recommended.

[0087] Next, conductive material is used to connect the contact holes formed in the second insulating layer 204 and the first insulating layer 202. The surface of the impurity regions 201b and 201c of the island-shaped single-crystal semiconductor layer 201 is filled with a suitable material. A second conductive layer 205 is formed to electrically connect the two layers. The conductive layer, which is formed by selectively etching the insulating layer 204, is formed by covering it. It is possible.

[0088] Next, a third insulating layer 206 is formed to cover the second insulating layer 204 and the second conductive layer 205. The third insulating layer 206 consists of silicon oxide, silicon nitride, silicon oxide nitride, and silicon oxide nitride. Aluminum nitride, aluminum oxide nitride (AlON), nitrogen content is higher than oxygen content Aluminum nitride (AlNO) or aluminum oxide, diamond-like Carbon (DLC), nitrogen-containing carbon film (CN), PSG (phosphorus glass), BPSG (phosphorus glass) Select from materials including boron glass, alumina film, polysilazane, and other inorganic insulating materials. It can be formed from the material that has been exposed. Siloxane resin may also be used. Insulating materials may be used, and as organic materials, either photosensitive or non-photosensitive materials may be used. Imides, acrylics, polyamides, polyimidamides, resists, or benzocyclobutene-based Resin can be used.

[0089] In this embodiment, the method for forming the third insulating layer 206 is a spin coating method or the like. And that is preferable.

[0090] Next, a resist is selectively formed on the third insulating layer 206, and etching is performed using the resist as a mask to form a contact hole reaching the second conductive layer 205. Subsequently, a pixel electrode 207 electrically connected to the second conductive layer 205 is formed on the third insulating layer 206, and an alignment film 208 is further formed on the third insulating layer 206 and the pixel electrode 207.

[0091] Next, a counter substrate 802 is prepared. The counter substrate 802 is composed of a glass substrate 300, a counter electrode 301 formed of a transparent conductive film, and an alignment film 302.

[0092] Next, the TFT substrate 801 and the counter substrate 802 obtained by the above process are bonded via a sealing material. Here, in order to keep the distance between both substrates constant, a spacer may be provided between the alignment film 208 and the alignment film 302. Then, liquid crystal is injected between both substrates and sealed with a sealing material, thereby completing a transmissive liquid crystal display device as shown in FIG. 15.

[0093] By using the present invention, the alignment margin during SOI layer formation is increased, and productivity can be improved and display defects can be reduced. That is, it becomes possible to fabricate a highly reliable display device.

[0094] In the present embodiment, a transmissive liquid crystal display device has been described. However, the display device to which the present invention is applied is not limited thereto. For example, by using an electrode layer having reflectivity as the pixel electrode 207 or providing a reflective film on the upper surface or the lower surface of the pixel electrode 207, it can be applied to a reflective liquid crystal display device. Further, it can also be applied to a display device having an electroluminescence element (EL display device).

[0095] ​​​​​​​​​​​​ (Embodiment 8) FIG. 16 shows an example of the configuration of a mobile phone 1000 to which the present invention is applied. FIG. 16(A) is a front view , FIG. 16(B) is a rear view, and FIG. 16(C) is an exploded view. The mobile phone 1000 has both functions of a phone and a portable information terminal, incorporates a computer, and is a so-called smartphone capable of various data processing in addition to voice calls.

[0096] The mobile phone 1000 is composed of two housings, housings 1001 and 1002. Housing 1 001 includes a display unit 1101, a speaker 1102, a microphone 1103, operation keys 1104, a pointing device 1105, a camera lens 1106, an external connection terminal 1 107, etc. Housing 1002 includes a keyboard 1201, an external memory slot 1202 , a camera lens 1203, a light 1204, an earphone terminal 1108, etc., and an antenna is built inside housing 1001. In addition to the above configuration, a non-contact IC chip, a small recording device, etc. may be incorporated.

[0097] The display unit 1101 can incorporate the display device shown in the above embodiment, and the display direction changes appropriately according to the usage

[0098] form. Since the camera lens 1 106 is provided on the same surface as the display unit 1101, a video phone is possible. Also, the display unit 1101 can be used as a finder to take still images and moving images with the camera lens 1203 and the light 1204 . The speaker 1102 and the microphone 1103 are not limited to voice calls and can be used for video phones, recording sounds, playing back, etc. With the operation keys 1104, incoming and outgoing calls of the phone, simple operations such as e-mails, etc. can be performed. Information input, screen scrolling, cursor movement, etc. are possible. Furthermore, overlapping casings 1 001 and the housing 1002 (Figure 16(A)) slide and unfold as shown in Figure 16(C), and carry It can be used as a mobile information terminal. In this case, keyboard 1201, pointing device Smooth operation is possible using 1105. External connection terminal 1107 is for AC adapter and US It can be connected to various cables such as B cables, and is suitable for charging and connecting to personal computers, etc. Data communication is possible. Furthermore, a recording medium can be inserted into the external memory slot 1202 for larger data transfer. It can handle the storage and transfer of large amounts of data.

[0099] Furthermore, in addition to the above functions, it may also be equipped with infrared communication functions, television reception functions, etc. stomach.

[0100] By using the present invention, a highly reliable display device with reduced display defects can be manufactured. This becomes possible. [Explanation of symbols]

[0101] 10 BM 11 BM 100 Single-crystal semiconductor substrates 101 Silicon oxide nitride film 102 Silicon nitride film 103 Hydrogen ions 104 Ion implantation layer 105 Silicon oxide film 106 Base board 107 Undercoat 108 Single-crystal semiconductor layer 109 Single-crystal semiconductor layer 110 joints 201 Island-shaped single-crystal semiconductor layer 201a Channel region 201b Impurity region 201c Impurity region 202 First insulating layer 203 First conductive layer 204 Second insulating layer 205 Second conductive layer 206 Third insulating layer 207 Pixel electrode 208 Alignment film 300 Glass substrate 301 Counter electrode 302 Alignment film 801 TFT substrate 802 Counter substrate 803 Liquid crystal 1000 Mobile phone 1001 Housing 1002 Housing 1101 Display unit 1102 Speaker<> 1103 Microphone 1104 Operation key 1105 Pointing device 1106 Camera lens 1107 External connection terminal 1108 Earphone terminal 1201 Keyboard External memory slot 1203 Camera lens 1204 Light

Claims

1. The pixel section includes a first scan line, a second scan line, a third scan line, a signal line, a first transistor, a second transistor, a third transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a black matrix. The first transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the first pixel electrode, and the gate electrically connected to the first scan line. The second transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the second pixel electrode, and the gate electrically connected to the second scan line. The third transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the third pixel electrode, and the gate electrically connected to the third scan line. In a plan view of the pixel portion, the first scan line, the second scan line, and the third scan line extend in the first direction. In a plan view of the pixel portion, the second scan line is positioned adjacent to the first scan line, and the second and third pixel electrodes are positioned between it and the third scan line. In a plan view of the pixel portion, the signal line has a region located between the first transistor and the second transistor, and a region located between the second transistor and the third transistor. In a plan view of the pixel portion, the area between the second transistor and the third transistor includes a region where the second pixel electrode is located and a region where the third pixel electrode is located. In a plan view of the pixel portion, the signal line has a first region extending in a second direction intersecting the first direction, and a second region extending in a third direction intersecting both the first and second directions. In a plan view of the pixel portion, the second region is located between the first scan line and the second scan line, and has a region positioned between the first pixel electrode and the second pixel electrode. A liquid crystal display device in which, in a plan view of the pixel portion, the black matrix has a region that overlaps with the first scan line, a region that overlaps with the second scan line, a region that overlaps with the space between the first scan line and the second scan line, and a region that overlaps with the signal line.

2. The pixel section includes a first scan line, a second scan line, a third scan line, a signal line, a first transistor, a second transistor, a third transistor, a first pixel electrode, a second pixel electrode, a third pixel electrode, and a black matrix. The first transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the first pixel electrode, and the gate electrically connected to the first scan line. The second transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the second pixel electrode, and the gate electrically connected to the second scan line. The third transistor has one source and drain electrically connected to the signal line, the other source and drain electrically connected to the third pixel electrode, and the gate electrically connected to the third scan line. In a plan view of the pixel portion, the first scan line, the second scan line, and the third scan line extend in the first direction. In a plan view of the pixel portion, the second scan line is positioned adjacent to the first scan line, and the second and third pixel electrodes are positioned between it and the third scan line. In a plan view of the pixel portion, the signal line has a region located between the first transistor and the second transistor, and a region located between the second transistor and the third transistor. In a plan view of the pixel portion, the area between the second transistor and the third transistor includes a region where the second pixel electrode is located and a region where the third pixel electrode is located. In a plan view of the pixel portion, the second pixel electrode has a region positioned between the first pixel electrode and the third pixel electrode. In a plan view of the pixel portion, the signal line has a first region extending in a second direction intersecting the first direction, and a second region extending in a third direction intersecting both the first and second directions. In a plan view of the pixel portion, the second region is located between the first scan line and the second scan line, and has a region positioned between the first pixel electrode and the second pixel electrode. A liquid crystal display device in which, in a plan view of the pixel portion, the black matrix has a region that overlaps with the first scan line, a region that overlaps with the second scan line, a region that overlaps with the space between the first scan line and the second scan line, and a region that overlaps with the signal line.

Images