Method and apparatus for manufacturing semiconductor devices
By using trained models based on waveform data from multiple semiconductor devices, the method improves judgment accuracy in determining which devices need high-voltage testing, reducing damage and costs in semiconductor manufacturing.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- DENSO CORP
- Filing Date
- 2022-10-10
- Publication Date
- 2026-05-26
AI Technical Summary
Existing semiconductor manufacturing methods face challenges in accurately determining which semiconductor devices require high-voltage testing, leading to potential damage and increased costs due to fixture replacement and foreign matter adhesion, as current methods rely on insufficient data analysis that loses valuable information.
A method involving training data acquisition from multiple semiconductor devices, creating a trained model using machine learning, and determining whether to perform electrical inspections based on input data characteristics, particularly waveform data, to improve judgment accuracy and prevent damage.
Enhances determination accuracy, reducing fixture damage and foreign matter adhesion, thereby lowering chip costs and maintaining throughput by accurately identifying devices that can withstand high-voltage tests.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a method and an apparatus for manufacturing a semiconductor device.
Background Art
[0002] Before shipping a semiconductor device including a MOSFET element or the like, a switching test or a breakdown voltage test in which a high voltage is applied is performed. When the element is short-circuited and damaged in these tests and foreign matter adheres to fixtures such as probes, stages, and collets of a chip tester, if the test is continued as it is, measurement failures and appearance failures frequently occur due to damage to subsequent chips. Therefore, when an element breakdown occurs, the fixture is replaced in order to avoid damage to subsequent chips.
[0003] When the fixture is replaced, the chip cost increases due to a decrease in throughput and the cost of the fixture. Therefore, when an element is short-circuited, an overcurrent is detected and the current is cut off to protect the fixture. For example, when the drain current sharply increases due to the breakdown of a MOSFET element and exceeds a reference value, the current supply to the element is cut off and the drain current is stopped.
[0004] However, in this method, since a large current flows before the current is cut off, it is difficult to reduce the adhesion of foreign matter to the fixture due to element breakdown.
[0005] Regarding the manufacture of semiconductor devices, for example, in Patent Document 1, it is proposed to determine the necessity of a burn-in test for each lot and perform a burn-in test before the final test process for the lot determined to require a burn-in test. Regarding the necessity of a burn-in test, a probe test and a burn-in test are performed in advance for a plurality of chips, and the determination is made based on a criterion set based on this result. Specifically, those having a high correlation with the result of the burn-in test among the test items of the probe test are selected, the inspection results of each chip in this test item are plotted as point data on a two-dimensional graph, and a determination criterion is set based on the distribution of the point data. [Prior art documents] [Patent Documents]
[0006] [Patent Document 1] Patent No. 6310782 [Overview of the Initiative] [Problems that the invention aims to solve]
[0007] For example, by using a burn-in test to remove defective chips before electrical testing, it is possible to suppress component damage during electrical testing and protect the fixture. However, in the method described in Patent Document 1, the test results are converted into one point data for each chip, resulting in significant information loss. Therefore, sufficient judgment accuracy cannot be obtained, and there is a risk of component damage.
[0008] In view of the above points, the present invention aims to provide a method for manufacturing a semiconductor device and a manufacturing apparatus that can suppress the destruction of semiconductor elements. [Means for solving the problem]
[0009] To achieve the above objective, the invention described in claim 1 provides a method for manufacturing a semiconductor device, wherein the semiconductor device to be inspected is a first semiconductor device (S1), and the semiconductor device for acquiring training data is a second semiconductor device (S2), the method involves acquiring training data including a plurality of data relating to the characteristics of the second semiconductor device, creating a trained model using the training data, and determining whether or not to perform an electrical inspection of the first semiconductor device based on the output obtained by inputting the plurality of data relating to the characteristics of the first semiconductor device into the trained model. The multiple data relating to the characteristics of the first semiconductor device include waveform data relating to the electrical characteristics of the first semiconductor device, and the multiple data relating to the characteristics of the second semiconductor device include waveform data relating to the electrical characteristics of the second semiconductor device. .
[0010] According to this method, multiple data points regarding the characteristics of the second semiconductor device are included in the training data, and the determination is made using multiple data points regarding the characteristics of the first semiconductor device. As a result, the determination accuracy is improved, and the destruction of the semiconductor device can be suppressed.
[0011] Furthermore, claims 10 The invention described herein is a semiconductor device manufacturing apparatus comprising a control unit (4) that determines whether or not to perform an electrical inspection of a semiconductor element (S1) based on an output obtained by inputting a plurality of data relating to the characteristics of the semiconductor element (S1) into a trained model, wherein the plurality of data relating to the characteristics of the semiconductor element includes waveform data relating to the electrical characteristics of the semiconductor element.
[0012] According to this method, since the determination is made using multiple data points regarding the characteristics of the first semiconductor device, the determination accuracy is improved and the destruction of the semiconductor device can be suppressed.
[0013] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]
[0014] [Figure 1] This figure shows the configuration of the inspection device in the first embodiment. [Figure 2] This is the circuit diagram of the test circuit. [Figure 3] This is a flowchart of the manufacturing process for semiconductor devices. [Figure 4] This diagram shows the breakdown voltage of a semiconductor device. [Figure 5] This is a diagram showing the threshold voltage of a semiconductor device. [Figure 6] This is a flowchart of the manufacturing process for a semiconductor device in the second embodiment. [Figure 7] This is a flowchart for high-voltage testing. [Figure 8] This is the waveform of the drain current during a high-voltage test. [Figure 9] This is the waveform of the gate-source voltage during a high-voltage test. [Figure 10] This is the waveform of the drain-source voltage during a high-voltage test. [Modes for carrying out the invention]
[0015] Hereinafter, embodiments of the present invention will be described based on the drawings. In the following embodiments, parts that are identical or equivalent to each other will be described with the same reference numerals.
[0016] (First Embodiment) The manufacturing apparatus for a semiconductor device according to the first embodiment includes the inspection apparatus shown in FIG. 1. This inspection apparatus includes a chip tester 1, a stage 2, a digitizer 3, and a control unit 4.
[0017] The chip tester 1 applies a voltage to a semiconductor element S1, which is a semiconductor element to be inspected, and measures voltages, currents, etc. output from the semiconductor element S1. The semiconductor element S1 in this embodiment is a chip-sized MOSFET element and is used in an inverter of a vehicle or the like. The semiconductor element S1 corresponds to the first semiconductor element.
[0018] As shown in FIG. 1, the semiconductor element S1 is placed on the upper surface of the stage 2. The upper surface of the semiconductor element S1 is connected to the chip tester 1 by a plurality of probes 1a provided on the chip tester 1. The chip tester 1 applies a voltage to the semiconductor element S1 via the plurality of probes 1a and measures the output of the semiconductor element S1.
[0019] The voltages and currents measured by the chip tester 1 are input to the digitizer 3. The digitizer 3 converts the input signal into a digital signal and transmits it to the control unit 4.
[0020] The control unit 4 controls the chip tester 1 based on data transmitted from the chip tester 1 via the digitizer 3. The control unit 4 is composed of a microcomputer, etc., which includes a CPU (not shown) and a memory unit composed of non-transitional physical storage media such as ROM, RAM, flash memory, and HDD. CPU stands for Central Processing Unit, ROM stands for Read Only Memory, RAM stands for Random Access Memory, and HDD stands for Hard Disk Drive.
[0021] The control unit 4 stores the trained model created in step S102, which will be described later, and controls the chip tester 1 based on the output obtained by inputting data transmitted from the chip tester 1 into the trained model.
[0022] Multiple circuit elements are arranged inside the chip tester 1. By applying the probe 1a to the semiconductor element S1, the semiconductor element S1 and the circuit elements arranged inside the chip tester 1 form the test circuit shown in Figure 2.
[0023] In the test circuit, MOSFET elements 12 and 13 are connected to power supply 11. Specifically, the drain electrode of MOSFET element 12 is connected to the positive electrode of power supply 11, the source electrode is connected to the drain electrode of MOSFET element 13, and the source electrode of MOSFET element 13 is grounded. MOSFET elements 12 and 13 are switched on and off by the voltage supplied to their gate electrodes from power supplies 14 and 15.
[0024] Furthermore, MOSFET elements 16, 17, 18, and S1 are connected in series between the positive and negative terminals of the power supply 11. Specifically, the drain electrode of MOSFET element 16 is connected to the positive terminal of the power supply 11, and its source electrode is connected to the source electrode of MOSFET element 17. The drain electrode of MOSFET element 17 is connected to the collector electrode of IGBT element 18, and the emitter electrode of IGBT element 18 is connected to the drain electrode of semiconductor element S1. The source electrode of semiconductor element S1 is grounded.
[0025] The MOSFET element 17 and the IGBT element 18 are switched on and off by the voltage supplied to their gate electrodes from power supplies 19 and 20, respectively. The connection points of MOSFET elements 12 and 13 and the connection points of MOSFET elements 17 and 18 are connected via coil 21.
[0026] The semiconductor device S1 has a drain electrode, a gate electrode, a source electrode, and a Kelvin source electrode. The power supply 22 that applies a gate voltage to the semiconductor device S1 is positioned between the gate electrode and the Kelvin source electrode of the semiconductor device S1.
[0027] A gate drive circuit 23 is positioned between the power supply 22 and the gate electrode of the semiconductor element S1. The gate drive circuit 23 consists of a diode 24, a resistor 25, and a diode 26 and a resistor 27 connected in parallel to diode 24 and resistor 25. The anode electrode of diode 24 is connected to the power supply 22, and the cathode electrode of diode 26 is connected to the power supply 22.
[0028] A voltmeter 28 is positioned between the drain electrode and the Kelvin source electrode of the semiconductor element S1. Additionally, a voltmeter 29 is positioned between the gate electrode and the Kelvin source electrode of the semiconductor element S1. Voltmeters 28 and 29 measure the drain-source voltage Vds and gate-source voltage Vgs of the semiconductor element S1.
[0029] An ammeter 30 is placed between the IGBT element 18 and the semiconductor element S1. The ammeter 30 measures the drain current Id of the semiconductor element S1. The measurement results of the drain-source voltage Vds, gate-source voltage Vgs, and drain current Id from the voltmeter 28, voltmeter 29, and ammeter 30 are input to the digitizer 3 and transmitted to the control unit 4.
[0030] Between the gate electrode and source electrode of the MOSFET element 16, a power supply 31 and a gate drive circuit 32 are arranged. The gate drive circuit 32 consists of a diode 33, a resistor 34, and a diode 35 and a resistor 36 connected in parallel to diode 33 and resistor 34. The anode electrode of diode 33 is connected to the power supply 31, and the cathode electrode of diode 35 is connected to the power supply 31.
[0031] Voltmeters 37 and 38 are positioned between the drain electrode and source electrode of the MOSFET element 16, and between the gate electrode and source electrode. Voltmeters 37 and 38 measure the drain-source voltage and gate-source voltage of the MOSFET element 16. An ammeter 39 is positioned between the MOSFET element 16 and the MOSFET element 17. The ammeter 39 measures the drain current of the MOSFET element 16. The measurement results of the drain-source voltage, gate-source voltage, and drain current of the MOSFET element 16, measured by voltmeters 37, 38, and 39, are input to the digitizer 3 and transmitted to the control unit 4.
[0032] When current is supplied to semiconductor element S1 in this test circuit, the output voltages of power supplies 14, 19, 20, and 22 are set to high levels to turn on MOSFET elements 12, 17, 18, and S1. On the other hand, the output voltages of power supplies 15 and 31 are set to low levels to turn off MOSFET elements 13 and 16. As a result, current flows through the path indicated by arrow A1 in Figure 2.
[0033] To interrupt the current flowing through the semiconductor element S1 in this state, the output voltage of the power supply 20 is set to a low level, turning off the IGBT element 18. This interrupts the current flowing through the semiconductor element S1, and the current that was flowing through the coil 21 recirculates through the path indicated by arrow A2.
[0034] A method for manufacturing a semiconductor device will be described. In this embodiment, the semiconductor device is inspected by steps S101 to S109 shown in Figure 3.
[0035] In step S101, a MOSFET element with the same design as semiconductor element S1 is prepared as semiconductor element S2, and training data containing multiple data points regarding the characteristics of semiconductor element S2 is acquired. Semiconductor element S2 is a semiconductor element used to acquire training data and corresponds to a second semiconductor element. Multiple semiconductor elements S2 are prepared, and multiple data points are acquired for each semiconductor element S2.
[0036] In this embodiment, waveform data relating to the electrical characteristics of the semiconductor element S2 is used as multiple data points relating to the characteristics of the semiconductor element S2. Specifically, the same tests as those described in steps S106 and S107 are performed on the semiconductor element S2 using the inspection apparatus shown in Figure 1. That is, DC tests and low-voltage AC tests are performed on multiple semiconductor elements S2 to check for gate leak, drain leak, threshold voltage Vth, on-voltage Von, breakdown voltage, etc. As a result, waveform data such as Id-Vgs characteristics, which are composed of multiple point data points, are obtained for each semiconductor element S2.
[0037] For example, by performing a withstand voltage test on the semiconductor element S2 up to approximately 1200V, waveform data of the Id-Vgs characteristic shown by the solid or dashed line in Figure 4 can be obtained. Furthermore, by varying the gate voltage of the semiconductor element S2 within the range of 0 to 5V, waveform data of the Id-Vgs characteristic shown by the solid or dashed line in Figure 5 can be obtained.
[0038] For semiconductor element S2, after the above inspection, the same inspection as in step S109 described later is performed. That is, a high-voltage AC test is performed on semiconductor element S2, which has a higher probability of destroying the element than the above inspection. The results of this test are also included in the training data. In Figures 4 and 5, the solid lines represent the waveform data of semiconductor element S2 that was not destroyed in the high-voltage test, and the dashed lines represent the waveform data of semiconductor element S2 that was destroyed in the high-voltage test.
[0039] In step S102, a trained model is created using machine learning with the training data obtained in step S101. For example, a trained model can be created using a neural network or deep learning.
[0040] The trained model is created so that when multiple data points relating to the characteristics of the semiconductor element S1 are input, a numerical value regarding the probability of element failure is output. In this embodiment, the multiple data points relating to the characteristics of the semiconductor element S1 are waveform data relating to the electrical characteristics of the semiconductor element S1. For example, when waveform data such as Id-Vgs characteristics obtained in an inspection such as a withstand voltage test, which has a low probability of element failure, is input, the trained model is created so that the probability of the semiconductor element S1 being destroyed in a high-voltage AC test, which has a high probability of element failure, is output. The control unit 4 stores the created trained model.
[0041] In step S103, a defect inspection of the wafer on which the semiconductor element S1 is formed is performed using an inspection device (not shown). For example, light is shone onto the wafer, and surface defects and internal defects are detected based on the intensity of the reflected light, etc.
[0042] In step S104, the above wafer is subjected to a semiconductor process to form multiple MOSFET elements, which are then diced to divide them into chip units. This results in the formation of multiple chip-shaped semiconductor elements S1.
[0043] In step S105, the same defect inspection as in step S103 is performed on multiple semiconductor elements S1. In addition, a visual inspection is performed on multiple semiconductor elements S1 to check for cracks or other defects.
[0044] After step S105, an electrical test of the semiconductor element S1 is performed. The electrical test includes a first electrical test and a second electrical test performed after the first electrical test. The second electrical test is a test that is more likely to cause elemental damage to the semiconductor element S1 than the first electrical test. Specifically, the second electrical test is a test in which a higher voltage is applied to the semiconductor element S1 than in the first electrical test. In this embodiment, steps S106 and S107 correspond to the first electrical test, and step S109 corresponds to the second electrical test.
[0045] In step S106, a DC test is performed on the semiconductor device S1 using the inspection apparatus shown in Figure 1, and waveform data such as gate leak, drain leak, threshold voltage Vth, on-voltage Von, and withstand voltage are acquired and transmitted to the control unit 4.
[0046] In step S107, an AC test is performed on the semiconductor element S1 using the inspection apparatus shown in Figure 1, waveform data relating to the characteristics of the semiconductor element S1 is acquired, and transmitted to the control unit 4. The AC test performed in step S107 is a low-voltage switching test, etc.
[0047] In step S108, the control unit 4 determines whether or not to perform step S109 for the semiconductor element S1 that has undergone steps S106 and S107. Specifically, the control unit 4 inputs multiple data points related to the characteristics of the semiconductor element S1 to be determined into the trained model created in step S102. As mentioned above, in this embodiment, these multiple data points are waveform data related to the electrical characteristics of the semiconductor element S1, and the control unit 4 inputs the waveform data acquired in steps S106 and S107 into the trained model. Then, based on the output obtained therefrom, the control unit 4 determines whether or not to perform step S109 for this semiconductor element S1. For example, if the numerical value indicating the probability of element failure output from the trained model is less than a predetermined value, the control unit 4 determines to perform step S109, and if this value is greater than or equal to the predetermined value, it determines not to perform step S109.
[0048] In step S109, for the semiconductor element S1 that was determined in step S108 to be suitable for step S109, a high-voltage switching test that is likely to cause element failure is performed to investigate the switching withstand capability, avalanche withstand capability, etc.
[0049] Subsequently, the semiconductor element S1 that has been determined to be a good product through inspections including steps S103, S105, S106, S107, and S109 is packaged, etc. In this way, a semiconductor device including the semiconductor element S1 is manufactured.
[0050] The effects of this embodiment will now be explained. When the results of DC tests and the like performed on multiple semiconductor elements S2 are converted into one point data for each semiconductor element S2 to create training data, a lot of information is lost, and sufficient judgment accuracy cannot be obtained in step S108. For example, when acquiring training data, if the data of point P1 or point P2 in Figure 4 is selected, the difference in data values between the semiconductor element S2 that was destroyed and the semiconductor element S2 that was not destroyed becomes small. Therefore, the difference between the two types of data is less likely to be reflected in the trained model, and the judgment accuracy decreases.
[0051] In contrast, in this embodiment, training data is created to include waveform data such as that shown in Figure 4. As a result, in addition to points P1 and P2 in Figure 4, the training data also includes data for points P3, P4, and P5 where differences occur between the two waveforms. Therefore, the differences between the two types of data are more easily reflected in the trained model, improving the accuracy of the judgment.
[0052] As described above, in this embodiment, multiple data points relating to the characteristics of semiconductor element S2 are included in the training data, and multiple data points relating to the characteristics of semiconductor element S1 are used to determine whether or not to perform a high-voltage test. Therefore, the accuracy of the determination is improved, and the destruction of semiconductor element S1 can be suppressed. This suppresses damage to fixtures such as probe 1a and the adhesion of foreign matter due to element destruction, and reduces the increase in chip cost due to decreased throughput and increased fixture costs.
[0053] (Second Embodiment) A second embodiment will now be described. This embodiment is similar to the first embodiment in that the timing of the determination of whether to perform the electrical inspection has been changed, and everything else is the same as the first embodiment. Therefore, only the parts that differ from the first embodiment will be described.
[0054] In this embodiment, the decision to perform the electrical inspection is made during the second electrical inspection. Specifically, as shown in Figure 6, after step S107, step S109 is started without performing step S108. Then, in step S109, as shown in Figure 7, steps S201 to S203 are performed in order.
[0055] In step S101 of this embodiment, a high-voltage test similar to that in step S109 of the first embodiment is performed on multiple semiconductor elements S2 using the inspection apparatus shown in Figure 1. Then, waveform data of drain current Id, gate-source voltage Vgs, and drain-source voltage Vds are acquired as shown in Figures 8 to 10. In addition, data on whether or not the elements were destroyed by the high-voltage test and data on the time until the elements were destroyed are acquired.
[0056] In Figures 8 to 10, the solid lines represent the waveform data of semiconductor element S2 that was not destroyed in the high-voltage test, while the dashed lines represent the waveform data of semiconductor element S2 that was destroyed in the high-voltage test. In Figures 8 to 10, the element is destroyed at time t1 from the start of the test, and the drain current Id increases sharply. Then, at time t2 from the start of the test, the drain current Id exceeds a predetermined value, the IGBT element 18 in Figure 2 is turned off, the current flowing to semiconductor element S2 is interrupted, and the drain current Id decreases.
[0057] As shown in Figures 8 and 9, the waveform data of semiconductor element S2 that was destroyed in the high-voltage test shows smaller values for drain current Id and gate-source voltage Vgs immediately after the start of the test compared to the waveform data of semiconductor element S2 that was not destroyed. This is thought to be because, for example, cracks began to form in the gate oxide film after the start of the test, causing the effective gate voltage to decrease.
[0058] In step S102, a trained model is created using machine learning with training data that includes the data acquired in step S101. The trained model is designed so that when waveform data from a high-voltage test of the semiconductor device S1 is input, it outputs the probability that the semiconductor device S1 will be destroyed if the high-voltage test is continued.
[0059] In step S201, a high-voltage test is performed on the semiconductor element S1. In step S201, the test is completed in a shorter time than in step S109 of the first embodiment. The time t3 until the end of the test is set to be shorter than the time t1 at which the semiconductor element S2 was destroyed in step S101. Also in step S201, waveform data of the drain-source voltage Vds, gate-source voltage Vgs, and drain current Id during the high-voltage test are transmitted to the control unit 4 by the digitizer 4.
[0060] In step S202, the control unit 4 determines whether or not to perform step S203 for the semiconductor element S1 for which step S201 was performed, based on the waveform data transmitted from the digitizer 4. Specifically, the control unit 4 inputs the waveform data acquired in step S201 for the semiconductor element S1 to be judged into the trained model created in step S102. Then, based on the output obtained therefrom, the control unit 4 determines whether or not to perform step S203 for this semiconductor element S1. For example, if the numerical value indicating the probability of element failure output from the trained model is less than a predetermined value, the control unit 4 determines to perform step S203, and if this value is greater than or equal to the predetermined value, it determines not to perform step S203.
[0061] In step S203, the high-voltage test is continued for the semiconductor device S1 that was determined in step S202 to be suitable for step S203.
[0062] This embodiment, with the same configuration and operation as the first embodiment, can obtain the same effects as the first embodiment.
[0063] (Other embodiments) It should be noted that the present invention is not limited to the embodiments described above, and can be modified as appropriate within the scope of the claims. Furthermore, it goes without saying that the elements constituting the embodiments in each of the embodiments are not necessarily essential unless explicitly stated to be particularly essential or unless they are clearly essential in principle. Also, if numerical values such as the number, numerical values, quantities, or ranges of the components of the embodiments are mentioned in each of the embodiments, the invention is not limited to those specific numbers unless explicitly stated to be particularly essential or unless they are clearly limited to a specific number in principle.
[0064] For example, in Wafer Acceptance Test (WAT) and package inspection, the determination of whether to perform electrical testing may be made in the same manner as in the first and second embodiments. This makes it possible to suppress damage to jigs caused by the destruction of wafers or packages.
[0065] Furthermore, in the second embodiment, step S108 may be performed as in the first embodiment. That is, step S108 may be performed after step S107, steps S201 and S202 may be performed for semiconductor elements S1 which are determined to perform step S109, and step S203 may be performed for semiconductor elements S1 which are determined to perform step S203. In this case, in step S101, the same inspection as in steps S106 and S107 is also performed on semiconductor elements S2, and training data including the data obtained therefrom is created. Then, in step S102, a trained model is created that takes the data obtained in steps S106 and S107 for semiconductor elements S1 as input, and a trained model is created that takes the data obtained in step S201 as input, and these are used for determination in steps S108 and S202.
[0066] Furthermore, steps S101 and S102 may be performed at different timings than those in the first and second embodiments. For example, steps S101 and S102 may be performed after steps S103 to S105.
[0067] Furthermore, image data of semiconductor elements S1 and S2 may be used as multiple data points relating to the characteristics of semiconductor elements S1 and S2. For example, a trained model may be created using training data that includes image data obtained from defect inspection of semiconductor element S2, and in step S108, image data obtained from defect inspection of semiconductor element S1 may be input into the trained model to perform the execution decision in step S109. Alternatively, a trained model may be created using training data that includes image data obtained from visual inspection of semiconductor element S2, and in step S108, image data obtained from visual inspection of semiconductor element S1 may be input into the trained model to perform the execution decision in step S109. When using image data, both waveform data relating to the electrical characteristics of semiconductor elements S1 and S2 and image data may be used as multiple data points relating to the characteristics of semiconductor elements S1 and S2, or only image data may be used without waveform data. Furthermore, when using image data, both image data obtained from defect inspection and image data obtained from visual inspection may be used. The multiple data points relating to the characteristics of semiconductor elements S1 and S2 may include data different from the above-mentioned waveform data and image data.
[0068] Furthermore, for semiconductor elements S1 that have been determined in steps S108 and S202 not to require steps S109 and S203, the same tests as in steps S109 and S203 may be performed, and the data obtained may be included in the training data. In other words, it may be possible to investigate whether semiconductor elements S1 that have been determined to have a high probability of failure are actually destroyed in the high-voltage test, and the results may be reflected in the training data. This can further improve the accuracy of the determination in steps S108 and S202.
[0069] The control unit and its method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the control unit and its method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the control unit and its method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.
[0070] (Features of this disclosure) [First point of view] A method for manufacturing a semiconductor device, Let the semiconductor device to be inspected be the first semiconductor device (S1). The semiconductor device used to acquire training data is designated as the second semiconductor device (S2). To acquire the training data which includes multiple data regarding the characteristics of the second semiconductor device, Creating a trained model using the aforementioned training data, A method for manufacturing a semiconductor device, comprising: inputting a plurality of data relating to the characteristics of the first semiconductor device into the trained model and determining whether or not to perform an electrical inspection of the first semiconductor device based on the output obtained; and [Second perspective] The multiple data relating to the characteristics of the first semiconductor device include waveform data relating to the electrical characteristics of the first semiconductor device. A method for manufacturing a semiconductor device according to the first aspect, wherein the plurality of data relating to the characteristics of the second semiconductor device include waveform data relating to the electrical characteristics of the second semiconductor device. [Third perspective] The aforementioned electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection. The training data includes data obtained in the first electrical inspection of the second semiconductor device. A method for manufacturing a semiconductor device according to the first or second aspect, wherein, in determining whether or not to perform the electrical inspection, the method for determining whether or not to perform a second electrical inspection is determined based on the output obtained by inputting the data obtained in the first electrical inspection of the first semiconductor device into the trained model. [Fourth perspective] The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The training data includes data obtained from the second electrical inspection of the second semiconductor device. The decision of whether or not to perform the aforementioned electrical inspection is made during the second electrical inspection. A method for manufacturing a semiconductor device according to the first or second aspect, wherein, in determining whether or not to perform the electrical inspection, the method for determining whether or not to continue performing the second electrical inspection is determined based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the first semiconductor device into the trained model. [Fifth perspective] The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The training data includes data obtained from the first electrical inspection of the second semiconductor device and data obtained from the second electrical inspection. The decision of whether or not to perform the aforementioned electrical inspection is made before the second electrical inspection and during the second electrical inspection. In determining whether or not to perform the electrical inspection, which is performed before the second electrical inspection, the decision to perform the second electrical inspection is made based on the output obtained by inputting the data obtained from the first electrical inspection of the first semiconductor element into the trained model, A method for manufacturing a semiconductor device according to the first or second aspect, wherein, in determining whether or not to perform the electrical inspection performed during the second electrical inspection, the method determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the first semiconductor device into the trained model. [Sixth perspective] Multiple data relating to the characteristics of the first semiconductor device include image data of the first semiconductor device. A method for manufacturing a semiconductor device according to any one of the first to fifth aspects, wherein the multiple data relating to the characteristics of the second semiconductor device include image data of the second semiconductor device. [Seventh perspective] The aforementioned training data includes data obtained from defect inspection of the second semiconductor device. A method for manufacturing a semiconductor device according to any one of the first to sixth aspects, wherein determining whether or not to perform the electrical inspection involves inputting the data obtained from the defect inspection of the first semiconductor device into the trained model. [Perspective 8] The aforementioned training data includes data obtained from the visual inspection of the second semiconductor device. A method for manufacturing a semiconductor device according to any one of the first to seventh aspects, wherein determining whether or not to perform the electrical inspection involves inputting the data obtained from the visual inspection of the first semiconductor device into the trained model. [Perspective 9] A method for manufacturing a semiconductor device according to any one of the first to eighth aspects, wherein the training data includes data obtained by performing an inspection similar to the electrical inspection on the first semiconductor element for which it has been determined that the electrical inspection will not be performed. [Perspective 10] A semiconductor device for manufacturing, A semiconductor device manufacturing apparatus comprising a control unit (4) that determines whether or not to perform an electrical inspection of a semiconductor element (S1) based on the output obtained by inputting multiple data regarding the characteristics of the semiconductor element (S1) into a trained model. [Perspective 11] A semiconductor device manufacturing apparatus according to a tenth aspect, wherein the plurality of data relating to the characteristics of the semiconductor device include waveform data relating to the electrical characteristics of the semiconductor device. [Perspective 12] The aforementioned electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection. The control unit, A semiconductor device manufacturing apparatus according to the tenth or eleventh aspect, which determines whether or not to perform the second electrical inspection based on the output obtained by inputting the data obtained in the first electrical inspection of the semiconductor device into the trained model. [Perspective 13] The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The semiconductor device manufacturing apparatus according to the tenth or eleventh aspect, wherein the control unit determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the semiconductor device into the trained model. [Perspective 14] The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The control unit, Based on the output obtained by inputting the data obtained in the first electrical inspection of the semiconductor device into the trained model, it is determined whether or not to perform the second electrical inspection. A semiconductor device manufacturing apparatus according to the tenth or eleventh aspect, which determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the semiconductor device into the trained model. [Perspective 15] A semiconductor device manufacturing apparatus according to any one of the 10th to 14th views, wherein the plurality of data relating to the characteristics of the semiconductor device include image data of the semiconductor device. [Perspective 16] The semiconductor device manufacturing apparatus according to any one of the 10th to 15th views, wherein the control unit inputs data obtained from defect inspection of the semiconductor element into the trained model. [Perspective 17] The semiconductor device manufacturing apparatus according to any one of the 10th to 16th views, wherein the control unit inputs data obtained from the visual inspection of the semiconductor element into the trained model. [Explanation of Symbols]
[0071] S1 Semiconductor device S2 Semiconductor device
Claims
1. A method for manufacturing a semiconductor device, Let the semiconductor device to be inspected be the first semiconductor device (S1), The semiconductor element used to acquire training data is designated as the second semiconductor element (S2). To acquire the training data which includes multiple data relating to the characteristics of the second semiconductor device, Creating a trained model using the aforementioned training data, Based on the output obtained by inputting multiple data regarding the characteristics of the first semiconductor device into the trained model, a determination is made as to whether or not to perform an electrical inspection of the first semiconductor device. The plurality of data relating to the characteristics of the first semiconductor device include waveform data relating to the electrical characteristics of the first semiconductor device. A method for manufacturing a semiconductor device, comprising a plurality of data relating to the characteristics of the second semiconductor device, including waveform data relating to the electrical characteristics of the second semiconductor device.
2. The aforementioned electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection. The training data includes data obtained in the first electrical inspection of the second semiconductor device, The method for manufacturing a semiconductor device according to claim 1, wherein the determination of whether or not to perform the electrical inspection is made by inputting the data obtained in the first electrical inspection of the first semiconductor element into the trained model and determining whether or not to perform a second electrical inspection based on the output obtained.
3. The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The training data includes data obtained from the second electrical inspection of the second semiconductor element. The decision of whether or not to perform the aforementioned electrical inspection is made during the second electrical inspection. The method for manufacturing a semiconductor device according to claim 1, wherein the determination of whether or not to perform the electrical inspection is made based on the output obtained by inputting the data obtained up to the middle of the second electrical inspection of the first semiconductor device into the trained model, and determining whether or not to continue performing the second electrical inspection.
4. The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The training data includes data obtained from the first electrical inspection of the second semiconductor element and data obtained from the second electrical inspection. The decision of whether or not to perform the aforementioned electrical inspection is made before the second electrical inspection and during the second electrical inspection. In determining whether or not to perform the electrical inspection, which is performed before the second electrical inspection, the decision to perform the second electrical inspection is made based on the output obtained by inputting the data obtained from the first electrical inspection of the first semiconductor element into the trained model, The method for manufacturing a semiconductor device according to claim 1, wherein, in determining whether or not to perform the electrical inspection performed during the second electrical inspection, the method for determining whether or not to continue the second electrical inspection is determined based on the output obtained by inputting the data obtained up to the middle of the second electrical inspection of the first semiconductor device into the trained model.
5. The multiple data relating to the characteristics of the first semiconductor device include image data of the first semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein the plurality of data relating to the characteristics of the second semiconductor device include image data of the second semiconductor device.
6. The aforementioned training data includes data obtained from defect inspection of the second semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein determining whether or not to perform the electrical inspection involves inputting the data obtained from the defect inspection of the first semiconductor element into the trained model.
7. The aforementioned training data includes data obtained from the visual inspection of the second semiconductor device. The method for manufacturing a semiconductor device according to claim 1, wherein determining whether or not to perform the electrical inspection involves inputting the data obtained from the visual inspection of the first semiconductor element into the trained model.
8. The method for manufacturing a semiconductor device according to claim 1, wherein the training data includes data obtained by performing an inspection similar to the electrical inspection on a first semiconductor element that has been determined not to undergo the electrical inspection.
9. A method for manufacturing a semiconductor device, Let the semiconductor device to be inspected be the first semiconductor device (S1), The semiconductor element used to acquire training data is designated as the second semiconductor element (S2). To acquire the training data which includes multiple data relating to the characteristics of the second semiconductor device, Creating a trained model using the aforementioned training data, Based on the output obtained by inputting multiple data regarding the characteristics of the first semiconductor device into the trained model, a determination is made as to whether or not to perform an electrical inspection of the first semiconductor device. The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The training data includes data obtained from the first electrical inspection of the second semiconductor element and data obtained from the second electrical inspection. The decision of whether or not to perform the aforementioned electrical inspection is made before the second electrical inspection and during the second electrical inspection. In determining whether or not to perform the electrical inspection, which is performed before the second electrical inspection, the decision to perform the second electrical inspection is made based on the output obtained by inputting the data obtained from the first electrical inspection of the first semiconductor element into the trained model, A method for manufacturing a semiconductor device, wherein, in determining whether or not to continue the second electrical inspection performed during the second electrical inspection, the method determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the first semiconductor element into the trained model.
10. A semiconductor device for manufacturing, The system includes a control unit (4) that determines whether or not to perform an electrical inspection of a semiconductor element (S1) based on the output obtained by inputting multiple data regarding the characteristics of the semiconductor element (S1) into a trained model, A semiconductor device manufacturing apparatus, comprising a plurality of data relating to the characteristics of the semiconductor element, including waveform data relating to the electrical characteristics of the semiconductor element.
11. The aforementioned electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection. The control unit, A semiconductor device manufacturing apparatus according to claim 10, which determines whether or not to perform a second electrical inspection based on the output obtained by inputting the data obtained in the first electrical inspection of the semiconductor device into the trained model.
12. The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The semiconductor device manufacturing apparatus according to claim 10, wherein the control unit determines whether or not to continue the second electrical inspection based on the output obtained by inputting the data obtained up to the middle of the second electrical inspection of the semiconductor element into the trained model.
13. The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The control unit, Based on the output obtained by inputting the data obtained from the first electrical inspection of the semiconductor element into the trained model, it is determined whether or not to perform the second electrical inspection. A semiconductor device manufacturing apparatus according to claim 10, which determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the semiconductor device into the trained model.
14. The semiconductor device manufacturing apparatus according to claim 10, wherein the plurality of data relating to the characteristics of the semiconductor device include image data of the semiconductor device.
15. The semiconductor device manufacturing apparatus according to claim 10, wherein the control unit inputs data obtained from defect inspection of the semiconductor element to the trained model.
16. The semiconductor device manufacturing apparatus according to claim 10, wherein the control unit inputs data obtained from the visual inspection of the semiconductor element into the trained model.
17. A semiconductor device for manufacturing, The system includes a control unit (4) that determines whether or not to perform an electrical inspection of a semiconductor element (S1) based on the output obtained by inputting multiple data regarding the characteristics of the semiconductor element (S1) into a trained model, The electrical inspection includes a first electrical inspection and a second electrical inspection performed after the first electrical inspection, to which a higher voltage than that applied in the first electrical inspection is applied. The control unit, Based on the output obtained by inputting the data obtained from the first electrical inspection of the semiconductor element into the trained model, it is determined whether or not to perform the second electrical inspection. A semiconductor device manufacturing apparatus that determines whether or not to continue the second electrical inspection based on the output obtained by inputting data obtained up to the middle of the second electrical inspection of the semiconductor device into the trained model.