Silicon carbide semiconductor device and method for manufacturing the same

Abstract

To suppress an increase in size while suppressing an increase in manufacturing processes.SOLUTION: A first impurity region 14 is an ion implantation layer. A second impurity region 15 is a recoil layer as an ion implantation layer containing impurities of a first conductivity type, the impurity concentration of a second conductivity type being made higher than the impurity concentration of the first conductivity type to make the second impurity region the second conductivity type. In the depth direction of a semiconductor substrate 10 from a reference surface which is along the interface between the first impurity region 14 and an electrode 20, a second peak position at which the impurity concentration of the second conductivity type in the second impurity region 15 is highest is set to a position deeper than a first peak position at which the impurity concentration of the first conductivity type in the first impurity region 14 is highest. The electrode 20 is configured to include a metal silicide layer 21 that is a compound with SiC and is in contact with the semiconductor substrate 10.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to a SiC semiconductor device composed of silicon carbide (hereinafter also simply referred to as SiC) and having a first impurity region and a second impurity region, and a method for manufacturing the same. [Background technology]

[0002] Conventionally, SiC semiconductor devices composed of SiC and having a first impurity region and a second impurity region have been proposed. For example, Patent Document 1 proposes a SiC semiconductor device in which a MOSFET is formed on a semiconductor substrate composed of SiC. Specifically, this SiC semiconductor device has a configuration having an n-type source region as the first impurity region, a p-type contact region as the second impurity region, and electrodes connected to the source region and the contact region. MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor.

[0003] In such a SiC semiconductor device, the source region and contact region are formed as follows: The source region is formed by ion implanting n-type impurities into the semiconductor substrate using a mask in which the area to be formed as the source region is opened. The contact region is formed by ion implanting p-type impurities into the semiconductor substrate using a mask in which the area to be formed as the contact region is opened. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 5408248 [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] However, when forming the source region and contact region as described above, separate masks must be prepared for the source region and the contact region, which tends to increase the manufacturing process. Furthermore, when forming the source region and contact region as described above, since separate masks are prepared for the source region and the contact region, it is necessary to consider the misalignment of each mask, which tends to increase the size of the SiC semiconductor device.

[0006] Therefore, the inventors are considering manufacturing a SiC semiconductor device as follows: First, an n-type source region is formed on a semiconductor substrate without forming a mask. Then, a mask is placed that exposes a portion of the source region, and p-type impurities are ion-implanted to implant a portion of the source region back into a p-type contact region, thereby manufacturing a SiC semiconductor device. According to this method, only a mask for forming the contact region needs to be prepared, eliminating the need to prepare separate masks for forming the source region and the contact region.

[0007] However, when manufacturing SiC semiconductor devices in this way, if the location where the impurity concentration is highest in the source region and the peak location where the impurity concentration is highest in the contact region are the same, damage may be significant. Specifically, if the peak locations in each region are the same, a large amount of p-type impurities need to be ion-implanted when implanting a portion of the source region back into the contact region, which can lead to significant damage due to ion implantation. In this case, this damage may cause variations in the characteristics of the SiC semiconductor device.

[0008] The purpose of this disclosure is to provide a SiC semiconductor device and a method for manufacturing the same that can suppress an increase in manufacturing steps, suppress an increase in size, and further suppress the occurrence of characteristic fluctuations. [Means for solving the problem]

[0009] According to one aspect of this disclosure, a SiC semiconductor device comprises a semiconductor substrate (10) made of SiC and having one side (10a) and another side (10b) opposite to the first side; a first impurity region (14) of a first conductivity type formed on one side of the semiconductor substrate; a second impurity region (15) of a second conductivity type formed on one side of the semiconductor substrate and having a portion in contact with the first impurity region; and an electrode (20) electrically connected to the first impurity region and the second impurity region, wherein the first impurity region is an ion implantation layer and the second impurity region is an ion implantation layer containing an impurity of the first conductivity type. This is a counter-punching layer, and the second conductivity type is defined by making the impurity concentration of the second conductivity type higher than the impurity concentration of the first conductivity type. The plane along the interface between the first impurity region and the electrode is used as a reference plane, and in the depth direction of the semiconductor substrate from the reference plane, the second peak position (P2) where the impurity concentration of the second conductivity type is highest in the second impurity region is deeper than the first peak position (P1) where the impurity concentration of the first conductivity type is highest in the first impurity region. The electrode is composed of a metal silicide layer (21) which is a compound with SiC and is in contact with the semiconductor substrate. Furthermore, the first and second peak positions are located at the interface with the metal silicide layer. .

[0010] According to this, the second impurity region is a counter-layer containing impurities of the first conductivity type. Therefore, a mask is not required when forming the first impurity region, which helps to suppress an increase in the manufacturing process. Furthermore, since a mask is not required when forming the first impurity region, only the misalignment of one mask needs to be considered, which helps to suppress an increase in the size of the SiC semiconductor device.

[0011] Furthermore, in this SiC semiconductor device, the second peak position is deeper than the first peak position. Therefore, compared to the case where the second peak position is at the same depth as the first peak position, the amount of second conductivity type impurity required to counteract the first impurity region and form the second impurity region can be reduced, thereby reducing the damage that may occur to the semiconductor substrate. Consequently, the occurrence of characteristic variations is suppressed.

[0012] Furthermore, in this SiC semiconductor device, the electrodes are composed of a metal silicide layer. The metal silicide layer is composed of SiC, which constitutes the semiconductor substrate. In other words, the metal silicide layer is formed by reacting the areas where damage occurs due to ion implantation. As a result, this SiC semiconductor device has less residual damage caused by ion implantation, and the occurrence of characteristic fluctuations is suppressed.

[0013] Furthermore, according to another aspect of this disclosure, the above-described method for manufacturing a SiC semiconductor device involves: preparing a semiconductor substrate; ion implanting a first impurity of a first conductivity type from one side of the semiconductor substrate to form a first conductivity type region (30); placing a mask (40) on one side of the semiconductor substrate with an opening in the area where a second impurity region is to be formed; ion implanting a second impurity of a second conductivity type from one side of the semiconductor substrate to form a second impurity region by impregnating a part of the first conductivity type region, and designating the region of the first conductivity type region that is different from the second impurity region as the first impurity region; and, after ion implanting the second impurity, placing a metal layer on one side of the semiconductor substrate and reacting the metal layer with the semiconductor substrate to form a metal silicide layer that constitutes an electrode; and in ion implanting the second impurity, the second impurity is ion implanted such that the second peak position is located deeper than the first peak position. Furthermore, by forming a metal silicide layer, the thickness of the metal silicide layer is adjusted so that the first and second peak positions are located at the interface between the metal silicide layer and the semiconductor substrate. .

[0014] According to this method, the first impurity region is reversed to form the second impurity region. Therefore, a mask is not required when forming the first impurity region, which helps to suppress an increase in the manufacturing process. Furthermore, since a mask is not required when forming the first impurity region, only the misalignment of one mask needs to be considered, which helps to suppress an increase in the size of the SiC semiconductor device.

[0015] Also, in this method for manufacturing a SiC semiconductor device, the second peak position is made deeper than the first peak position. For this reason, compared with the case where the second peak position is set to the same depth as the first peak position, the amount of impurities of the second conductivity type required to turn back the first impurity region and form the second impurity region can be reduced, and the damage that can occur to the semiconductor substrate can be reduced. Therefore, a SiC semiconductor device in which characteristic variations are suppressed can be manufactured.

[0016] Furthermore, in this method for manufacturing a SiC semiconductor device, an electrode including a metal silicide layer is formed. And the metal silicide layer is configured to include SiC constituting the semiconductor substrate. That is, the metal silicide layer is formed by reacting a portion where damage occurs due to ion implantation. For this reason, in this method for manufacturing a SiC semiconductor device, the remaining of the portion where damage occurs due to ion implantation can be reduced, and a SiC semiconductor device in which characteristic variations are suppressed can be manufactured.

[0017] The reference numerals with parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0018] [Figure 1] It is a cross-sectional view of the SiC semiconductor device in the first embodiment. [Figure 2A] It is a diagram showing the impurity concentration along line IIA-IIA in FIG. 1. [Figure 2B] It is a diagram showing the impurity concentration along line IIB-IIB in FIG. 1. [Figure 3A] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device shown in FIG. 1. [Figure 3B] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 3A. [Figure 3C] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 3B. [Figure 3D] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device following FIG. 3C. [Figure 3E] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 3D. [Figure 3F] This is a cross-sectional view showing the manufacturing process of SiC semiconductor devices, following Figure 3E. [Figure 4] This is a cross-sectional view showing the impurity concentration along the line IV-IV in Figure 3D. [Figure 5] This is a cross-sectional view of a SiC semiconductor device according to a second embodiment. [Modes for carrying out the invention]

[0019] The embodiments of this disclosure will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0020] (First Embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device in which a trench gate structure inverted MOSFET is formed will be used as an example.

[0021] As shown in Figure 1, the SiC semiconductor device is constructed using a semiconductor substrate 10 made of SiC. Specifically, the semiconductor substrate 10 of the SiC semiconductor device is made of n + The substrate 11 is of a specific type. In this embodiment, the substrate 11 has, for example, an off-angle of 0 to 8° with respect to the (0001)Si plane, and the concentration of n-type impurities such as nitrogen and phosphorus is 1.0 × 10⁻⁶. 19 / cm 3 It is said that a substrate with a thickness of approximately 50 to 300 μm is used. In this embodiment, the substrate 11 constitutes the drain region.

[0022] On the surface of the substrate 11, an n-type drift layer 12, a p-type base layer 13, etc. made of SiC are formed by epitaxial growth or the like. Hereinafter, the surface of the semiconductor substrate 10 on the base layer 13 side will be described as one surface 10a of the semiconductor substrate 10, and the surface of the semiconductor substrate 10 on the substrate 11 side will be described as the other surface 10b of the semiconductor substrate 10.

[0023] The drift layer 12 has, for example, an n-type impurity concentration of about 1.0 to 50.0×10 15 / cm 3 and a thickness of about 5 to 50 μm. The base layer 13 is formed on the drift layer 12 and has, for example, a p-type impurity concentration of about 2.0×10 17 / cm 3 and a thickness of about 0.5 to 2 μm.

[0024] On the surface layer portion of the base layer 13, an n + type source region 14 and a p + type contact region 15 are formed. The source region 14 is formed so as to contact the side surface of a trench 17 described later. The contact region 15 is formed on the opposite side of the trench 17 with the source region 14 interposed therebetween, abuts on the source region 14, and is formed deeper than the source region 14.

[0025] Here, in the present embodiment, a recess 16 recessed from the one surface 10a is formed in the one surface 10a of the semiconductor substrate 10. And the contact region 15 is formed so as to be exposed from the bottom surface of the recess 16, and the source region 14 is formed so as to be exposed from a portion different from the portion where the recess 16 is formed in the one surface 10a of the semiconductor substrate 10. In other words, in the normal direction with respect to the one surface 10a of the semiconductor substrate 10, the contact region 15 is formed so as to overlap the recess 16, and the source region 14 is formed in a region different from the region overlapping the recess 16. Note that the normal direction with respect to the one surface 10a of the semiconductor substrate 10 can also be said to be when viewed from the normal direction with respect to the one surface 10a of the semiconductor substrate 10.

[0026] Furthermore, as will be described later, the contact region 15 in this embodiment is constructed by ion implanting more p-type impurities than n-type impurities into the n-type region, thereby punching the n-type region back into the p-type region. For this reason, the contact region 15 is also composed of n-type impurities. In this embodiment, the source region 14 corresponds to the first impurity region, and the contact region 15 corresponds to the second impurity region. Also, the source region 14 and the contact region 15 are ion-implanted layers constructed by ion implantation, as will be described later, and the contact region 15 corresponds to the punched-back layer into which the n-type region has been punched back.

[0027] Trenches 17, for example, with a width of about 0.8 μm, are formed in the semiconductor substrate 10 so as to penetrate the base layer 13 and the source region 14 and reach the drift layer 12. Although Figure 1 shows two trenches 17, in reality, multiple trenches 17 are arranged in a stripe pattern at equal intervals in the left-right direction of the paper.

[0028] Each trench 17 is filled with a gate insulating film 18 formed to cover the wall surface of each trench 17, and a gate electrode 19 made of polysilicon or the like formed on the gate insulating film 18. In this embodiment, the trench gate structure is configured in this way. In this embodiment, the portion of the trench 17 wall surface that is in contact with the base layer 13 becomes the surface of the base layer 13 sandwiched between the first impurity region and the drift layer 12.

[0029] An upper electrode 20 is formed on one surface 10a of the semiconductor substrate 10, which is electrically connected to the source region 14 and the contact region 15. In this embodiment, the upper electrode 20 has a configuration comprising a metal silicide layer 21 formed at the interface with the semiconductor substrate 10 and a main portion 22 disposed on the metal silicide layer 21.

[0030] Specifically, the metal silicide layer 21 is a metal layer that is a compound that has undergone a silicide reaction with SiC (i.e., the semiconductor substrate 10), and its purpose is to reduce the contact resistance with SiC and create an ohmic contact. The metal silicide layer 21 is formed along one surface 10a of the semiconductor substrate 10. In this embodiment, since a recess 16 is formed on one surface 10a of the semiconductor substrate 10, the portion of the metal silicide layer 21 located on the recess 16 is recessed.

[0031] The metal silicide layer 21 is composed of a high-melting-point metal or noble metal silicide, such as a nickel silicide layer, titanium silicide layer, tantalum silicide layer, tungsten silicide layer, or molybdenum silicide layer. In this case, the metal silicide layer 21 may be composed of one type of metal or multiple types of metals. For example, the types of metals constituting the metal silicide layer 21 may differ between n-type SiC and p-type SiC. In this embodiment, an example in which the metal silicide layer 21 is composed of a nickel silicide layer will be described. The film thickness of the metal silicide layer 21 can be changed as appropriate, but is typically around 10 to 100 nm.

[0032] The main portion 22 is made of, for example, aluminum silicon and is formed to be thicker than the metal silicide layer 21. Although not specifically shown in the figures, the main portion 22 may have a plating film of nickel, gold, or the like formed on the surface opposite to the metal silicide layer 21.

[0033] On the other side 10b of the semiconductor substrate 10, a lower electrode 23 is formed which is electrically connected to the substrate 11. In the SiC semiconductor device of this embodiment, this structure constitutes a trench gate structure MOSFET that is an n-channel inverting type. In this embodiment, n-type corresponds to the first conductivity type, and p-type corresponds to the second conductivity type.

[0034] In such a SiC semiconductor device, when a voltage lower than that of the lower electrode 23 is applied to the upper electrode 20 and a voltage above a predetermined threshold voltage is applied to the gate electrode 19, an n-type inversion layer (i.e., a channel) is formed in the portion of the base layer 13 that is in contact with the trench 17. Then, electrons are supplied from the source region 14 to the drift layer 12 via the inversion layer, causing the device to turn on.

[0035] The above describes the basic configuration of the SiC semiconductor device in this embodiment. Next, the impurity concentrations of the source region 14 and the contact region 15 in the SiC semiconductor device will be explained with reference to Figures 2A and 2B. In the following explanation, the plane along the interface between the source region 14 and the upper electrode 20 will be used as the reference plane.

[0036] As will be described later, the contact region 15 of this embodiment is formed by ion implanting p-type impurities into the n-type region and returning a portion of the n-type region to the p-type region. As will be described later, the source region 14 is composed of a portion of the n-type region that is different from the contact region 15.

[0037] Furthermore, as shown in Figure 2A, the first peak position P1 where the n-type impurity concentration is highest in the source region 14 is defined as the reference plane. In other words, the first peak position P1 where the n-type impurity concentration is highest in the source region 14 is defined as the interface with the metal silicide layer 21. Hereafter, the first peak position P1 where the n-type impurity concentration is highest in the source region 14 will also simply be referred to as the first peak position P1 of the source region 14.

[0038] The contact region 15 is formed by converting an n-type region into a p-type region. Therefore, as shown in Figure 2B, the contact region 15 also contains n-type impurities, and is defined as a p-type region when the concentration of p-type impurities is higher than the concentration of n-type impurities. The second peak position P2 in the contact region 15, where the concentration of p-type impurities is highest, is the interface with the bottom surface of the recess 16. In other words, the second peak position P2 in the contact region 15, where the concentration of p-type impurities is highest, is the interface with the metal silicide layer 21. Hereafter, the second peak position P2 in the contact region 15, where the concentration of p-type impurities is highest, will also be simply referred to as the second peak position P2 of the contact region 15.

[0039] In this embodiment, as described above, the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are different, with the second peak position P2 being formed at a deeper position than the first peak position P1. Since the source region 14 and the contact region 15 are composed of ion implantation, the impurity concentration decreases in the depth direction from each peak position P1 and P2. For this reason, the n-type impurity concentration at the second peak position P2 is lower than the n-type impurity concentration at the first peak position P1.

[0040] Furthermore, the contact region 15 is composed of n-type impurities as described above. In such a contact region 15, the contact resistance between it and the upper electrode 20 (metal silicide layer 21) depends on the concentration difference d between the p-type impurity concentration and the n-type impurity concentration, and decreases as the concentration difference d increases. For this reason, in this embodiment, the impurity concentration at the second peak position P2 is higher than the impurity concentration at the first peak position P1.

[0041] Next, the manufacturing methods for the source region 14 and contact region 15 in the SiC semiconductor device described above will be explained with reference to Figures 3A to 3F. Note that in Figures 3A to 3F, the other side 10b of the semiconductor substrate 10 is omitted.

[0042] First, as shown in Figure 3A, a semiconductor substrate 10 with a base layer 13 formed is prepared, and without placing a mask, n-type impurities are ion-implanted from one side 10a of the semiconductor substrate 10 to form an n-type region 30 on the base layer 13. The n-type region 30 is a part of which becomes the source region 14 and corresponds to the first conductivity type region.

[0043] Next, as shown in Figure 3B, a mask 40 is placed on one surface 10a of the semiconductor substrate 10. Then, the mask 40 is patterned so that the area on one surface 10a of the semiconductor substrate 10 that is to be formed for the contact region 15 is open.

[0044] Next, as shown in Figure 3C, RIE (Reactive Ion Etching) and the like are performed to form a recess 16 on the portion of one surface 10a of the semiconductor substrate 10 that is exposed from the mask 40. The depth of the recess 16 is set according to the amount of SiC reacted when forming the metal silicide layer 21, and after the process in Figure 3C is completed, it is shallower than the recess 16 of the SiC semiconductor device shown in Figure 1.

[0045] Next, as shown in Figure 3D, the mask 40 used to form the recess 16 is used as is, and p-type impurities are ion-implanted from the bottom surface of the recess 16, causing the portion of the n-type region 30 exposed from the mask 40 to be pushed back into the p-type region. As a result, a contact region 15 is formed in the pushed-back portion of the n-type region 30, and a source region 14 is formed in the portion of the n-type region 30 that is different from the contact region 15.

[0046] In this embodiment, when ion implanting p-type impurities, the p-type impurities are implanted at approximately the same acceleration voltage as when ion implanting n-type impurities. Therefore, the relationship between the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 after the process shown in Figure 3D is shown in Figure 4. Although not specifically shown, ion implantation of n-type and p-type impurities causes defects due to damage on one side 10a of the semiconductor substrate 10. Figure 4 also shows the n-type impurity concentration in the source region 14 and the p-type impurity concentration in the contact region 15 along the IV-IV line in Figure 3D. The n-type impurity concentration in the contact region 15 at a position deeper than the bottom surface of the recess 16 in Figure 4 is the same as that in the source region 14. Furthermore, the period after the process shown in Figure 3D can be rephrased as the period before the formation of the metal silicide layer 21.

[0047] When n-type and p-type impurities are ion-implanted at approximately the same acceleration voltage, the distance between the peak position where the impurity concentration is highest and the implantation surface is approximately the same. Therefore, as shown in Figure 4, the first distance L1 between one surface 10a of the semiconductor substrate 10 and the first peak position P1 is approximately equal to the second distance L2 between the bottom surface of the recess 16 and the second peak position P2. In this embodiment, the first distance L1 and the second distance L2 are adjusted according to the amount of SiC that reacts when forming the metal silicide layer 21, which will be described later.

[0048] Furthermore, as described above, the contact resistance between the contact region 15 and the upper electrode 20 depends on the concentration difference d between the p-type impurity concentration and the n-type impurity concentration. Therefore, in this embodiment, the contact resistance can be reduced by increasing the concentration difference by making the p-type impurity concentration at the second peak position P2 higher than the n-type impurity concentration at the first peak position P1. Note that if the first peak position P1 and the second peak position P2 are at the same depth, it would be necessary to further increase the p-type impurity concentration to achieve the same contact resistance as in this embodiment, which would make one surface 10a of the semiconductor substrate 10 more prone to roughening.

[0049] Next, as shown in Figure 3E, a trench 17 is formed by placing a mask (not shown) and performing anisotropic etching such as RIE. Then, a gate insulating film 18 and a gate electrode 19 are formed in the trench 17 by CVD (chemical vapor deposition) or the like. Finally, any unwanted gate insulating film 18 and gate electrode 19 formed on one surface 10a of the semiconductor substrate 10 are removed.

[0050] Next, as shown in Figure 3F, a metal layer such as nickel is formed on one surface 10a of the semiconductor substrate 10 by sputtering or the like, and a heat treatment is performed to react the semiconductor substrate 10 (i.e., SiC) with the metal layer to form a metal silicide layer 21. In other words, the damaged portion of the semiconductor substrate 10 is reacted to form the metal silicide layer 21. In this embodiment, the heating temperature and the like are adjusted so that the first peak position P1 of the source region 14 and the second peak position P2 of the contact region 15 are located at the interface with the metal silicide layer 21, thereby adjusting the thickness of the metal silicide layer 21. That is, by adjusting the amount of reaction between the semiconductor substrate 10 and the metal layer to adjust the thickness of the metal silicide layer 21, the first peak position P1 and the second peak position P2 of the source region 14 are located at the interface with the metal silicide layer 21. As a result, the impurity concentration in the depth direction of the source region 14 is as shown in Figure 2A, and the impurity concentration in the depth direction of the contact region 15 is as shown in Figure 2B.

[0051] In this process, the semiconductor substrate 10 reacts with the metal layer to form a metal silicide layer 21. As a result, one surface 10a of the semiconductor substrate 10 and the bottom surface of the recess 16 become more recessed than before the formation of the metal silicide layer 21. In this process, the metal silicide layer 21 is formed such that the first peak position P1 and the second peak position P2 of the source region 14 are located at the interface with the metal silicide layer 21. However, slight deviations from the target position may be acceptable due to manufacturing errors, etc.

[0052] Subsequently, although not specifically shown in the diagram, the SiC semiconductor device shown in Figure 1 is manufactured by arranging the metal layer that will become the main part 22 to form the upper electrode 20 and the lower electrode 23.

[0053] According to the embodiment described above, the contact region 15 is a re-punched layer having n-type impurities. Therefore, a mask is not required when forming the source region 14, and an increase in the manufacturing process can be suppressed. Furthermore, since a mask is not required when forming the source region 14, only the positional misalignment of the mask when forming the contact region 15 needs to be considered, and an increase in the size of the SiC semiconductor device can be suppressed.

[0054] Furthermore, in the SiC semiconductor device of this embodiment, the second peak position P2 is deeper than the first peak position P1. Therefore, compared to the case where the second peak position is at the same depth as the first peak position, the amount of p-type impurities required to punch back the source region 14 and form the contact region 15 can be reduced, thereby reducing the damage that may occur to the semiconductor substrate 10. Consequently, the occurrence of characteristic fluctuations is suppressed.

[0055] Furthermore, in this SiC semiconductor device, the upper electrode 20 is composed of a metal silicide layer 21. The metal silicide layer 21 is composed of SiC that makes up the semiconductor substrate 10. In other words, the metal silicide layer 21 is formed by reacting the areas where damage occurs due to ion implantation. As a result, this SiC semiconductor device has less residual damage caused by ion implantation, and the occurrence of characteristic fluctuations is suppressed.

[0056] (1) In this embodiment, a recess 16 is formed, and p-type impurities are ion-implanted into the bottom surface of the recess 16, thereby making the second peak position P2 deeper than the first peak position P1. As a result, n-type and p-type impurities can be ion-implanted with the same acceleration voltage, and the manufacturing process can be further simplified.

[0057] (2) In this embodiment, the first peak position P1 and the second peak position P2 are located at the interface between the upper electrode 20 and the metal silicide layer 21 that constitutes the upper electrode 20. Therefore, the contact resistance between the upper electrode 20 and both the source region 14 and the contact region 15 can be reduced.

[0058] In this embodiment, the contact region 15 is composed of n-type impurities. The contact resistance between the contact region 15 and the metal silicide layer 21 is due to the concentration difference d between the n-type impurity concentration and the p-type impurity concentration at the interface between the contact region 15 and the metal silicide layer 21, and decreases as the concentration difference d increases. In this embodiment, the second peak position P2 is formed at a deeper position than the first peak position P1. Therefore, compared to the case where the first peak position P1 is the same as the second peak position P2, it is easier to increase the concentration difference d without increasing the p-type impurity concentration, and thus easier to reduce the contact resistance.

[0059] (Second Embodiment) A second embodiment will now be described. This embodiment modifies the method of forming the contact region 15 compared to the first embodiment. Other aspects are the same as in the first embodiment, so a detailed explanation will be omitted here.

[0060] In the SiC semiconductor device of this embodiment, as shown in Figure 5, the metal silicide layer 21 has a flattened surface on the side opposite to the semiconductor substrate 10. Furthermore, in this embodiment, the portion of the metal silicide layer 21 located on the contact region 15 is thicker than the portion located on the source region 14.

[0061] The above describes the configuration of the SiC semiconductor device in this embodiment. Next, the manufacturing process of the SiC semiconductor device in this embodiment will be described.

[0062] In this embodiment, after performing the process shown in Figure 3B, p-type impurities are ion-implanted to push back the portion of the n-type region 30 exposed from the mask 40 into the p-type region, thereby forming the contact region 15 and the source region 14. Specifically, in this embodiment, unlike the process shown in Figure 3C, p-type impurities are ion-implanted without forming the recess 16. In this case, in this embodiment, p-type impurities are ion-implanted at a higher acceleration voltage than when forming the n-type region 30 by ion-implanting n-type impurities, so that the second peak position P2 is deeper than the first peak position P1.

[0063] In this case, since the acceleration voltage used for ion implantation of p-type impurities is greater than the acceleration voltage used for ion implantation of n-type impurities, the portion of one surface 10a of the semiconductor substrate 10 that has been ion-implanted with p-type impurities is more prone to damage and a breakdown of its crystallinity.

[0064] Next, the steps shown in Figures 3E and 3F are performed. When forming the metal silicide layer 21 in the step shown in Figure 3F, the more the crystallinity is disrupted, the easier it is for the metal layer and the semiconductor substrate 10 to react and form the metal silicide layer 21. For this reason, the metal silicide layer 21 is more easily formed in the contact region 15 than in the source region 14, and in the contact region 15, the metal silicide layer 21 is formed to a greater depth. As a result, a recess 16 is formed in the semiconductor substrate 10 in the area where the contact region 15 is formed. In addition, in this embodiment, the SiC that reacts with the metal layer is adjusted by the roughness of one surface 10a of the semiconductor substrate 10, so the surface of the metal silicide layer 21 opposite to the semiconductor substrate 10 is flattened.

[0065] Subsequently, in the same manner as in the first embodiment described above, the SiC semiconductor device shown in Figure 5 is manufactured by arranging the main part 22 to form the upper electrode 20 and the lower electrode 23.

[0066] According to the embodiment described above, since the contact region 15 is a counter-returning layer, the same effects as in the first embodiment can be obtained.

[0067] (1) In this embodiment, the second peak position P2 is made deeper than the first peak position P1 by changing the acceleration voltage. Therefore, the process for forming the recess 16 is not required, and the manufacturing process can be reduced.

[0068] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0069] For example, in each of the above embodiments, an example was described in which a SiC semiconductor device is constructed by forming an n-channel type trench gate structure MOSFET with the first conductivity type being n-type and the second conductivity type being p-type. However, the SiC semiconductor device may also be constructed by forming a p-channel type trench gate structure MOSFET with the first conductivity type being p-type and the second conductivity type being n-type. Furthermore, the SiC semiconductor device may also be configured to have IGBTs with a similar structure in addition to MOSFETs. In the case of IGBTs, the n in each of the above embodiments + The substrate 11 of type p + Aside from changing the collector layer type, it is the same as the vertical MOSFET described in each of the embodiments above.

[0070] Furthermore, in each of the above embodiments, a method was described in which p-type impurities are ion-implanted after the formation of the n-type region 30, thereby impounding a portion of the n-type region 30 back into the p-type region. However, it is also possible to form the p-type region first, and then ion-implant n-type impurities to impound a portion of the p-type region back into the n-type region.

[0071] Furthermore, in each of the above embodiments, the n-type impurity concentration at the first peak position P1 and the p-type impurity concentration at the second peak position P2 may be the same, or the n-type impurity concentration at the first peak position P1 may be higher than the p-type impurity concentration at the second peak position P2. [Explanation of symbols]

[0072] 10 Semiconductor substrates 10a one side 10b Other side 14. Source region (first impurity region) 15. Contact area (second impurity area) 20 Upper electrode 21 Metal silicide layer

Claims

1. A silicon carbide semiconductor device composed of silicon carbide, A semiconductor substrate (10) made of silicon carbide, having one surface (10a) and another surface (10b) opposite to the said surface, A first impurity region (14) of a first conductivity type formed on one side of the semiconductor substrate, A second impurity region (15) of a second conductivity type is formed on one side of the semiconductor substrate and has a portion that contacts the first impurity region, The device comprises an electrode (20) electrically connected to the first impurity region and the second impurity region, The aforementioned first impurity region is an ion implantation layer, The second impurity region is a counter-implantation layer containing the first conductivity type impurities, and the second conductivity type is determined by making the impurity concentration of the second conductivity type higher than the impurity concentration of the first conductivity type. With the surface along the interface between the first impurity region and the electrode as the reference plane, the second peak position (P2) in the depth direction of the semiconductor substrate from the reference plane, where the impurity concentration of the second conductivity type in the second impurity region is highest, is located at a deeper position than the first peak position (P1) in the first impurity region, where the impurity concentration of the first conductivity type is highest. The electrode is composed of a compound with silicon carbide and includes a metal silicide layer (21) that comes into contact with the semiconductor substrate. The silicon carbide semiconductor device wherein the first and second peak positions are located at the interface with the metal silicide layer.

2. The semiconductor substrate has a recess (16) formed on one side, The silicon carbide semiconductor device according to claim 1, wherein the second impurity region is formed in a position that overlaps with the recess in the direction normal to one surface of the semiconductor substrate.

3. The silicon carbide semiconductor device according to claim 2, wherein the first impurity region is formed only at a position different from the position overlapping with the recess in the normal direction.

4. A semiconductor substrate (10) made of silicon carbide, having one surface (10a) and another surface (10b) opposite to the said surface, A first impurity region (14) of a first conductivity type formed on one side of the semiconductor substrate, A second impurity region (15) of a second conductivity type is formed on one side of the semiconductor substrate and has a portion that contacts the first impurity region, The device comprises an electrode (20) electrically connected to the first impurity region and the second impurity region, The aforementioned first impurity region is an ion implantation layer, The second impurity region is a counter-implantation layer containing the first conductivity type impurities, and the second conductivity type is determined by making the impurity concentration of the second conductivity type higher than the impurity concentration of the first conductivity type. With the surface along the interface between the first impurity region and the electrode as the reference plane, the second peak position (P2) in the depth direction of the semiconductor substrate from the reference plane, where the impurity concentration of the second conductivity type in the second impurity region is highest, is located at a deeper position than the first peak position (P1) in the first impurity region, where the impurity concentration of the first conductivity type is highest. The electrode is composed of a compound with silicon carbide and includes a metal silicide layer (21) that comes into contact with the semiconductor substrate. A method for manufacturing a silicon carbide semiconductor device, wherein the first peak position and the second peak position are located at the interface with the metal silicide layer, To prepare the aforementioned semiconductor substrate, Forming a first conductivity type region (30) by ion implanting a first impurity of the first conductivity type from one side of the semiconductor substrate, A mask (40) having an opening in the region where the second impurity region is to be formed is placed on one side of the semiconductor substrate. A second impurity of the second conductivity type is ion-implanted from one side of the semiconductor substrate, a portion of the first conductivity type region is reversed to form the second impurity region, and a region of the first conductivity type region that is different from the second impurity region is designated as the first impurity region. After ion implanting the second impurity, a metal layer is placed on one side of the semiconductor substrate, and the metal layer is reacted with the semiconductor substrate to form the metal silicide layer that constitutes the electrode. By ion implanting the second impurity, the second impurity is ion implanted such that the second peak position is located at a deeper position than the first peak position. A method for manufacturing a silicon carbide semiconductor device, wherein the thickness of the metal silicide layer is adjusted so that the first peak position and the second peak position are located at the interface between the metal silicide layer and the semiconductor substrate.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the ion implantation of the second impurity comprises forming a recess (16) in a region of one surface of the semiconductor substrate that forms the second impurity region, and ion implanting the second impurity into the bottom surface of the recess.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the recess is formed by arranging a mask (40) in which the area to be formed in the second impurity region is to be opened, and the second impurity is ion-implanted from the bottom surface of the recess using the mask as is.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein the ion implantation of the second impurity region is performed by ion implanting the second impurity at an acceleration voltage higher than the acceleration voltage used when ion implanting the first impurity, thereby causing the second peak position to be deeper than the first peak position.

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