Switching control devices, isolated switching power supplies, and electrical equipment

Abstract

To provide a switching control device capable of providing good load regulation of an isolated type switching power supply.SOLUTION: A switching control device is configured to control a switching element (SW1) connected to a primary winding (L1) of a transformer (TR1). The switching control device includes: sample-hold circuits (S5, C7) configured to perform sample-hold of a feedback voltage resulting from an induction voltage generated in an auxiliary winding (L3) of the transformer; control parts (5 to 8) configured to control the switching element based on the output of the sample-hold circuits; and timing signal generation circuits (2 to 4, Q1 to Q11, C3 to C5, S1 to S4) configured to generate a timing signal according to the induction voltage. The sample-hold circuit is configured to sample the feedback voltage according to the timing signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The inventions disclosed herein relate to a switching control device, and an isolated switching power supply device and electrical equipment using the same. [Background technology]

[0002] Conventionally, isolated switching power supplies, which generate a desired output voltage from an input voltage while insulating the primary and secondary circuit systems, have been used in various electrical devices. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-76962 [Overview of the project] [Problems that the invention aims to solve]

[0004] Generally, isolated switching power supplies use photocouplers for output feedback control. However, conventional configurations using photocouplers have faced challenges such as decreased long-term reliability and increased costs due to the increased number of components.

[0005] Furthermore, isolated switching power supplies have been proposed that perform output feedback control using the auxiliary windings of the transformer without using photocouplers.

[0006] Generally, in conventional configurations using auxiliary windings, the feedback voltage is sampled a certain time after the switching element turns off. This sampled feedback voltage contains information about the forward voltage VF of the diodes provided in the secondary circuit system. Since the forward voltage VF of the diodes provided in the secondary circuit system fluctuates depending on the load, the load regulation of the isolated switching power supply deteriorates.

[0007] The isolated switching power supply proposed in Patent Document 1 improves the accuracy of output feedback control by measuring the period from when the primary current is turned off until the feedback voltage falls below a threshold voltage, and sampling the feedback voltage based on the measurement results. However, a configuration that samples the feedback voltage based on measurement results results in a complex circuit configuration.

[0008] Therefore, it is desirable to improve the load regulation of an isolated switching power supply using an auxiliary winding using a method other than that described in Patent Document 1. [Means for solving the problem]

[0009] A switching control device disclosed herein is configured to control a switching element connected to the primary winding of a transformer. The switching control device includes a sample-and-hold circuit configured to sample and hold a feedback voltage based on an induced voltage generated in the auxiliary winding of the transformer; a control unit configured to control the switching element based on the output of the sample-and-hold circuit; and a timing signal generation circuit configured to generate a timing signal corresponding to the induced voltage. The sample-and-hold circuit is configured to sample the feedback voltage according to the timing signal.

[0010] The isolated switching power supply device disclosed herein comprises the switching control device having the above configuration, the transformer, and the switching element.

[0011] The electrical equipment disclosed herein includes an isolated switching power supply having the above configuration. [Effects of the Invention]

[0012] According to the inventions disclosed herein, load regulation of an isolated switching power supply can be improved. [Brief explanation of the drawing]

[0013] [Figure 1] Figure 1 is a diagram showing the configuration of an isolated switching power supply device according to the first embodiment. [Figure 2] Figure 2 is a timing chart showing the voltage and current of each part of the isolated switching power supply device according to the first embodiment. [Figure 3] Figure 3 is a diagram showing a voltage dividing circuit used in a modification of the first embodiment. [Figure 4] Figure 4 is a diagram showing the configuration of an isolated switching power supply device according to the second embodiment. [Figure 5] Figure 5 is a timing chart showing the voltage and current of each part of the isolated switching power supply device according to the second embodiment. [Figure 6] Figure 6 is an external view of an electrical device.

MODE FOR CARRYING OUT THE INVENTION

[0014] In this specification, a MOS (Metal Oxide Semiconductor) field effect transistor refers to a field effect transistor whose gate structure consists of at least three layers of "a layer made of a conductor or a semiconductor such as polysilicon with a small resistance value", "an insulating layer", and "a P-type, N-type, or intrinsic semiconductor layer". That is, the gate structure of a MOS field effect transistor is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0015] In this specification, the reference voltage means a voltage that is constant in an ideal state, and is actually a voltage that can vary slightly due to temperature changes or the like.

[0016] <First Embodiment> Figure 1 is a diagram showing the configuration of an isolated switching power supply device 101 according to the first embodiment. The isolated switching power supply device 101 according to the first embodiment includes a transformer TR1, a diode D1, an output capacitor C1, a capacitor C2, a resistor R1, and a semiconductor device 201.

[0017] The transformer TR1 includes a primary winding L1 and a secondary winding L2 that are electromagnetically coupled to each other with opposite polarities. The primary winding L1 and the secondary winding L2 electrically insulate the primary and secondary circuit systems from each other. The first end of the primary winding L1 is subjected to an input voltage V IN A voltage is applied. The second end of the primary winding L1 is connected to terminal T3 of the semiconductor device 201. The first end of the secondary winding L2 is connected to the anode of diode D1. The cathode of diode D1 is connected to the first end of output capacitor C1. The second end of the secondary winding L2 and the second end of output capacitor C1 are connected to the ground potential of the secondary circuit system. The induced voltage generated in the secondary winding L2 is rectified by diode D1 and smoothed by output capacitor C1 to produce the output voltage V OUT It is converted to the output voltage V. OUT This is output from the connection node between the cathode of diode D1 and the first end of output capacitor C1.

[0018] Transformer TR1 includes an auxiliary winding L3 in addition to the primary winding L1 and secondary winding L2. The first end of the auxiliary winding L3 is connected to the first end of resistor R1, the first end of capacitor C2, and terminal T1 of semiconductor device 201. The second end of the auxiliary winding L3 and the second end of capacitor C2 are connected to the ground potential of the primary circuit system. The second end of resistor R1 is connected to terminal T2 of semiconductor device 201. The induced voltage Vd generated in the auxiliary winding L3 is smoothed by capacitor C2 and converted into the power supply voltage Vcc. The power supply voltage Vcc is applied to terminal T1. The induced voltage Vd generated in the auxiliary winding L3 is converted into a current Id by resistor R1. Current Id is supplied to terminal T2, and the first feedback voltage V FB1 The first feedback voltage V is applied. FB1 It can be expressed by the following formula, where R1 is the resistance value of resistor R1. V FB1 =Vd-Id×R1

[0019] The semiconductor device 201 includes a switching element SW1, a switching control device for controlling the switching element SW1, a sense resistor R4 for detecting the current flowing through the switching element SW1, a clamper 1A, and terminals T1 to T3.

[0020] In this embodiment, the switching element SW1 is an N-channel MOS field-effect transistor. The drain of the switching element SW1 is connected to the primary winding L1 via terminal T3. The source of the switching element SW1 is connected to ground potential via sense resistor R4. In a modification of this embodiment, the switching element SW1 may be an element other than an N-channel MOS field-effect transistor.

[0021] The switching control device includes a sample-and-hold circuit, a control unit, and a timing signal generation circuit.

[0022] The sample-and-hold circuit includes a switch S5 and a capacitor C7. The sample-and-hold circuit has a second feedback voltage V based on the induced voltage Vd generated in the auxiliary winding L3. FB2 The sample-and-hold circuit samples and holds the second feedback voltage V according to the timing signal generated by the timing signal generation circuit. FB2 Sample the data.

[0023] The control unit controls the switching element SW1 based on the output of the sample-and-hold circuit. The control unit includes a reference voltage source 5, an error amplifier 6, a comparator 7, a control unit 8, a capacitor C8, and a resistor R3.

[0024] The timing signal generation circuit generates a timing signal corresponding to the induced voltage Vd. The timing signal generation circuit includes comparators 2 and 3, a flip-flop 4, MOS field-effect transistors Q1 to Q10, capacitors C3 to C5, switches S1 to S3, a one-shot circuit 9, and a NOT gate N1.

[0025] The switching control device further comprises a switch S4, a capacitor C6, a MOS field-effect transistor Q11, a resistor R2, a NOT gate N2, a switch S6, and a clamper 1A.

[0026] Next, we will explain the connections within the internal circuitry of the semiconductor device 201.

[0027] The power supply voltage Vcc is applied to the sources of the P-channel MOS field-effect transistors Q1, Q2, Q5-Q7, and Q11, and to the first terminal of capacitor C6. The sources of the N-channel MOS field-effect transistors Q3, Q4, and Q8-Q10 are connected to ground potential. Hereafter, MOS field-effect transistors Q1-Q11 will be abbreviated as transistors Q1-Q11.

[0028] Terminal T2 is connected to the drain and gate of transistor Q1, as well as the gate of transistor Q1, via clamper 1A. Terminal T2 is also connected to the gates of transistors Q3 and Q4, and to the drain of transistor Q3 via switch S6.

[0029] The drain of transistor Q2 is connected to the first terminal of capacitor C3 via switch S1. The second terminal of capacitor C3 is connected to ground potential.

[0030] The drain of transistor Q4 is connected to the drain of transistor Q5 and to the gates of transistors Q5 through Q7. Additionally, the drain of transistor Q4 is connected via switch S4 to the gate of transistor Q11 and to the second terminal of capacitor C6.

[0031] The drain of transistor Q6 is connected to the first terminal of capacitor C4 via switch S2. The second terminal of capacitor C4 is connected to ground potential.

[0032] The drain of transistor Q7 is connected to the first terminal of capacitor C5 via switch S3. The second terminal of capacitor C5 is connected to ground potential.

[0033] The first terminal of capacitor C3 is connected to the non-inverting input terminal of comparator 2, the inverting input terminal of comparator 3, and the drain of transistor Q8. The first terminal of capacitor C4 is connected to the inverting input terminal of comparator 2 and the drain of transistor Q9. The first terminal of capacitor C5 is connected to the non-inverting input terminal of comparator 3 and the drain of transistor Q10.

[0034] The output terminal of comparator 2 is connected to the reset terminal of flip-flop 4. The output terminal of comparator 3 is connected to the clock terminal of flip-flop 4. The power supply voltage Vcc is applied to the data input terminal of flip-flop 4. Switches S4 and S5 are controlled by the voltage VSMP output from the output terminal of flip-flop 4. Switches S4 and S5 turn on when the voltage VSMP is at the HIGH level and turn off when the voltage VSMP is at the LOW level.

[0035] The drain of transistor Q11 is connected to the first terminal of resistor R2 and the first terminal of switch S5. The second terminal of resistor R2 is connected to the ground potential. Resistor R2 converts the drain current of transistor Q11 corresponding to the current Id into the second feedback voltage V FB2 to.

[0036] The second terminal of switch S5 is connected to the non-inverting input terminal of error amplifier 6 and the first terminal of capacitor C7. The second terminal of capacitor C7 is connected to the ground potential. The reference voltage output from reference voltage source 5 is supplied to the inverting input terminal of error amplifier 6.

[0037] The non-inverting input terminal of comparator 7 is connected to the output terminal of error amplifier 6 and the first terminal of capacitor C8. The second terminal of capacitor C8 is connected to the ground potential via resistor R3. The inverting input terminal of comparator 7 is connected to the connection node between the source of switching element SW1 and sense resistor R4.

[0038] The output signal of comparator 7 is supplied to control unit 8. Control unit 8 switches the voltage VGATE from LOW level to HIGH level at a predetermined period, for example. Also, when the output signal of comparator 7 switches from HIGH level to LOW level, control unit 8 switches the voltage VGATE from HIGH level to LOW level. The voltage VGATE output from control unit 8 is supplied to the gate of switching element SW1 and to one-shot circuit 9. The voltage VOS output from one-shot circuit 9 is supplied to the gates of transistors Q8 to Q10. Voltage VOS is the voltage at which a one-shot pulse is generated when the voltage VGATE switches from LOW level to HIGH level. Switch S1 is controlled by the voltage VGATE. NOT gate N2 inverts the voltage VGATE. Switch S6 is controlled by the output voltage of NOT gate N2. Switch S1 is turned on when the voltage VGATE is at HIGH level and turned off when the voltage VGATE is at LOW level. Switch S6 turns on when the voltage VGATE is at a LOW level and turns off when the voltage VGATE is at a HIGH level. In a modified version of this embodiment, the sense resistor R4 may be an external component of the semiconductor device 201. Also, in a modified version of this embodiment, the capacitor C8 and resistor R3 may be external components of the semiconductor device 201.

[0039] Figure 2 is a timing chart showing the voltage and current of each part of the isolated switching power supply 101 according to the first embodiment.

[0040] The timing signal generation circuit generates a timing signal (voltage VSMP) based on the comparison result (output of comparator 2) between the voltage VC1 output from the first terminal of capacitor C3 and the voltage VC2 output from the first terminal of capacitor C4. More specifically, the timing signal generation circuit sets the pulse termination timing PETM of the timing signal (voltage VSMP) based on the output of comparator 2.

[0041] Voltage VC1 increases in accordance with the induced voltage Vd during the period T1 when the switching element SW1 is ON, and the increase stops when the switching element SW1 switches from ON to OFF. Voltage VC2 increases in accordance with the induced voltage Vd during the period when the switching element SW1 is OFF.

[0042] The timing signal generation circuit sets the pulse start timing PSTM, which precedes the pulse end timing PETM. The timing signal generation circuit sets the pulse start timing PSTM of the timing signal (voltage VSMP) based on the comparison result (output of comparator 3) between voltage VC1 and voltage VC3 output from the first terminal of capacitor C5. Voltage VC3 increases in accordance with the induced voltage Vd during the period when the switching element SW1 is off, and its rate of increase is greater than that of voltage VC2. For example, by making the drain current of transistor Q5 greater than the drain current of transistor Q2, the rate of increase of voltage VC3 can be made greater than the rate of increase of voltage VC2. Also, for example, by making the capacitance of capacitor C5 smaller than the capacitance of capacitor C3, the rate of increase of voltage VC3 can be made greater than the rate of increase of voltage VC2.

[0043] As a variation of this embodiment, the timing signal generation circuit may set the pulse start timing PSTM based on the comparison result of voltage VC2 with a voltage smaller than voltage VC1. In this case, instead of transistor Q7, switch S3, capacitor C5, and transistor Q10, for example, the voltage divider circuit 20 shown in Figure 3 can be used. The voltage divider circuit 20 generates a voltage divide of voltage VC1 and supplies the voltage divide of voltage VC1 to the non-inverting input terminal of comparator 3.

[0044] Next, we will explain the period T2 during which the secondary current Is flows.

[0045] The period T2 during which the secondary current Is flows can be calculated using the following procedure.

[0046] Peak value I of the current flowing through switching element SW1 ppk This is expressed by the following equation (1). Note that Lp This is the inductance of the primary winding L1.

number

[0047] The turns ratio N of a transformer is equal to the number of turns of the primary winding L1. p The number of turns of the secondary winding L2 is N s It is the value obtained by dividing by [a certain factor].

[0048] Peak value of secondary current Is I spk It is expressed by the following formula. Note that V F V is the forward voltage of diode D1, rip This is a ripple component. And V OUT +V F +V rip V O By setting this, we obtain equation (2) below.

number

[0049] By substituting equation (1) above into equation (2) above, we obtain the following equation.

number

[0050] Inductance L of primary winding L1 p , the inductance L of the secondary winding L2 s Number of turns of primary winding L1 N p , and the number of turns of the secondary winding L2 N s Using the following relationship that holds between the two, the period T2 can be expressed by the following formula.

number

[0051] Rewriting the period T2 using the relationship between the secondary winding L2 and the auxiliary winding L3 results in the following. Note that N dis the number of turns of the auxiliary winding L3. Also, Vd here is the maximum value of the induced voltage Vd.

number

[0052] Next, we will explain the pulse termination timing (PETM) of the timing signal (voltage VSMP).

[0053] In the circuit configuration of semiconductor device 201, the following equation holds true when the switching element SW1 is ON. Note that I1 is the charging current of capacitor C3, and C1 is the capacitance of capacitor C3. Here, the Miller ratios of transistors Q1 and Q2 are assumed to be 1, but the Miller ratios of transistors Q1 and Q2 may be other than 1.

number

[0054] In the circuit configuration of semiconductor device 201, the following equation holds true when the switching element SW1 is off. I2 is the charging current of capacitor C4, and C2 is the capacitance of capacitor C4. Here, we consider the Miller ratios of transistors Q3 and Q4 to be 1, and the Miller ratios of transistors Q5 and Q6 to be 1. However, the Miller ratios of transistors Q3 and Q4 may be other than 1, and the Miller ratios of transistors Q5 and Q6 may be other than 1.

number

[0055] In the circuit configuration of semiconductor device 201, the pulse termination timing PETM of the timing signal (voltage VSMP) occurs when voltages VC1 and VC2 are equal. Therefore, the following equation holds true for the pulse termination timing PETM. The following equation is the same as the equation for period T2 described above. Thus, in the circuit configuration of semiconductor device 201, the pulse termination timing PETM can be made to coincide with the end of period T2. However, considering manufacturing tolerances, etc., it is preferable to set the pulse termination timing PETM slightly ahead of the end of period T2 (see Figure 2). One way to set the pulse termination timing PETM slightly ahead of the end of period T2 is to set the current I2 to a value slightly larger than the value obtained by the above equation.

number

[0056] Next, I will explain Clamper 1A.

[0057] The clamper 1A includes N-channel type MOS field-effect transistors 11 and 12, and a current source 13. Hereinafter, the MOS field-effect transistors 11 and 12 will be abbreviated as transistors 11 and 12.

[0058] The drain of transistor 11 is connected to the gate of transistor Q2 and the drain and gate of transistor Q1. The source of transistor 11 is connected to terminal T2. The power supply voltage Vcc is applied to the first terminal of current source 13. The second terminal of current source 13 is connected to the drain and gate of transistor 12 and the gate of transistor 11. The source of transistor 12 is connected to ground potential.

[0059] The clamper 1A is connected to the voltage V applied to terminal T2. FB1 The voltage is clamped at 0V. Here, terminal T2 is connected to the first end of the parasitic capacitance. The second end of the parasitic capacitance is connected to ground potential. Therefore, when the induced voltage Vd transitions from negative to positive, the voltage V is charged until the parasitic capacitance is charged. FB1This results in a delay. In other words, in this embodiment, the problem remains that the induced voltage Vd cannot be immediately converted into a current signal.

[0060] <Second Embodiment> The isolated switching power supply device 102 according to the second embodiment is a switching power supply device that can solve the problems of the isolated switching power supply device 101 according to the first embodiment.

[0061] Figure 4 shows the configuration of the isolated switching power supply 102 according to the second embodiment. Figure 5 is a timing chart showing the voltage and current of each part of the isolated switching power supply 102 according to the second embodiment.

[0062] The isolated switching power supply device 102 according to the second embodiment includes a transformer TR1, a diode D1, an output capacitor C1, a capacitor C2, a resistor R1, and a semiconductor device 202.

[0063] The semiconductor device 202 is configured by removing the clamper 1A from the semiconductor device 201 and replacing it with a clamper 1B.

[0064] Clamper 1B includes an N-channel MOS field-effect transistor 14, an operational amplifier 15, a current source 16, and an N-channel MOS field-effect transistor 17. Hereinafter, MOS field-effect transistors 14 and 17 will be abbreviated as transistors 14 and 17.

[0065] The drain of transistor 14 is connected to the gate of transistor Q2 and the drain and gate of transistor Q1. The source of transistor 14 is connected to terminal T2 and the inverting input terminal of operational amplifier 15. The gate of transistor 14 is connected to the output terminal of operational amplifier 15. The power supply voltage Vcc is applied to the first terminal of current source 16. The second terminal of current source 16 is connected to the non-inverting input terminal of operational amplifier 15 and the drain and gate of transistor 17. The source of transistor 17 is connected to ground potential.

[0066] The clamper 1B is connected to the voltage V applied to terminal T2. FB1 The current is clamped by the voltage VTH1 supplied to the inverting input terminal of the operational amplifier 15. When the induced voltage Vd becomes equal to the voltage VTH1, only the same current as the output current of the current source 16 can flow from the clamper 1B. Therefore, when the induced voltage Vd rises and becomes greater than the voltage VTH1, the current supply from the clamper 1B stops, and the voltage V applied to terminal T2 is reduced. FB1 The voltage becomes VTH2, and all the current flows to transistor Q3. As a result, as shown in Figure 5, the voltage V applied to terminal T2 is FB1 It transitions between voltage VTH1 and voltage VTH2.

[0067] Voltage VTH1 is a predetermined value greater than 0V and immediately transitions from voltage VTH1 to voltage VTH2. Therefore, semiconductor device 202, voltage V FB1 This can suppress the delay caused by the influence of parasitic capacity.

[0068] <Examples of applications for isolated switching power supplies> Figure 6 is an external view showing one example configuration of an air conditioner. The air conditioner Y in this example configuration has an indoor unit Y1, an outdoor unit Y2, and piping Y3 connecting them. The indoor unit Y1 mainly incorporates an evaporator and an indoor fan, while the outdoor unit Y2 mainly incorporates a compressor, condenser, expansion valve, and outdoor fan. The indoor unit Y1 also incorporates an isolated switching power supply 101 according to the first embodiment or an isolated switching power supply 102 according to the second embodiment.

[0069] During cooling operation of air conditioner Y, the refrigerant is first compressed into a high-temperature, high-pressure gas by the compressor of the outdoor unit Y2, and then liquefied by the condenser of the outdoor unit Y2 through heat dissipation. At this time, the outdoor fan is turned on to blow air onto the condenser to promote heat dissipation, so hot air is blown out from the outdoor unit Y2. Next, the liquefied refrigerant is depressurized into a low-temperature, low-pressure liquid by the expansion valve of the outdoor unit Y2, and then sent to the indoor unit Y1 via piping Y3, where it is vaporized in the evaporator of the indoor unit Y1. At this time, the evaporator becomes cold due to the heat of vaporization of the refrigerant, so by turning on the indoor fan to blow air onto the evaporator, cool air is sent out from the indoor unit Y1 into the room. The vaporized refrigerant is sent back to the outdoor unit Y2 via piping Y3, and the same heat exchange process as above is repeated.

[0070] During heating operation of air conditioner Y, the refrigerant circulation direction is reversed, and the roles of the evaporator in indoor unit Y1 and the condenser in outdoor unit Y2 are swapped, but the heat exchange process is basically the same as described above.

[0071] Here, we have used consumer electronics as an example of the application of isolated switching power supplies, but isolated switching power supplies may also be installed in industrial equipment, automotive equipment, and other devices. In other words, the electrical equipment in which isolated switching power supplies are installed is not limited to consumer electronics.

[0072] <Other> The structure of the invention can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the invention. The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention is indicated by the claims, not by the description of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0073] The switching control device described above is a switching control device configured to control a switching element (SW1) connected to the primary winding (L1) of a transformer (TR1), and comprises: a sample-and-hold circuit (S5, C7) configured to sample and hold a feedback voltage based on an induced voltage generated in the auxiliary winding (L3) of the transformer; a control unit (5-8) configured to control the switching element based on the output of the sample-and-hold circuit; and a timing signal generation circuit (2-4, Q1-Q10, C3-C5, S1-S3) configured to generate a timing signal corresponding to the induced voltage, wherein the sample-and-hold circuit is configured to sample the feedback voltage according to the timing signal (first configuration).

[0074] The switching control device with the first configuration described above can suppress the inclusion of forward voltage information of the diodes provided in the secondary circuit system of the isolated switching power supply in the feedback voltage, thereby improving the load regulation of the isolated switching power supply.

[0075] In the switching control device of the first configuration described above, the timing signal generation circuit is configured to generate the timing signal based on the comparison result of a first voltage and a second voltage, wherein the first voltage increases in accordance with the induced voltage during the period when the switching element is ON, and the increase stops at the timing when the switching element switches from ON to OFF, and the second voltage increases in accordance with the induced voltage during the period when the switching element is OFF (second configuration).

[0076] The switching control device with the second configuration described above can implement the timing signal generation circuit with a simple circuit configuration.

[0077] In the switching control device of the second configuration described above, the timing signal generation circuit may be configured to set the pulse end timing of the timing signal based on the comparison result and to set the pulse start timing that precedes the pulse end timing of the timing signal (third configuration).

[0078] The switching control device with the third configuration described above can reliably ensure the pulse width of the timing signal.

[0079] In the switching control device of the third configuration described above, the timing signal generation circuit sets the pulse start timing based on the comparison result of the first voltage and the third voltage, and the third voltage may be configured to increase in accordance with the induced voltage during the period when the switching element is off, and to have a larger rate of increase than the second voltage (fourth configuration).

[0080] The switching control device with the fourth configuration described above can reliably secure the pulse width of the timing signal while realizing the timing signal generation circuit with a simple circuit configuration.

[0081] In the switching control device of the third configuration described above, the timing signal generation circuit may be configured to set the pulse start timing based on the comparison result between the second voltage and a voltage smaller than the first voltage (fifth configuration).

[0082] The switching control device with the fifth configuration described above can reliably secure the pulse width of the timing signal while realizing the timing signal generation circuit with a simple circuit configuration.

[0083] In a switching control device according to any of the first to fifth configurations described above, there may also be a sixth configuration (sixth configuration) which includes a terminal configured to receive a first current corresponding to the induced voltage, and a conversion unit (R2) configured to convert a second current corresponding to the first current into the feedback voltage.

[0084] The switching control device with the sixth configuration described above can share terminals required for the sample-and-hold circuit and terminals required for the timing signal generation circuit.

[0085] In the switching control device of the sixth configuration described above, there may also be a configuration (seventh configuration) that includes a clamper (1B) configured to clamp the voltage applied to the terminal to a predetermined value greater than 0V.

[0086] The switching control device with the seventh configuration described above can suppress the delay in the voltage applied to a terminal configured to receive a first current corresponding to the induced voltage due to the effect of parasitic capacitance.

[0087] The isolated switching power supply devices (101, 102) described above have a configuration (8th configuration) comprising a switching control device having one of the first to seventh configurations described above, the transformer, and the switching element.

[0088] The isolated switching power supply with the eighth configuration described above can suppress the inclusion of forward voltage information of the diodes in the secondary circuit system into the feedback voltage, thereby enabling good load regulation.

[0089] The electrical equipment (Y) described above has a configuration (9th configuration) that includes an isolated switching power supply unit as described in the 8th configuration above.

[0090] The electrical equipment with the ninth configuration described above can suppress the inclusion of forward voltage information of the diodes provided in the secondary circuit system of the isolated switching power supply in the feedback voltage, thereby improving the load regulation of the isolated switching power supply. [Explanation of Symbols]

[0091] 1A, 1B Clamper 2, 3 Comparators 4 Flip-flops 5. Reference voltage source 6 Error Amplifier 7 Comparator 8 Control Unit 9. One-shot circuit 11, 12, 14, 17, Q1~Q11 MOS field-effect transistors 13, 16 current source 15 Op-amps 20-volt voltage divider circuit 101 Isolated switching power supply according to the first embodiment 102 Isolated switching power supply according to the second embodiment 201, 202 Semiconductor equipment C1 output capacitor C2~C8 Capacitors D1 diode L1 Primary winding L2 Secondary winding L3 Auxiliary winding N1, N2 NOT gates R1~R3 ​​resistance R4 Sense Resistance S1~S6 Switch SW1 Switching element T1~T3 terminals TR1 Transformer Y Air Conditioner Y1 Indoor Unit Y2 outdoor unit Y3 Piping

Claims

1. A switching control device configured to control a switching element connected to the primary winding of a transformer, A sample-and-hold circuit configured to sample and hold a feedback voltage based on an induced voltage generated in the auxiliary winding of the transformer, A control unit configured to control the switching element based on the output of the sample-and-hold circuit, A timing signal generation circuit configured to generate a timing signal corresponding to the induced voltage, It has, The sample-and-hold circuit is configured to sample the feedback voltage according to the timing signal. The timing signal generation circuit is configured to generate the timing signal based on the comparison result of the first voltage and the second voltage. The first voltage increases in accordance with the induced voltage during the period when the switching element is ON, and the increase stops when the switching element switches from ON to OFF. A switching control device wherein the second voltage increases in accordance with the induced voltage during the period when the switching element is off.

2. The aforementioned timing signal generation circuit is Based on the comparison results, set the pulse termination timing of the timing signal. The switching control device according to claim 1, which sets a pulse start timing that precedes the pulse end timing of the timing signal.

3. The timing signal generation circuit sets the pulse start timing based on the comparison result of the first voltage and the third voltage. The switching control device according to claim 2, wherein the third voltage increases in accordance with the induced voltage during the period when the switching element is off, and the rate of increase is greater than that of the second voltage.

4. The switching control device according to claim 2, wherein the timing signal generation circuit sets the pulse start timing based on the result of comparing the second voltage with a voltage smaller than the first voltage.

5. A terminal configured to receive a first current corresponding to the induced voltage, A conversion unit configured to convert a second current corresponding to the first current into the feedback voltage, A switching control device according to any one of claims 1 to 4, having the following features.

6. The switching control device according to claim 5, further comprising a clamper configured to clamp the voltage applied to the terminal to a predetermined value greater than 0V.

7. A switching control device according to claim 1, The aforementioned transformer, An isolated switching power supply device having the aforementioned switching element.

8. An electrical device having an isolated switching power supply device as described in claim 7.

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