Information processing device and control method

Abstract

The system complies with the display device standard while appropriately configuring the operating mode without adding signal terminals. [Solution] The information processing device comprises a main system that performs information processing, and a display device that displays information based on the information processing, and includes a power management unit that manages the power supply of the display device. Among the signal terminals of the standardized interface of the display device, a signal terminal whose state is fixed at startup and which is used with a fixed state during the normal operation of the display device is designated as a shared terminal. The power management unit detects the impedance connected to the shared terminal during a predetermined period from the power startup of the display device, and sets an operating mode for the display device according to the detected impedance.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus and a control method.

Background Art

[0002] In an information processing apparatus such as a notebook personal computer (notebook PC), for example, a display device such as a liquid crystal display is mounted. The display device manages the power supply for display using a power management unit such as a PMIC (Power Management Integrated Circuit) (for example, see Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in a conventional information processing apparatus, when trying to flexibly cope with the power management unit of the display device according to the power supply configuration such as the configuration of the battery, for example, it is necessary to set an operation mode according to the power supply configuration. However, in recent years, the interface of the display device is defined by a standard specification such as eDP (Embedded Display Port), and it has been difficult for a conventional information processing apparatus to newly add signal terminals for mode setting.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide an information processing apparatus and a control method capable of appropriately setting an operation mode without adding signal terminals while conforming to the standard specification of the display device.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention is an information processing device comprising: a main system that performs information processing; and a display device that displays information based on the information processing, the display device including a power management unit that manages the power supply of the display device, wherein a signal terminal among the signal terminals of the standardized interface of the display device that has a fixed state at startup and is used with a fixed state during normal operation of the display device is designated as a shared terminal, and the power management unit detects the impedance connected to the shared terminal within a predetermined period from the power startup of the display device, and sets an operating mode for the display device according to the detected impedance.

[0007] Furthermore, in one aspect of the present invention, in the information processing apparatus described above, the combined terminal is a BIST_EN terminal that enables a display test using the manufacturer's reserve terminal of the eDP (Embedded Display Port) standard, and the power management unit may set the operating mode that indicates the power supply configuration supplied to the display device according to the impedance connected to the BIST_EN terminal within the predetermined period.

[0008] Furthermore, in one aspect of the present invention, in the information processing apparatus described above, the display device includes a timing controller that controls the timing for driving the display panel, and the BIST_EN terminal may be connected to the timing controller via a diode and pull-up resistor for preventing reverse current when the power management unit detects the impedance.

[0009] Furthermore, in one aspect of the present invention, in the information processing apparatus described above, the display device includes a timing controller that controls the timing for driving the display panel, and the power management unit includes an analog logic unit that, within a predetermined period, flows a constant current to the BIST_EN terminal to detect the impedance and set the operating mode, and a digital input unit that, after the predetermined period, determines the logic level input by the BIST_EN terminal, and outputs the logic level based on the determination result determined by the digital input unit to the input terminal of the BIST_EN signal of the timing controller.

[0010] Furthermore, in one aspect of the present invention, in the information processing apparatus described above, the display device includes a timing controller that controls the timing for driving the display panel, and the power management unit includes an analog logic unit that, within a predetermined period, flows a constant current to the BIST_EN terminal, detects the impedance, and sets the operating mode; a digital input unit that, after the predetermined period, determines the logic level input by the BIST_EN terminal; and a fault notification unit that, when it is determined that the BIST_EN terminal has become active based on the input logic level, outputs a fault notification signal to the timing controller to notify of a fault, and, at the request of the timing controller, outputs information indicating that the BIST_EN terminal has become active as a fault cause.

[0011] Furthermore, in one aspect of the present invention, in the information processing apparatus described above, the power management unit may set different operating modes according to the cell configuration of the battery mounted in the information processing apparatus.

[0012] Furthermore, one aspect of the present invention is a control method for an information processing apparatus comprising a main system for performing information processing and a display device for displaying information based on the information processing, the display device including a power management unit for managing the power supply of the display device, wherein a signal terminal among the signal terminals of the standardized interface of the display device whose state is fixed at startup and which is used with a fixed state during normal operation of the display device is designated as a shared terminal, and the power management unit detects the impedance connected to the shared terminal within a predetermined period from the power startup of the display device, and sets an operating mode for the display device according to the detected impedance. [Effects of the Invention]

[0013] According to the above embodiment of the present invention, the operating mode can be appropriately set without adding signal terminals, while complying with the standard specifications for display devices. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows an example of the main hardware configuration of a notebook PC according to the first embodiment. [Figure 2] This is a block diagram showing an example of the configuration of a display device in the first embodiment. [Figure 3] This is a block diagram showing an example configuration of the PMIC in the first embodiment. [Figure 4] A flowchart is provided showing an example of the process for setting the operating mode of the PMIC in the first embodiment. [Figure 5] This block diagram shows an example of the configuration of a display device in the second embodiment. [Figure 6] This block diagram shows an example configuration of the PMIC in the second embodiment. [Figure 7] This block diagram shows an example of the configuration of a display device in the third embodiment. [Figure 8] This block diagram shows an example configuration of the PMIC in the third embodiment. [Figure 9]It is a flowchart showing an example of the operation of TCON in the third embodiment.

Embodiments for Carrying Out the Invention

[0015] Hereinafter, an information processing apparatus and a control method according to an embodiment of the present invention will be described with reference to the drawings.

[0016] [First Embodiment] FIG. 1 is a diagram showing an example of the main hardware configuration of the notebook PC1 according to the first embodiment. In this embodiment, the notebook PC1 will be described as an example of the information processing apparatus.

[0017] As shown in FIG. 1, the notebook PC1 includes a CPU 11, a main memory 12, a video subsystem 13, a display device 14, a chipset 21, a BIOS memory 22, an SSD 23, an audio system 24, a WLAN card 25, a USB connector 26, an embedded controller 31, an input unit 32, a power supply circuit 33, and a battery 34.

[0018] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire notebook PC1.

[0019] The main memory 12 is a writable memory that is used as a reading area for the execution program of the CPU 11 or as a working area for writing the processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. This execution program includes BIOS (Basic Input Output System), OS, various drivers for operating peripheral devices, various services / utilities, application programs, and the like.

[0020] The video subsystem 13 is a subsystem for implementing functions related to image display and includes a video controller. This video controller processes drawing instructions from the CPU 11, writes the processed drawing information to video memory, reads this drawing information from video memory, and outputs it to the display device 14 as drawing data (display data).

[0021] The display device 14 is, for example, a liquid crystal display, and displays a screen based on drawing data (display data) output from the video subsystem 13. Details of the display device 14 will be described later with reference to Figure 2.

[0022] The chipset 21 includes controllers for USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count) bus, and multiple devices are connected to it. In Figure 1, as examples of devices, the BIOS memory 22, SSD 23, audio system 24, WLAN card 25, and USB connector 26 are connected to the chipset 21.

[0023] The BIOS memory 22 consists of electrically rewritable non-volatile memory, such as EEPROM (Electrically Erasable Programmable Read Only Memory) or flash ROM. The BIOS memory 22 stores the BIOS and system firmware for controlling the embedded controller 31, etc.

[0024] An SSD (Solid State Drive) 23 (an example of a non-volatile storage device) stores the OS, various drivers, various services / utilities, application programs, and various data. The audio system 24 records, plays back, and outputs sound data.

[0025] The WLAN (Wireless Local Area Network) card 25 connects to the network via wireless LAN and performs data communication. USB connector 26 is a connector for connecting peripheral devices that use USB.

[0026] The embedded controller 31 (an example of a sub-control unit) is a one-chip microcomputer that monitors and controls various devices (peripherals, sensors, etc.) regardless of the system state of the notebook PC 1. The embedded controller 31 also has a power management function that controls the power supply circuit 33.

[0027] The embedded controller 31 consists of a CPU, ROM, RAM, etc. (not shown), and is equipped with multiple channels of A / D input terminals, D / A output terminals, a timer, and digital input / output terminals. The embedded controller 31 is connected to, for example, the input unit 32 and the power supply circuit 33 via these input / output terminals, and the embedded controller 31 controls the operation of these components.

[0028] The input unit 32 is, for example, an input device such as a keyboard, pointing device, or touchpad.

[0029] The power supply circuit 33 includes, for example, a DC / DC converter and a charge / discharge unit, and converts the DC voltage supplied from the AC / DC adapter or battery 34 into multiple voltages necessary to operate the notebook PC 1. The power supply circuit 33 also supplies power to various parts of the notebook PC 1 based on control from the embedded controller 31.

[0030] The battery 34 supplies power to various parts of the notebook PC 1 via the power supply circuit 33. The DC voltage supplied to the display device 14 varies depending on the cell configuration of the battery 34, and the operating mode of the display device 14 is set according to the cell configuration of the battery 34.

[0031] In this embodiment, the CPU 11, main memory 12, video subsystem 13, chipset 21, BIOS memory 22, SSD 23, audio system 24, WLAN card 25, USB connector 26, embedded controller 31, input unit 32, power supply circuit 33, and battery 34 correspond to the main system 100. Notebook PC 1 comprises the main system 100 and a display device 14.

[0032] Next, with reference to Figure 2, the details of the display device configuration in this embodiment will be described. Figure 2 is a block diagram showing an example configuration of the display device 14 in this embodiment.

[0033] As shown in Figure 2, the notebook PC 1 comprises a main system 100 and a display device 14, and the main system 100 and the display device 14 are connected by, for example, an eDP (Embedded Display Port) standard interface. The eDP standard interface is an example of a standardized interface for the display device 14.

[0034] The display device 14 includes a TCON 143, a PMIC 40, a shared terminal T1, a diode 141, and a pull-up resistor 142. The multi-purpose terminal T1 is connected to the BEST_EN signal terminal of the main system 100 via resistor R1.

[0035] Resistor R1 is connected between the shared terminal T1 and the BEST_EN signal terminal of the main system 100, and is an example of the impedance connected to the shared terminal T1. The resistance value (impedance value) of resistor R1 is set to differ depending on the cell configuration of the battery 34 installed in the main system 100.

[0036] The BEST_EN signal terminal is a signal terminal of the standardized interface of the display device 14 whose state is fixed at startup and is used in a fixed state during the normal operation of the display device 14. The BEST_EN signal is a display test terminal that utilizes the manufacturer's reserved terminal of the eDP standard interface of the display device 14 (for example, the 30-pin NC-RESERVED (Reserved for LCD manufacturer's use) of the eDP standard), and is a signal that is fixed to the L state (Low state) at startup and remains fixed to the L state during the normal operation of the display device 14. The BEST_EN signal is changed to the H state (High state) when the display test of the display device 14 is performed.

[0037] The shared terminal T1 is branched inside the display device 14 into a MODE signal line connected to the PMIC 40 and a BIST signal line (BIST_EN signal line) connected to the TCON 143.

[0038] The multi-purpose terminal T1 is connected to the BIST signal terminal of TCON143 via diode 141. Additionally, a pull-up resistor 142 is connected to the BIST signal line.

[0039] Diode 141 has its anode terminal connected to the BIST signal terminal of TCON143, and its cathode terminal connected to the combined terminal T1. Diode 141 is connected between the combined terminal T1 and the BIST signal terminal of TCON143 to prevent current from flowing back to the BIST signal terminal when detecting the impedance (resistance value) of resistor R1.

[0040] The pull-up resistor 142 is connected between the IO power supply and the BIST signal line (the anode terminal of the diode 141), and when the BIST_EN signal (shared terminal T1) is in the H state, it holds the BIST signal line (the anode terminal of the diode 141) in the H state.

[0041] The TCON 143 (Timing Controller) controls the timing for driving the display panel (not shown). When the BIST_EN signal is set to the H state and the BIST signal terminal is in the H state, the TCON 143 executes a display test of the display device 14.

[0042] The PMIC 40 (Power Management IC, an example of a power management unit) manages the power supply of the display device 14. The PMIC 40 detects the impedance (resistor R1) connected to the shared terminal T1 within a predetermined period (for example, within a period of several tens of mS (milliseconds)) from the power-on of the display device 14, and sets the operation mode regarding the display device 14 according to the detected impedance.

[0043] Note that the shared terminal T1 is a BIST_EN terminal that enables a display test using a manufacturer's reserved terminal of the eDP standard. The PMIC 40 sets the operation mode indicating the power supply configuration supplied to the display device 14 according to the impedance connected to the BIST_EN terminal within a predetermined period.

[0044] The PMIC 40 detects the impedance connected to the BIST_EN terminal, and when the impedance is, for example, not less than the resistance value R11 and less than the resistance value R12 (R11 ≤ R < R22), it sets the operation mode to the (1 / 2) mode in which the supplied power supply VBAT is used after being halved (1 / 2). Also, when the impedance is, for example, not less than the resistance value R12 (R12 ≤ R), the PMIC 40 sets the operation mode to the (1 / 3) mode in which the supplied power supply VBAT is used after being divided by three (1 / 3).

[0045] The PMIC40 generates power supplies VCORE, VDDA, and VIO for the display device 14 based on power supplies VBAT and VCC33 supplied from the main system 100, and supplies them to the TCON143.

[0046] Now, with reference to Figure 3, we will explain an example configuration of the PMIC40. Figure 3 is a block diagram showing an example configuration of the PMIC40 in this embodiment.

[0047] As shown in Figure 3, the PMIC 40 includes an analog logic section 41. The analog logic unit 41 is connected to the MODE signal terminal which is connected to the shared terminal T1, and detects the impedance (resistance value) of the resistor R1 connected to the shared terminal T1 and outputs a mode output signal to set the operating mode.

[0048] The analog logic unit 41 includes a constant current source 411 and an ADC (Analog to Digital Converter) unit 412. The constant current source 411 generates a constant current to detect the impedance (resistance value) of resistor R1 connected to the shared terminal T1. The constant current source 411 supplies a constant current to the shared terminal T1 when the PMIC 40 detects the impedance.

[0049] The ADC unit 412 detects the voltage value of the MODE signal terminal when the constant current source 411 supplies a constant current to the shared terminal T1, and converts it into a digital value. The analog logic unit 41 detects the impedance (resistance value) of resistor R1 based on the voltage value detected by the ADC unit 412.

[0050] Next, the operation of the notebook PC 1 according to this embodiment will be described with reference to the drawings. Figure 4 is a flowchart showing an example of the process for setting the operating mode of the PMIC40 in this embodiment.

[0051] As shown in FIG. 4, when the notebook PC 1 is powered on, the PMIC 40 first detects the impedance connected between the shared terminal T1 and GND (ground) (step S101). Note that when the notebook PC 1 is powered on, the main system 100 fixes the BIST_EN terminal connected to the shared terminal T1 to GND. The analog logic unit 41 of the PMIC 40 supplies a constant current to the shared terminal T1 by the constant current source 411, and detects the impedance (resistance value) of the resistor R1 based on the voltage value detected by the ADC unit 412.

[0052] Next, the analog logic unit 41 sets an operation mode according to the impedance (step S102). When the impedance is, for example, not less than the resistance value R11 and less than the resistance value R12 (R11≦R<R22), the analog logic unit 41 sets the operation mode to the (1 / 2) mode in which the supplied power supply VBAT is halved and used. When the impedance is, for example, not less than the resistance value R12 (R12≦R), the analog logic unit 41 sets the operation mode to the (1 / 3) mode in which the supplied power supply VBAT is reduced to one-third and used.

[0053] Next, the PMIC 40 makes a transition to the normal operation (step S103). After the processing of step S103, the PMIC 40 ends the operation mode setting process. Note that the PMIC 40 executes the processing from step S101 to step S103 within a predetermined time. The BIST_EN terminal is used as a terminal for the display test in the normal operation after a predetermined period.

[0054] Note that in the normal operation, when the shared terminal T1 (BIST_EN terminal) of the PMIC 40 is set to the H state, the display test becomes valid, and the TCON 143 executes the display test of the display device 14 by itself.

[0055] As described above, the Note PO1 (information processing device) according to this embodiment comprises a main system 100 that performs information processing, and a display device 14 that displays information based on the information processing, and includes a PMIC 40 (power management unit) that manages the power supply of the display device 14. Among the signal terminals of the standardized interface of the display device 14, the signal terminal whose state is fixed at startup and which is used with a fixed state during the normal operation of the display device 14 is designated as the shared terminal T1. Within a predetermined period from the power-up of the display device 14, the PMIC 40 detects the impedance (resistance R1) connected to the shared terminal T1, and sets the operating mode for the display device 14 according to the detected impedance.

[0056] As a result, the Note PO1 (information processing device) according to this embodiment can appropriately set the operating mode for the display device 14 in accordance with the impedance (resistance R1) connected to the shared terminal T1, without adding any signal terminals, while complying with the display device standard (e.g., the eDP standard).

[0057] Furthermore, in this embodiment, the shared terminal T1 is the BIST_EN terminal, which enables a display test using the manufacturer's reserve terminal of the eDP standard. The PMIC40 sets an operating mode that indicates the power supply configuration supplied to the display device 14 according to the impedance connected to the BIST_EN terminal within a predetermined period.

[0058] As a result, the Note PO1 (information processing device) in this embodiment uses the BIST_EN terminal, which enables the display test of the eDP standard, as a shared terminal T1, allowing for the appropriate setting of the operating mode using a simple method without adding signal terminals.

[0059] In this embodiment, the display device 14 is equipped with a TCON 143 (timing controller) that controls the timing for driving the display panel. The BIST_EN terminal is connected to the TCON 143 via a diode 141 and a pull-up resistor 142 that prevent reverse current when the PMIC 40 detects impedance.

[0060] As a result, the Note PO1 (information processing device) according to this embodiment can safely set the operating mode while preventing reverse current flow to the TCON143 (timing controller) when detecting impedance.

[0061] Furthermore, in this embodiment, the PMIC 40 sets different operating modes depending on the cell configuration of the battery 34 installed in the notebook PC 1.

[0062] As a result, the Note PO1 (information processing device) according to this embodiment can appropriately set the operating mode according to the cell configuration of the battery 34 installed in the Note PC 1.

[0063] Furthermore, the control method according to this embodiment is a control method for a notebook PC 1 comprising a main system 100 that performs information processing, and a display device 14 that displays information based on the information processing, the display device 14 including a PMIC 40 that manages the power supply of the display device 14, and includes a setting step. Among the signal terminals of the standardized interface of the display device 14, the signal terminal whose state is fixed at startup and which is used with a fixed state during the normal operation of the display device 14 is defined as the shared terminal T1. In the setting step, the PMIC 40 detects the impedance connected to the shared terminal T1 within a predetermined period from the power-up of the display device 14, and sets the operating mode for the display device 14 according to the detected impedance.

[0064] As a result, the control method according to this embodiment has the same effect as Note PO1 described above, and allows for proper setting of the operating mode without adding signal terminals, while complying with the standard specifications of the display device.

[0065] [Second Embodiment] Next, with reference to the drawings, a notebook PC 1a according to a second embodiment will be described. In the second embodiment, a modification is described in which the BIST_EN_O signal generated in the PMIC40a is supplied to the BIST signal terminal of the TCON143.

[0066] The hardware configuration of the notebook PC 1a in the second embodiment is the same as that of the first embodiment shown in Figure 1 above, so its explanation is omitted here.

[0067] Figure 5 is a block diagram showing an example configuration of the display device 14a in this embodiment. As shown in Figure 5, the notebook PC 1a comprises a main system 100 and a display device 14a, and the main system 100 and the display device 14a are connected by, for example, an eDP standard interface.

[0068] In Figure 5, components identical to those shown in Figure 2 are given the same reference numerals, and their descriptions are omitted.

[0069] The display device 14a includes a TCON 143, a PMIC 40a, and a shared terminal T1. The multi-purpose terminal T1 is connected to the BEST_EN signal terminal of the main system 100 via resistor R1.

[0070] The PMIC40a (an example of a power management unit) manages the power supply of the display device 14a. Within a predetermined period (for example, within a period of several tens of milliseconds) after the power of the display device 14a is started, the PMIC40a detects the impedance (resistance R1) connected to the shared terminal T1 and sets the operating mode for the display device 14a according to the detected impedance.

[0071] The shared terminal T1 is the BIST_EN terminal, which enables the eDP standard display test. The PMIC40a sets an operating mode that indicates the power supply configuration supplied to the display device 14, according to the impedance connected to the BIST_EN terminal, within a predetermined period.

[0072] Furthermore, PMIC40a generates a BIST_EN_O signal based on the MODE signal supplied from the shared terminal T1, and supplies the generated BIST_EN_O signal to the BIST signal terminal of TCON143.

[0073] Now, with reference to Figure 6, an example configuration of the PMIC40a will be described. Figure 6 is a block diagram showing an example configuration of the PMIC40a in this embodiment.

[0074] As shown in Figure 6, the PMIC 40a comprises an analog logic section 41 and a digital input section 42. Here, the analog logic unit 41 has the same configuration as in the first embodiment described above, so its explanation is omitted here.

[0075] The digital input unit 42 determines the logic level input by the BIST_EN terminal after a predetermined period of time. The digital input unit 42 outputs the result of the logic level determination as a BIST_EN_O signal.

[0076] The process for setting the operating mode of the PMIC40a in this embodiment is the same as that of the first embodiment shown in Figure 4 above, so its explanation is omitted here.

[0077] As described above, the notebook PC 1a according to this embodiment comprises a main system 100 and a display device 14a, the display device 14a comprising a TCON 143 and a PMIC 40a. The PMIC 40a comprises an analog logic unit 41 and a digital input unit 42. The analog logic unit 41 sets the operating mode by passing a constant current through the BIST_EN terminal within a predetermined period to detect the impedance. After the predetermined period, the digital input unit 42 determines the logic level input by the BIST_EN terminal. The PMIC 40a outputs the logic level based on the determination result made by the digital input unit 42 to the BIST_EN signal input terminal (for example, the BIST signal terminal) of the TCON 143.

[0078] As a result, the notebook PC 1a according to this embodiment achieves the same effects as the first embodiment described above, and allows for proper setting of the operating mode without adding signal terminals, while complying with the display device standard. Furthermore, in the notebook PC 1a according to this embodiment, the diode 141 and pull-up resistor 142 are unnecessary, further simplifying the configuration.

[0079] [Third Embodiment] Next, with reference to the drawings, a notebook PC 1b according to a third embodiment will be described. In the third embodiment, a modified example is described in which the display test is performed using a fault notification signal (-FAULT signal) generated within the PMIC40a, instead of using the BIST signal terminal of the TCON143.

[0080] The hardware configuration of the notebook PC 1b in the third embodiment is the same as that of the first embodiment shown in Figure 1 above, so its explanation is omitted here.

[0081] Figure 7 is a block diagram showing an example configuration of the display device 14b in this embodiment. As shown in Figure 7, the notebook PC 1b comprises a main system 100 and a display device 14b, and the main system 100 and the display device 14b are connected by, for example, an eDP standard interface.

[0082] In Figure 7, components identical to those shown in Figure 5 are given the same reference numerals, and their descriptions are omitted.

[0083] The display device 14b includes a TCON 143a, a pull-up resistor 144, a PMIC 40b, and a shared terminal T1. The multi-purpose terminal T1 is connected to the BEST_EN signal terminal of the main system 100 via resistor R1.

[0084] The PMIC40b (an example of a power management unit) manages the power supply of the display device 14b. Within a predetermined period (for example, within a period of several tens of milliseconds) after the power of the display device 14b is started, the PMIC40b detects the impedance (resistance R1) connected to the shared terminal T1 and sets the operating mode for the display device 14b according to the detected impedance.

[0085] The shared terminal T1 is the BIST_EN terminal, which enables the eDP standard display test. The PMIC40b sets an operating mode that indicates the power supply configuration supplied to the display device 14, according to the impedance connected to the BIST_EN terminal, within a predetermined period.

[0086] Furthermore, PMIC40b generates a -FAULT signal (fault notification signal) as the output of the BIST_EN signal based on the MODE signal supplied from the shared terminal T1, and supplies the generated -FAULT signal to the -FAULT signal input terminal of TCON143a. In this embodiment, the -FAULT signal is used not only for fault notification but also for notification of the output of the BIST_EN signal.

[0087] Furthermore, a pull-up resistor 144 is connected to the signal line of the -FAULT signal, and under normal circumstances, it is maintained in an H state. In this embodiment, the -FAULT signal outputs an L state when any fault is detected by the display device 14b or when an H state is supplied to the BIST_EN terminal. In other words, the PMIC 40b outputs an L state to the -FAULT signal when any fault is detected or when the shared terminal T1 becomes H.

[0088] Furthermore, when the BIST_EN terminal is supplied with a high state, the PMIC40b sets information indicating that the BIST_EN terminal has been supplied with a high state in a register (not shown) that stores failure cause information. Also, when any failure is detected in the display device 14b, the PMIC40b sets information corresponding to the failure in the register that stores failure cause information.

[0089] The pull-up resistor 144 is connected to the signal line of the -FAULT signal. The pull-up resistor 144 holds the -FAULT signal in a high state, except when the PMIC40b outputs a low state to the -FAULT signal.

[0090] When the -FAULT signal is supplied in the L state, TCON143a obtains fault cause information for the fault notification from PMIC40b and performs processing according to the obtained fault cause information. If the fault cause information indicates that the BIST_EN terminal is supplied in the H state, TCON143a performs a display test.

[0091] Now, with reference to Figure 8, we will describe an example configuration of the PMIC40b. Figure 8 is a block diagram showing an example configuration of the PMIC40b in this embodiment.

[0092] As shown in Figure 8, the PMIC 40b comprises an analog logic unit 41, a digital input unit 42, and a fault notification unit 43. Here, the analog logic section 41 and the digital input section 42 have the same configuration as in the second embodiment described above, so their explanation is omitted here.

[0093] The fault notification unit 43 outputs a fault notification signal (the low state of the -FAULT signal) to TCON143a when it determines that the BIST_EN terminal has become active based on the logic level input from the digital input unit 42. In response to a request from TCON143a, the fault notification unit 43 outputs information indicating that the BIST_EN terminal has become active as the cause of the fault.

[0094] The fault notification unit 43 is equipped with a register (not shown) for storing fault cause information, and stores the fault cause information in this register when outputting the L state of the -FAULT signal. Furthermore, the fault notification unit 43 includes a NOR gate 431.

[0095] The NOR gate 431 is a logic gate of negative OR, and outputs an L state to the -FAULT signal, either by an output indicating an H state in the digital input section 42, or by an output indicating an H state that some kind of fault has been detected. Furthermore, after a predetermined period, for example, if the shared terminal T1 connected to the BIST_EN terminal becomes high, the digital input unit 42 outputs a high state, and the NOR gate 431 outputs a low state to the -FAULT signal.

[0096] Next, the operation of the notebook PC 1b according to this embodiment will be described with reference to the drawings. The process for setting the operating mode of the PMIC40b in this embodiment is the same as that of the first embodiment shown in Figure 4 above, so its explanation is omitted here.

[0097] Now, with reference to Figure 9, the operation of TCON143a in this embodiment will be described. Figure 9 is a flowchart showing an example of the operation of TCON143a in this embodiment.

[0098] As shown in Figure 9, in this embodiment, TCON143a first determines whether the -FAULT signal has become low (step S201). If the -FAULT signal output by PMIC40b is low (step S201: YES), TCON143a proceeds to step S202. If the -FAULT signal output by PMIC40b is not low (it is high) (step S201: NO), TCON143a returns to step S201.

[0099] In step S202, TCON143a obtains failure cause information from PMIC40b.

[0100] Next, TCON143a determines whether the failure cause information indicates a high state for the BIST_EN signal (step S203). If the failure cause information indicates a high state for the BIST_EN signal (step S203: YES), TCON143a proceeds to step S204. If the failure cause information does not indicate a high state for the BIST_EN signal (step S203: NO), TCON143a proceeds to step S205.

[0101] In step S204, TCON143a performs a display test on the display device 14b. After the processing in step S204, TCON143a returns to step S201.

[0102] In step S205, TCON143a performs other fault response processing according to the fault cause information. After processing in step S205, TCON143a returns to step S201.

[0103] As described above, the notebook PC 1b according to this embodiment comprises a main system 100 and a display device 14b, the display device 14b comprising a TCON 143a and a PMIC 40b. The PMIC 40b comprises an analog logic unit 41, a digital input unit 42 and a fault notification unit 43. The analog logic unit 41 sets the operating mode by flowing a constant current through the BIST_EN terminal within a predetermined period to detect the impedance. After a predetermined period, the digital input unit 42 determines the logic level input by the BIST_EN terminal. If the fault notification unit 43 determines that the BIST_EN terminal has become active based on the input logic level, it outputs a fault notification signal to the TCON 143a to notify of a fault. The fault notification unit 43 also outputs information indicating that the BIST_EN terminal has become active as a fault cause (e.g., fault cause information) in response to a request from the TCON 143.

[0104] As a result, the notebook PC 1b according to this embodiment achieves the same effects as the first embodiment described above, and allows for proper setting of the operating mode without adding signal terminals, while complying with the display device standard. Furthermore, in the notebook PC 1b according to this embodiment, the diode 141 and pull-up resistor 142 are unnecessary, and the BIST terminal of TCON 143a is also unnecessary, further simplifying the configuration.

[0105] It should be noted that the present invention is not limited to the embodiments described above, and can be modified without departing from the spirit of the invention. For example, in each of the embodiments described above, the information processing device was described as a notebook PC 1 (1a, 1b), but it is not limited to this, and other information processing devices such as tablet terminals or smartphones may also be used.

[0106] Furthermore, although the above embodiments describe an example where the shared terminal T1 is the BIST_EN terminal, the invention is not limited to this. The shared terminal T1 may be any other terminal, such as a backlight enable terminal (BL_EN terminal), which has a fixed state at startup and is used with a fixed state during the normal operation of the display device 14 (14a, 14b).

[0107] Furthermore, although the above embodiments describe examples using the eDP standard as the standard specification for the display device, other standard specifications may also be used.

[0108] Furthermore, although the above embodiments described the display device 14 (14a, 14b) as a liquid crystal display, it is not limited to this and may be other types of displays, such as an organic EL (Electro-Luminescence) display.

[0109] Furthermore, in each of the above embodiments, an example was described in which two operating modes, (1 / 2) mode and (1 / 3) mode, are switched using the impedance connected to the shared terminal T1. However, the invention is not limited to this, and three or more operating modes may be switched depending on the impedance.

[0110] Furthermore, while the above embodiments describe examples of changing the operating mode based on the power supply configuration (cell configuration of the battery 34) using the shared terminal T1, the present invention is not limited to this, and may be used to change the settings of other operating modes.

[0111] Furthermore, while the third embodiment described above illustrates the use of the -FAULT terminal, the invention is not limited to this, and other terminals, such as interrupt terminals, may also be used.

[0112] Furthermore, each component of the aforementioned Notebook PC 1 contains an internal computer system. The processing in each component of Notebook PC 1 (1a, 1b) may be performed by recording a program for realizing the functions of each component on a computer-readable recording medium, loading the program recorded on this recording medium into the computer system, and executing it. Here, "loading the program recorded on the recording medium into the computer system and executing it" includes installing the program into the computer system. Here, "computer system" includes hardware such as the operating system and peripheral devices.

[0113] Furthermore, "computer system" may include multiple computer devices connected via a network, including communication lines such as the Internet, WAN, LAN, and dedicated lines. "Computer-readable recording medium" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Thus, the recording medium storing the program may be a non-transient recording medium such as a CD-ROM.

[0114] Furthermore, the recording medium includes internal or external recording media accessible from the distribution server for distributing the program. The program may be divided into multiple parts, downloaded at different times, and then combined in the respective configurations of Notebook PC 1 (1a, 1b). The distribution servers for each divided program may also be different. Additionally, "computer-readable recording medium" includes volatile memory (RAM) within computer systems that act as servers or clients when a program is transmitted over a network, which retains the program for a certain period of time. Moreover, the program may be intended to implement only a portion of the functions described above. Furthermore, the program may be a so-called differential file (differential program) that can implement the functions described above in combination with programs already recorded in the computer system.

[0115] Furthermore, some or all of the above-mentioned functions may be implemented as integrated circuits such as LSIs (Large Scale Integrations). Each of the above-mentioned functions may be implemented as an individual processor, or some or all of them may be integrated into a single processor. In addition, the method of implementing integrated circuits is not limited to LSIs; they may also be implemented using dedicated circuits or general-purpose processors. Furthermore, if advances in semiconductor technology lead to the emergence of integrated circuit technologies that can replace LSIs, integrated circuits using such technologies may be used. [Explanation of Symbols]

[0116] 1, 1a, 1b Notebook PC 11 CPU 12 Main Memory 13 Video Subsystems 14, 14a, 14b Display device 21 Chipset 22 BIOS memory 23 SSD 24 Audio Systems 25 WLAN cards 26 USB connectors 31. Embedded Controller (EC) 32 Input section 33 Power supply circuit 34 batteries 40, 40a, 40b PMIC 41 Analog Logic Section 42 Digital Input Section 43 Failure notification section 100 Main System 141 diodes 142, 144 pull-up resistors 143, 143a TCON 411 Constant current source 412 ADC section 431 NOR Gate R1 Resistor T1 Dual-purpose terminal

Claims

1. The main system that performs information processing, A display device that displays information based on the aforementioned information processing, the display device including a power management unit that manages the power supply of the display device, Equipped with, Among the signal terminals of the standardized interface of the display device, the signal terminal whose state is fixed at startup and which is used with a fixed state during the normal operation of the display device shall be designated as a shared terminal. The aforementioned power management unit, Within a predetermined period from the power-up of the display device, the impedance connected to the shared terminal is detected, and the operating mode for the display device is set according to the detected impedance. Information processing device.

2. The aforementioned multi-purpose terminal is the BIST_EN terminal, which enables display testing using the manufacturer's reserved terminal of the eDP (Embedded DisplayPort) standard. The power management unit sets the operating mode, which indicates the power supply configuration supplied to the display device, according to the impedance connected to the BIST_EN terminal, within the predetermined period. The information processing apparatus according to claim 1.

3. The display device includes a timing controller that controls the timing for driving the display panel, The BIST_EN terminal is connected to the timing controller via a reverse current prevention diode and pull-up resistor used by the power management unit to detect the impedance. The information processing apparatus according to claim 2.

4. The display device includes a timing controller that controls the timing for driving the display panel, The aforementioned power management unit, An analog logic unit that, within the predetermined period, supplies a constant current to the BIST_EN terminal to detect the impedance and set the operating mode, After the predetermined period, a digital input unit determines the logic level input by the BIST_EN terminal. The system includes a function that outputs a logic level based on the determination result made by the digital input unit to the input terminal of the BIST_EN signal of the timing controller. The information processing apparatus according to claim 2.

5. The display device includes a timing controller that controls the timing for driving the display panel, The aforementioned power management unit, An analog logic unit that, within the predetermined period, supplies a constant current to the BIST_EN terminal to detect the impedance and set the operating mode, A digital input unit that determines the logic level input by the BIST_EN terminal after the predetermined period, Based on the input logic level, if it is determined that the BIST_EN terminal has become enabled, the fault notification unit outputs a fault notification signal to the timing controller to notify of a fault, and, in response to a request from the timing controller, outputs information indicating that the BIST_EN terminal has become enabled as the cause of the fault. The information processing apparatus according to claim 2, comprising:

6. The power management unit sets different operating modes according to the cell configuration of the battery installed in the information processing device. The information processing apparatus according to any one of claims 2 to 5.

7. A control method for an information processing apparatus comprising a main system that performs information processing, and a display device that displays information based on the information processing, the display device including a power management unit that manages the power supply of the display device, Among the signal terminals of the standardized interface of the display device, the signal terminal whose state is fixed at startup and which is used with a fixed state during the normal operation of the display device shall be designated as a shared terminal. The power management unit includes a setting step in which, within a predetermined period from the power-up of the display device, it detects the impedance connected to the shared terminal and sets the operating mode for the display device according to the detected impedance. Control method.

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