Semiconductor structure and method for manufacturing the same

Abstract

To provide an innovative semiconductor structure and a method for manufacturing the same that improve the metal spillage and planarity problems that occur in the ohmic contact alloy process and increase process yields.SOLUTION: The present invention is a semiconductor structure 10 having a substrate 100, a channel layer 130, a barrier layer 140, a source electrode 150, a gate electrode 180, a drain electrode 160, and a cover layer 170. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, the gate electrode and the drain electrode are disposed on the barrier layer. The cover layer covers the areas other than the top of the source and drain electrodes.SELECTED DRAWING: Figure 9

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a manufacturing method thereof, and particularly relates to a High Electron Mobility Transistor (HEMT) structure and a manufacturing method thereof.

Background Art

[0002] In recent years, the demand for high-frequency and high-power products has been increasing. Gallium nitride-based semiconductor power components such as aluminum gallium nitride / gallium nitride (AlGaN / GaN) can achieve a very high switching speed due to their wide bandgap and fast-moving electrons. In addition, because they operate at high frequencies, high powers, and high temperatures, they are widely used in high-power semiconductor structures for radio frequency and power applications in particular. Conventionally, high electron mobility transistors have been made by laminating III-V semiconductors and forming a heterojunction at their interface. Since the energy band of the heterojunction is bent, a potential well is formed in the deep part of the bend of the conduction band, and a two-dimensional electron gas (2DEG) is formed in the potential well.

[0003] Generally, high electron mobility transistors are normally-on (D-mode) or depletion-mode (D-mode) elements, requiring a negative bias voltage to turn them off. In addition to being relatively inconvenient to use, their application range is also limited. On the other hand, another type of high electron mobility transistor, enhancement-mode, has also been proposed. This type of transistor is fabricated by either destroying the lattice structure of the aluminum gallium nitride layer by fluoride ion bombardment before forming a metal gate, or by etching to create a recess in the aluminum gallium nitride layer. Because the gate stacked structure of P-type impurities in the gallium nitride layer exists in the epitaxial crystal at the bottom of the recess, this transistor does not require an additional bias voltage to turn off the normally-off (E-mode) element of the two-dimensional electron gas.

[0004] Currently, when manufacturing the two types of semiconductor devices mentioned above, titanium / aluminum is commonly used as the electrode material for the source and drain electrodes of the device. High-temperature heating between these electrodes and the aluminum gallium nitride barrier layer forms an ohmic contact in the alloy between the electrodes and the gallium nitride. If the alloy temperature is too low, it is difficult to form an ohmic contact between the electrodes and the gallium nitride. On the other hand, if the alloy temperature is too high, the low melting point of aluminum in the electrodes makes metal leakage more likely, negatively impacting the process yield. The dotted lines in Figure 1 show lateral and upward metal leakage due to high temperature during the process of forming an ohmic contact between the source and drain electrodes of a conventional HEMT device. Figure 1A is a magnified microscopic image of lateral metal leakage. Lateral metal leakage during the process can cause a short circuit between the gate and source during subsequent gate electrode formation. Figure 1B, on the other hand, is a magnified microscopic image of upward metal leakage. If metal flows upward during the process, it negatively affects the flatness of the metal layer surface, which is detrimental to subsequent metal lamination processes.

[0005] To overcome the aforementioned problems, developing innovative semiconductor structures and manufacturing methods that improve metal outflow and flatness issues in the ohmic contact alloy process and enhance process yield has become an urgent challenge for the industry. [Overview of the Initiative]

[0006] The main objective of the present invention is to provide an innovative semiconductor structure and a method for manufacturing the same that improves the metal outflow and flatness problems that occur in the process of ohmic contact alloys in the manufacture of heterostructured field-effect transistors, thereby improving process yield.

[0007] To achieve the above objective, the present invention provides a semiconductor structure comprising a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode, and a cover layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, gate electrode, and drain electrode are disposed on the barrier layer. The cover layer covers the portions of the source electrode and drain electrode other than the upper parts.

[0008] In embodiments of the present invention, the materials for the source electrode and drain electrode of the semiconductor structure are selected from the group consisting of titanium, aluminum, nickel, and gold.

[0009] In embodiments of the present invention, the material for the cover layer of the semiconductor structure is selected from the group consisting of silicon nitride, silicon dioxide, and silicon oxynitride.

[0010] In embodiments of the present invention, the present invention further includes a first metal layer positioned above the source electrode and the drain electrode and electrically connected to the source electrode and the drain electrode.

[0011] In embodiments of the present invention, the semiconductor structure further includes a portion of the barrier layer, a cover layer, the first metal layer, and a padding layer covering the gate electrode, except for the upper portion of the first metal layer.

[0012] In embodiments of the present invention, the material for the padding layer of the semiconductor structure is selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide.

[0013] In embodiments of the present invention, the semiconductor structure further includes a communication structure and a second metal layer, which are sequentially arranged above the first metal layer and electrically connected to the first metal layer.

[0014] In embodiments of the present invention, the material of the barrier layer of the semiconductor structure is aluminum indium gallium nitride (Al x In y Ga (1-x-y) It includes N) and satisfies 0≦x<1 and 0≦x+y≦1.

[0015] In embodiments of the present invention, the semiconductor structure further includes a two-dimensional electron gas located at the interface between the channel layer and the barrier layer.

[0016] In embodiments of the present invention, the material of the semiconductor substrate is selected from the group consisting of silicon, sapphire, and silicon carbide.

[0017] To achieve the above objective, the present invention provides a semiconductor structure comprising a substrate, a channel layer, a barrier layer, a source electrode, a gate electrode, a drain electrode, and a conductive cover layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source electrode, gate electrode, and drain electrode are disposed on the barrier layer. The conductive cover layer covers the source electrode and the drain electrode.

[0018] In embodiments of the present invention, the material of the conductive cover layer of the semiconductor structure is selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite.

[0019] In embodiments of the present invention, the semiconductor structure further includes a first metal layer disposed above a conductive cover layer and electrically connected to the conductive cover layer, the source electrode, and the drain electrode.

[0020] To achieve the above objective, the present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: sequentially forming a channel layer and a barrier layer on a substrate and forming a two-dimensional electron gas at the interface between the channel layer and the barrier layer; forming a source electrode and a drain electrode on the barrier layer; forming a cover layer that covers the source electrode and the drain electrode; and heating the source electrode and the drain electrode to form an ohmic contact between the source electrode and the drain electrode and the barrier layer.

[0021] In an embodiment of the present invention, the method for manufacturing a semiconductor structure further includes the steps of forming a gate electrode on a barrier layer between a source electrode and a drain electrode, and forming a first metal layer electrically connected to the source electrode and the drain electrode in a region above the source electrode and the drain electrode.

[0022] In embodiments of the present invention, a method for manufacturing a semiconductor structure further includes the steps of forming a padding layer that covers the first metal layer, a part of the barrier layer, a cover layer, and a gate electrode; removing a part of the padding layer on the first metal layer to expose the upper region of the first metal layer; and annealing the exposed upper region of the first metal layer at a high temperature.

[0023] Those skilled in the art will be able to understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described later. [Brief explanation of the drawing]

[0024] [Figure 1] A schematic diagram showing lateral and upward metal outflow at the source and drain electrodes of a conventional high-electron-mobility transistor. [Figure 1A]Microscopic magnified photograph of lateral metal outflow in a conventional high electron mobility transistor [Figure 1B] Microscopic magnified photograph of upward metal outflow in a conventional high electron mobility transistor [Figure 2] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 3] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 4] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 5A] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 5B] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 6] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 7] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 8] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention [Figure 9] Diagram showing the manufacturing process and structure of a semiconductor structure according to an embodiment of the present invention

Mode for Carrying Out the Invention

[0025] Hereinafter, the content of the present invention will be described through examples. Note that the examples of the present invention are examples of embodiments, and are not intended to be limited to the environments, applications, or specific aspects as described in the examples. Therefore, the description of the examples is for explaining the present invention, but does not limit the present invention. In the embodiments and the drawings, components not directly related to the present invention are omitted and not shown. The dimensional relationships of the components in the drawings are for easy understanding and do not limit the actual dimensions.

[0026] Figure 2 shows a semiconductor structure and a manufacturing method thereof according to an embodiment of the present invention. A nucleation layer 110, a buffer layer 120, a channel layer 130, and a barrier layer 140 are sequentially formed on a substrate 100. The material of the substrate 100 is silicon, sapphire, gallium nitride, silicon carbide, gallium arsenide, etc. The nucleation layer 110 is placed on the substrate 100. The thickness of the nucleation layer 110 is about several tens to several hundred nanometers, which can reduce the lattice difference between the substrate 100 and the barrier layer 140. The nucleation layer 110 is a Group III-V material including, for example, aluminum nitride, gallium nitride, and aluminum gallium nitride. The buffer layer 120 is placed on the nucleation layer 110. The thickness of the buffer layer 120 is about several micrometers to several tens of micrometers, and it is made of a Group III-V material, which can similarly reduce the lattice difference between the substrate 100 and the barrier layer 140. In this embodiment, the buffer layer 120 is either a single-layer or multilayer structure. The buffer layer 120 is, for example, a multilayer superlattice multilayer, or a single layer of a III-V semiconductor material such as aluminum nitride, gallium nitride, or aluminum gallium nitride.

[0027] The channel layer 130 is formed on the buffer layer 120 and has a first energy gap. The barrier layer 140 is formed on the channel layer 130 and has a second energy gap. The second energy gap is higher than the first energy gap. The barrier layer 140 has a smaller lattice constant than the channel layer 130. In this embodiment, the material of the channel layer 130 and the barrier layer 140 is aluminum indium gallium nitride (Al x In y Ga (1-x-y)The vector N) contains 0≦x<1 and 0≦x+y≦1. In this embodiment, the channel layer 130 is a gallium nitride layer, and the barrier layer 140 is an aluminum gallium nitride layer or an indium gallium nitride layer. Spontaneous polarization in the channel layer 130 and the barrier layer 140, and piezoelectric polarization between the channel layer 130 and the barrier layer 140, form a two-dimensional electron gas 132 in the heterojunction between the channel layer 130 and the barrier layer 140.

[0028] As shown in Figure 2, a source electrode 150 and a drain electrode 160 are formed on a barrier layer 140. The material of the source electrode and drain electrode is selected from the group consisting of titanium, aluminum, nickel, gold, or their alloys. Next, as shown in Figure 3, a cover layer 170 is formed to cover the source electrode 150 and drain electrode 160. The material of the cover layer 170 is a hard insulating dielectric material, or a hard conductive ceramic or metallic material. For example, it is selected from the group consisting of silicon nitride, silicon dioxide, silicon oxynitride, titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite. The material of the cover layer 170 prevents lateral and upward metal outflow from the source electrode and drain electrode during the subsequent high-temperature process of ohmic contact. Next, a high-temperature heat treatment is performed at a temperature of approximately 850°C to form ohmic contact between the metals such as titanium and aluminum of the source electrode 150 and drain electrode 160 and the aluminum gallium nitride barrier layer 140. In more detail, since the source electrode 150 and drain electrode 160 are covered by the cover layer 170, lateral and upward metal outflow that occurs in semiconductor processes due to electrode melting and flow is prevented even at high temperatures. Short-circuit problems between the source electrode and the drain electrode can also be avoided in subsequent gate manufacturing. In addition, metal outflow that could adversely affect surface flatness can be prevented above the source and drain electrodes, thus facilitating subsequent metal stacking processes.

[0029] In specific embodiments, an insulating ion implantation process is then performed between elements to destroy any two-dimensional electron gas that may be present between elements in order to ensure insulation between elements on the wafer. Specifically, a boron ion beam is used for insulating ion implantation. The boron ion concentration is 1E15 / cm³. 3 It is controlled to the extent that the ion implantation energy is approximately 180 kev. As shown in Figure 4, the next step is to form the gate electrode. The gate electrode 180 is formed on a barrier layer 140 between the source electrode 150 and the drain electrode 160. In a preferred embodiment of the present invention, a field plate 182 may be added to the gate structure to effectively increase the breakdown voltage and reduce the gate leakage current. Again, in the semiconductor structure disclosed in the present invention, the periphery of the source electrode 150 and the drain electrode 160 is covered by a cover layer 170 so that lateral metal outflow can be avoided when the subsequent high-temperature alloying process of the ohmic contact is carried out. As a result, the problem of lateral metal outflow and short circuits between the gate electrode is avoided and the process yield is improved.

[0030] Next, a metal lamination process is performed on the source electrode and drain electrode. The metal lamination process varies depending on the conductivity of the cover layer. As shown in Figure 5A, if the cover layer 170 is an insulating dielectric material such as silicon nitride, silicon dioxide, or silicon oxynitride as described above, a portion of the cover layer 170 above the source electrode 150 and drain electrode 160 is removed beforehand to expose the upper regions of the source electrode 150 and drain electrode 160, respectively, before performing the metal lamination process. Then, a first metal layer 190 is formed on the upper regions of the source electrode 150 and drain electrode 160. The lamination height of the first metal layer 190 must be greater than the height between the field-effect board 182 and the gate electrode 180. This prevents damage to the gate electrode during the subsequent planarization process. The material of the first metal layer 190 includes aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, tantalum carbide, tantalum silicon nitride, tantalum carbonitride, titanium aluminide, titanium aluminum nitride, metal alloys, or other suitable conductive materials. On the other hand, as shown in Figure 5B, if the cover layer 170 is a conductive material such as titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, or graphite, then the cover layer 170 is conductive and is a conductive cover layer. Therefore, when carrying out the metal lamination process, it is not necessary to remove the cover layer 170 above the source electrode 150 and drain electrode 160 beforehand, and the first metal layer 190 can be formed directly on the cover layer 170 above the source electrode 150 and drain electrode 160. Similarly, the lamination height of the first metal layer 190 must be greater than the height between the field effect board 182 and the gate electrode 180.

[0031] The above process may differ depending on the conductivity of the cover layer 170, but the subsequent semiconductor structure process of the present invention is generally the same. For the sake of brevity, an embodiment in which the cover layer 170 is insulating will be described below. Those skilled in the art should be able to easily infer a specific embodiment in the case of a conductive cover layer 170 from the above disclosure of the present invention. Therefore, a description of that is omitted.

[0032] As shown in Figure 6, a padding layer 200 is formed that covers the first metal layer 190, a portion of the barrier layer 140, the cover layer 170, and the gate electrode 180. Next, as shown in Figure 7, an inner dielectric layer 210 is formed that covers the entire wafer surface, and then a planarization process is performed. Specifically, as shown in Figure 8, this planarization process uses the padding layer 200 above the first metal layer 190 as a stopping layer and removes the padding layer 200 on the first metal layer 190 by chemical mechanical polishing or etch-back, exposing the upper region of the first metal layer 190. Specifically, the height of the metal lamination of the first metal layer 190 is higher than the height of the gate electrode 180 and the field effect board 182, and the planarization process described above stops at the padding layer 200 above the first metal layer 190, so the planarization process does not damage the gate electrode 180 and the field effect board 182. Next, the upper region of the first metal layer 190 is planarized by a high-temperature annealing process. In a preferred embodiment, the surface flatness of the upper region of the first metal layer 190, which has been annealed at a high temperature, is less than 0.1 micrometers, thereby facilitating the subsequent metal lamination process.

[0033] As shown in Figure 9, the next step is the internal connection process of the metal stacking of electrodes. A dielectric layer 220 is formed on the padding layer 200. Next, a communication structure 230 is formed within the dielectric layer 220. Finally, a second metal layer 240 is formed, electrically connected to the communication structure 230 and the first metal layer 190. The second metal layer 240 is electrically connected to the source electrode 150 and the drain electrode 160, respectively. In this way, the semiconductor structure 10 of the present invention is completed. The materials of the communication structure 230 and the second metal layer 240 may be the same as the material of the first metal layer 190, but that explanation is omitted.

[0034] The above description is merely one example of an embodiment of the present invention. The structures disclosed in the present invention can be applied to normally open or normally off type elements of high electron mobility transistors, such as Schottky gate structures, metal-insulator-semiconductor gate structures, normally off type elements, recess gate structures, and p-type doped gallium nitride (pGaN) gate structures. The isolation function of the cover layer 170 described above can be applied when manufacturing these various gate structures. During the manufacturing process of these elements, it is possible to prevent short circuits between the source electrode and the gate electrode due to lateral metal outflow from the source electrode. In the subsequent metal lamination process, the flatness of the metal electrode surface can also be ensured, improving the process yield.

[0035] The above-described embodiments illustrate embodiments of the present invention and describe the characteristic configuration of the present invention. The present invention is not limited to the above embodiments. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention shall be based on the claims. [Explanation of symbols]

[0036] 10 Semiconductor Structures 100 circuit boards 110 Nucleation layer 120 buffer layers 130 channel layers 132 Two-dimensional electron gas 140 Barrier layer 150 source electrodes 160 Drain electrode 170 Cover layer 180 gate 182 Field Effect Board 190 1st metal layer 200 padding layers 210 Inner dielectric layer 220 Dielectric layer 230 Communication structure 240 2nd metal layer

Claims

1. It is a semiconductor structure, circuit board and A channel layer disposed on the substrate, A barrier layer disposed on the channel layer, A source electrode, a gate electrode, and a drain electrode are arranged on the barrier layer, Includes a conductive cover layer, The conductive cover layer covers the source electrode and the drain electrode, but does not cover the gate electrode. A semiconductor structure further comprising a first metal layer disposed in the conductive cover layer above the source electrode and the drain electrode, and electrically connected to the conductive cover layer, the source electrode and the drain electrode.

2. The semiconductor structure according to claim 1, characterized in that the material of the source electrode and the drain electrode is one selected from the group consisting of titanium, aluminum, nickel, and gold.

3. The semiconductor structure according to claim 1, characterized in that the material of the conductive cover layer is one selected from the group consisting of titanium nitride, titanium tungsten, titanium tungsten nitride, aluminum nitride, and graphite.

4. The semiconductor structure according to claim 1, further comprising a part of the barrier layer, the conductive cover layer, the first metal layer, and a padding layer covering the gate electrode, excluding the upper portion of the first metal layer.

5. The semiconductor structure according to claim 4, characterized in that the material of the padding layer is one selected from the group consisting of silicon nitride, silicon dioxide, aluminum nitride, and silicon carbide.

6. The semiconductor structure according to claim 1, further comprising a communication structure and a second metal layer sequentially arranged above the first metal layer and electrically connected to the first metal layer.

7. The semiconductor structure according to claim 1, further comprising a two-dimensional electron gas located at the interface between the channel layer and the barrier layer.

8. The material of the barrier layer is aluminum indium gallium nitride (Al ｘ In ｙ Ga （１－ｘ－ｙ） The semiconductor structure according to claim 1, characterized in that it includes N) and 0 ≤ x < 1 and 0 ≤ x + y ≤ 1.

9. The semiconductor structure according to claim 1, characterized in that the substrate material is one selected from the group consisting of silicon, sapphire, and silicon carbide.

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