Model generation method for SRAM analysis

Abstract

This invention provides a model generation method for SRAM analysis that enables accurate yield analysis of SRAM while reducing computational resources. [Solution] The model generation method for SRAM analysis calculates the three-dimensional Mahalanobis distance based on the threshold voltage of the pull-up transistor, the threshold voltage of the pull-down transistor, and the threshold voltage of the pass-gate transistor. In three-dimensional space, the threshold voltage is identified on the surface of an equiprobability ellipsoid for each σ value. For each threshold voltage, a voltage value is extracted from the identified equiprobability ellipsoid. The extracted voltage value indicates the boundary value of the σ interval. Subsequently, the model generation method calculates the two-dimensional Mahalanobis distance based on the threshold voltage and drain current. In the two-dimensional plane, the voltage value of the threshold voltage and the current value of the drain current are identified on an equiprobability ellipsoid line for each σ value. The current value is calculated from the equiprobability ellipsoid according to the extracted voltage value (boundary value). The calculated current value indicates the boundary value of the σ interval.

Description

Technical Field

[0001] The present invention relates to a method for generating a model for analyzing SRAM (Static Random Access Memory).

Background Art

[0002] In the analysis of SRAM, simulations such as SPICE (Simulation Program with Integrated Circuit Emphasis) are widely used. Generally, in the SPICE model, only the vertices of 5 corners (typical-typical / fast-fast / slow-slow / fast-slow / slow-fast) are used for yield prediction. This simulation model can identify only 4 analysis points. Moreover, unbalanced vertices (fast-slow / slow-fast) are not accurately identified from measured values. The boundary values of the σ interval, which is the area surrounded by the 4 analysis points at a given σ, are ambiguously identified.

[0003] In the yield prediction of SRAM, variations in the threshold voltage of pMOS and variations in the threshold voltage of nMOS that make up the SRAM are assigned to the coordinate values in the two-dimensional plane. In this two-dimensional plane, the window of the operating range of the SRAM and the σ interval are compared. The margin of the σ interval with respect to the window of the operating range is calculated. If the boundary values of the σ interval are ambiguous, the yield cannot be accurately predicted.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

[0005] To improve yield prediction accuracy, Monte Carlo simulations are used, for example. For instance, with 6σ, only 3 or 4 boundary values ​​appear out of 1 million analysis points. Identifying these boundary values ​​requires a massive amount of computation, occupying computational resources for extended periods.

[0006] The present invention aims to provide a model generation method for SRAM analysis that can perform SRAM yield analysis with high accuracy while reducing computational resources. [Means for solving the problem]

[0007] One embodiment of the present invention is a step of acquiring an actual value dataset including the threshold voltage and drain current of a pull-down transistor, the threshold voltage and drain current of a pull-up transistor, and the threshold voltage and drain current of a pass-gate transistor of an SRAM cell; assigning the threshold voltage of the pull-down transistor, the threshold voltage of the pull-up transistor, and the threshold voltage of the pass-gate transistor to coordinate axes in three-dimensional space, calculating a three-dimensional variance-covariance matrix based on the threshold voltages included in the actual value dataset, and calculating the three-dimensional Mahalanobis distance of the actual value dataset; identifying an equiprobability ellipsoid in the three-dimensional space according to a specified probability value, and extracting an equiprobability dataset present on the surface of the equiprobability ellipsoid; and the step of identifying an equiprobability ellipsoid in the three-dimensional space according to a specified probability value, and extracting an equiprobability dataset present on the surface of the equiprobability ellipsoid. The process includes: assigning a threshold voltage and drain current to the coordinate axes of a two-dimensional plane for each pull-down transistor, pull-up transistor, and pass-gate transistor; calculating a two-dimensional variance-covariance matrix based on the threshold voltage and drain current included in the measured value dataset; calculating the two-dimensional Mahalanobis distance of the measured value dataset; identifying an equiprobability ellipse in the two-dimensional plane according to a specified probability value; identifying a drain current on the equiprobability ellipse corresponding to the threshold voltage included in the equiprobability dataset; calculating an offset value based on the threshold voltage included in the equiprobability dataset and the corresponding drain current identified on the equiprobability ellipse; and writing the calculated offset value to the netlist. [Effects of the Invention]

[0008] As described above, the form of disclosure provides a model generation method for SRAM analysis that can perform accurate SRAM yield analysis while reducing computational resources. [Brief explanation of the drawing]

[0009] [Figure 1] This is a circuit diagram showing the configuration of an SRAM cell. [Figure 2] This is a block diagram schematically showing the configuration of a circuit simulation system according to an embodiment of the present invention. [Figure 3] A flowchart illustrating the operation of a circuit simulation system. [Figure 4] This is a conceptual diagram illustrating a specific example of map data. [Figure 5] This figure illustrates the concept of an equiprobability ellipsoid specified in three-dimensional space based on the Mahalanobis distance. [Figure 6] This diagram illustrates the concepts of SRAM's margins and corner model. [Figure 7] This figure illustrates the concept of an equally probable ellipse, specified in a two-dimensional plane based on the Mahalanobis distance. [Figure 8] This is a conceptual diagram showing a specific example of an offset value. [Figure 9] This is a conceptual diagram showing the results of a simulation plotted against a limit line. [Modes for carrying out the invention]

[0010] One embodiment of the present invention will be described below with reference to the drawings.

[0011] Figure 1 schematically shows the circuit configuration of an SRAM (Static Random Access Memory) cell 11. The SRAM cell 11 comprises two CMOS (Complementary Metal-Oxide-Semiconductor) inverters 12 and 13, and nMOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) 14 and 15 individually connected to each CMOS inverter 12 and 13. In each CMOS inverter 12 and 13, the drains of pMOSFETs 12a and 13a are connected in series with the drains of nMOSFETs 12b and 13b. The connection points between the series-connected pMOSFETs 12a and 13a and nMOSFETs 12b and 13b become individual memory nodes N, or complementary memory nodes / N. The sources of pMOSFETs 12a and 13a are connected to the operating voltage VDD. The sources of nMOSFETs 12b and 13b are connected to the reference voltage GND. pMOSFETs 12a and 13a are referred to as load transistors (or pull-up transistors PU), for example. nMOSFETs 12b and 13b are referred to as driver transistors (or pull-down transistors PD), for example.

[0012] A common memory node N is connected to the gates of both pMOSFET13a and nMOSFET13b. The source of nMOSFET14 is connected to memory node N, and its drain is connected to bit line 16. A common memory node N is connected to the gates of both pMOSFET12a and nMOSFET12b. The source of nMOSFET15 is connected to memory node N, and its drain is connected to complementary bit line 17. Word lines 18 are connected to the gates of nMOSFET14 and 15. nMOSFET14 and 15 are referred to as transfer transistors (or pass-gate transistors PG).

[0013] During writing, the voltage of word line 18 is set to H (high). The potential of bit line 16 is set to H, and the potential of complementary bit line 17 is set to L (low). nMOSFET 14 turns on, and the potential of memory node N rises to H due to the potential of bit line 16. On the other hand, the potential of complementary memory node / N becomes L.

[0014] In the standby state with the power off, memory node N is high, so nMOSFET13b is on and pMOSFET13a is off, and memory node / N is held low. On the other hand, since memory node / N is low, nMOSFET12b is off and pMOSFET12a is on, and memory node N is held high.

[0015] For reading, the voltage on word line 18 is set to high. nMOSFETs 14 and 15 are turned on, and the potentials of memory nodes N and / N are read out to bit lines 16 and 17, respectively.

[0016] Figure 2 schematically shows the configuration of a circuit simulation system 21 according to an embodiment of the present invention. The circuit simulation system 21 calculates a three-dimensional Mahalanobis distance from the variances in the coordinate axes of a three-dimensional coordinate system of the threshold voltage Vtpd of a pull-down transistor PD, the threshold voltage Vtpu of a pull-up transistor PU, and the threshold voltage Vtpg of a pass-gate transistor PG of a plurality of SRAM cells, and includes a first Mahalanobis distance calculation unit 22, and for each of the pull-down transistor PD, the pull-up transistor PU, and the pass-gate transistor PG, calculates a two-dimensional Mahalanobis distance from the variances in the coordinate axes of a two-dimensional coordinate system of the threshold voltage Vt and the drain current Id of a plurality of SRAM cells, and a second Mahalanobis distance calculation unit 23.

[0017] For one SRAM cell, one data set (Vtpd, Vtpu, Vtpg) of threshold voltages is obtained. The first Mahalanobis distance calculation unit 22 calculates a three-dimensional scatter covariance matrix based on the plurality of data sets (Vtpd, Vtpu, Vtpg) of the plurality of SRAM cells. First matrix data 24 for specifying the Mahalanobis distance based on the calculated three-dimensional scatter covariance matrix is temporarily stored in a temporary storage device 25.

[0018] The first Mahalanobis distance calculation unit 22 calculates the three-dimensional Mahalanobis distance of the plurality of data sets (Vtpd, Vtpu, Vtpg) of the plurality of SRAM cells based on the three-dimensional scatter covariance matrix. An equal-probability ellipsoid is calculated according to a specified probability value nσ. The size of the equal-probability ellipsoid is determined according to the specified probability value nσ. First equal-probability data 26 for specifying the calculated equal-probability ellipsoid is temporarily stored in the temporary storage device 25.

[0019] The first Mahalanobis distance calculation unit 22 extracts an equal-probability data set (Vtpd, Vtpu, Vtpg) 27 that exists on the surface of the equal-probability ellipsoid in the three-dimensional space of the three-dimensional Mahalanobis distance coordinates. The extracted equal-probability data set 27 is temporarily stored in the temporary storage device 25.

[0020] For each threshold voltage, a single threshold voltage and drain current dataset (Vt, Id) is obtained. The second Mahalanobis distance calculation unit 23 calculates a two-dimensional variance-covariance matrix for each pull-down transistor PD, pull-up transistor PU, and pass-gate transistor PG based on multiple datasets (Vt, Id). The second matrix data 29, which identifies the Mahalanobis distance based on the calculated two-dimensional variance-covariance matrix, is temporarily stored in the temporary storage device 25.

[0021] The second Mahalanobis distance calculation unit 23 calculates the two-dimensional Mahalanobis distance of multiple datasets (Vt, Id) based on a two-dimensional variance-covariance matrix. Equal probability ellipses are calculated according to a specified probability value nσ. The size of the equal probability ellipses is determined according to the specified probability value nσ. The second equal probability data 31 that identifies the calculated equal probability ellipses is temporarily stored in the temporary storage device 25.

[0022] The second Mahalanobis distance calculation unit 23 identifies a dataset (Vt, Id) that lies on an equiprobability ellipse within the two-dimensional plane of the two-dimensional Mahalanobis distance coordinate system. The target dataset 32, which identifies the threshold voltage Vt and drain current Id, is temporarily stored in the temporary storage device 25.

[0023] The circuit simulation system 21 includes a SPICE model correction unit 33 that calculates an offset value for the SPICE model based on a target dataset 32, and a SPICE 34 that simulates the operation of SRAM cells based on the netlist of the SPICE model. The offset data 35 that identifies the calculated offset value is temporarily stored in a temporary storage device 25. The offset value is registered in the netlist of the SPICE model. SPICE 34 calculates a margin for the operating range of the SRAM based on the netlist of the SPICE model. In calculating the margin, SPICE 34 assigns the variation in the threshold voltage of the pMOS ΔVt and the variation in the threshold voltage of the nMOS ΔVt to the coordinate axes of a two-dimensional plane. The first Mahalanobis distance calculation unit 22, the second Mahalanobis distance calculation unit 23, and the SPICE model correction unit 33 constitute a model generation device that implements the model generation method according to the embodiment of the present invention. This model generation device is combined with SPICE 34 to constitute the circuit simulation system 21.

[0024] The circuit simulation system 21 includes an input interface 36 connected to a first Mahalanobis distance calculation unit 22, a second Mahalanobis distance calculation unit 23, and a SPICE model correction unit 33. Measured value datasets 37 and probability value data 38 are passed from the input interface 36 to the first Mahalanobis distance calculation unit 22 and the second Mahalanobis distance calculation unit 23. The measured value datasets 37 may be stored, for example, in a mass storage device (e.g., a hard disk drive HDD) or directly acquired from a wafer inspection device. Each measured value dataset 37 includes, for each SRAM cell, the voltage value of the threshold voltage Vtpd and the current value of the drain current Idpd of the pull-down transistor PD, the voltage value of the threshold voltage Vtpu and the current value of the drain current Idpu of the pull-up transistor PU, and the voltage value of the threshold voltage Vtpg and the current value of the drain current Idpg of the pass-gate transistor PG. The measured value dataset (Vtpd, Vtpu, Vtpg, Idpd, Idpu, Idpg) is described in the map data. The threshold voltage Vt and drain current Id are measured in the SRAM cells of the TEG (Test Element Group) created on the wafer.

[0025] The probability value data 38 identifies the probability values ​​that determine the size of the equiprobability ellipsoid and equiprobability ellipsoid. The probability value data 38 can be obtained, for example, from a keyboard or other input device. The probability values ​​can be set arbitrarily. Here, the probability values ​​are identified, for example, by σ (1σ, 3σ, 6σ, etc.).

[0026] The SPICE model 39 is passed from the input interface 36 to the SPICE model correction unit 33. The SPICE model 39 identifies, for example, a standard pMOSFET model or an nMOSFET model. The SPICE model 39 can be stored, for example, in a large-capacity memory device.

[0027] Here, the first Mahalanobis distance calculation unit 22, the second Mahalanobis distance calculation unit 23, and the SPICE model correction unit 33 may be implemented by a processing unit (processor) 41. In implementing the first Mahalanobis distance calculation unit 22, the second Mahalanobis distance calculation unit 23, and the SPICE model correction unit 33, the processing unit 41 acquires software programs from, for example, a large-capacity storage device. The processing unit 41 executes the software programs while storing the software programs and data in a temporary storage device 25. Such a processing unit 41 is incorporated into, for example, a computer device.

[0028] Next, the operation of the circuit simulation system 21 will be described. As shown in Figure 3, map data (multi-point measurement data) is acquired in step S1. As shown in Figure 4, the map data is input to a measured value dataset 37 (Vtpd, Vtpu, Vtpg, Idpd, Idpu, Idpg) for each individual SRAM cell 11. In generating the map data, the threshold voltage Vt and drain current Id are measured at pMOSFETs 12a, 13a, nMOSFETs 12b, 13b and nMOSFETs 14, 15 of one SRAM cell 11 of the TEG created on the wafer. For example, five points of measurement are taken for the SRAM cell 11 of the TEG on one wafer. The map data is stored in a mass storage device, for example.

[0029] In step 2, the σ value is obtained. The σ value is specified, for example, by a keyboard or other input device. Once the σ value is specified, the probability value is determined. Probability value data 38 is generated. The probability value data is stored, for example, in temporary storage device 25.

[0030] In step S3, the first Mahalanobis distance calculation unit 22 calculates a three-dimensional variance-covariance matrix based on the threshold voltages Vtpd of pMOSFETs 12a and 13a, Vtpu of nMOSFETs 12b and 13b, and Vtpg of nMOSFETs 14 and 15. The threshold voltage dataset (Vtpd, Vtpu, Vtpg) is acquired from the measured value dataset 37 of the map data. The first Mahalanobis distance calculation unit 22 generates the first matrix data 24. The first matrix data 24 is stored in the temporary storage device 25.

[0031] In step S4, the first Mahalanobis distance calculation unit 22 calculates the three-dimensional Mahalanobis distance based on the three-dimensional variance-covariance matrix. As shown in Figure 5, an equiprobability ellipsoid 43 is identified in the three-dimensional space of the three-dimensional coordinate system according to the calculated Mahalanobis distance. The size of the equiprobability ellipsoid is determined by the probability value data 38. The first Mahalanobis distance calculation unit 22 generates the first equiprobability data 26. The first equiprobability data 26 is stored in the temporary storage device 25.

[0032] In step S5, the first Mahalanobis distance calculation unit 22 extracts the equiprobability datasets 27 (Vtpd, Vtpu, Vtpg) present on the surface of the equiprobability ellipsoid. The number n of the equiprobability datasets 27 can be set arbitrarily. For example, as shown in Figure 6, the density of the equiprobability datasets 27 selected on the surface of the equiprobability ellipsoid 43 should be set according to the vertices FF (fast-fast), SS (slow-slow), FS (fast-slow), and SF (slow-fast) of the corner model. The first Mahalanobis distance calculation unit 22 generates the equiprobability datasets 27. The equiprobability datasets 27 are stored in the temporary storage device 25.

[0033] In step S6, the second Mahalanobis distance calculation unit 23 calculates a two-dimensional variance-covariance matrix for each pMOSFET 12a, 13a, nMOSFET 12b, 13b, and nMOSFET 14, 15 based on the threshold voltage Vt and drain current Id. In calculating the two-dimensional variance-covariance matrix, the second Mahalanobis distance calculation unit 23 assigns the threshold voltage Vt and drain current Id to the coordinate axes of the two-dimensional coordinate system, respectively. The threshold voltage and drain current dataset (Vt, Id) is acquired from the measured value dataset 37 of the map data. The second Mahalanobis distance calculation unit 23 generates the second matrix data 29. The second matrix data 29 is stored in the temporary storage device 25.

[0034] In step S7, the second Mahalanobis distance calculation unit 23 calculates the two-dimensional Mahalanobis distance based on the two-dimensional variance-covariance matrix. As shown in Figure 7, an equiprobability ellipse 45 is identified in the two-dimensional plane of the two-dimensional coordinate system according to the calculated two-dimensional Mahalanobis distance. The size of the equiprobability ellipse 45 is determined by the probability value data 38. The second Mahalanobis distance calculation unit 23 generates second equiprobability data 31. The second equiprobability data 31 is stored in the temporary storage device 25.

[0035] In step S8, the second Mahalanobis distance calculation unit 23 associates the drain current Id with the threshold voltage Vt based on the equiprobability ellipse 45. The threshold voltage Vt included in the equiprobability dataset 27 is identified on the major axis of the equiprobability ellipse 45. The drain current Id is identified at the intersection of the line perpendicular to the major axis and the equiprobability ellipse 45. For example, in a fast analysis, the intersection is selected in the region where the drain current Id is greater than the value of the major axis. In a slow analysis, the intersection is selected in the region where the drain current Id is smaller than the value of the major axis. The second Mahalanobis distance calculation unit 23 generates a target dataset 32(Vt,Id). The target dataset 32(Vt,Id) is stored in the temporary storage device 25.

[0036] In step S9, the SPICE model correction unit 33 calculates the offset value of the SPICE model. To calculate the offset value, the SPICE model correction unit 33 acquires the SPICE model 39. As shown in Figure 8, the SPICE model correction unit 33 identifies the difference between the threshold voltage Vt and drain current Id of the SPICE model 39 and the target dataset 32(Vt,Id). The SPICE model correction unit 33 generates offset data 35. The offset data 35 is stored in the temporary storage device 25. In step S10, the SPICE model correction unit 33 writes the offset value to the netlist of SPICE 34. For example, optimization of SPICE 34 may be used to calculate the offset value.

[0037] In step S11, SPICE34 calculates a margin for the operating range of, for example, SRAM, based on the netlist of the SPICE model. As shown in Figure 9, in calculating the margin, SPICE34 assigns the variation in the threshold voltage of the pMOS ΔVt and the variation in the threshold voltage of the nMOS ΔVt to the coordinate axes of a two-dimensional coordinate system. For each target dataset 32(Vt,Id), SPICE34 runs a simulation based on the netlist including the offset value. The simulation results (analysis point 46) are plotted at the boundaries of the σ intervals. From the analysis point 46, margins are read for the fast-fast standby current limit line, the slow-slow access speed limit and data retention limit line, the fast-slow read limit line, and the slow-fast write limit line. In this way, the boundary values ​​of the σ intervals are identified for each σ value. The yield is predicted.

[0038] When the three-dimensional Mahalanobis distance is calculated in a three-dimensional coordinate system based on the threshold voltages Vtpd of pMOSFETs 12a and 13a, Vtpu of nMOSFETs 12b and 13b, and Vtpg of nMOSFETs 14 and 15, the voltage values ​​of the threshold voltages Vtpd, Vtpu, and Vtpg are identified on the surface of the equiprobability ellipsoid 43 for each σ value in three-dimensional space. For each threshold voltage Vtpd of pMOSFETs 12a and 13a, Vtpu of nMOSFETs 12b and 13b, and Vtpg of nMOSFETs 14 and 15, voltage values ​​are extracted from the identified equiprobability ellipsoid 43. The extracted voltage values ​​indicate the boundary values ​​of the σ interval. When the two-dimensional Mahalanobis distance is calculated in a two-dimensional coordinate system based on the threshold voltage Vt and drain current Id for each pMOSFET 12a, 13a, nMOSFET 12b, 13b, and nMOSFET 14, 15, the voltage value of the threshold voltage Vt and the current value of the drain current Id are identified in the two-dimensional plane for each σ value by an equiprobability ellipse (line) 45. The current value is calculated from the equiprobability ellipse 45 according to the extracted voltage value (boundary value). The calculated current value indicates the boundary value of the σ interval. All boundary values ​​are accurately identified from the equiprobability ellipsoid 43 and the equiprobability ellipse 45. Therefore, manufacturing variations in the device characteristics of the SRAM cell 11 can be accurately identified while reducing computational resources. And, while reducing computational resources, SRAM yield analysis can be performed accurately.

[0039] In this embodiment, when calculating the equiprobability ellipsoid 43, the size of the equiprobability ellipsoid 43 is determined in three-dimensional space based on probability value data 38. The size of the equiprobability ellipsoid 43 is specified by the probability value data 38. The manufacturing variation of the device characteristics of the SRAM cell 11 is calculated for each probability value (σ value). Similarly, when calculating the equiprobability ellipse 45, the size of the equiprobability ellipse 45 is determined in a two-dimensional plane based on probability value data 38. The size of the equiprobability ellipse 45 is specified by the probability value data 38. The manufacturing variation of the device characteristics of the SRAM cell 11 is calculated for each probability value. [Explanation of symbols]

[0040] 11 SRAM cells 12a Pull-up transistor (pMOSFET) 12b Pull-down transistor (nMOSFET) 13a Pull-up transistor (pMOSFET) 13b Pull-down transistor (nMOSFET) 14. Pass-gate transistor (nMOSFET) 15. Pass-gate transistor (nMOSFET) 38 Probability Value Data 43 Equiprobability ellipsoid 45 Equal Probability Ellipse

Claims

1. A step of acquiring an actual value dataset including the threshold voltage and drain current of the pull-down transistors, the threshold voltage and drain current of the pull-up transistors, and the threshold voltage and drain current of the pass-gate transistors of an SRAM cell, The process involves assigning the threshold voltage of the pull-down transistor, the threshold voltage of the pull-up transistor, and the threshold voltage of the pass-gate transistor to the coordinate axes in three-dimensional space, calculating a three-dimensional variance-covariance matrix based on the threshold voltages included in the measured value dataset, and calculating the three-dimensional Mahalanobis distance of the measured value dataset. A step of identifying an equiprobability ellipsoid in the three-dimensional space according to a specified probability value, and extracting an equiprobability dataset present on the surface of the equiprobability ellipsoid, The process involves assigning a threshold voltage and drain current to the coordinate axes of a two-dimensional plane for each of the pull-down transistor, the pull-up transistor, and the pass-gate transistor, calculating a two-dimensional variance-covariance matrix based on the threshold voltage and drain current included in the measured value dataset, and calculating the two-dimensional Mahalanobis distance of the measured value dataset. A step of identifying an equiprobability ellipse in the two-dimensional plane according to a specified probability value, and identifying a drain current on the equiprobability ellipse corresponding to a threshold voltage included in the equiprobability dataset, The process involves calculating an offset value based on the threshold voltage included in the equiprobability dataset and the corresponding drain current identified on the equiprobability ellipse, and writing the calculated offset value to the netlist. A model generation method for SRAM analysis, comprising the following features.

2. The calculation of the equiprobability ellipsoid includes a step of acquiring probability value data that identifies the probability value that determines the size of the equiprobability ellipsoid in the three-dimensional space. A method for generating a model for SRAM analysis according to claim 1.

3. The calculation of the aforementioned equiprobability ellipse includes a step of acquiring probability value data that identifies the probability value that determines the size of the equiprobability ellipse within the two-dimensional plane. A method for generating a model for SRAM analysis according to claim 2.

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