Semiconductor equipment

Abstract

One of the objectives is to provide a semiconductor device with a new structure. 【Solution means】A first transistor having a first wiring, a second wiring, a third wiring, a fourth wiring, a first gate electrode, a first source electrode, and a first drain electrode, and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided on a substrate containing a semiconductor material, and the second transistor is configured to include an oxide semiconductor layer. One of the first gate electrode and the second source electrode or the second drain electrode is electrically connected. The first wiring and the first source electrode are electrically connected. The second wiring and the first drain electrode are electrically connected. The third wiring and the other of the second source electrode or the second drain electrode are electrically connected. The fourth wiring and the second gate electrode are electrically connected semiconductor device.

Description

[Technical Field]

[0001] The disclosed invention relates to a semiconductor device utilizing a semiconductor element and a method for manufacturing the same. ru. [Background technology]

[0002] Memory devices using semiconductor elements are volatile memory devices, meaning that the stored data is lost when the power supply is cut off. They are broadly classified into two types: memory devices and non-volatile memory devices that retain their contents even when the power supply is cut off. It can be done.

[0003] A typical example of a volatile memory device is DRAM (Dynamic Random Access Memory). DRAM has a memory (cess memory). DRAM selects transistors that make up the memory elements. By accumulating electric charge in the capacitor, it stores information.

[0004] Based on the principle described above, in DRAM, when information is read, the charge in the capacitor is lost. Therefore, a write operation is required each time data is read. Also, the memory element The transistors that make up the system have leakage current, and when no transistor is selected... Because charge flows out or into, the data retention period is short. Therefore, at a predetermined interval A rewrite operation (refresh operation) is required, and power consumption must be kept sufficiently low. This is difficult. Also, if the power supply is cut off, the contents of the memory will be lost, so long-term memory For retention, another storage device utilizing magnetic or optical materials would be required.

[0005] Another example of volatile memory is SRAM (Static Random Access Memory). SRAM has memory. SRAM uses circuits such as flip-flops to store information. Because it retains data, a refresh operation is unnecessary, which is an advantage over DRAM in this respect. However, because it uses circuits such as flip-flops, the cost per unit of memory capacity is high. There is a problem that it will become less effective. Also, there is the issue that if the power supply is cut off, the memory contents will be lost. Therefore, it is no different from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory is a type of non-volatile memory device. The transistor has a floating gate between its gate electrode and channel formation region, Because memory is stored by holding an electric charge in a floating gate, the data retention period is extremely short. It has the advantage of being extremely long-lasting (semi-permanent) and not requiring the refresh operations necessary for volatile memory devices. It has points (see, for example, Patent Document 1).

[0007] However, the gate insulating layer that makes up the memory element is affected by the tunnel current generated during writing. Because it deteriorates, the memory element will stop functioning after repeated writing. This problem can be avoided by, for example, equalizing the number of write cycles for each memory element. While this method is employed, achieving it requires complex peripheral circuits. However, even if such methods are adopted, the fundamental problem of lifespan will not be resolved. Therefore, flash memory is unsuitable for applications where information needs to be rewritten frequently.

[0008] Furthermore, in order to inject or remove charge from a floating gate, high A certain voltage is required. Furthermore, a relatively long time is required for charge injection or removal. However, there is also the problem that it is not easy to speed up writing and erasing. [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Application Publication No. 57-105889 [Overview of the Initiative] [Problems that the invention aims to solve]

[0010] In view of the above-mentioned problems, in one aspect of the disclosed invention, the stored contents are stored even when power is not supplied. To provide a new semiconductor device structure that allows for data retention and has no limit on the number of write cycles. One of its objectives is to achieve this. [Means for solving the problem]

[0011] One aspect of the present invention relates to a transistor formed using an oxide semiconductor and other materials This is a semiconductor device relating to a stacked structure with transistors formed using the following: A configuration can be adopted.

[0012] One aspect of the present invention is a first wiring (source line), a second wiring (bit line), and a third wiring (First signal line), fourth wiring (second signal line), first gate electrode, first source electrode , and a first transistor having a first drain electrode, and a second gate electrode, second A second transistor having a source electrode and a second drain electrode, and a first The transistor is mounted on a substrate containing semiconductor material, and the second transistor is an oxide semiconductor. It is composed of layers, a first gate electrode and a second source electrode or a second drain electrode. One side is electrically connected to the first wiring (source wire) and the first source electrode, The second wire (bit wire) and the first drain electrode are electrically connected. And the third wiring (first signal line) and the other of the second source electrode or the second drain electrode The fourth wire (second signal line) and the second gate electrode are electrically connected. It is a connected semiconductor device.

[0013] In the above, the first transistor is a channel forming device provided on a substrate containing a semiconductor material. A region, an impurity region provided so as to sandwich the channel formation region, and on the channel formation region A first gate insulating layer, a first gate electrode on the first gate insulating layer, an impurity region and an electrical It has a first source electrode and a first drain electrode that are connected to each other.

[0014] Furthermore, in the above, the second transistor is a second gate electrode on a substrate containing semiconductor material. The electrode, the second gate insulating layer on the second gate electrode, and the oxide semiconductor on the second gate insulating layer. A body layer and a second source electrode and a second drain electrode electrically connected to the oxide semiconductor layer. It has the following characteristics.

[0015] Furthermore, in the above, the substrate containing the semiconductor material may be a single-crystal semiconductor substrate or an SOI substrate. It is preferable to use a plate. In particular, silicon is preferred as the semiconductor material.

[0016] Furthermore, in the above, the oxide semiconductor layer is an In-Ga-Zn-O based oxide semiconductor material. It is preferable to include it. In particular, the oxide semiconductor layer contains crystals of In2Ga2ZnO7. The following is preferable. Furthermore, the hydrogen concentration of the oxide semiconductor layer is 5 × 10 19 atoms / cm 3 The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -13 A The following is preferable. Also, the off-current of the second transistor is 1 × 10⁻⁶. -20 A The following is preferable.

[0017] Furthermore, in the above, the second transistor is provided in a region that overlaps with the first transistor. It can be configured in this way.

[0018] In this specification, the terms "above" and "below" refer to the relative position of the constituent elements, not just "directly above". This does not necessarily mean "directly below". For example, "gate electricity on the gate insulating layer" If the expression is "pole," then excludes those that include other components between the gate insulating layer and the gate electrode. No. Also, the terms "upper" and "lower" are merely expressions used for the sake of explanation, and not particularly... Unless otherwise specified, this also includes the inverted versions.

[0019] Furthermore, in this specification, the terms "electrode" and "wiring" refer to these components functionally. It is not limited to this. For example, "electrode" can be used as part of "wiring". And the reverse is also true. Furthermore, the terms "electrode" and "wiring" refer to multiple "electrodes". This also includes cases where the "wiring" is formed as an integrated part.

[0020] Furthermore, the "source" and "drain" functions are used when employing transistors with different polarities. However, this can change when the direction of current changes during circuit operation. In this specification, the terms "source" and "drain" are interchangeable. It is assumed that this is possible.

[0021] In this specification, "electrically connected" means "having some kind of electrical effect." This includes cases where the connection is made via a means of "something that has some electrical effect." There are no particular restrictions as long as it enables the exchange of electrical signals between connected objects.

[0022] For example, "something that has some kind of electrical effect" includes not only electrodes and wiring, but also... Switching elements such as inverters, resistive elements, inductors, capacitors, and various other components. This includes elements that possess certain capabilities.

[0023] Furthermore, generally speaking, an "SOI substrate" is a substrate in which a silicon semiconductor layer is provided on an insulating surface. However, in this specification, a semiconductor layer made of a material other than silicon is provided on the insulating surface. It is used as a concept that also includes substrates with the constructed configuration. In other words, the semiconductor layer that the "SOI substrate" has This is not limited to silicon semiconductor layers. Also, the substrate in the "SOI substrate" is silicon This applies not only to semiconductor substrates such as wafers, but also to glass substrates, quartz substrates, sapphire substrates, and metal substrates. This includes any non-semiconductor substrate. In other words, a semiconductor on a conductive substrate or an insulating substrate having an insulating surface. The term "SOI substrate" broadly includes those having layers made of materials. Furthermore, in this specification... Furthermore, the term "semiconductor substrate" refers not only to a substrate made solely of semiconductor materials, but also to a substrate made of semiconductor materials. This term refers to all substrates, including those containing SOI. In other words, in this specification, "SOI substrate" is broadly referred to as "semi- It is included in "Conducting substrate". [Effects of the Invention]

[0024] In one aspect of the present invention, the lower part has a transistor made of a material other than an oxide semiconductor, and the upper A semiconductor device having a transistor made of an oxide semiconductor is provided.

[0025] Transistors using oxide semiconductors have extremely low off-currents, so we decided to use them. It is possible to retain memory content for an extremely long period of time. In other words, refresh function This eliminates the need for manual operation, or makes it possible to significantly reduce the frequency of refresh operations. Therefore, power consumption can be significantly reduced. Also, even if there is no power supply... It is possible to retain memory content over a long period of time.

[0026] Furthermore, it does not require high voltage for writing information, and there are no issues with component degradation. Because information is written by switching the inverter on and off, High-speed operation can also be easily achieved. Furthermore, by controlling the potential input to the transistor, information can be processed. Since it is rewritable, it also has the advantage of not requiring any action to erase the information. ru.

[0027] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0028] Thus, transistors using materials other than oxide semiconductors and transistors using oxide semiconductors By integrating a transistor, a semiconductor device with unprecedented features can be realized. It is possible. [Brief explanation of the drawing]

[0029] [Figure 1] Circuit diagram for explaining semiconductor devices [Figure 2] Cross-sectional and plan views illustrating a semiconductor device. [Figure 3]Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 4] Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 5] Cross-sectional diagram illustrating the manufacturing process of semiconductor devices. [Figure 6] Cross-sectional diagram for explaining semiconductor devices [Figure 7] Cross-sectional diagram for explaining semiconductor devices [Figure 8] Cross-sectional diagram for explaining semiconductor devices [Figure 9] Cross-sectional diagram for explaining semiconductor devices [Figure 10] A diagram illustrating electronic devices using semiconductor devices. [Figure 11] Longitudinal cross-section of an inverse staggered transistor using an oxide semiconductor. [Figure 12] Figure 11 shows the energy band diagram (schematic diagram) in the A-A' section. [Figure 13] (A) shows the state where a positive potential (+VG) is applied to the gate (GE1), and (B) shows the state where a negative potential (-VG) is applied to the gate (GE1). [Figure 14] This diagram shows the relationship between the vacuum level, the work function (φM) of metals, and the electron affinity (χ) of oxide semiconductors. [Figure 15] Circuit diagram for explaining semiconductor devices [Figure 16] Circuit diagram for explaining semiconductor devices [Figure 17] Circuit diagram for explaining semiconductor devices [Figure 18] Circuit diagram for explaining semiconductor devices [Figure 19] Circuit diagram for explaining semiconductor devices [Figure 20] Timing chart showing the relationship between electrical potentials [Figure 21] Circuit diagram for explaining semiconductor devices [Figure 22] Cross-sectional and plan views illustrating a semiconductor device. [Figure 23] Cross-sectional diagram for explaining semiconductor devices [Figure 24] Cross-sectional diagram for explaining semiconductor devices [Figure 25] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 26] Circuit diagram for characterizing transistors using oxide semiconductors [Figure 27] Timing chart for characterizing transistors using oxide semiconductors [Figure 28] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 29] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 30] A diagram showing the characteristics of a transistor using an oxide semiconductor. [Figure 31] Figure showing the results of the memory window width investigation. [Modes for carrying out the invention]

[0030] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is as follows The description is not limited to the present invention, and without departing from the spirit and scope of the present invention, its form and Those skilled in the art will readily understand that the details can be modified in various ways. Therefore, the present invention is as follows: The description of the embodiment shown is not to be limited to the content described therein.

[0031] Furthermore, the position, size, and scope of each component shown in the drawings are, for the sake of easier understanding, The actual location, size, and range may not be represented. Therefore, the drawings may not always show the actual location, size, or range. It is not limited to the indicated location, size, or range.

[0032] Furthermore, the ordinal numbers such as "1st," "2nd," and "3rd" used in this specification are intended to avoid confusion of constituent elements. It should be noted that this is added to avoid the issue and does not limit the number of occurrences.

[0033] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention are described below. This will be explained with reference to Figures 1 to 9.

[0034] <Circuit configuration of semiconductor device> Figure 1 shows an example of the circuit configuration of a semiconductor device. This semiconductor device is made of materials other than oxide semiconductors. Transistor 160 using a material (e.g., silicon) and transistor using an oxide semiconductor It is composed of Ta162. In the following, the semiconductor device shown in Figure 1 is referred to as a memory cell. It is sometimes called that.

[0035] Here, the gate electrode of transistor 160 and the source electrode or dot of transistor 162 It is electrically connected to one of the rain electrodes. Also, the first line The source wire (also called SL) and the source electrode of transistor 160 are electrically connected. The second line (also called the bit line BL) and the dray of transistor 160 The electrodes are electrically connected. And the third wire (3rd Line: 1st signal) The other side of the source electrode or drain electrode of transistor 162 (also called line S1) Electrically connected, the fourth wire (4th Line: also called the second signal line S2), and the transistor It is electrically connected to the gate electrode of the inverter 162.

[0036] Transistor 160, which uses materials other than oxide semiconductors, is a transistor that uses oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform readouts and other operations at high speed. Furthermore, it uses an oxide semiconductor transistor. Transistor 162 has the characteristic of having an extremely low off-current. Therefore, transistor 1 By turning off 62, the potential of the gate electrode of transistor 160 can be kept at that level for an extremely long time. It is possible to hold it over time. Also, with the oxide semiconductor transistor 162 This also has the advantage of making short-channel effects less likely to occur.

[0037] By taking advantage of the characteristic that the potential of the gate electrode can be maintained, information can be obtained as follows: It is possible to write, hold, and read data.

[0038] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential at which transistor 162 turns on is set to the ON state, and transistor 162 is turned ON. As a result, the potential of the third wire is applied to the gate electrode of transistor 160 (write (Including). Then, the potential of the fourth wire is set as the potential at which transistor 162 is in the off state. By turning off transistor 162, the gate electrode of transistor 160 The electric potential is maintained (held).

[0039] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The potential is maintained for a long time. For example, the potential of the gate electrode of transistor 160 is If the potential is such that transistor 160 is turned on, then transistor 160 will remain in the turned-on state for a long time. This will be maintained over time. Also, the potential of the gate electrode of transistor 160 If the potential is such that transistor 160 is in the off state, then transistor 160 will remain in the off state for a long time. It is retained over time.

[0040] Next, we will explain how to read the information. As mentioned above, the ON state of transistor 160 Alternatively, when the OFF state is maintained, a predetermined potential (low potential) is applied to the first wiring. When this happens, the potential of the second wiring differs depending on whether transistor 160 is on or off. It takes the following value. For example, when transistor 160 is ON, the potential of the first wiring is As a result, the potential of the second wiring decreases. Conversely, transistor 160 is In the "F" state, the potential of the second wiring does not change.

[0041] In this way, while the information is retained, the potential of the second wiring is compared with a predetermined potential. This allows us to extract the information.

[0042] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. To achieve this potential, transistor 162 is turned ON. This results in the potential of the third wiring. (A potential related to new information) is applied to the gate electrode of transistor 160. Then, The potential of the fourth wire is set to the potential at which transistor 162 is in the OFF state, By turning off 62, the new information is retained.

[0043] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. This eliminates the need for an erase operation, thus suppressing the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices will be achieved.

[0044] The off-current of the writing transistor 162, which uses an oxide semiconductor, is extremely small. The potential of the gate electrode of ZISTA 160 is maintained for a long time. Therefore, for example, The refresh operation required in previous DRAMs will become unnecessary, or the refresh operation will no longer be required. It is possible to reduce the frequency of production to an extremely low level (for example, once a month to once a year). Thus, the semiconductor device of the disclosed invention has the characteristics of a substantially non-volatile memory device. Yes, they are.

[0045] Furthermore, unlike conventional DRAMs, the semiconductor device of the disclosed invention allows information to be read out. Because the data is never lost, there is no need to rewrite the information each time it is read. In this way, Compared to DRAM, the frequency of information writing can be significantly reduced, thus reducing power consumption. It is possible to sufficiently suppress it.

[0046] Furthermore, the semiconductor device of the disclosed invention can directly generate information by writing information to the semiconductor device again. It is possible to rewrite information. For this reason, flash memory and other similar devices are necessary. This eliminates the need for an erase operation and suppresses the decrease in operating speed caused by the erase operation. In other words, high-speed operation of semiconductor devices is realized. Also, conventional floating gate type Because it does not require the high voltage needed for writing and erasing with transistors, semiconductors The power consumption of the device can be further reduced.

[0047] Furthermore, the semiconductor device according to the disclosed invention includes a writing transistor and a reading transistor It is sufficient to include at least st and , and requires 6 transistors per memory cell. Compared to SRAM and other technologies, it is possible to significantly reduce the area per memory cell. Therefore, semiconductor devices can be arranged at high density.

[0048] In a conventional floating gate transistor, during writing, charges move through the gate insulating film (tunnel insulating film), so deterioration of the gate insulating film (tunnel insulating film) was inevitable. However, in the memory cell according to one aspect of the present invention, since information is written by the switching operation of the writing transistor, it is possible to eliminate the deterioration of the gate insulating film, which has been a conventional problem. This means that there is no theoretical limit on the number of write cycles and the write endurance is extremely high. For example, even after writing 1 × 10 times (one billion times) or more, no deterioration is seen in the current-voltage characteristics. 10 9

[0049] The field-effect mobility of the writing transistor 162 using an oxide semiconductor is 3 cm / Vs or more and 250 cm 2 / Vs or less in the on state, preferably 5 cm 2 / Vs or more and 200 cm 2 / Vs or less, more preferably 10 cm / Vs or more and 150 cm[[ID=三十三]] 2 / Vs or less. Also, the transistor using an oxide semiconductor is made to have a subthreshold swing value (S value) of 0.1 V / dec. or less. By using such a transistor, the time required for writing information can be made sufficiently short. 2 2

[0050] Further, the channel length L of the writing transistor 162 using an oxide semiconductor is preferably 10 nm or more and 400 nm or less. By setting the channel size in this way, the transistor ​​​​​​​​​​​​This allows for various benefits, such as faster operation of the ZISTA, lower power consumption, and higher integration.

[0051] Furthermore, a transistor using crystalline silicon is suitable for the readout transistor 160. It is preferable to use single-crystal silicon. In particular, from the viewpoint of speeding up the read operation, it is preferable to use single-crystal silicon. It is better to use an n-channel type transistor. Such a single-crystal silicon transistor For example, it can be formed using bulk silicon (so-called silicon wafers). ru.

[0052] Note that the above explanation applies when using an n-type transistor (n-channel transistor). However, a p-type transistor can be used instead of an n-type transistor. That goes without saying.

[0053] <Planar and cross-sectional configurations of semiconductor devices> Figure 2 shows an example of the configuration of the semiconductor device described above. Figure 2(A) shows a cross-section of the semiconductor device. Figure 2(B) shows the planes of the semiconductor device. Here, Figure 2(A) is the same as Figure 2(B). This corresponds to the cross-section along lines A1-A2 and B1-B2. Figures 2(A) and 2(B) The semiconductor device shown in ) has a transistor 160 at the bottom that uses a material other than an oxide semiconductor. It has a transistor 162 made of oxide semiconductor on its upper part. Transistor 160 and transistor 162 are both described as n-type transistors. However, a p-type transistor may also be used. In particular, transistor 160 should be a p-type transistor. This is easy.

[0054] The transistor 160 is located in a channel formation region 11 provided on a substrate 100 containing semiconductor material. 6 and the impurity region 114 and high concentration impurity region provided so as to sandwich the channel formation region 116. The pure material region 120 (these are also simply called the impurity region) and the channel-forming region 11 A gate insulating layer 108 provided on 6, and a gate electrode provided on the gate insulating layer 108 Source electrode or drain electrode 130a that is electrically connected to 110 and the impurity region 114. It has a source electrode or a drain electrode 130b.

[0055] Here, a sidewall insulating layer 118 is provided on the side surface of the gate electrode 110. Furthermore, as shown in the cross-sectional view of the substrate 100, there is a region that does not overlap with the sidewall insulating layer 118. It has a high-concentration impurity region 120, and on the high-concentration impurity region 120 there is a metal compound region 1 24 exists. Also, on the substrate 100, element isolation and insulation surround the transistor 160. A layer 106 is provided, and an interlayer insulating layer 126 and cover the transistor 160. An interlayer insulating layer 128 is provided. Source electrode or drain electrode 130a, source electrode The electrode or drain electrode 130b is formed in the interlayer insulating layer 126 and the interlayer insulating layer 128. It is electrically connected to the metal compound region 124 through the opening. In other words, the source electrode. Alternatively, the drain electrode 130a, source electrode, or drain electrode 130b is a metal compound region. Electrically connected to the high-concentration impurity region 120 and the impurity region 114 via region 124. It is. Also, the gate electrode 110 has a source electrode or drain electrode 130a and a source electrode Electrode 130c, which is provided similarly to electrode or drain electrode 130b, is electrically connected. ru.

[0056] The transistor 162 has a gate electrode 136d provided on the interlayer insulating layer 128, and a gate A gate insulating layer 138 provided on electrode 136d, and a gate insulating layer 138 provided on An oxide semiconductor layer 140, and provided on the oxide semiconductor layer 140, and The electrically connected source electrode or drain electrode 142a, source electrode or drain It has an in electrode 142b.

[0057] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0058] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0059] Here, the oxide semiconductor layer 140 is purified to a high degree by sufficiently removing impurities such as hydrogen. It is desirable that the hydrogen concentration of the oxide semiconductor layer 140 be 5 × 10⁻¹⁰. Specifically, the hydrogen concentration of the oxide semiconductor layer 140 should be 5 × 10⁻¹⁰. 19 atoms / cm 3 The following is preferable: 5 x 10 18 atoms / cm 3 Below, more desired Mashikuha 5 x 10 17 atoms / cm 3 The following applies. This will result in a general silicon In silicon wafers (silicon wafers with trace amounts of impurity elements such as phosphorus and boron added), Rear concentration (1 x 10 14 / cm 3 (e.g., a sufficiently small carrier concentration value compared to the degree) For example, 1 x 10 12 / cm 3 Less than, or 1.45 × 10 10 / cm 3 (less than) In this way, the hydrogen concentration is sufficiently reduced, resulting in high purity, and the substance becomes intrinsically purified (type i) or essentially By using an intrinsically purified (i-type) oxide semiconductor, extremely excellent off-current characteristics are achieved. A transistor 162 can be obtained. For example, at room temperature (25°C) of transistor 162. The off-current (here, the value per unit channel width (1 μm)) is 10 zA / μm( 1 zA (zeptampere) is equal to 1 × 10⁻¹⁴ -21 A) Preferably, the following: Yes. Also, at 85℃, 100 zA / μm (1 × 10⁻⁶ -19 A / μm) or less, preferably is 10 zA / μm (1 × 10 -20 The hydrogen concentration is less than or equal to A / μm. A reduced, intrinsically or substantially intrinsically By reducing the off-current of the ZISTRA 162, a new semiconductor device configuration can be realized. This can be done. Furthermore, the hydrogen concentration in the oxide semiconductor layer 140 mentioned above can be determined by secondary ion mass spectrometry. Measured using SIMS (Secondary Ion Mass Spectroscopy). That is what happened.

[0060] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0061] In other words, in the semiconductor device shown in Figure 2, the gate electrode 110 of transistor 160 and The source electrode or drain electrode 142a of the lampistor 162 is connected to electrode 130c, electrode 1 36c, electrode 150c, electrode 154c and electrode 150d are electrically connected. ru.

[0062] <Method for fabricating semiconductor devices> Next, we will describe an example of a method for manufacturing the above semiconductor device. Below, we will first explain the lower part The method for fabricating the transistor 160 will be explained with reference to Figure 3, and then the upper transistor The method for manufacturing Ta162 will be explained with reference to Figures 4 and 5.

[0063] <Method for fabricating the lower transistor> First, prepare a substrate 100 containing semiconductor material (see Figure 3(A)). The plate 100 can be a single-crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. Compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied. Here, we will use a single-crystal silicon substrate as the substrate 100 containing semiconductor material. One example will be provided.

[0064] A protective layer 102 is formed on the substrate 100, which serves as a mask for forming an element isolation insulating layer. (See Figure 3(A)). The protective layer 102 can be, for example, silicon oxide or silicon nitride. An insulating layer made of silicon nitride or similar material can be used. In order to control the threshold voltage of the transistor, an impurity is imparted to impart n-type conductivity. Monochemical elements or impurity elements that impart p-type conductivity may be added to the substrate 100. In the case of ricon, impurities that impart n-type conductivity include, for example, phosphorus and arsenic. This can be achieved. Furthermore, examples of impurities that impart p-type conductivity include boron and aluminum. Materials such as nium and gallium can be used.

[0065] Next, etching is performed using the protective layer 102 as a mask, and the material covered by the protective layer 102 is then... A portion of the substrate 100 in the area that is not present (exposed area) is removed. This separates the half A conductive region 104 is formed (see Figure 3(B)). Dry etching is used for this etching process. It is preferable to use an etching gas, but wet etching may also be used. The etching solution can be appropriately selected depending on the material to be etched.

[0066] Next, an insulating layer is formed to cover the semiconductor region 104, and the region superimposed on the semiconductor region 104 By selectively removing the insulating layer, an element isolation insulating layer 106 is formed (see Figure 3(B)). The insulating layer is formed using silicon oxide, silicon nitride, silicon nitride oxide, etc. Methods for removing the insulating layer include polishing treatments such as CMP and etching treatments. Either of these may be used. Note that after the formation of the semiconductor region 104, or after device isolation and insulation After the formation of layer 106, the protective layer 102 is removed.

[0067] Next, an insulating layer is formed on the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. ru.

[0068] The insulating layer will later become the gate insulating layer, and can be obtained using methods such as CVD or sputtering. Silicon oxide, silicon nitride, silicon nitride, hafnium oxide, aluminum oxide A single-layer or multi-layer structure of a film containing aluminum, tantalum oxide, etc. is preferable. By oxidizing and nitriding the surface of the semiconductor region 104 through lazma treatment or thermal oxidation treatment, The above insulating layer may be formed. High-density plasma treatment may be performed using, for example, He, Ar, Kr, Using noble gases such as Xe and mixed gases such as oxygen, nitrogen oxides, ammonia, nitrogen, and hydrogen This can be done. Furthermore, the thickness of the insulating layer is not particularly limited, but for example, 1 nm or more. It can be reduced to 0 nm or less.

[0069] The layer containing conductive material is made of metallic materials such as aluminum, copper, titanium, tantalum, and tungsten. It can be formed using semiconductor materials such as polycrystalline silicon containing conductive materials. A layer containing a conductive material may be formed using [a specific method]. The formation method is not particularly limited and may include vapor deposition, C [another specific method]. Various film deposition methods such as the VD method, sputtering method, and spin coating method can be used. In this embodiment, an example of forming a layer containing a conductive material using a metal material is described below. This shall be shown.

[0070] Subsequently, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 , forming the gate electrode 110 (see Figure 3(C)).

[0071] Next, an insulating layer 112 is formed to cover the gate electrode 110 (see Figure 3(C)). Then, half By adding phosphorus (P) or arsenic (As) to the conductive region 104, a shallow bonding depth with the substrate 100 is achieved. This forms an impurity region 114 (see Figure 3(C)). Note that this is an n-type transistor. Phosphorus or arsenic is added to form the transistor, but when forming a p-type transistor, You can add impurity elements such as boron (B) or aluminum (Al). The formation of region 114 results in channel formation below the gate insulating layer 108 of the semiconductor region 104. Region 116 is formed (see Figure 3(C)). Here, the concentration of the added impurities is set as appropriate. However, when semiconductor devices are miniaturized to a high degree, it is possible to increase the concentration. This is desirable. Also, here, the impurity region 114 is formed after the insulating layer 112 is formed. The process employs a method of forming an insulating layer 112 after forming an impurity region 114. That's also acceptable.

[0072] Next, the sidewall insulating layer 118 is formed (see Figure 3(D)). Layer 118 is formed to cover the insulating layer 112, and then an insulating layer is formed to provide high anisotropy to the insulating layer. By applying an etching process, it can be formed in a self-aligned manner. The insulating layer 112 is partially etched, and the upper surface of the gate electrode 110 and the impurity region 1 It's best to expose the top surface of part 14.

[0073] Next, to cover the gate electrode 110, impurity region 114, sidewall insulating layer 118, etc. Then, an insulating layer is formed. And in the region where the insulating layer is in contact with the impurity region 114, phosphorus ( By adding P or arsenic (As), a high-concentration impurity region 120 is formed (see Figure 3(E)). (Illuminate). After that, remove the above insulating layer, gate electrode 110, sidewall insulating layer 118, A metal layer 122 is formed to cover the high-concentration impurity region 120, etc. (See Figure 3(E)). The metal layer 122 is formed by various thin-film deposition methods such as vacuum deposition, sputtering, and spin coating. It can be formed using the semiconductor material that constitutes the semiconductor region 104. It is desirable to form this using a metallic material that reacts with the material to form a low-resistance metallic compound. Examples of such metallic materials include titanium, tantalum, tungsten, nickel, and cobalt. Examples include platinum, etc.

[0074] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. This results in high A metal compound region 124 is formed adjacent to the concentration impurity region 120 (see Figure 3(F)). Furthermore, when using polycrystalline silicon or the like as the gate electrode 110, A metal compound region will also be formed in the area that comes into contact with the metal layer 122.

[0075] As for the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but the chemical reaction involved in the formation of metal compounds is important. To improve controllability, it is desirable to use a method that enables very short heat treatment times. It appears that the above-mentioned metallic compound region is formed by the reaction between a metallic material and a semiconductor material. This is a region in which conductivity is sufficiently enhanced. This allows for a significant reduction in electrical resistance and improvement of the device characteristics. After forming region 124, the metal layer 122 is removed.

[0076] Next, an interlayer insulating layer 126 and an interlayer insulating layer are formed to cover each of the components formed by the above process. Forms 128 (see Figure 3(G)). Interlayer insulating layers 126 and 128 are formed of oxides Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tahnix oxide It can be formed using materials containing inorganic insulating materials such as tar. Also, polyimide, It is also possible to form it using organic insulating materials such as acrylic resin. It has a two-layer structure consisting of an interlayer insulating layer 126 and an interlayer insulating layer 128, but the configuration of the interlayer insulating layer is as follows Not limited. After the formation of the interlayer insulating layer 128, its surface may be treated with CMP or etching. It is desirable to flatten it out by doing so.

[0077] Subsequently, openings are formed in the interlayer insulating layers 126 and 128 that extend to the metal compound region 124. The opening is then fitted with a source electrode or drain electrode 130a, and a source electrode or drain Form electrode 130b (see Figure 3(H)). Source electrode or drain electrode 130a or The source electrode or drain electrode 130b is subjected to, for example, PVD or CVD in the region including the opening. After forming a conductive layer using methods such as etching and CMP, the upper It can be formed by removing a portion of the conductive layer.

[0078] Furthermore, a portion of the above conductive layer can be removed to form the source electrode or drain electrode 130a or source electrode. Alternatively, when forming the drain electrode 130b, the surface is processed to be flat. This is desirable. For example, after forming a thin titanium film or titanium nitride film in the region including the opening, When forming a tungsten film to fill an opening, subsequent CMP (Chemical Polishing) can cause problems. The necessary tungsten film, titanium film, titanium nitride film, etc., are removed, and the flatness of the surface is improved. This can improve the source electrode or drain electrode 130a, By planarizing the surface including the drain electrode 130b, in subsequent processes This makes it possible to form good electrodes, wiring, insulating layers, semiconductor layers, etc.

[0079] In this case, the source electrode or drain electrode 130 that comes into contact with the metal compound region 124 Although only a and the source electrode or drain electrode 130b are shown, in this process, The electrode that comes into contact with the electrode 110 (for example, electrode 130c in Figure 2) is then combined to form This can be achieved. Source electrode or drain electrode 130a, source electrode or drain There are no particular limitations on the material that can be used as electrode 130b; various conductive materials can be used. It can be used. For example, molybdenum, titanium, chromium, tantalum, tungsten, Conductive materials such as aluminum, copper, neodymium, and scandium can be used.

[0080] As a result, a transistor 160 is formed using a substrate 100 containing semiconductor material. After the above process, electrodes, wiring, insulating layers, etc. may be formed. Furthermore, by adopting a multilayer wiring structure consisting of a laminated structure of interlayer insulating layers and conductive layers, high We can provide a semiconductor device with integrated components.

[0081] <Method for fabricating the upper transistor> Next, using Figures 4 and 5, the process of fabricating the transistor 162 on the interlayer insulating layer 128 is described. The process will be explained. Figures 4 and 5 show various electrodes on the interlayer insulating layer 128 and the trap. This shows the manufacturing process for transistor 162, and is therefore located at the bottom of transistor 162. Details regarding transistor 160 and other components have been omitted.

[0082] First, the interlayer insulating layer 128, the source electrode or drain electrode 130a, the source electrode or drain An insulating layer 132 is formed on the rain electrode 130b and electrode 130c (see Figure 4(A)). The marginal layer 132 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide It can be formed using materials containing inorganic insulating materials such as ru.

[0083] Next, the source electrode or drain electrode 130a, source electrode or An opening is formed that extends to the drain electrode 130b and electrode 130c. An opening is also formed in the region where the gate electrode 136d is formed. A conductive layer 134 is formed to embed it (see Figure 4(B)). The above opening is made using a mask. It can be formed by methods such as etching. The mask is a photomask. It can be formed by methods such as exposure. Etching methods include wet etching. Either etching or dry etching can be used, but from the perspective of microfabrication, dry etching is preferable. It is preferable to use a chipping method. The conductive layer 134 is formed by methods such as PVD or CVD. This can be done using a film deposition method. Materials that can be used to form the conductive layer 134 include It is molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium Examples include conductive materials such as aluminum and scandium, as well as their alloys and compounds (e.g., nitrides). It can be done.

[0084] More specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and CV After forming a thin titanium nitride film using method D, a tungsten film was formed to embed it in the opening. A method can be applied to achieve this. Here, the titanium film formed by the PVD method is below Partial electrode (here, source electrode or drain electrode 130a, source electrode or drain electrode The oxide film on the surface of electrodes (such as electrode 130b and electrode 130c) is reduced, thereby lowering the contact resistance with the lower electrode. It has the function of causing [something]. Furthermore, the titanium nitride film that is formed afterward suppresses the diffusion of the conductive material. It has a barrier function that controls it. In addition, a barrier film made of titanium or titanium nitride is formed. Later, a copper film may be formed by a plating method.

[0085] After forming the conductive layer 134, the conductive layer 1 is formed using methods such as etching and CMP. Remove a portion of 34 to expose the insulating layer 132, and then remove electrode 136a, electrode 136b, electrode 1 36c, forming the gate electrode 136d (see Figure 4(C)). Note that the conductive layer 134 By removing a portion, electrodes 136a, 136b, 136c, and gate electrode 136d are formed. When doing so, it is desirable to process the surface so that it becomes flat. In this way, insulating layer 13 2. Planarize the surfaces of electrode 136a, electrode 136b, electrode 136c, and gate electrode 136d. This allows for the formation of good electrodes, wiring, insulating layers, semiconductor layers, etc., in subsequent processes. This becomes possible.

[0086] Next, insulating layer 132, electrode 136a, electrode 136b, electrode 136c, gate electrode 136d A gate insulating layer 138 is formed to cover it (see Figure 4(D)). Gate insulating layer 138 This can be formed using methods such as CVD or sputtering. Also, the gate insulating layer 138 is silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide nitride, aluminum oxide, oxide It is preferable to form the gate insulation to include hafnium, tantalum oxide, etc. Layer 138 may be a single-layer structure or a multi-layer structure. For example, as a raw material gas By plasma CVD using silane (SiH4), oxygen, and nitrogen, silicon oxide nitride is produced. A gate insulating layer 138 can be formed. The thickness of the gate insulating layer 138 is not particularly limited. However, it is not possible to set it to, for example, 10 nm to 500 nm. For example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less, and the first gate insulating It is preferable to laminate a second gate insulating layer with a thickness of 5 nm to 300 nm on the layer.

[0087] Furthermore, by removing impurities, the oxide semiconductor can be made i-type or substantially i-type (high Purified oxide semiconductors are extremely sensitive to interface states and interface charges, therefore When using oxide semiconductors like the one shown in the image for the oxide semiconductor layer, the interface with the gate insulating layer is important. Therefore, the gate insulating layer 138 in contact with the highly purified oxide semiconductor layer is made of high-grade material. This will require a change in quality.

[0088] For example, high-density plasma CVD using μ-wave (2.45 GHz) is a method that produces dense materials with high dielectric strength. It is suitable in that it can form a high-quality gate insulating layer 138. The contact between the conductor layer and the high-quality gate insulating layer reduces the interface state and improves the interface properties. Because it can be made into something like that.

[0089] Of course, if it can form a good insulating layer as a gate insulating layer, then high-purity material Even when using an oxide semiconductor layer, other methods such as sputtering and plasma CVD are used. The method can be applied. Furthermore, by heat treatment after formation, the film quality and oxide semiconductor layer can be modified. An insulating layer that modifies the interface properties may be applied. In any case, the gate insulating layer 138 The film quality is good, and the interface level density with the oxide semiconductor layer is reduced, resulting in a good interface. You just need to create something that can form a surface.

[0090] When impurities are present in an oxide semiconductor, stress such as a strong electric field or high temperature can cause them to... The bond between the impurity and the main component of the oxide semiconductor is broken, and the resulting unbonded bonds are at the threshold voltage. This induces a shift in (Vth).

[0091] To remove impurities from oxide semiconductors, especially impurities such as hydrogen and water, and as described above... By improving the interfacial characteristics with the insulating layer, it is possible to reduce stress such as strong electric fields and high temperatures. It is also possible to obtain a stable transistor.

[0092] Next, an oxide semiconductor layer is formed on the gate insulating layer 138, and etching is performed using a mask. The oxide semiconductor layer is processed by methods such as those described above to form island-shaped oxide semiconductor layers 140. (See Figure 4(E)).

[0093] Examples of oxide semiconductor layers include In-Ga-Zn-O, In-Sn-Zn-O, and In-A l-Zn-O series, Sn-Ga-Zn-O series, Al-Ga-Zn-O series, Sn-Al-Zn -O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O series, Sn- It is preferable to use an O-based or Zn-O-based oxide semiconductor layer, particularly an amorphous oxide semiconductor layer. In this embodiment, an In-Ga-Zn-O based oxide semiconductor film is deposited as the oxide semiconductor layer. An amorphous oxide semiconductor layer will be formed using a target by sputtering. Furthermore, by adding silicon to the amorphous oxide semiconductor layer, its crystallization is suppressed. Therefore, for example, a target containing 2% to 10% by weight of SiO2 can be used. A oxide semiconductor layer may be formed.

[0094] For example, an oxide semiconductor layer can be fabricated using the sputtering method. A zinc-based oxide semiconductor film deposition target can be used. A target for oxide semiconductor film deposition containing Ga and Zn (composition ratio: In2O3:G You can also use a ratio such as a2O3:ZnO=1:1:1 [mol ratio]. In addition, In In2O3:Ga2O3 is used as a target for depositing oxide semiconductor films containing Ga and Zn. :ZnO=1:1:2 [mol ratio], or In2O3:Ga2O3:ZnO=1:1: A target having a composition ratio of 4 [mol ratio] may also be used. The filling rate of the container is 90% to 100%, preferably 95% or more (for example, 99.9%). ) By using a target for oxide semiconductor film deposition with a high packing density, dense oxidation A semiconductor layer is formed.

[0095] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride is removed to about several ppm (preferably about several ppb). Preferably, it is a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride is removed to about several ppm (preferably about several ppb). For example, the concentration of impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride is removed to about several ppm (preferably about several ppb). It is preferable to use a high-purity gas in which the concentration of impurities such as hydrogen, water, a compound having a hydroxyl group, or a hydride is removed to about several ppm (preferably about several ppb). It is suitable.

[0096] When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage to the oxide semiconductor layer due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. When forming the oxide semiconductor layer, the substrate is held in a processing chamber maintained in a reduced pressure state, and the substrate temperature is set to 100°C or higher and 600°C or lower, preferably 200°C or higher and 400°C or lower. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage to the oxide semiconductor layer due to sputtering is reduced. Then, while removing the residual moisture in the processing chamber, a sputtering gas from which hydrogen and water have been removed is introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. By forming the oxide semiconductor layer while heating the substrate, the impurity concentration contained in the oxide semiconductor layer can be reduced. Also, damage to the oxide semiconductor layer due to sputtering is reduced. It can be reduced. Also, damage to the oxide semiconductor layer due to sputtering is reduced. [[ID=2"]] introduced, and an oxide semiconductor layer is formed using a metal oxide as a target. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. To remove the residual moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. For example, a cryopump, an ion pump, or a titanium sublimation pump can be used. Also, as an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. As an evacuation step, a turbo pump with a cold trap added may be used. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The film formation chamber evacuated using a cryopump, for example, in addition to a compound containing carbon atoms, compounds containing hydrogen atoms such as hydrogen atoms, water (H2O), etc. are evacuated, so that the concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced. The concentration of impurities contained in the oxide semiconductor layer formed in the film formation chamber can be reduced.

[0097] As formation conditions, for example, the distance between the substrate and the target is 100 mm, and the pressure is 0.6 ​Pa, DC power is 0.5 kW, the atmosphere is an oxygen (oxygen flow ratio 100%) atmosphere, and the following conditions can be applied. When using a pulsed DC power supply, the powdery substances (also called particles and dust) generated during film formation can be reduced, and the film thickness distribution can also be made smaller. Therefore, it is preferable. The thickness of the oxide semiconductor layer is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. Note that the appropriate thickness varies depending on the oxide semiconductor material to be applied, so the thickness may be appropriately selected according to the material used. Since it varies, the thickness may be appropriately selected according to the material used. Before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas and remove the dust adhering to the surface of the gate insulating layer 138. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, whereas in normal sputtering, ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used instead of the argon atmosphere.

[0098] For the etching of the oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can be used in combination. Set the etching conditions (etching gas, etching solution, etching time, temperature, etc.) appropriately according to the material so that the desired shape can be etched. By introducing argon gas to generate plasma and removing the dust adhering to the surface of the gate insulating layer 138, it is preferable. Here, reverse sputtering refers to a method of modifying the surface by colliding ions with the processing surface, while in normal sputtering, ions are collided with the sputtering target. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used instead of the argon atmosphere. Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, whereas in normal sputtering, ions are collided with the sputtering target. Conversely, it refers to a method of modifying the surface by colliding ions with the processing surface. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. may be used instead of the argon atmosphere. It is also possible to use a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. instead of the argon atmosphere.

[0099] But both can also be used in combination. Set the etching conditions (etching gas, etching solution, etching time, temperature, etc.) appropriately according to the material so that the desired shape can be etched. For the etching of the above oxide semiconductor layer, either dry etching or wet etching may be used. Of course, both can be used in combination. Set the etching conditions (etching gas, etching solution, etching time, temperature, etc.) appropriately according to the material so that the desired shape can be etched. It is also possible to use a nitrogen atmosphere, a helium atmosphere, an oxygen atmosphere, etc. instead of the argon atmosphere.

[0100] Etching gases used in dry etching include, for example, chlorine-containing gases (chlorine-based gases, For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride ( Examples include CCl4, etc. Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride) are used. Fluorine (CF4), sulfur fluoride (SF6), nitrogen fluoride (NF3), trifluoromethane (CHF) 3) etc.), hydrogen bromide (HBr), oxygen (O2), and these gases with helium (He) or Gases to which noble gases such as argone (Ar) have been added may also be used.

[0101] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. It can etch into the desired shape. Etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The power consumption, electrode temperature on the substrate, etc., should be set as appropriate.

[0102] Etching solutions used in wet etching include a solution of phosphoric acid, acetic acid, and nitric acid. You can use this. Alternatively, you may use ITO07N (manufactured by Kanto Chemical Co., Ltd.).

[0103] Next, it is desirable to perform a first heat treatment on the oxide semiconductor layer. This first heat treatment This allows for the dehydration or dehydrogenation of the oxide semiconductor layer. The temperature of the first heat treatment is The temperature should be between 300°C and 750°C, preferably above 400°C and below the substrate's strain point. For example, The substrate is introduced into an electric furnace using a resistance heating element, and the oxide semiconductor layer 140 is exposed to a nitrogen atmosphere. A heat treatment is performed at 450°C under atmospheric pressure for 1 hour. During this time, the oxide semiconductor layer 140 is exposed to the atmosphere. Avoid contact and prevent re - mixing of water and hydrogen.

[0104] Note that the heat treatment apparatus is not limited to an electric furnace, and it may be an apparatus that heats the workpiece by heat conduction from a medium such as heated gas, or by thermal radiation. For example, it may be an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus. An LRTA apparatus is an apparatus that heats the workpiece by radiation of light (electromagnetic wave) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high - pressure sodium lamps, high - pressure mercury lamps, etc. A GRTA apparatus is an apparatus that performs heat treatment using high - temperature gas. As the gas, noble gases such as argon, or inert gases such as nitrogen that do not react with the workpiece during heat treatment are used.

[0105] For example, as the first heat treatment, a GRTA treatment can be performed in which a substrate is introduced into an inert gas heated to a high temperature of 650 °C to 700 °C, heated for several minutes, and then the substrate is taken out from the inert gas. Using GRTA treatment enables high - temperature heat treatment in a short time. Also, since it is a short - time heat treatment, it can be applied even under temperature conditions exceeding the distortion point of the substrate.

[0106] Note that the first heat treatment is preferably performed in an atmosphere mainly composed of nitrogen or noble gases (helium, neon, argon, etc.) and free of water, hydrogen, etc. For example, the purity of nitrogen or noble gases such as helium, neon, argon, etc. introduced into the heat treatment apparatus is

[0107] 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e.) The impurity concentration shall be 1 ppm or less, preferably 0.1 ppm or less.

[0107] Depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize. Furthermore, it may be microcrystalline or polycrystalline. For example, the crystallinity rate may be 90% or more, or 80%. In some cases, a microcrystalline oxide semiconductor layer of % or more may be formed. Also, depending on the conditions of the first heat treatment, Depending on the material of the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer that does not contain crystalline components. There are also combinations.

[0108] Furthermore, microcrystals (with a particle size of 1 nm or less) can be placed on amorphous oxide semiconductors (for example, on the surface of an oxide semiconductor layer). The oxide semiconductor layer will have a mixture of elements smaller than 20 nm (typically between 2 nm and 4 nm). In some cases, it may be the case.

[0109] Furthermore, by arranging microcrystals within the amorphous region, the electrical properties of the oxide semiconductor layer can be altered. It is also possible to do so. For example, In-Ga-Zn-O-based oxide semiconductor film deposition targets When forming an oxide semiconductor layer using a net, electrically anisotropic In2Ga2Z By forming microcrystalline regions with oriented nO7 crystal grains, the electrical properties of the oxide semiconductor layer are altered. It can be transformed.

[0110] More specifically, for example, if the c-axis of In2Ga2ZnO7 is perpendicular to the surface of the oxide semiconductor layer By orienting the material in a specific direction, the conductivity in the direction parallel to the surface of the oxide semiconductor layer is improved. This allows for improved insulation in the direction perpendicular to the surface of the oxide semiconductor layer. These microcrystalline regions have the function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer. It has.

[0111] Furthermore, the oxide semiconductor layer having the above-mentioned microcrystalline portion is an oxide semiconductor layer obtained by GRTA treatment. It can be formed by heating. Also, the Zn content is greater than the In or Ga content. By using a smaller sputtering target, it is possible to form the material more favorably.

[0112] The first heat treatment of the oxide semiconductor layer 140 involves processing it into island-shaped oxide semiconductor layers 140. This can also be done on the previous oxide semiconductor layer. In that case, after the first heat treatment, a heating device or The substrate is then removed and subjected to the photolithography process.

[0113] Furthermore, the first heat treatment described above has the effect of dehydrating and dehydrogenating the oxide semiconductor layer 140. Therefore, it can also be called a dehydration treatment, a dehydrogenation treatment, etc. Such dehydration treatment, de Hydrogenation treatment involves, after the formation of the oxide semiconductor layer, placing a source electrode or a dot on the oxide semiconductor layer 140. After stacking the rain electrodes, a protective insulating layer is formed on the source electrode or drain electrode. This can be done at times such as, and also, such dehydration treatment, dewatering The grading process can be performed multiple times, not just once.

[0114] Next, the source electrode or drain electrode 142a is brought into contact with the oxide semiconductor layer 140. A source electrode or drain electrode 142b is formed (see Figure 4(F)). The drain electrode 142a, the source electrode or drain electrode 142b are oxide semiconductor layer 1 After forming a conductive layer to cover 40, selectively etch the conductive layer by It can be formed.

[0115] The conductive layer is produced using PVD methods such as sputtering, or CVD methods such as plasma CVD. It can be formed by [doing something]. Also, the conductive layer material can be aluminum, chromium, copper, Elements selected from tantalum, titanium, molybdenum, and tungsten, or the elements mentioned above, are used as components. Alloys such as manganese, magnesium, zirconium, and beryllium can be used. One or more materials selected from aluminum and thorium may be used. In addition to nium, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and Scandinavian Materials consisting of one or more elements selected from um may be used. The conductive layer is It may be a single-layer structure or a laminated structure of two or more layers. For example, a structure containing silicon. Aluminum film single layer structure, aluminum film with titanium film laminated on top of aluminum film, titanium Examples include a three-layer structure in which a film, an aluminum film, and a titanium film are stacked.

[0116] Here, the exposure used during mask formation for etching includes ultraviolet light, KrF laser light, and ArF Using laser light is preferable.

[0117] The channel length (L) of the transistor is the length between the lower end of the source electrode or drain electrode 142a and the lower end of the source electrode or drain electrode 142a. This is determined by the distance between the source electrode or the lower end of the drain electrode 142b. When exposure is performed with a channel length (L) of less than 25 nm, the range is from a few nanometers to several tens of nanometers. For the first time, using extremely short wavelength ultraviolet light, a mask shape Perform exposure. Ultra-ultraviolet exposure provides high resolution and a large depth of field. Therefore, later The channel length (L) of the formed transistor shall be between 10 nm and 1000 nm. This is also possible, and the operating speed of the circuit can be increased. Furthermore, because the off-current value is extremely small, This prevents increased power consumption.

[0118] Furthermore, when etching the conductive layer, care is taken to ensure that the oxide semiconductor layer 140 is not removed. Adjust the materials and etching conditions as appropriate. In this process, a portion of the oxide semiconductor layer 140 is etched, and grooves (recesses) are formed. ) can also form an oxide semiconductor layer having ).

[0119] Furthermore, between the oxide semiconductor layer 140 and the source electrode or drain electrode 142a, and the oxide semiconductor An oxide conductive layer is formed between the conductive layer 140 and the source electrode or drain electrode 142b. It may also be an oxide conductive layer and a source electrode or drain electrode 142a or source electrode or The metal layer for forming the drain electrode 142b is formed continuously (continuous deposition). It is possible. The oxide conductive layer can function as either a source region or a drain region. By providing a conductive oxide layer, the resistance of the source region or drain region can be reduced. This enables high-speed operation of transistors.

[0120] Furthermore, in order to reduce the number of masks used and the number of processes, exposure is performed in which transmitted light has multiple intensities. A resist mask is formed using a multi-gradation mask, and this is used for etching. The process may be carried out. A resist mask formed using a multi-gradation mask has multiple thicknesses. It takes on a stepped shape, and the shape can be further deformed by ashing, It can be used in multiple etching processes to process different patterns. In other words, one sheet A multi-gradation mask allows for registration masks that correspond to at least two different patterns. A cavity can be formed. Therefore, the number of exposure masks can be reduced, and the corresponding cavity can be formed. Since the trisography process can also be reduced, the process can be simplified.

[0121] Furthermore, after the above-mentioned process, plasma treatment is performed using gases such as N2O, N2, or Ar. It is preferable to perform the following: The plasma treatment will cause the surface of the exposed oxide semiconductor layer to Adhering water and other substances are removed. Additionally, plasma treatment is performed using a mixed gas of oxygen and argon. You may go.

[0122] Next, a protective insulating layer 14 that is in contact with a portion of the oxide semiconductor layer 140 without being exposed to the atmosphere. Form 4 (see Figure 4(G)).

[0123] The protective insulating layer 144 is formed by methods such as sputtering, which introduces impurities such as water and hydrogen into the protective insulating layer 144. It can be formed using appropriate methods that do not cause damage. Furthermore, its thickness should be 1 nm or more. Materials that can be used for the protective insulating layer 144 include silicon oxide, silicon nitride, and silicon oxide-nitride. Examples include silicon dioxide and silicon nitride. Furthermore, its structure can be a single layer or a multilayer structure. It is permissible to do so. The substrate temperature when forming the protective insulating layer 144 shall be between room temperature and 300°C. It is preferable that the atmosphere be a noble gas atmosphere (typically argon), an oxygen atmosphere, or a rare gas atmosphere. A mixed atmosphere of gas (typically argon) and oxygen is preferable.

[0124] If hydrogen is present in the protective insulating layer 144, the hydrogen may penetrate into the oxide semiconductor layer, and the hydrogen may... This can lead to oxygen abstraction in the oxide semiconductor layer, and the back channel side of the oxide semiconductor layer This can lead to a decrease in resistance and the formation of parasitic channels. Therefore, protective insulating layer 1 It is important to avoid using hydrogen in the formation process of 44, as it contains as little hydrogen as possible. That is the case.

[0125] Furthermore, it is preferable to form the protective insulating layer 144 while removing residual moisture in the processing chamber. The ion semiconductor layer 140 and the protective insulating layer 144 are designed to not contain hydrogen, hydroxyl groups, or water. That is the reason.

[0126] To remove residual moisture from the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, cryopumps, ion pumps, and titanium sublimation pumps can be used. It is preferable. Furthermore, as an exhaust method, a turbo pump with a cold trap is used. It is also acceptable. The deposition chamber, which has been evacuated using a cryopump, contains, for example, hydrogen atoms and water (H2 Because compounds containing hydrogen atoms, such as O), are removed, the protective insulation formed in the deposition chamber is The concentration of impurities in layer 144 can be reduced.

[0127] The sputtering gas used to form the protective insulating layer 144 contains hydrogen, water, and hydroxyl groups. The concentration of impurities such as compounds or hydrides is around a few ppm (preferably around a few ppb). It is preferable to use a high-purity gas that has been removed to this extent.

[0128] Next, a second heat treatment (preferably 20) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is desirable to perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). Next, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. After the second heat treatment, This can reduce variations in the electrical characteristics of the converter.

[0129] Furthermore, even if heat treatment is performed in air at temperatures between 100°C and 200°C for 1 hour to 30 hours Good. This heat treatment may be performed by heating while maintaining a constant heating temperature, or from room temperature to 100°C or higher. The process involves repeatedly raising the temperature to a heating temperature of 200°C or lower, and then lowering it from the heating temperature back to room temperature. This may be done. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the protective insulating layer. Performing heat treatment under reduced pressure can shorten the heating time. This process may be performed instead of the second heat treatment described above, or before or after the second heat treatment. stomach.

[0130] Next, an interlayer insulating layer 146 is formed on the protective insulating layer 144 (see Figure 5(A)). The marginal layer 146 can be formed using methods such as PVD or CVD. Silicon nitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide Formation of interlayer insulating layer 146 is possible using materials containing inorganic insulating materials such as ru. Afterward, it is desirable to planarize the surface using methods such as CMP or etching. It's nice.

[0131] Next, the interlayer insulating layer 146, the protective insulating layer 144, and the gate insulating layer 138 are treated with electrode 1 36a, electrode 136b, electrode 136c, source electrode or drain electrode 142a, source An opening is formed that reaches the electrode or drain electrode 142b, and the electrode is embedded in the opening. A conductive layer 148 is formed (see Figure 5(B)). The above opening is made by etching using a mask, etc. It can be formed by the following method. The mask can be formed by methods such as exposure using a photomask. Therefore, it is possible to form it. Etching methods include wet etching and dry etching. Either etching method can be used, but from the perspective of microfabrication, dry etching is recommended. The following is preferable. The conductive layer 148 is formed using a film deposition method such as PVD or CVD. This is possible. Materials that can be used to form the conductive layer 148 include molybdenum, cyanoacrylate, and cyanoacrylate. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Examples include conductive materials, their alloys, and compounds (such as nitrides).

[0132] Specifically, for example, a thin titanium film is formed in the region including the opening by the PVD method, and then the CVD method is applied. After forming a thin titanium nitride film, a tungsten film is formed to fill the opening. The following method can be applied. Here, the titanium film formed by the PVD method is the lower electric Electrodes (here, electrode 136a, electrode 136b, electrode 136c, source electrode or drain) The oxide film formed on the surface of electrode 142a, source electrode or drain electrode 142b) is reduced. It has the function of reducing contact resistance with the lower electrode. Furthermore, the titanium nitride that is subsequently formed The film has a barrier function that suppresses the diffusion of conductive materials. In addition, titanium and titanium nitride are used. After forming a barrier film using methods such as the above, a copper film may be formed by a plating method.

[0133] After forming the conductive layer 148, the conductive layer 148 is formed using methods such as etching and CMP. By removing a portion of it and exposing the interlayer insulating layer 146, electrodes 150a, 150b, and 1 50c, electrode 150d, and electrode 150e are formed (see Figure 5(C)). Note that the above conductive layer Remove a portion of 148 to obtain electrodes 150a, 150b, 150c, 150d, and When forming the 150e pole, it is desirable to process the surface so that it is flat. Sea urchin, interlayer insulating layer 146, electrode 150a, electrode 150b, electrode 150c, electrode 150d, By flattening the surface of electrode 150e, a good electrode, wiring, and insulation can be achieved in subsequent processes. This makes it possible to form marginal layers and other structures.

[0134] Furthermore, an insulating layer 152 is formed, and electrodes 150a, 150b, and 1 An opening is formed that extends to electrode 50c, electrode 150d, and electrode 150e, and the material is embedded in the opening. After forming a conductive layer, a portion of the conductive layer is removed using methods such as etching or CMP. , exposing the insulating layer 152, electrode 154a, electrode 154b, electrode 154c, electrode 154 Form d (see Figure 5(D)). This step is the same as when forming electrode 150a, etc. Since there is some information available, I will omit the details.

[0135] When transistor 162 is fabricated using the method described above, the hydrogen concentration of the oxide semiconductor layer 140 The degree is 5x10 19 atoms / cm 3 The following applies, and also the off-current of transistor 162. The hydrogen concentration becomes 100 zA / μm or less. By applying the oxide semiconductor layer 140, a transistor 162 with excellent characteristics can be obtained. This is possible. Furthermore, it has a transistor 160 at the bottom made of a material other than an oxide semiconductor, and the top To fabricate a semiconductor device with excellent properties having a transistor 162 made of oxide semiconductor in the part. It is possible.

[0136] Furthermore, as a semiconductor material that can be compared to oxide semiconductors, silicon carbide (for example, 4H) is a suitable example. There is -SiC). Oxide semiconductors and 4H-SiC have several things in common. RIA density is one example. The intrinsic carriers of oxide semiconductors at room temperature are 10 -7 / cm 3 degree It is estimated to be 6.7 × 10 in 4H-SiC. -11 / cm 3 Similar , an extremely low value. Intrinsic carrier density of silicon (1.4 × 10⁻⁶) 10 / cm 3 degree) In comparison, it becomes clear just how extraordinary its degree is.

[0137] Furthermore, the energy band gap of oxide semiconductors is 3.0~3.5eV, and 4H-S Since the energy bandgap of iC is 3.26 eV, it is a wide-bandgap semiconductor. In this respect, oxide semiconductors and silicon carbide have something in common.

[0138] On the other hand, there is a very significant difference between oxide semiconductors and silicon carbide. This is the process temperature. Silicon carbide generally requires heat treatment at 1500°C to 2000°C. Therefore, stacked structures with semiconductor elements using other semiconductor materials are difficult. This is because semiconductor substrates and semiconductor elements are destroyed. On the other hand, oxide semiconductors It is manufactured by heat treatment at 300°C to 500°C (below the glass transition temperature, with a maximum of approximately 700°C). It is possible to form an integrated circuit using other semiconductor materials, and then use an oxide semiconductor. This makes it possible to form semiconductor devices.

[0139] Furthermore, unlike with silicon carbide, it is possible to use substrates with low heat resistance, such as glass substrates. It has the advantage of not requiring high-temperature heat treatment, compared to silicon carbide. This has the advantage of significantly reducing energy costs.

[0140] Furthermore, although much research has been done on the physical properties of oxide semiconductors, the energy gap is It does not include the idea of ​​sufficiently reducing the localized energy level itself. In one aspect of the disclosed invention, By removing water and hydrogen, which can cause the presence of energy levels, from the oxide semiconductor, a highly purified oxide is achieved. To fabricate a semiconductor, the localized energy levels within the energy gap are significantly reduced. This is based on the idea that, through this, the manufacture of extremely superior industrial products can be achieved. It makes it possible.

[0141] Furthermore, it supplies oxygen to the unbonded metals that occur due to oxygen deficiency, and the oxygen vacancies By reducing localized energy levels, an even higher purity (type i) oxide semiconductor can be obtained. It is also possible to form an oxygen-rich oxide film in contact with the channel-forming region. It is possible to supply oxygen from the oxide film to reduce localized energy levels caused by oxygen vacancies. .

[0142] Defects in oxide semiconductors include shallow energy levels below the conduction band due to excess hydrogen, and deep levels due to oxygen deficiency. These are believed to be caused by energy levels, etc. In order to eliminate these defects, hydrogen is thoroughly removed. Remove the bacteria and ensure a sufficient oxygen supply.

[0143] <Conductivity mechanism of transistors using oxide semiconductors> Next, the conductivity mechanism of an oxide semiconductor transistor will be explained using Figures 11 to 14. Let me explain. Please note that the following explanation assumes an ideal scenario for the sake of ease of understanding.

[0144] Figure 11 is a cross-sectional view of an inverse stagger transistor using an oxide semiconductor. An oxide semiconductor layer (OS) is provided on the polar layer (GE1) via a gate insulating layer (GI). A source electrode (S) and a drain electrode (D) are provided above it.

[0145] Figures 12(A) and 12(B) show the energy band structure along A-A' in Figure 11. A schematic diagram is shown. Figure 12(A) shows the case where no voltage is applied to the gate electrode layer (V G =0), and No voltage is applied to either the drain electrode or the source electrode, or the same voltage is applied to both. This is the case (V S =V D = 0, or V S =V D Figure 12(B) shows the drain electrode. Positive voltage (V D When a voltage >0) is applied, the dashed line represents the case where no voltage is applied to the gate electrode layer (V G (=0), the solid line represents a positive voltage (V) across the gate electrode layer. G This shows the case when >0) is applied. If no voltage is applied to the polar layer, the high potential barrier causes oxide semiconductors to leak from the source electrode. No carriers (electrons) are injected into the body, indicating an off state where no current flows. On the other hand, the gate current... Applying a positive voltage to the polar layer lowers the potential barrier, resulting in an ON state where current flows.

[0146] Figures 13(A) and 13(B) show the energy band diagrams in the B-B' section of Figure 11. (Schematic diagram) is shown. Figure 13(A) shows a positive potential (V) in the gate electrode layer (GE1). G >0) In the given state, carriers (electrons) flow between the source electrode and the drain electrode. This shows the state. Also, Figure 13(B) shows a negative potential (V) on the gate electrode layer (GE1). G When <0) is applied, and the state is off (minority carriers do not flow), show.

[0147] Figure 14 shows the vacuum level and the work function of the metal (φ M ), Relationship of electron affinity (χ) of oxide semiconductors This indicates.

[0148] Metals are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are It is of type n, and its Fermi level (E f ) is the true Fermi located in the center of the band gap. Level (E i It is located away from the conduction band and closer to it. Note that in oxide semiconductors, hydrogen Some of them become donors and are known to be one of the factors that lead to n-type formation. Also, oxygen deficiency It is known that losses are one of the factors that contribute to the n-type transformation.

[0149] In contrast, the oxide semiconductor according to one aspect of the disclosed invention uses hydrogen, which is a factor in n-type formation, as an acid By removing elements from oxide semiconductors, the oxide semiconductor contains as few elements other than the main components (impurity elements) as possible. By purifying it to a high degree and removing oxygen deficiencies, it is made into true (type i), or true It is an oxide semiconductor that approaches the properties of a material. In other words, it is not made i-type by adding impurity elements. By removing impurities such as hydrogen and water, as well as oxygen deficiencies, as much as possible, high-purity type i (intrinsic) It is characterized by being a semiconductor or approaching it. This results in the Fermi level (E f ) is the true Fermi level (E i ) can be considered to be of a similar degree.

[0150] Band gap (E) of oxide semiconductors g The voltage is 3.15 eV, and the electron affinity (χ) is 4.3 eV. It is said to be V. The work function of titanium (Ti) that makes up the source electrode and drain electrode is It is approximately equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface... Therefore, a Schottky-type barrier is not formed for electrons.

[0151] Work function of metal (φ M When the electron affinity (χ) of the oxide semiconductor is equal to that of the semiconductor, the two come into contact. This yields an energy band diagram (schematic diagram) as shown in Figure 12(A).

[0152] In Figure 12(B), the black circles (●) represent electrons. When a positive potential is applied to the drain electrode... Electrons are injected into the oxide semiconductor, crossing the barrier (h), and flow towards the drain electrode. The height of the barrier (h) is determined by the gate voltage (V G It varies depending on the positive drain voltage. When a voltage is applied to the drain electrode, the barrier height in Figure 12(A) without voltage application is... Nawachi Band Gap (E g It becomes half of that, or lower.

[0153] At this time, as shown in Figure 13(A), electrons are in the gate insulating layer and the highly purified oxide semiconductor It moves near the interface with the body (the lowest, most energetically stable part of the oxide semiconductor).

[0154] Furthermore, as shown in Figure 13(B), when a negative potential is applied to the gate electrode (GE1), Since the holes, which are only a few carriers, are practically zero, the current will be extremely close to zero. .

[0155] For example, the off-current at room temperature (25°C) is 10 zA / μm (1 × 10⁻⁶). -20 A / μm ) or less, or 1 zA / μm (1 × 10⁻⁶ -21 It is less than A / μm, and therefore, sub A transistor with a threshold swing value (S value) of 0.1V / dec. can be obtained.

[0156] In this way, oxide semiconductors are manufactured in such a way that they contain as few impurities as possible other than the main components of the oxide semiconductor. By increasing the purity, the operation of the transistor can be improved.

[0157] <Variation> Figures 6 to 9 show modified configurations of the semiconductor device. In the following, the modified configurations are described as follows: This section describes a configuration of transistor 162 that differs from the one described above. The configuration of the Ta160 is the same as described above.

[0158] Figure 6 shows a gate electrode 136d located beneath an oxide semiconductor layer 140, with a source electrode or a gate electrode. The rain electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 14 The transistor 162 has a configuration in which it is in contact with the oxide semiconductor layer 140 on the lower surface of 0. An example is shown. Note that the planar structure can be modified as appropriate to correspond to the cross-section, so here, cross-section Only the surface will be shown.

[0159] A major difference between the configuration shown in Figure 6 and the configuration shown in Figure 2 is the source electrode or the drain electrode. Connection between 142a, the source electrode or drain electrode 142b, and the oxide semiconductor layer 140. There is a position there. In other words, in the configuration shown in Figure 2, on the upper surface of the oxide semiconductor layer 140 , source electrode or drain electrode 142a, or source electrode or drain electrode 142b In contrast to contact, in the configuration shown in Figure 6, on the lower surface of the oxide semiconductor layer 140, Contact with the source electrode or drain electrode 142a, or the source electrode or drain electrode 142b And, due to this difference in contact, the arrangement of other electrodes, insulating layers, etc. may differ. The details of each component are the same as in Figure 2.

[0160] Specifically, the gate electrode 136d provided on the interlayer insulating layer 128 and the gate electrode 136 A gate insulating layer 138 provided on d, and a source electric field provided on the gate insulating layer 138. A electrode or drain electrode 142a, a source electrode or drain electrode 142b, and a source electrode Alternatively, contacting the upper surface of the drain electrode 142a, source electrode, or drain electrode 142b It has an oxide semiconductor layer 140 and

[0161] Here, the gate electrode 136d is embedded in the insulating layer 132 formed on the interlayer insulating layer 128. It is provided so as to be inserted. Also, similar to the gate electrode 136d, the source electrode or Electrode 136a is in contact with drain electrode 130a, and is connected to source electrode or drain electrode 130b Electrode 136b is formed in contact with electrode 130c, and electrode 136c is formed in contact with electrode 130c. ru.

[0162] Furthermore, a protective layer is placed on top of the transistor 162 so as to be in contact with a portion of the oxide semiconductor layer 140. An insulating layer 144 is provided, and an interlayer insulating layer 146 is provided on the protective insulating layer 144. Here, the protective insulating layer 144 and the interlayer insulating layer 146 have a source electrode or drain. An opening is provided that reaches the source electrode 142a, or the drain electrode 142b. Furthermore, through the opening, electrodes 150d and 150e are connected to the source electrode or drain electrode. It is formed in contact with electrode 142a, source electrode or drain electrode 142b. Similar to pole 150d and electrode 150e, the gate insulating layer 138, protective insulating layer 144, and interlayer insulating layer Through the opening provided in layer 146, electrodes 136a, 136b, and 136c are in contact. Electrodes 150a, 150b, and 150c are formed.

[0163] Furthermore, an insulating layer 152 is provided on the interlayer insulating layer 146, and embedded in the insulating layer 152. Electrodes 154a, 154b, 154c, and 154d are provided so as to be inserted. Here, electrode 154a is in contact with electrode 150a, and electrode 154b is in contact with electrode 150 It is in contact with b, and electrode 154c is in contact with electrode 150c and electrode 150d, and electrode 1 Electrode 54d is in contact with electrode 150e.

[0164] Figure 7 shows an example of a configuration having a gate electrode 136d on an oxide semiconductor layer 140. Figure 7(A) shows the source electrode or drain electrode 142a, and the source electrode or drain The electrode 142b is in contact with the oxide semiconductor layer 140 on the lower surface of the oxide semiconductor layer 140. This is an example of such a configuration, and Figure 7(B) shows the source electrode or drain electrode 142a, and the source The electrode or drain electrode 142b is on the upper surface of the oxide semiconductor layer 140. This is an example of a configuration in which the conductor layer 140 is in contact with the conductor layer.

[0165] The main difference between the configurations shown in Figures 2 and 6 and the configuration shown in Figure 7 is that the oxide semiconductor layer 140 is placed on top of the oxide semiconductor layer 140. The point is that it has a gate electrode 136d. Also, the configuration shown in Figure 7(A) and Figure 7(B) The main difference in configuration is the source electrode or drain electrode 142a, or the source electrode or drain The rain electrode 142b is located on either the lower or upper surface of the oxide semiconductor layer 140. The point is whether or not they make contact. And due to these differences, other electrodes, insulation The arrangement of layers and other elements differs. The details of each component are the same as in Figure 2, etc.

[0166] Specifically, in Figure 7(A), the source electrode or drain is provided on the interlayer insulating layer 128. A source electrode 142a, a source electrode or drain electrode 142b, and a source electrode or drain Oxide semiconductor in contact with the upper surface of electrode 142a, source electrode, or drain electrode 142b Layer 140, gate insulating layer 138 provided on oxide semiconductor layer 140, and gate insulating layer It has a gate electrode 136d in a region that overlaps with the oxide semiconductor layer 140 on 138.

[0167] Furthermore, in Figure 7(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and the oxide Source electrode or drain electrode 1 provided so as to be in contact with the upper surface of the material semiconductor layer 140 42a, source electrode or drain electrode 142b, oxide semiconductor layer 140, source electrode Alternatively, provided on the drain electrode 142a and the source electrode or drain electrode 142b The gate insulating layer 138 is superimposed on the oxide semiconductor layer 140 on the gate insulating layer 138. It has a gate electrode 136d in the region.

[0168] In addition, in the configuration shown in Figure 7, some components can be omitted compared to the configuration shown in Figure 2, etc. There are (for example, electrode 150a and electrode 154a). In this case, the manufacturing process is simplified and This can also be obtained as a secondary effect. Of course, it is not essential in the configuration shown in Figure 2, etc. It goes without saying that some components can be omitted.

[0169] Figure 8 shows the case where the device size is relatively large, with a gate below the oxide semiconductor layer 140. This is an example of a configuration having electrode 136d. In this case, the requirements for surface flatness and coverage are Since the pressure is relatively gentle, wiring and electrodes are formed so as to be embedded in the insulating layer. It is not necessary. For example, by performing patterning after the formation of the conductive layer, the gate electrode 136 It is possible to form d, etc. Although not shown in the diagram here, transistor 160 It is possible to manufacture the same in the same way.

[0170] The main difference between the configuration shown in Figure 8(A) and the configuration shown in Figure 8(B) is the source electrode or drain. The in electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 140 The point is whether contact occurs on the lower surface or the upper surface. Due to these differences, the arrangement of other electrodes, insulating layers, etc., is different. The details of the constituent elements are the same as in Figure 2, etc.

[0171] Specifically, in Figure 8(A), the gate electrode 136d is provided on the interlayer insulating layer 128, A gate insulating layer 138 provided on the gate electrode 136d, and provided on the gate insulating layer 138 Source electrode or drain electrode 142a, source electrode or drain electrode 142 b, and source electrode or drain electrode 142a, source electrode or drain electrode 142b It has an oxide semiconductor layer 140 in contact with the upper surface of

[0172] Furthermore, in Figure 8(B), the gate electrode 136d provided on the interlayer insulating layer 128 and the gate A gate insulating layer 138 provided on electrode 136d, and a gate electrode on gate insulating layer 138. An oxide semiconductor layer 140 is provided in the region overlapping with 136d, and the oxide semiconductor layer 140 Source electrode or drain electrode 142a provided so as to be in contact with the upper surface, source electrode Alternatively, it has a drain electrode 142b.

[0173] Furthermore, even in the configuration shown in Figure 8, components can be omitted compared to the configuration shown in Figure 2, etc. This can sometimes happen. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0174] Figure 9 shows the case where the device size is relatively large, with a gate on the oxide semiconductor layer 140. This is an example of a configuration having electrode 136d. In this case as well, surface flatness and coverage The requirements are relatively lenient, so wiring and electrodes can be embedded in the insulating layer. It is not necessary to do so. For example, by performing patterning after the formation of the conductive layer, the gate electrode 1 It is possible to form 36d, etc. Although not shown in the diagram here, transistor 1 The same method can be used to manufacture the 60 as well.

[0175] The main difference between the configuration shown in Figure 9(A) and the configuration shown in Figure 9(B) is the source electrode or drain. The in electrode 142a, or the source electrode or drain electrode 142b, is located in the oxide semiconductor layer 140 The point is whether contact occurs on the lower surface or the upper surface. Due to these differences, the arrangement of other electrodes, insulating layers, etc., is different. The details of the constituent elements are the same as in Figure 2, etc.

[0176] Specifically, in Figure 9(A), the source electrode or drain is provided on the interlayer insulating layer 128. A source electrode 142a, a source electrode or drain electrode 142b, and a source electrode or drain Oxide semiconductor in contact with the upper surface of electrode 142a, source electrode, or drain electrode 142b Layer 140, source electrode or drain electrode 142a, source electrode or drain electrode 1 42b, a gate insulating layer 138 provided on the oxide semiconductor layer 140, and gate insulating layer 13 8 has a gate electrode 136d provided in a region that overlaps with the oxide semiconductor layer 140 on the above. ru.

[0177] Furthermore, in Figure 9(B), the oxide semiconductor layer 140 provided on the interlayer insulating layer 128 and the oxide Source electrode or drain electrode 1 provided so as to be in contact with the upper surface of the material semiconductor layer 140 42a, source electrode or drain electrode 142b, and source electrode or drain electrode 14 2a, source electrode or drain electrode 142b, a gate provided on the oxide semiconductor layer 140 A gate insulating layer 138 and an oxide semiconductor layer 140 on the gate insulating layer 138 are provided in the region where they overlap. It has a gate electrode 136d that is kicked.

[0178] Furthermore, even in the configuration shown in Figure 9, components can be omitted compared to the configuration shown in Figure 2, etc. This can sometimes happen. In this case as well, the benefit of simplifying the manufacturing process can be obtained.

[0179] As described above, one aspect of the disclosed invention realizes a semiconductor device with a new configuration. In this embodiment, transistors 160 and 162 are stacked to form the transistor. Although an example has been given, the configuration of the semiconductor device is not limited to this. In this configuration, the channel length directions of transistors 160 and 162 are perpendicular to each other. I have explained an example, but the positional relationship between transistor 160 and transistor 162 is not the same. It is not limited. Furthermore, by superimposing transistor 160 and transistor 162 It is permissible to set one up.

[0180] Furthermore, in this embodiment, for the sake of ease of understanding, the semiconductor device is the smallest memory unit (1 bit). As explained above, the configuration of semiconductor devices is not limited to this. Multiple semiconductor devices can be used. By connecting them appropriately, it is also possible to configure more advanced semiconductor devices. For example, the above semiconductor device By using multiple units, it is possible to configure NAND and NOR type semiconductor devices. The configuration is not limited to Figure 1 and can be changed as appropriate.

[0181] The semiconductor device according to this embodiment is extremely efficient due to the low off-current characteristics of the transistor 162. It is possible to retain information for a long period of time. In other words, it is required for DRAM, etc. Refresh operations are unnecessary, and power consumption can be reduced. Furthermore, it is virtually non-volatile. It can be used as a semiconductor device that generates electricity.

[0182] Furthermore, information is written through the switching operation of transistor 162, It does not require high voltage and there are no issues with component degradation. Furthermore, the on / off switching of the transistor... Therefore, since information is written to and erased, high-speed operation can be easily achieved. Because it is possible to directly rewrite the information by controlling the potential input to the transistor. Another advantage is that it eliminates the need for any action to erase the information.

[0183] Furthermore, transistors using materials other than oxide semiconductors are different from transistors using oxide semiconductors. Compared to standard, it allows for even faster operation, and by using this, the stored contents can be processed It is possible to perform reading at high speed.

[0184] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. They can be used together.

[0185] (Embodiment 2) In this embodiment, the configuration and manufacturing method of a semiconductor device according to another aspect of the disclosed invention are described below. This will be explained with reference to Figure 15.

[0186] Figure 15(A) shows an example of the circuit configuration of a semiconductor device. The difference from Figure 1 is the capacitive element 16 The presence or absence of 4. That is, in Figure 15(A), the source electrode of transistor 162 Or, one of the drain electrodes, one of the electrodes of the capacitive element 164, and the gate of the transistor 160 The electrode and the source are electrically connected. Also, the first line (source line) The source electrode of transistor 160 (also called BL) is electrically connected to the second wiring (2nd Line: also called bit line BL) and the drain electrode of transistor 160 are , electrically connected. Also, the third wiring (3rd Line: first signal line S1 and The other of the source electrode or drain electrode of transistor 162 (also called) is electrically connected. Next, the fourth wire (4th Line: also called the second signal line S2) and the transistor It is electrically connected to the gate electrode of 162. And the 5th wire (5th Li The other electrode of the capacitive element 164 is electrically connected to the word line (also called WL). In addition, Figure 15 shows that it is a transistor using an oxide semiconductor. The OS code is also attached to it.

[0187] Here, the transistor 162 is a transistor using the oxide semiconductor described above. Transistors using oxide semiconductors have the characteristic of having an extremely small off-current. Therefore, by turning off transistor 162, the gate of transistor 160 It is possible to maintain the potential of the electrode for an extremely long period of time. And, capacitive element Having 164 allows the charge applied to the gate electrode of transistor 160 to be retained. It becomes easier, and it also becomes easier to read the stored information.

[0188] Note that the transistor 160 is not particularly limited. From this perspective, for example, transistors using single-crystal silicon, switching It is preferable to use high-speed transistors.

[0189] In the semiconductor device shown in Figure 15(A), the potential of the gate electrode of transistor 160 can be maintained. By taking advantage of these characteristics, it is possible to write, store, and read information as follows: .

[0190] First, we will explain how to write and retain information. First, the potential of the fourth wire is... The potential is set so that transistor 162 is turned on, thereby turning on transistor 162. As a result, the potential of the third wiring is controlled by the gate electrode of transistor 160 and the capacitive element 1 It is given to 64. That is, a predetermined charge is given to the gate electrode of transistor 160. (to write). Here, two charges that give different potentials (hereinafter referred to as giving a low potential) Charge Q L Charge Q, which gives a high potential H (i.e.) one of the transistors 16 This is to be applied to the gate electrode of a 0 potential. Furthermore, three or more different potentials are applied. The memory capacity may be improved by applying a charge. Then, the potential of the fourth wiring is changed The potential is set so that the zista 162 is in the off state, thereby turning off the transistor 162. Therefore, the charge applied to the gate electrode of transistor 160 is retained (held).

[0191] Since the off-current of transistor 162 is extremely small, the gate electrode of transistor 160 The electric charge is retained for a long period of time.

[0192] Next, we will explain how to read the information. When a predetermined potential (constant potential) is applied to the first wiring... In this state, when the appropriate potential (readout potential) is applied to the fifth wiring, the gate of transistor 160 Depending on the amount of charge held in the electrode, the second wiring takes on a different potential. Generally, If transistor 160 is an n-channel type, then the Q value is applied to the gate electrode of transistor 160. H Given Apparent threshold V in this case th_H Q is the gate electrode of transistor 160. L but Apparent threshold V when given th_L This is because it will be lower. Here, The threshold voltage is the fifth voltage required to turn transistor 160 into the "on state". This refers to the potential of the wiring. Therefore, the potential of the fifth wiring is V th_H and V th_L By setting the potential V0 to the intermediate potential, the charge applied to the gate electrode of transistor 160 It is possible to determine Q. For example, in writing, H If given, the fifth wiring The potential is V0 (>V th_H ) In that case, transistor 160 will be in the "on state". Q L If given, the potential of the fifth wire is V0( <V th_L Even if that happens, The transistor 160 remains in the "off state". Therefore, we can observe the potential of the second wiring. Then, the stored information can be read.

[0193] Furthermore, when memory cells are arranged in an array, only the information of the desired memory cell is used. It is necessary to be able to read the information. In this way, the information of a predetermined memory cell is read, and If information from an external memory cell is not read, the number of memory cells that are not the target of the read operation will be read. For wiring 5, regardless of the gate electrode state, transistor 160 is in the "off state". A potential such that, that is, V th_H A smaller potential should be applied. Alternatively, the gate voltage... Regardless of the polarity, the potential at which transistor 160 is in the "on state" is V. th_L A higher potential should be applied to the fifth wire.

[0194] Next, we will explain how to rewrite information. Rewriting information involves writing the information as described above and This is done in the same way as holding. In other words, the potential of the fourth wire is set when transistor 162 is ON. The potential is set to such a state, and transistor 162 is turned on. This changes the potential of the third wiring. (The potential related to the new information) is applied to the gate electrode of transistor 160 and the capacitive element 164. It is then given. After that, the potential of the fourth wire is set to the potential at which transistor 162 turns off. By turning off transistor 162, the gate voltage of transistor 160 is turned off. The poles become charged with new information.

[0195] Thus, the semiconductor device relating to the disclosed invention directly generates information through subsequent writing. It is possible to rewrite the information. Therefore, it is necessary in flash memory and other applications. It eliminates the need to extract charge from the floating gate using high voltage, and the erase operation This can suppress the decrease in operating speed caused by this. In other words, high-speed operation of semiconductor devices is possible. It will be revealed.

[0196] Note that the source or drain electrode of transistor 162 is connected to the gate of transistor 160. By being electrically connected to the electrode, it is used as a non-volatile memory element. It performs the same function as the floating gate of a ting-gate transistor. In the figure, the source electrode or drain electrode of transistor 162 and the gate of transistor 160. The part where the electrode is electrically connected is sometimes called the floating gate section (FG). When the transistor 162 is off, the floating gate section FG is embedded in the insulator. It can be seen that charge is held in the floating gate portion FG. Oxide semiconductor The off-current of transistor 162 using is due to the transistor formed by silicon semiconductors, etc. Because it is less than 1 / 100,000th of the current level, the floating is due to leakage in transistor 162. The dissipation of charge accumulated in the gate portion FG can be ignored. In other words, oxide semiconductors The transistor 162, which uses a body, allows for the retention of information even without a power supply. It is possible to create a sex memory device.

[0197] For example, the off-current of transistor 162 at room temperature (25°C) is 10 Hz (1 Hz (Zepto Amperes are 1 x 10 -21 A) The capacitance value of the capacitive element 164 is approximately 10 fF. In some cases, at least 10 4 Data can be retained for more than a second. However, it goes without saying that this will vary depending on the transistor characteristics and capacitance values.

[0198] Furthermore, in this case, the gate issue that has been pointed out in conventional floating-gate transistors The problem of degradation of the tunnel insulating film (tunnel insulating film) does not exist. In other words, the conventional problem is The goal was to eliminate the degradation of the gate insulating film when injecting electrons into the floating gate. This is possible. This means that, in principle, there is no limit to the number of write cycles. Furthermore, in conventional floating-gate transistors, the necessary processes for writing and erasing are required. The high voltage required is also unnecessary.

[0199] The semiconductor device shown in Figure 15(A) has elements such as transistors that make up the semiconductor device. It is possible to consider it as including resistance and capacitance, as shown in Figure 15(B). In Figure 15(B), transistor 160 and capacitive element 164 are resistors, respectively. It is assumed that it is composed including the capacity. R1 and C1 are, respectively, The resistance and capacitance values ​​of the capacitance element 164 are shown, and the resistance value R1 is the capacitance value of the capacitance element 164. This corresponds to the resistance due to the edge layer. Also, R2 and C2 are, respectively, transistor 160 These are the resistance and capacitance values, where the resistance value R2 is the gate value when transistor 160 is ON. The resistance value due to the insulating layer corresponds to the capacitance value C2, and the capacitance value C2 is the so-called gate capacitance (gate electrode and source Capacitance formed between the electrode or drain electrode, and the gate electrode and channel formation region. This corresponds to the capacity value of the capacity formed between the two.

[0200] The resistance between the source and drain electrodes when transistor 162 is in the off state (actual) If ROS (also called effective resistance) is defined as the gate leakage of transistor 162 is sufficiently small. In the given conditions, if R1 and R2 satisfy R1≧ROS and R2≧ROS, then the charge The retention period (which can also be called the information retention period) is mainly due to the operation of transistor 162. This will be determined by the current.

[0201] Conversely, if the above conditions are not met, the off-current of transistor 162 will be sufficiently small. However, it becomes difficult to ensure a sufficient retention period. Other than the off-current of transistor 162. The leakage current (for example, the leakage current that occurs between the source electrode and the gate electrode) is large. Therefore, the semiconductor device disclosed in this embodiment has the above-mentioned relationship It is desirable that the conditions be met.

[0202] On the other hand, it is desirable that C1 and C2 satisfy the relationship C1 ≥ C2. Therefore, when controlling the potential of the floating gate section FG by the fifth wiring (for example, read This is because it allows for keeping the potential fluctuation of the fifth wiring low during the disconnection process.

[0203] By satisfying the above-mentioned relationship, it is possible to realize a more suitable semiconductor device. R1 and R2 are the gate insulating layer of transistor 160 and the insulating layer of capacitive element 164. It is controlled by the same for C1 and C2. Therefore, the material and thickness of the gate insulating layer It is desirable to set appropriate values ​​such as 's' to satisfy the above-mentioned relationship.

[0204] In the semiconductor device shown in this embodiment, the floating gate portion FG is a flash It functions similarly to the floating gate of a floating-gate transistor in memory, etc. However, the floating gate portion FG of this embodiment is a flash memory, etc. It has characteristics that are fundamentally different from control gates. In flash memory, control gates Because the voltage applied to the cell is high, the potential of that cell affects the floating gate of the adjacent cell. To prevent this from extending to the tide, it becomes necessary to maintain a certain amount of spacing between cells. This is one of the factors that hinders the high integration of semiconductor devices. And this factor is high-voltage This stems from the fundamental principle of flash memory, which involves generating tunnel current by applying a boundary. It is.

[0205] Furthermore, due to the above principle of flash memory, the insulating film deteriorates, limiting the number of write cycles. Kai (10 4 ~10 5 Another problem arises (approximately a few times).

[0206] The semiconductor device according to the disclosed invention is a transistor switching device using an oxide semiconductor. Therefore, it operates without using the principle of charge injection by tunnel current as described above. That is, Unlike flash memory, it does not require a high electric field for charge injection. Because it is not necessary to consider the effect of the high electric field from the control gate on the tangent cell, Integration becomes easier.

[0207] Furthermore, because it does not use charge injection via tunnel current, there is a cause for memory cell degradation. No. In other words, it has higher durability and reliability compared to flash memory. .

[0208] Furthermore, the fact that a high electric field is not required and large peripheral circuits (such as boost converters) are not needed is also a plus. This is an advantage over Shumemori.

[0209] Note that the relative permittivity εr1 of the insulating layer constituting C1 and the relative permittivity εr of the insulating layer constituting C2 If 2 is to be different, then the area S1 of C1 and the area S2 of C2 must be 2·S2≧S1( It is easy to achieve C1 ≥ C2 while preferably satisfying S2 ≥ S1. For example, in C1, there is a film made of a high-k material such as hafnium oxide, This is a layered structure consisting of a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor. By adopting this, εr1 is set to 10 or more, preferably 15 or more, and in C2, silicon oxide By adopting this configuration, we can set εr² = 3 to 4. This enables high integration of the semiconductor device according to the disclosed invention.

[0210] Note that the above explanation applies when using an n-type transistor (n-channel transistor). However, a p-type transistor can be used instead of an n-type transistor. That goes without saying.

[0211] As described above, a semiconductor device according to one aspect of the disclosed invention has a source and a drain in the off state. A writing transistor with low leakage current (off-current) between transistors, said writing transistor Non-volatile reading transistors and capacitive elements using semiconductor materials different from those used in the DISTRA. It has memory cells.

[0212] The off-current of the writing transistor is 100 Hz (1 × 10⁻¹⁰) at room temperature (e.g., 25°C). -19 A) Preferably 10 zA (1 × 10 -20 A) More preferably, 1 zA(1×10 -21 A) Below. In typical silicon semiconductors, as mentioned above, the low o Although obtaining current is difficult, transformers obtained by processing oxide semiconductors under appropriate conditions This can be achieved in a zista. For this reason, oxide semiconductors are used as writing transistors. It is preferable to use a transistor that includes [a specific component / feature].

[0213] Furthermore, transistors using oxide semiconductors have a small subthreshold swing value (S value). Therefore, it is possible to achieve a sufficiently high switching speed even with relatively low mobility. Therefore, by using the transistor in question as a writing transistor, floating The rising edge of the write pulse supplied to the writing gate section FG can be made extremely steep. It can. Also, because the off-current is small, the amount of charge that needs to be held in the floating gate section FG is small. It is possible to reduce the amount. In other words, a transistor using an oxide semiconductor for writing By using it as a transistor, information can be rewritten at high speed.

[0214] As a readout transistor, a high-speed operating transistor is used to increase the readout speed. It is preferable to use a transistor. For example, a switching transistor can be used as the readout transistor. It is preferable to use transistors with a speed of 1 nanosecond or less.

[0215] Information is written to the memory cell by turning on the writing transistor. , one of the source or drain electrodes of the writing transistor and the electrode of the capacitive element One side is electrically connected to the gate electrode of the readout transistor. By supplying potential to the FG in the lute section, and then turning off the writing transistor, This is done by holding a predetermined amount of charge in the floating gate section FG. Because the off-current of the transistor used for charging is extremely small, it is supplied to the floating gate section FG. The charged charge is retained for a long time. If the off-current is, for example, substantially zero, conventionally The refresh operation required for the DRAM will become unnecessary, or the refresh operation will be eliminated. This makes it possible to reduce the frequency of this to an extremely low level (for example, once a month or once a year), and semiconductor The power consumption of the device can be significantly reduced.

[0216] Furthermore, it is possible to directly rewrite information by rewriting it to the memory cell. It is capable of this. Therefore, the erase operation required in flash memory and the like is unnecessary. This can suppress the decrease in operating speed caused by the erase operation. In other words, it can suppress the high speed of semiconductor devices. The operation is realized. In addition, writing and erasing can be done with conventional floating-gate transistors. Because it does not require the high voltage needed in the previous process, it further reduces the power consumption of semiconductor devices. This is possible. The voltage applied to the memory cell according to this embodiment (each terminal of the memory cell) The maximum value of the difference between the maximum and minimum potentials applied simultaneously is in two stages (1 bit). When writing information to a single memory cell, the voltage should be 5V or less, or 3V or less. It is possible.

[0217] The memory cell arranged in the semiconductor device according to the disclosed invention includes a writing transistor and It is sufficient to include at least a readout transistor, for example, one memory cell. Compared to SRAM, which requires 6 transistors per memory cell, the area per memory cell is It is possible to make it sufficiently small. In other words, it is possible to make memory cells densely in semiconductor devices. It can be placed.

[0218] Furthermore, in conventional floating-gate transistors, the gate insulating film (T) is used during writing. As electric charge moves through the tunnel insulating film, the gate insulating film (tunnel insulating film) deteriorates. This was unavoidable. However, in a memory cell according to one aspect of the present invention, writing Since information is written by the switching operation of the transistor, gate isolation is necessary. There is no problem with film degradation. This means that there is no theoretical limit to the number of write cycles, and it has rewrite endurance. This means that it is extremely high. For example, a memory cell according to one aspect of the present invention is 1 x 10 9 Even after more than 1 billion write cycles, degradation of the current-voltage characteristics is observed. do not have.

[0219] Furthermore, an oxide semiconductor transistor is used as the writing transistor for the memory cell. When using this, oxide semiconductors generally have a large energy gap (for example, In-Ga -In the case of Zn-O systems, the thermal excitation carriers are extremely few (3.0~3.5eV), for example For example, no degradation is observed in the current-voltage characteristics of the memory cell even in high-temperature environments of 150°C.

[0220] Transistors with the above-mentioned excellent characteristics are used as writing transistors for memory cells. By applying this method, it is possible to provide a semiconductor device with unprecedented features.

[0221] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0222] (Embodiment 3) In this embodiment, an application example of a semiconductor device according to one aspect of the disclosed invention is shown in Figure 16. This will be explained using Figure 21.

[0223] Figure 16 shows a schematic diagram of the semiconductor device according to this embodiment.

[0224] Figure 16 shows the semiconductor device shown in Figure 1 or Figure 15(A) (hereinafter also referred to as memory cell 1200). This is an example of a circuit diagram for a semiconductor device formed using multiple ( ) elements.

[0225] The semiconductor device shown in Figure 16 is a memory device in which multiple memory cells 1200 are arranged in a matrix. The recell array, the first drive circuit 1211, the second drive circuit 1212, and the third drive circuit The circuit 1213, the fourth drive circuit 1214, and the first drive circuit 1211 are electrically connected. Furthermore, there are multiple wires L1 and multiple wires L2 that are electrically connected to the second drive circuit 1212. And, multiple wires L3 electrically connected to the third drive circuit 1213, and the fourth drive circuit It has multiple wires L4 that are electrically connected to 1214.

[0226] As shown in Figure 16, each memory cell 1200 has wiring L1, wiring L2, wiring L3 and Wiring L4 is electrically connected. This allows each memory cell 1200 to be driven by the first drive circuit 1 211, second drive circuit 1212, third drive circuit 1213 and fourth drive circuit 121 The operation of the memory cell can be controlled using 4. Also, each memory cell 1200 Arranged in a matrix, each wiring L1, L2, L3, L4 in a grid pattern in the row or column direction. By providing this, the writing and reading operations of the semiconductor device are performed by the memory cell 120 This can also be done row by row or column by column.

[0227] Note that the memory cell 1200 shown in Figure 16 is part of the first drive circuit 1211 to the fourth drive circuit Each of the wires from 1214 is electrically connected, but the disclosed invention is related to this Not limited to. Multiple wires from any one or more drive circuits to the memory cell 120 It may be electrically connected to 0. Also, one or more memory cells 120 The configuration is such that one or more drive circuits are not electrically connected to point 0. You can.

[0228] Furthermore, in the semiconductor device shown in Figure 16, the first drive circuit 1211 and the second drive circuit 1212 The third drive circuit 1213 and the fourth drive circuit 1214 are provided independently of each other. The disclosed invention is not limited to the above. A drive circuit having any one or more functions It may be used. Furthermore, the drive circuit uses a single-crystal semiconductor to ensure sufficient operating speed. It is desirable to form it using a material. For example, bulk silicon (so-called silicon wick) It would be good to use something that uses (eh).

[0229] Next, we will explain a more specific example configuration.

[0230] Figures 17(A) and 17(B) show the semiconductor device (hereinafter referred to as memory cell) shown in Figure 15(A). This is an example of a circuit diagram of a semiconductor device formed using multiple 400s. (Also written as 400.) Figure 17 (A) is a so-called NAND type semiconductor device in which memory cells 400 are connected in series. This is a circuit diagram, and Figure 17(B) shows a so-called NOR type, where the memory cells 400 are connected in parallel. This is a circuit diagram of a semiconductor device.

[0231] The semiconductor device shown in Figure 17(A) has a source line SL, a bit line BL, a first signal line S1, and multiple other lines. It has one second signal line S2, multiple word lines WL, and multiple memory cells 400. Figure 17 In (A), the configuration has one source line SL and one bit line BL, It is not limited to this configuration, and may also be configured with multiple source lines SL and bit lines BL. stomach.

[0232] In each memory cell 400, the gate electrode of transistor 160 and transistor 162 One of the source or drain electrodes of the capacitor and one of the electrodes of the capacitive element 164 are electrically connected. They are connected. Also, the first signal line S1 and the source electrode or drain of transistor 162 are connected. The other electrode is electrically connected to the second signal line S2 and the gate of transistor 162. The electrodes are electrically connected. And the word line WL and the electrode of the capacitive element 164 The other is electrically connected.

[0233] Furthermore, the source electrode of the transistor 160 of the memory cell 400 is adjacent to the memory cell The memory cell 400 is electrically connected to the drain electrode of transistor 160. The drain electrode of transistor 160 is connected to the transistor of the adjacent memory cell 400. It is electrically connected to 160 source electrodes. However, it is connected in series to multiple memory cells. Of these, the drain of the transistor 160 of the memory cell 400 located at one end The electrodes are electrically connected to the bit line BL. Additionally, multiple memory cells are connected in series. Of these, the source power of the transistor 160 in the memory cell 400 located at the other end The poles are electrically connected to the source line SL.

[0234] The semiconductor device shown in Figure 17(A) performs line-by-line writing and reading operations. The write operation is performed as follows: A transient is applied to the second signal line S2 of the row to be written. A potential is applied to turn on transistor 162, and the transistor 162 of the row to be written is turned on. This sets the first signal line S to the gate electrode of transistor 160 in the specified row. A potential of 1 is applied, and a predetermined charge is applied to the gate electrode. In this way, Data can be written to the memory cells in the row below.

[0235] Furthermore, the reading operation is performed as follows: First, the word lines WL other than the line to be read. Regardless of the charge applied to the gate electrode of transistor 160, transistor 160 By applying a potential that turns it on, the transistors 160 other than those in the row being read are turned on. Then, the gate of transistor 160 is connected to the word line WL of the row to be read. The on or off state of transistor 160 is selected based on the charge present in the electrodes. A certain potential (readout potential) is applied. Then, a constant potential is applied to the source line SL, and the bit line The readout circuit (not shown) connected to BL is set to the operating state. Here, the source line Multiple transistors 160 between SL and bit line BL are ON except for the row being read out. Because of this state, the conductance between the source line SL and the bit line BL is read out. Determined by the state (on or off) of transistor 160 in the "U" row. The charge on the gate electrode of transistor 160 in the row that performs the discharge is due to the charge on the transistor Since the conductances are different, the potential of the bit line BL will take on different values ​​accordingly. This is achieved by reading the potential of bit line BL using a reading circuit, and then memoizing the specified line. Information can be read from the recell.

[0236] The semiconductor device shown in Figure 17(B) has a source line SL, a bit line BL, a first signal line S1, and a second signal line S1. It has multiple signal lines S2 and multiple word lines WL, and multiple memory cells 400. The gate electrode of each transistor 160 and the source electrode or drain of transistor 162. One of the in electrodes and one of the electrodes of the capacitive element 164 are electrically connected. The source line SL and the source electrode of transistor 160 are electrically connected, and the bit line BL The drain electrode of transistor 160 is electrically connected to the first signal line. S1 and the other of the source or drain electrode of transistor 162 are electrically connected. Therefore, the second signal line S2 and the gate electrode of transistor 162 are electrically connected. Furthermore, the word line WL and the other electrode of the capacitive element 164 are electrically connected.

[0237] The semiconductor device shown in Figure 17(B) performs line-by-line writing and reading operations. The writing operation is performed in the same manner as the semiconductor device shown in Figure 17(A) above. The operation is performed as follows: First, a transition is made to the word line WL other than the line to be read. Regardless of the charge applied to the gate electrode of transistor 160, transistor 160 will be in the off state. By applying such a potential, the transistors 160 other than those in the row being read are turned off. Then, the gate electrode of transistor 160 is connected to the word line WL of the row to be read. The charge determines the potential such that the on or off state of transistor 160 is selected. A readout potential is applied. Then, a constant potential is applied to the source line SL and connected to the bit line BL. The readout circuit (not shown) is set to the operating state. Here, the source line SL-bit The conductance between lines BL is determined by the state of transistor 160 in the row being read (on state). This is determined by the state (or off state) of the transistor 160 of the row that performs the readout. The potential of the bit line BL will take on different values ​​depending on the charge on the gate electrode. By reading the potential of bit line BL using a readout circuit, the memory cell of the specified row can be read. Information can be retrieved.

[0238] In the above, the amount of information to be held in each memory cell 400 was set to 1 bit, however The configuration of the memory device shown in the embodiment is not limited thereto. The gate electrode of transistor 160 It is also possible to increase the amount of information held by each memory cell 400 by providing a potential of 3 or more. For example, if we want to apply four different potentials to the gate electrode of transistor 160, Each memory cell can hold 2 bits of information.

[0239] Next, Figure 17 shows an example of a readout circuit that can be used in semiconductor devices, etc. Let's explain using 18.

[0240] Figure 18(A) shows a schematic of the readout circuit. This readout circuit consists of a transistor and a It has a balance amplifier circuit.

[0241] During reading, terminal A is connected to bit line BL, to which the memory cell to be read is connected. Furthermore, a bias potential Vbias is applied to the gate electrode of the transistor, and terminal A The potential is controlled.

[0242] The memory cell 400 exhibits different resistance values ​​depending on the data stored. Specifically, If the selected memory cell 400's transistor 160 is in the ON state, it will be in a low-resistance state. If transistor 160 of the selected memory cell 400 is in the off state, it will be in a high-resistance state. .

[0243] When the memory cell is in a high-resistance state, the potential at terminal A becomes higher than the reference potential Vref, and sense The amplifier outputs a potential corresponding to the potential at terminal A. On the other hand, when the memory cell is in a low-resistance state... When the potential at terminal A becomes lower than the reference potential Vref, the sense amplifier circuit reacts to the potential at terminal A. It outputs the corresponding potential.

[0244] In this way, by using a read circuit, data can be read from the memory cell. The readout circuit in this embodiment is just one example. Other circuits may be used. The readout circuit may have a precharge circuit. Instead of a reference potential Vref, a reference It is also possible to configure it so that the bit line BL is connected.

[0245] Figure 18(B) shows a differential sense amplifier, which is an example of a sense amplifier circuit. The amplifier has input terminals Vin(+) and Vin(-) and output terminal Vout, and Vin( The potential difference between Vin(+) and Vin(-) is amplified. If the voltage is higher, Vout outputs a High signal, and the potential of Vin(+) is higher than Vin(-). If the reading is also low, Vout outputs a Low signal. The differential sense amplifier reads out... When used in a circuit, one of Vin(+) and Vin(-) is connected to terminal A, and Vin(+) and The other side of Vin(-) is given a reference potential Vref.

[0246] Figure 18(C) shows a latch-type sense amplifier, which is an example of a sense amplifier circuit. The sense amplifier has input / output terminals V1 and V2, and input terminals for control signals Sp and Sn. First, set signal Sp to High and signal Sn to Low to cut off the power supply potential (Vdd). Then, apply potential V1in and V2in for comparison to V1 and V2 respectively. After that, when signal Sp is set to Low and signal Sn is set to High to supply the power supply potential (Vdd), if the potentials V1in and V2in for comparison are in the relationship V1in > V2in, the output of V1 will be High and the output of V2 will be Low. If they are in the relationship V1in < V2in, the output of V1 will be Low and the output of V2 will be High. Utilizing such a relationship, the difference between V1in and V2in can be amplified. When using this latch-type sense amplifier in a read circuit, one of V1 and V2 is connected to terminal A and the output terminal via a switch, and a reference potential Vref is applied to the other of V1 and V2.

[0247] FIG. 19 is an example of a circuit diagram of a semiconductor device formed using a plurality of the semiconductor devices shown in FIG. 15(A). The semiconductor device shown in FIG. 19 has a storage capacity of m × n bits.

[0248] The semiconductor device according to FIG. 19 includes m word lines WL, m second signal lines S2, n bit lines BL, n source lines SL, n first signal lines S1, and a plurality of memory cells 1100 arranged in a matrix of m (rows) × n (columns) (m and n are natural numbers), and peripheral circuits such as a first drive circuit 1111, a second drive circuit 1112, a third drive circuit 1113, and a fourth drive circuit 1114. Here, as the memory cell 1100, the configuration described in the previous embodiment (for example, the configuration shown in FIG. 15(A)) is applied. ​

[0249] In other words, each memory cell 1100 is connected to the first transistor 160, the second transistor 16 2. Each has a capacitive element 164. The gate electrode of the first transistor 160 and The source electrode or drain electrode of the second transistor 162 and the capacitive element 164 One side of the electrode is connected to the source wire SL and the source electrode of the first transistor 160. The bit line BL and the drain electrode of the first transistor 160 are connected. The first signal line S1 and the source electrode or drain electrode of the second transistor 162 On the other hand, the second signal line S2 and the gate electrode of the second transistor 162 are connected. The word line WL and the other electrode of the capacitive element 164 are connected.

[0250] Furthermore, the memory cell 1100 is connected in parallel between the source line SL and the bit line BL. Yes, there is. For example, memory cell 1100(i,j) in row i and column j (where i is an integer between 1 and m, and j is an integer between 1 and m). (where is an integer between 1 and n) is the source line SL(j), the bit line BL(j), and the first signal line S It is connected to 1(j), the word line WL(i), and the second signal line S2(i), respectively.

[0251] The source line SL and the bit line BL are connected to the first drive circuit 1111, and the first signal Line S1 is connected to the second drive circuit 1112, and the second signal line S2 is connected to the third drive The word line WL is connected to the fourth drive circuit 1114, and is connected to the drive circuit 1113. Here, the first drive circuit 1111, the second drive circuit 1112, and the third drive circuit are described. The drive circuit 1113 and the fourth drive circuit 1114 are provided independently, but the disclosure The explanation is not limited to this. A decoder having one or more of these functions may also be used. stomach.

[0252] Next, using the timing chart shown in Figure 20, the writing timing of the semiconductor device shown in Figure 19 is used. The operation and reading processes will be explained.

[0253] For simplicity, we will explain the operation of a 2x2 semiconductor device here. The disclosed inventions are not limited to these.

[0254] Figure 20 is a diagram illustrating the operation of the semiconductor device shown in Figure 19. In Figure 20, S1(1) and S1(2) are the potentials of the first signal line S1, S2(1) and S 2(2) is the potential of the second signal line S2, respectively, and BL(1) and BL(2) are respectively The potentials of Levitt line BL, WL(1) and WL(2) are as follows: the potential of Ward line WL, SL(1) ) and SL(2) correspond to the potential of the source line SL, respectively.

[0255] First, write to memory cells (1,1) and (1,2) in the first row, row 1 When reading from memory cells (1,1) and (1,2) of the eye Let me explain. In the following, the data written to memory cell (1,1) will be "1". This section explains the case where the data written to memory cells (1,2) is "0".

[0256] First, let's explain the writing process. During the writing period for the first line, the second message of the first line Apply a potential VH to line S2(1) and turn on the second transistor 162 in the first row. Also, apply 0V to the second signal line S2(2) in the second row, and the second transistor 1 in the second row Turn 62 off.

[0257] Next, the potential V2 is applied to the first signal line S1(1) in the first column, and to the first signal line S1(2) in the second column. Apply a potential of 0V.

[0258] As a result, a potential V2 is present at the floating gate portion FG of the memory cell (1,1), A voltage of 0V is applied to the floating gate FG of cell (1,2). Here, the potential V 2 is set to a potential higher than the threshold voltage of the first transistor 160. And the first row With the potential of signal line S2(1) set to 0V, the second transistor 162 in the first row is turned OFF. This action will terminate the writing process.

[0259] Note that the word lines WL(1) and WL(2) should be set to 0V. Also, the first signal line in the first column Before changing the potential of S1(1), set the second signal line S2(1) on the first line to 0V. After connection, the terminal connected to the word line WL is the control gate electrode, the first transistor 160 The source electrode of the first transistor is the source electrode, and the drain electrode of the second transistor 162 is the drain electrode. The threshold values ​​for the memory elements considered to be Vw0 for data "0", and for data "1", Vw1 is obtained. Here, the threshold value of the memory cell is the source of the first transistor 160. This refers to the voltage at the terminal connected to the word line WL, where the resistance between the electrode and the drain electrode changes. Let's assume that Vw0 > 0 > Vw1.

[0260] Next, we will explain the reading process. During the reading period of the first line, the word line W of the first line Apply 0V to L(1) and apply potential VL to the second word line WL(2). Potential VL is The potential is set to be lower than the threshold Vw1. If WL(1) is 0V, then in the first row, The first transistor 160 of the memory cell (1,2) that holds the value "0" is in the off state. The first transistor 160 of the memory cell (1,1) that holds data "1" is The state becomes "n". If WL(2) is the potential VL, then in the second row, the data "0", "1" Regardless of which memory cell is being held, the first transistor 160 is in the off state. This is the result.

[0261] Next, apply a potential of 0V to the first source line SL(1) and the second source line SL(2).

[0262] As a result, the bit line BL(1)-source line SL(1) is the first of the memory cells (1,1) Because the transistor is ON, the resistance is low, bit line BL(2) - source line SL( 2) During this time, the first transistor 160 of the memory cell (1,2) is in the off state, therefore This creates resistance. The readout circuit connected to bit line BL(1) and bit line BL(2) is bit The difference in resistance of the T-wire allows us to read the data.

[0263] Furthermore, 0V is applied to the second signal line S2(1) and a potential VL is applied to the second signal line S2(2). The second transistor 162 is kept completely off. Floating gate in the first row Since the potential of section FG is 0V or V2, by setting the second signal line S2(1) to 0V The second transistor 162 in the first row can all be turned off. On the other hand, the second row The potential of the floating gate section FG is such that when a potential VL is applied to the word line WL(2), The potential becomes lower than the potential immediately after writing. As a result, the second transistor 16 To prevent 2 from being in the ON state, the second signal line S2(2) is connected to the word line WL(2 ) is set to the same low potential. As a result, the second transistor 162 is completely turned off. It is possible.

[0264] Next, we will explain the output potential when using the circuit shown in Figure 21 as the readout circuit. The bit line BL(1) and source line SL(1) have low resistance, therefore the clocked inverter A low potential is input to the terminal, and output D(1) becomes High. Bit line BL(2) - Source Because the resistance between lines SL(2) is high, a high potential is input to the clocked inverter, and the output D(2) is Low.

[0265] The operating voltages are, for example, VDD=2V, V2=1.5V, VH=2V, and VL=-2V. It is possible.

[0266] As shown above in this embodiment, by providing multiple memory cells, the semiconductor device The memory capacity can be increased. Note that the number and arrangement of memory cells, the number and arrangement of wiring, and the drive The number and arrangement of the drive circuits can be designed as appropriate, so it is not limited to the above configuration. isn't it.

[0267] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0268] (Embodiment 4) This embodiment presents a different aspect of the disclosed invention from Embodiments 1 and 2. The configuration of the semiconductor device and its manufacturing method will be explained with reference to Figures 22 to 24. The transistor 260 described in this embodiment is the same as in the previous embodiment. In the circuit diagram, transistor 160 is represented as transistor 262 in the previous embodiment. In the circuit diagram, the transistor 162 is represented as the capacitive element 264 in the previous embodiment. It can be used as the capacitive element 164 in the circuit diagram.

[0269] <Cross-sectional and planar configurations of semiconductor devices> Figure 22 shows an example of the configuration of the semiconductor device described above. Figure 22(A) shows a cross-section of the semiconductor device. Figure 22(B) shows the plane of the semiconductor device. Here, Figure 22(A) is a figure This corresponds to the cross-sections at C1-C2 and D1-D2 in 22(B). Plan view of Figure 22(B) In the diagram, to avoid complexity, the source electrode or drain electrode 254, Some components, such as wiring 256, have been omitted. These are shown in Figures 22(A) and 22(B). The semiconductor device being constructed has a transistor 260 at the bottom that uses a semiconductor material other than an oxide semiconductor. It has a transistor 262 made of oxide semiconductor on top. Transistors using semiconductor materials other than conductors can easily operate at high speeds. On the other hand, oxides Transistors, which use semiconductors, can retain charge for extended periods due to their properties.

[0270] The above explanation assumes that all transistors are n-channel transistors. However, it goes without saying that p-channel transistors can be used. The technical essence of the invention is to use an oxide semiconductor in transistor 262 to hold information. Since the focus is on its application, it is not necessary to limit the specific configuration of the semiconductor device shown here to that which is not applicable. .

[0271] The semiconductor device shown in Figure 22 has a transistor 262 and a capacitive element 264, It is installed so as to overlap with sta260. Planar layout as shown in Figure 22(B) By adopting this method, high integration is possible. For example, if the minimum processing dimension is F, The area occupied by Morisel is 15F 2 ~25F 2 It is possible to do so.

[0272] One of the differences between the semiconductor device shown in Figure 22 and the semiconductor device shown in the previous embodiment is that The difference lies in the presence or absence of a sidewall insulating layer in the transistor 260. That is, as shown in Figure 22. The semiconductor device does not have a sidewall insulating layer. By not doing so, the impurity region 114 (see, for example, Figure 2) is not formed. In contrast, if a sidewall insulating layer is not provided, the results will be different from when a sidewall insulating layer is provided. In comparison, integration is easier. Also, compared to the case where a sidewall insulating layer is provided, The process can be simplified.

[0273] Another difference between the semiconductor device shown in Figure 22 and the semiconductor device shown in the previous embodiment is This is the interlayer insulating layer in transistor 260. In other words, it is the semiconductor device shown in Figure 22. Then, the hydrogen-containing interlayer insulating layer 225 is in contact with the metal compound region 224 of the transistor 260. By providing the hydrogen-containing interlayer insulating layer 225 in contact with the metal compound region 224, By supplying hydrogen to transistor 260, the characteristics of transistor 260 can be improved. It is possible. Such an interlayer insulating layer 225 can be formed, for example, by plasma CVD. This includes a silicon nitride layer containing hydrogen. Furthermore, as an interlayer insulating layer 226, hydrogen Applying a low-concentration insulating layer may degrade the characteristics of transistor 262. This makes it possible to prevent hydrogen from entering transistor 262. For example, silicon nitride formed by sputtering in the absence of hydrogen. There are layers, etc. By adopting this configuration, transistor 260 and transistor It is possible to significantly enhance the characteristics of the TA262. In Figure 22, the substrate 200 is In the substrate 100 of Embodiment 1, the element isolation insulating layer 206 is the element isolation insulating layer 1 of Embodiment 1 06 The gate insulating layer 208 is the gate insulating layer 108 of Embodiment 1, and the gate electrode 210 The gate electrode 110 of Embodiment 1, and the channel formation region 216 are channel formation regions of Embodiment 1 In the pulp formation region 116, the high-concentration impurity region 220 is the high-concentration impurity region 120 of Embodiment 1. In this embodiment, the metal compound region 224 corresponds to the metal compound region 124 of Embodiment 1, respectively. .

[0274] Another difference between the semiconductor device shown in Figure 22 and the semiconductor device shown in the previous embodiment is In transistor 262, insulating layer 243a and insulating layer 243b are oxide semiconductor layers Between 244 and the source electrode or drain electrode 242a, and between the oxide semiconductor layer 244 and the source electrode This point is located between the - electrode or the drain electrode 242b. In this way, insulation By providing layer 243a and insulating layer 243b, the gate electrode 248a and the source electric current The electrode or drain electrode 242a (or the gate electrode 248a and the source electrode or drain The so-called gate capacitance formed by the in electrode 242b) is reduced, and the operation of transistor 262 It can improve speed.

[0275] Furthermore, as in Embodiment 1, the lower transistor 260 and the upper transistor 262 are, By directly forming a source electrode or drain electrode 242a on the gate electrode 210, electricity They are connected by air. This configuration is compared to cases where electrodes and wiring are provided separately. In comparison, the degree of integration is improved. Furthermore, the manufacturing process is simplified.

[0276] In this embodiment, the above-mentioned differences are shown as an integrated configuration, but these differences A configuration having only one of the following is also acceptable.

[0277] <Methods for fabricating semiconductor devices> Next, an example of a method for manufacturing the above semiconductor device will be described. In the following, the lower transistor Figure 23 shows the process after forming transistor 260 and the method for fabricating the upper transistor 262. This will be explained with reference to Figure 24. The lower transistor 260 is shown in Embodiment 1. It can be manufactured using a method similar to the one described above. For details, please refer to the description in Embodiment 1. This can be taken into consideration. In this embodiment, it is assumed that a capacitive element 264 is provided. Furthermore, in this embodiment, an interlayer insulating layer 225 covers the transistor 260, interlayer insulating Three types of interlayer insulating layers are formed: layer 226 and interlayer insulating layer 228. In this embodiment, in the process of manufacturing the transistor 260, the source in Embodiment 1 is used. No electrode or drain electrode 130a, source electrode or drain electrode 130b is formed. However, source electrode or drain electrode 130a and source electrode or drain electrode 130 Even when b is not formed, we will refer to it as transistor 260 for convenience.

[0278] First, the lower transistor 260 is formed using the method shown in Embodiment 1, and then the transistor The part of the gate electrode 210 above the top surface of 260 is removed. This removal process involves CMP (Chemical Polishing). A polishing treatment such as mechanical polishing can be applied. This will make the upper surface of the gate electrode 210 The interlayer insulating layers 225, 226, and 228 are removed. By sufficiently flattening the surface during the polishing process, good electrodes and distribution can be achieved in subsequent processes. This makes it possible to form wires, insulating layers, semiconductor layers, and so on.

[0279] Next, on gate electrode 210, interlayer insulating layer 225, interlayer insulating layer 226, and interlayer insulating layer 228 A conductive layer is formed, and the conductive layer is selectively etched to form a source electrode or drain electrode. 242a forms the source electrode or drain electrode 242b (see Figure 23(A)). In this case, the source electrode or drain electrode 242a is directly connected to the gate electrode 210. It forms a sea urchin.

[0280] Form source electrode or drain electrode 242a, source electrode or drain electrode 242b The conductive layer for this purpose is the source electrode or drain electrode 142a shown in Embodiment 1, It can be formed using the same material as the base electrode or drain electrode 142b. Furthermore, the etching of the conductive layer is also performed using the same method as shown in Embodiment 1. This can be done. For details, please refer to the description of Embodiment 1.

[0281] Next, source electrode or drain electrode 242a, source electrode or drain electrode 242b An insulating layer is formed to cover the source electrode or An insulating layer 243a is placed on the drain electrode 242a, and on the source electrode or drain electrode 242b. An insulating layer 243b is formed on each of them (see Figure 23(B)).

[0282] By providing the insulating layer 243a and insulating layer 243b, the gate electrode 2 that will be formed later will be provided. 48a, source electrode or drain electrode 242a, and source electrode or drain It is possible to reduce the parasitic capacitance between electrode 242b and the electrode.

[0283] Next, source electrode or drain electrode 242a, source electrode or drain electrode 242b An oxide semiconductor layer 244 is formed to cover the oxide semiconductor layer 244, and a gate insulating layer 2 Forms 46 (see Figure 23(C)).

[0284] The oxide semiconductor layer 244 is made using the same materials and methods as the oxide semiconductor layer 140 described in Embodiment 1. It can be formed in this way. In addition, the oxide semiconductor layer 244 can be subjected to heat treatment (first heat treatment It is desirable to perform the following. For details, please refer to the description in Embodiment 1. ru.

[0285] The gate insulating layer 246 is formed using the same material and method as the gate insulating layer 138 shown in Embodiment 1. This can be achieved. Furthermore, after the formation of the gate insulating layer 246, under an inert gas atmosphere, Alternatively, it is preferable to perform heat treatment (second heat treatment) under an oxygen atmosphere. For details, see Implementation. The description of Form 1 can be taken into consideration.

[0286] Next, on the gate insulating layer 246, the region that will become the channel formation region of the transistor 262 A gate electrode 248a is formed in the region overlapping with the region, and the source electrode or drain electrode 242 Electrode 248b is formed in the region overlapping with a (see Figure 23(D)).

[0287] The gate electrode 248a and electrode 248b are formed after a conductive layer is formed on the gate insulating layer 246. The conductive layer can be formed by selectively etching the gate electric The conductive layers that will become electrode 248a and electrode 248b are produced by PVD methods including sputtering, It can be formed using CVD methods such as plasma CVD. For details, see source electrode. This is similar to the case of drain electrode 242a, and these descriptions can be taken into consideration.

[0288] Next, an interlayer insulating layer is placed on the gate insulating layer 246, the gate electrode 248a, and the electrode 248b. Forms the interlayer insulating layer 250 and the interlayer insulating layer 252 (see Figure 24(A)). The interlayer insulating layer 252 is the same as the protective insulating layer 144 and interlayer insulating layer 146 shown in Embodiment 1. It can be formed by the following materials and methods. For details, please refer to the description in Embodiment 1. It is possible.

[0289] Furthermore, it is desirable that the interlayer insulating layer 252 be formed so that its surface is flat. By forming an interlayer insulating layer 252 so that the surface is flat, the semiconductor device can be miniaturized. Even in combination, electrodes, wiring, etc., can be suitably formed on the interlayer insulating layer 252. This is for the purpose of flattening the interlayer insulating layer 252, such as CMP (chemical mechanical polishing). This can be done using the method.

[0290] Next, interlayer insulating layer 225, interlayer insulating layer 226, interlayer insulating layer 228, oxide semiconductor layer 244 The gate insulating layer 246, the interlayer insulating layer 250, and the interlayer insulating layer 252 are selectively etched. , forming an opening that extends to the metal compound region 224 of transistor 260 (Figure 24(B) (See reference). For etching, either dry etching or wet etching is used. While other methods are acceptable, from the perspective of miniaturization, dry etching is preferable.

[0291] Then, a source electrode or drain electrode 254 is formed so as to be embedded in the opening. Then, a wiring 256 is formed to connect to the source electrode or drain electrode 254 (Figure 24). (See (C)).

[0292] The source electrode or drain electrode 254 is subjected to, for example, PVD or CVD methods in the region including the opening. After forming a conductive layer using methods such as etching and CMP, the above It can be formed by removing a portion of the conductive layer. More specifically, for example, open A thin titanium film is formed in the area including the mouth using the PVD method, and then a thin titanium nitride film is formed using the CVD method. After forming, a method is applied to form a tungsten film so as to embed it in the opening. Yes, it is possible. Here, the titanium film formed by the PVD method is the oxide film (native oxide film) on the surface to be formed. It reduces (etc.) and reduces the contact resistance with the lower electrode (here, the metal compound region 224). It has the function of suppressing the diffusion of conductive materials. Furthermore, the titanium nitride film that is formed afterward suppresses the diffusion of conductive materials. It has a barrier function. Furthermore, after forming a barrier film made of titanium or titanium nitride, A copper film may be formed on it by a plating method.

[0293] After forming a conductive layer that contacts the source electrode or drain electrode 254, the wiring 256 The conductive layer can be formed by selective etching. The conductive layer is Formed using PVD methods such as sputtering, and CVD methods such as plasma CVD. This is possible. Details are the same as for the source electrode or drain electrode 242a, etc. ru.

[0294] As described above, a semiconductor having transistor 260, transistor 262 and capacitive element 264 The conductive device is completed.

[0295] The semiconductor device shown in this embodiment has a transistor 262 and a capacitive element 264, It has a configuration that is superimposed with the ZISTA 260, and the transistor 260 has a sidewall insulation It does not have a margin layer, and the source electrode or drain electrode 242a is directly on the gate electrode 210. High integration is possible due to the bonding process, etc. Furthermore, the manufacturing process has been simplified. It is being done.

[0296] Furthermore, the semiconductor device shown in this embodiment uses an insulating layer containing hydrogen as the interlayer insulating layer 225. By applying an insulating layer with a low hydrogen concentration as the interlayer insulating layer 226, the transient The characteristics of transistor 260 and transistor 262 have been improved. Also, the insulating layer 243a and By having an insulating layer 243b, the so-called gate capacitance is reduced, and transistor 262 The operating speed has improved.

[0297] The above-described features of this embodiment provide a semiconductor device with extremely excellent characteristics. This is possible.

[0298] The configurations and methods described in this embodiment are compatible with the configurations and methods described in other embodiments. They can be used in any combination.

[0299] (Embodiment 5) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment is described below. Let's explain using Figure 10. The semiconductor device obtained in the previous embodiment does not have a power supply. Even in such cases, it is possible to retain information. Furthermore, no degradation occurs due to writing and erasing. Furthermore, its operation is also high-speed. For this reason, a new configuration of electric device can be created using this semiconductor device. It is possible to provide sub-devices. Furthermore, the semiconductor device according to the above embodiment is integrated These components are then mounted on circuit boards and installed inside various electronic devices.

[0300] Figure 10(A) shows a notebook-type personal computer including a semiconductor device according to the above embodiment. It is a data system consisting of the main unit 301, the casing 302, the display unit 303, the keyboard 304, etc. It has been done.

[0301] Figure 10(B) shows a personal digital assistant (PDA) including a semiconductor device according to the previously described embodiment. The main unit 311 includes a display unit 313, an external interface 315, and operation buttons 314, etc. A stylus 312 is provided as an accessory for operation.

[0302] Figure 10(C) shows an example of an electronic paper including a semiconductor device according to the above embodiment, This shows the e-book 320. The e-book 320 is housed in two enclosures, enclosure 321 and enclosure 323. It is constructed such that the housing 321 and housing 323 are integrated by the shaft portion 337. The shaft portion 337 can be used as an axis for opening and closing operations. With this configuration, electronic books Book 320 can be used like a paper book.

[0303] The display unit 325 is incorporated into the housing 321, and the display unit 327 is incorporated into the housing 323. The display units 325 and 327 may be configured to display a continuation screen, or differently. It is also possible to configure the system to display a different screen. By configuring the system to display different screens, for example, Text is displayed on the right-hand display unit (display unit 325 in Figure 10(C)), and on the left-hand display unit (Figure 10 (C) allows an image to be displayed on the display unit 327).

[0304] Furthermore, Figure 10(C) shows an example in which the housing 321 is equipped with an operating section, etc. The body 321 is equipped with a power supply 331, operation keys 333, speaker 335, etc. Pages can be turned using -333. Note that the keyboard and port are located on the same surface as the display unit. The configuration may also include input devices, etc. Connection terminals (earphone jack, USB terminal, or AC adapter and USB cable, etc.) The configuration may also include terminals that can be connected to various cables, a recording medium insertion section, and so on. Furthermore, eBook 320 may be configured to also function as an electronic dictionary.

[0305] Furthermore, the e-book 320 may be configured to transmit and receive information wirelessly. It is also possible to configure the system to allow users to purchase and download desired book data from a sub-book server. It is possible.

[0306] Furthermore, electronic paper can be applied to any field that displays information. For example, in addition to ebooks, there are posters, advertisements on trains and other vehicles, and credit cards. This can be applied to displays on various types of cards, such as TCG cards.

[0307] Figure 10(D) shows a mobile phone including a semiconductor device according to the previous embodiment. The telephone consists of two housings, housing 340 and housing 341. Housing 341 is front Display panel 342, speaker 343, microphone 344, pointing device 3 It is equipped with 46, a camera lens 347, an external connection terminal 348, etc. Also, housing 340 This includes a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. It is equipped with it. Furthermore, the antenna is built into the casing 341.

[0308] The display panel 342 has a touch panel function, and the image displayed in Figure 10(D) is Multiple operation keys 345 are shown with dotted lines. Note that the mobile phone has a solar cell 34 A boost circuit is implemented to increase the voltage output from 9 to the voltage required for each circuit. Furthermore, in addition to the above configuration, the configuration will incorporate a contactless IC chip, a small recording device, etc. It's also possible.

[0309] The display panel 342 changes its orientation as appropriate depending on the usage mode. Since the camera lens 347 is located on the same plane as 42, video calls are possible. Speaker 343 and microphone 344 are not limited to voice calls, but also video calls, recording, and playback. Raw materials can be used, etc. Furthermore, the housing 340 and housing 341 slide together, as shown in Figure 10(D) It can be transformed from an unfolded state to an overlapping state, and can be made smaller for portability. It is Noh.

[0310] External connection terminal 348 can be connected to various cables such as AC adapters and USB cables. It also enables charging and data communication. Furthermore, the external memory slot 350 can be used for recording media. By inserting this, it can handle the storage and movement of larger amounts of data. In addition to the above functions, It may also be equipped with infrared communication capabilities, television reception capabilities, etc.

[0311] Figure 10(E) shows a digital camera including a semiconductor device according to the previous embodiment. The digital camera consists of the main unit 361, the display unit (A) 367, the eyepiece 363, and the operation switch 364. It consists of a display unit (B) 365, a battery 366, and the like.

[0312] Figure 10(F) shows a television apparatus including a semiconductor device according to the previous embodiment. In the vision device 370, the display unit 373 is incorporated into the housing 371. This makes it possible to display video. Note that here, the enclosure is connected by stand 375. This shows the configuration that supported 371.

[0313] The television device 370 can be operated using the control switches on the housing 371 or a separate remote control. This can be done using the control unit 380. The operation keys 379 on the remote control unit 380 This allows you to control the channel and volume, and manipulate the image displayed on the display unit 373. It is possible to output from the remote control unit 380 to the remote control unit 380. A display unit 377 that displays the information may also be provided.

[0314] Furthermore, it is preferable that the television equipment 370 be configured to include a receiver, modem, etc. The receiver can receive regular television broadcasts. It can also receive broadcasts via a modem. By connecting to a wired or wireless communication network, one-way communication (from sender to receiver) is possible. (Sender) or two-way information communication (between sender and receiver, or between receivers, etc.) This is possible.

[0315] The configurations and methods shown in this embodiment may be combined with the configurations and methods shown in other embodiments as appropriate. Can be used together [Examples]

[0316] In this example, the off-current of a transistor using a highly purified oxide semiconductor was determined. Let's explain the results.

[0317] First, the off-current of a transistor using a highly purified oxide semiconductor must be sufficiently small. Taking this into consideration, a transistor with a sufficiently large channel width W of 1m was prepared to measure the off-current. The following was performed. Figure 25 shows the results of measuring the off-current of a transistor with a channel width W of 1m. In Figure 25, the horizontal axis represents the gate voltage VG, and the vertical axis represents the drain current ID. When voltage VD is +1V or +10V, the gate voltage VG is in the range of -5V to -20V. The off-current of the thin-film transistor is 1 × 10⁻⁶, which is the detection limit. -13 It must be A or less. Also, the off-current of the transistor (here, per unit channel width (1 μm)) The value is 1 aA / μm (1 × 10⁻¹⁰). -18 It was found that the value would be less than or equal to A / μm.

[0318] Next, we will further refine the off-current of thin-film transistors using highly purified oxide semiconductors. I will now explain the results obtained. As mentioned above, using a highly purified oxide semiconductor... The off-current of the transistor is 1 × 10⁻¹⁶, which is the detection limit of the measuring instrument. -13 It must be A or less. Therefore, a characteristic evaluation element was fabricated to obtain a more accurate value of the off-current (in the above measurement). We will now explain the results obtained for values ​​below the detection limit of the measuring instrument.

[0319] First, the characteristic evaluation elements used in the current measurement method will be explained with reference to Figure 26.

[0320] The characteristic evaluation element shown in Figure 26 consists of three measurement systems 800 connected in parallel. 0 represents the capacitive element 802, transistor 804, transistor 805, and transistor 806. , has transistor 808. Transistor 804, transistor 805, transistor The Ta806 incorporates transistors using highly purified oxide semiconductors.

[0321] In the measurement system 800, one of the source terminals and drain terminals of transistor 804 is connected to, One terminal of the capacitive element 802 and the source and drain terminals of the transistor 805 One side is connected to the power supply (the power supply that provides V2). Also, the saw of transistor 804 The other end of the terminals, the source terminal and the drain terminal, and the source terminal and drain terminal of transistor 808. One side of the child, the other side of the terminal of the capacitive element 802, and the gate terminal of the transistor 805 are connected. It is continued. Also, the source terminal and the other drain terminal of transistor 808, One of the source and drain terminals of transistor 806 and the gateway of transistor 806 The terminal is connected to the power supply (the power supply that provides V1). Also, the base of transistor 805 The other end of the drain terminal and the source terminal and drain of transistor 806 The other end of the terminal is connected to it and serves as an output terminal.

[0322] The gate terminal of transistor 804 has two states: ON state and OFF state. A potential Vext_b2 that controls the state is supplied, and the gate terminal of transistor 808 is The potential Vext_b1 that controls the ON and OFF states of the transistor 808 is supplied. Additionally, a voltage (Vout) is output from the output terminal.

[0323] Next, a method for measuring current using the above-mentioned characteristic evaluation element will be described.

[0324] First, we will briefly describe the initial period during which a potential difference is applied to measure the off-current. During this period, the gate terminal of transistor 808 is set to the ON state. Input a potential Vext_b1 to the source terminal or drain of transistor 804. The node connected to the other terminal (i.e., the source terminal and the slave terminal of transistor 808) One terminal of the transistor, the other terminal of the capacitive element 802, and the gate terminal of the transistor 805 A potential V1 is applied to node A, which is a connected node. Here, the potential V1 is, for example, high The potential is set to [value]. Also, transistor 804 is kept in the OFF state.

[0325] Subsequently, a potential is applied to the gate terminal of transistor 808 to turn it off. Enter Vext_b1 to turn off transistor 808. Transistor 808 After turning it off, the potential V1 is set to a low potential. Here too, transistor 804 is off. Let's leave it as that state. Also, let's assume that potential V2 is the same potential as potential V1. Based on the above, the initial period is Terminate. When the initial period is over, the source terminals of node A and transistor 804 and A potential difference is generated between node A and one of the drain terminals, and also between node A and transistor 808. A potential difference will be generated between the drain terminal and the other terminal of the transistor. A small charge flows through transistors 804 and 808. In other words, an off-current is generated. .

[0326] Next, we will briefly explain the measurement period for the off-current. During the measurement period, the transistor The potential of either the source or drain terminal of the 804 (i.e., V2), and The potential (i.e., V1) of the other terminal of the source or drain terminal of the transistor 808 is Keep it fixed at a low potential. On the other hand, during the measurement period, the potential of node A is not fixed (flow (This puts it into a charging state). As a result, charge flows to transistor 804, and over time... The amount of charge held at node A fluctuates. Consequently, the potential of node A fluctuates. In other words, the output potential Vout at the output terminal also fluctuates. .

[0327] Details of the relationship between each potential during the initial period in which the above potential difference is applied, and during the subsequent measurement period. The timing chart is shown in Figure 27.

[0328] In the initial period, first, the potential Vext_b2 is turned ON when transistor 804 is turned ON. Let's assume a potential like this (high potential). As a result, the potential at node A will be V2, which is a low potential (V SS) This is what happens. After that, the potential Vext_b2 is set so that transistor 804 is in the OFF state. To achieve a low potential, transistor 804 is turned off. Then, the potential Set Vext_b1 to a potential (high potential) that turns on transistor 808. As a result, the potential at node A becomes V1, i.e., high potential (VDD). Then Ve Set xt_b1 to a potential such that transistor 808 is in the OFF state. Node A enters a floating state, and the initial period ends.

[0329] During the subsequent measurement period, potentials V1 and V2 are measured as charge flows into node A. Alternatively, the potential is set such that charge flows out from node A. Here, potentials V1 and V Set 2 to low potential (VSS). However, at the timing when measuring the output potential Vout... This requires the output circuit to be activated, so V1 is temporarily set to a high potential (VDD). There are such cases. Note that the period during which V1 is at a high potential (VDD) is short enough not to affect the measurement. This will be the period.

[0330] As described above, a potential difference is applied, and once the measurement period begins, as time progresses, at node A... The amount of charge held fluctuates, and the potential of node A fluctuates accordingly. This is a transient. This means that the potential at the gate terminal of the 805 fluctuates, and therefore, over time, the output... The potential of the terminal's output potential Vout will also change.

[0331] The method for calculating the off-current from the obtained output potential Vout is described below.

[0332] Before calculating the off-current, the potential V at node A is... A Then, find the relationship with the output potential Vout. Place it there. This will allow you to measure the potential V at node A from the output potential Vout. A It is possible to find the above. From the relationship described above, the potential V of node A A It can be expressed as a function of the output potential Vout as follows: It is possible.

[0333]

number

[0334] Also, the charge Q at node A. A The potential V of node A is A Capacity C connected to node A A , fixed Using a constant, it can be expressed as follows: Here, the capacity connected to node A CA is the sum of the capacitance of the capacitive element 802 and other capacitances.

[0335]

Number

[0336] The current I at node A A is the time derivative of the charge flowing into (or out of) node A. Therefore, the current I at node A is expressed as follows. A is expressed by the following equation.

[0337]

Number

[0338] Thus, from the capacitance C connected to node A A and the output potential Vout of the output terminal, the current I at node A can be obtained. A can be determined.

[0339] By the method shown above, the leakage current (off-current) flowing between the source and drain of the transistor in the off state can be measured. can be measured.

[0340] In this embodiment, transistors 804, 805, 806, and 808 were fabricated using a highly purified oxide semiconductor with a channel length L = 10 μm and a channel width W = 50 μm. Also, in each measurement system 800 connected in parallel, the capacitance values of the capacitive elements 802a to 802c were set to 100 fF for the capacitive element 802a, 1 pF for the capacitive element 802b, and 3 pF for the capacitive element 802c, respectively. ~802c were set to 100 fF for the capacitive element 802a, 1 pF for the capacitive element 802b, and 3 pF for the capacitive element 802c, respectively.

[0341] In the measurement according to this embodiment, VDD = 5 V and VSS = 0 V were used. Also, during the measurement period In this case, the potential V1 is set to VSS as a general rule, and every 10 to 300 seconds, 100 mse Vout was measured as VDD only during period c. It was also used to calculate the current I flowing through the element. The time interval Δt was assumed to be approximately 30,000 seconds.

[0342] Figure 28 shows the relationship between the elapsed time (Time) and the output potential (Vout) related to the current measurement described above. Figure 28 shows that the electrical potential changes over time.

[0343] Figure 29 shows the off-current at room temperature (25°C) calculated by the current measurement described above. Figure 29 shows the relationship between the source-drain voltage V and the off-current I. From 29, under the condition of a source-drain voltage of 4V, the off-current is approximately 40 zA / μm. It was found that... Also, under the condition of a source-drain voltage of 3.1V, the off-current... It was found to be less than 10 zA / μm. Note that 1 zA is equal to 10 -21 It represents A.

[0344] Furthermore, regarding the off-current calculated by the above current measurement under a temperature environment of 85°C: This is shown in Figure 30. Figure 30 shows the source-drain voltage V and the off voltage at a temperature of 85°C. This shows the relationship with current I. Figure 30 shows the condition where the source-drain voltage is 3.1V. In this case, the off-current was found to be 100 zA / μm or less.

[0345] In this embodiment, a transistor using a highly purified oxide semiconductor can be used for off-voltage operation. It was confirmed that the flow was sufficiently reduced. [Examples]

[0346] The number of rewriteable cycles of a semiconductor device according to one embodiment of the disclosed invention was investigated. This example Now, let's explain the results of this survey with reference to Figure 31.

[0347] The semiconductor device used in the investigation is the one with the circuit configuration shown in Figure 15(A). An oxide semiconductor is used for the transistor corresponding to transistor 162, and a capacitive element 164 is used. A capacitor with a capacitance value of 0.33 pF was used as the corresponding capacitance element.

[0348] The investigation involves determining the initial memory window width and the number of times information is retained and written. This was done by comparing it with the memory window width after it was returned. Information retention and information The writing process involves applying either 0V or 5V to the wiring corresponding to the third wiring in Figure 15(A). By applying either of these, the wiring corresponding to the fourth wiring is given either 0V or 5V. This was done. If the potential of the wiring corresponding to the fourth wiring is 0V, then transistor 162 Since the corresponding transistor (the writing transistor) is in the off state, at node FG... The given potential is maintained. If the potential of the wiring corresponding to the fourth wiring is 5V, then Since the transistor corresponding to transistor 162 is in the ON state, the wiring corresponding to the third wiring The potential of the line is applied to node FG.

[0349] Memory window width is one of the indicators that show the characteristics of a storage device. Here, different notations The potential Vcg of the wiring corresponding to the fifth wiring during the memory state, and the potential corresponding to transistor 160. A curve showing the relationship with the drain current Id of the transistor (readout transistor) ( This refers to the shift amount ΔVcg of the Vcg-Id curve. Different memory states are, The state in which 0 V is applied to FG (hereinafter referred to as the Low state) and the state in which 5 V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. Figure 31 shows the investigation results of the memory window width in the initial state and after 1×10

[0350] Figure 31 shows the investigation results of the memory window width in the initial state and after 1×10 9 write operations. In Figure 31, the horizontal axis represents Vcg (V) and the vertical axis represents Id (A). From Figure 31, it can be confirmed that the memory window width has not changed before and after 1×10 write operations. The fact that the memory window width does not change before and after 1×10 9 write operations indicates that the semiconductor device does not deteriorate at least during this period. As described above, the semiconductor device according to one aspect of the disclosed invention has high write durability, with characteristics remaining unchanged even after repeating holding and writing operations 1×1 9 write operations indicates that the semiconductor device does not deteriorate at least during this period. times. That is, according to one aspect of the disclosed invention, a highly reliable semiconductor device can be realized. As described above, the semiconductor device according to one aspect of the disclosed invention has high write durability, with characteristics remaining unchanged even after repeating holding and writing operations 1×1

[0351] times. That is, according to one aspect of the disclosed invention, a highly reliable semiconductor device can be realized. 0 9 times. That is, according to one aspect of the disclosed invention, a highly reliable semiconductor device can be realized. times. That is, according to one aspect of the disclosed invention, a highly reliable semiconductor device can be realized.

Explanation of Reference Numerals

[0352] 100 Substrate 102 Protective layer 104 Semiconductor region 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate electrode 112 Insulating layer 114 Impurity region 116 Channel formation region 118 Sidewall insulating layer 120 High-concentration impurity region 122 Metal layer 124 Metal compound area 126 Interlayer insulating layer 128 Interlayer insulating layer 130a Source electrode or drain electrode 130b Source electrode or drain electrode 130c electrode 132 Insulating layer 134 Conductive layer 136a electrode 136b Electrode 136c electrode 136d Gate 138 Gate Insulation Layer 140 Oxide semiconductor layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 144 Protective insulating layer 146 Interlayer insulating layer 148 Conductive layer 150a electrode 150b electrode 150c electrode 150d electrode 150e electrode 152 Insulating layer 154a electrode 154b electrode 154c electrode 154d electrode 160 transistors 162 transistors 164 Capacitive elements 200 circuit boards 206 Element Isolation Insulating Layer 208 Gate Insulation Layer 210 Guard Station 216 Channel formation region 220 High concentration impurity region 224 Metal compound area 225 Interlayer insulating layer 226 Interlayer insulating layer 228 Interlayer insulating layer 242a Source electrode or drain electrode 242b Source electrode or drain electrode 243a Insulating layer 243b Insulating layer 244 oxide semiconductor layer 246 Gate Insulation Layer 248a Electrode gate 248b Electrode 250 interlayer insulating layer 252 Interlayer insulating layer 254 Source electrode or drain electrode 256 Wiring 260 transistors 262 transistors 264 Capacitive elements 301 Main Unit 302 enclosures 303 Display section 304 Keyboard 311 Main Unit 312 Stylus 313 Display section 314 Operation Buttons 315 External Interface 320 eBooks 321 cabinet 323 enclosures 325 Display section 327 Display section 331 Power supply 333 Operation Keys 335 speakers 337 Shaft 340 cabinets 341 cabinets 342 Display Panel 343 speakers 344 Microphone 345 Operation Keys 346 Pointing devices 347 Camera Lenses 348 External connection terminals 349 solar cells 350 external memory slots 361 Main Unit 363 Eyepiece 364 Operation Switches 365 Display section (B) 366 Battery 367 Display section (A) 370 Television equipment 371 cabinets 373 Display section 375 Stand 377 Display section 379 Operation Keys 380 Remote Control Unit 400 memory cells 800 Measurement System 802 Capacitive element 802a Capacitive element 802b Capacitive element 802c capacitive element 804 Transistor 805 Transistor 806 Transistors 808 transistors 1100 cell cells 1111 Drive Circuit 1112 Drive Circuit 1113 Drive Circuit 1114 Drive Circuit 1200 memory cells 1211 Drive Circuit 1212 Drive Circuit 1213 Drive Circuit 1214 Drive Circuit

Claims

1. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, It comprises a third insulating film having a region positioned above the oxide semiconductor film, The oxide semiconductor film is electrically connected to the first conductive film via a third conductive film having a region located above the third insulating film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. Semiconductor equipment.

2. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, It comprises a third insulating film having a region positioned above the oxide semiconductor film, The oxide semiconductor film is electrically connected to the first conductive film via a third conductive film having a region located above the third insulating film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. The second insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. The third insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. Semiconductor equipment.

3. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor in which the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. Semiconductor equipment.

4. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. A semiconductor device in which the source or drain of the second transistor is electrically connected to the gate of the first transistor, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor in which the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. The second insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. The third insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. Semiconductor equipment.

5. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor in which the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. Semiconductor equipment.

6. The device comprises a first transistor having silicon in its first channel formation region, and a second transistor having an oxide semiconductor in its second channel formation region. Either the source or the drain of the second transistor is electrically connected to the gate of the first transistor. A semiconductor device in which two or more potentials are input to the gate of the first transistor via the second channel formation region, A first conductive film having a region positioned above the first channel forming region and functioning as the gate of the first transistor, A first insulating film having a region positioned above the first conductive film, A second conductive film having a region positioned above the first insulating film and functioning as the gate of the second transistor, A second insulating film having a region positioned above the second conductive film and functioning as a gate insulating film of the second transistor, An oxide semiconductor film having a region positioned above the second insulating film and having the second channel-forming region, A third insulating film having a region positioned above the oxide semiconductor film, A third conductive film having a region positioned above the third insulating film, The first conductive film is electrically connected to the oxide semiconductor film via the third conductive film. In a plan view, the first conductive film does not have a region that overlaps with the oxide semiconductor film. In a plan view, the maximum length of the oxide semiconductor film in the channel length direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. In a plan view, the maximum length of the third conductive film in the channel length direction of the second transistor is greater than the maximum length of the third conductive film in the channel width direction of the second transistor. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the region in the channel width direction of the second transistor in which the third conductive film overlaps with the first conductive film. In a plan view, the maximum length of the first conductive film in the channel width direction of the second transistor is greater than the maximum length of the oxide semiconductor film in the channel width direction of the second transistor. The second insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. The third insulating film has a region in contact with the oxide semiconductor film and contains oxygen and silicon. Semiconductor equipment.

7. In claims 3 to 6, A fourth insulating film having a region positioned above the third insulating film and a region positioned below the third conductive film, A fourth conductive film having a region positioned above the fourth insulating film and electrically connected to the silicon semiconductor layer having the first channel-forming region, A constant potential is applied to the fourth conductive film. When the constant potential is applied to either the source or the drain of the first transistor, the potential of the other source or drain of the first transistor is controlled according to the charge held at least at the gate of the first transistor. The third conductive film and the fourth conductive film have regions that are in contact with the fourth insulating film. Semiconductor equipment.

8. In any one of claims 1 to 7, In a plan view, the channel formation region of the first transistor has a region in which current flows in a direction intersecting the channel length direction of the second transistor. Semiconductor equipment.

9. In any one of claims 1 to 8, The charge held at the gate of the first transistor corresponds to three or more potentials, Semiconductor equipment.

10. In any one of claims 1 to 9, The first insulating film comprises nitrogen and silicon, Semiconductor equipment.

11. In any one of claims 1 to 10, The second transistor has an off-current of 1 × 10⁻⁶. －１８ It is less than or equal to A / μm. Semiconductor equipment.

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