Semiconductor devices and power converters
The semiconductor device with electrode plates on both surfaces and conductive coatings enhances mounting and heat dissipation, addressing integration and efficiency issues in power conversion devices.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- KK TOSHIBA
- Filing Date
- 2023-03-23
- Publication Date
- 2026-06-01
AI Technical Summary
Existing semiconductor devices are difficult to mount on printed circuit boards and lack effective heat dissipation, making them inefficient for use in power conversion devices.
The semiconductor device includes a semiconductor chip with electrode plates on both surfaces, connected via conductive layers and coated with films to enhance adhesion and heat dissipation, allowing easy integration into multilayer printed circuit boards.
The configuration enables easy embedding of semiconductor devices in printed circuit boards with improved heat dissipation, facilitating efficient power conversion and wiring formation.
Smart Images
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Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to a semiconductor device and a power conversion device.
Background Art
[0002] As a switching element used in a power conversion device (for example, a DC-DC converter), a semiconductor device such as a power MOSFET surface-mounted on a printed circuit board is known.
Prior Art Documents
Patent Documents
[0003]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0004] To provide a semiconductor device that is easy to mount on a printed circuit board, and a power conversion device including the semiconductor device.
Means for Solving the Problems
[0005] The semiconductor device of the embodiment includes a semiconductor chip having a drain region on a first surface, a source region and a gate region on a second surface facing the first surface, a drain electrode plate provided in the drain region, a source electrode plate provided in the source region, a gate electrode plate provided in the gate region, a mold layer provided on a side surface of the semiconductor chip, the source electrode plate, and the gate electrode plate, and a first coating film provided on a lower surface and a side surface of the drain electrode plate, an upper surface of the source electrode plate, and an upper surface of the gate electrode plate, and a second coating film provided on an upper surface and a side surface of the mold layer.
Brief Description of the Drawings
[0006] [Figure 1] It is a perspective view of a semiconductor device according to a first embodiment. [Figure 2] This is a top view of a semiconductor device according to the first embodiment. [Figure 3] Figure 2 is a cross-sectional view of the semiconductor device shown along line III-III. [Figure 4] This is a cross-sectional view showing in detail the semiconductor chip and conductive layer according to the first embodiment. [Figure 5] This is a top view of a semiconductor device according to the second embodiment. [Figure 6] Figure 5 is a cross-sectional view of the semiconductor device shown along the line VI-VI. [Figure 7] This is a cross-sectional view showing in detail the semiconductor chip and conductive layer according to the second embodiment. [Figure 8] This is a circuit diagram of a power converter according to the third embodiment. [Figure 9] This is a top view of a power conversion device according to the third embodiment. [Figure 10] Figure 9 is a cross-sectional view of the power converter shown along line XX. [Figure 11] This is a top view of a power conversion device according to the fourth embodiment. [Figure 12] Figure 11 is a cross-sectional view of the power converter shown along line XII-XII. [Figure 13] This is a cross-sectional view of a power conversion device according to the fifth embodiment. [Modes for carrying out the invention]
[0007] Embodiments will be described below with reference to the drawings. In the following description, components having the same function and configuration will be denoted by the same reference numerals. Furthermore, the embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this embodiment, and do not specify the materials, shapes, structures, and arrangements of the components as described below. In addition, in the drawings referenced below, components such as insulating layers, coatings, wiring, and contacts have been appropriately omitted in this specification for the sake of clarity.
[0008] 1. First Embodiment A semiconductor device of the first embodiment will be described. The semiconductor device includes, for example, a MOS field-effect transistor (hereinafter referred to as MOSFET) as a switching element. The MOSFET of the first embodiment has a drain on the first surface (or bottom surface, back surface) and a source and gate on the second surface (or top surface, front surface) opposite the first surface. The MOSFET is used in power conversion devices, such as DC-DC converters or inverters. Examples of applying the MOSFET to power conversion devices will be described in the third embodiment and subsequent embodiments.
[0009] Figure 1 is a perspective view of a semiconductor device according to the first embodiment. Figure 2 is a top view of the semiconductor device according to the first embodiment, and Figure 3 is a cross-sectional view of the semiconductor device shown in Figure 2 along line III-III. In these figures and subsequent drawings, the two directions parallel to the first surface of the semiconductor device and perpendicular to each other are referred to as the X direction and the Y direction, and the direction perpendicular to the plane containing these X and Y directions (the XY plane) is referred to as the Z direction. Note that the peritoneum and mold layer, etc., are omitted in Figures 1 and 2.
[0010] As shown in Figures 1, 2, and 3, the semiconductor device 1 comprises a semiconductor chip 10, a drain electrode plate (or drain electrode layer) 11, a source electrode plate (or source electrode layer) 12, a gate electrode plate (or gate electrode layer) 13, conductive layers 14, 15a, 15b, a mold layer 16, and coating films 17 and 18.
[0011] The semiconductor chip 10 constitutes, for example, a MOSFET. The semiconductor chip 10 has a first surface orthogonal to the Z direction and a second surface opposite the first surface. The first surface is the bottom surface of the semiconductor chip 10 shown in Figure 3, and the second surface is the top surface of the semiconductor chip 10 shown in Figure 3. The semiconductor chip 10 has a drain region on the first surface and a source region and a gate region on the second surface.
[0012] The semiconductor chip 10 is provided between a drain electrode plate 11, a source electrode plate 12, and a gate electrode plate 13. That is, the drain electrode plate 11 is provided under the drain region of the semiconductor chip 10. The source electrode plate 12 is provided on the source region of the semiconductor chip 10. Further, the gate electrode plate 13 is provided on the gate region of the semiconductor chip 10.
[0013] The drain electrode plate 11 has a thin plate shape and includes, for example, a lead frame. The thickness of the drain electrode plate 11 is, for example, 50 μm or more, or 150 μm or more and 300 μm or less. Similar to the drain electrode plate 11, the source electrode plate 12 has a thin plate shape and includes, for example, a lead frame. The thickness of the source electrode plate 12 is, for example, 50 μm or more, or 150 μm or more and 300 μm or less. The gate electrode plate 13 has a thin plate shape and includes, for example, a lead frame. The thickness of the gate electrode plate 13 is, for example, 50 μm or more, or 150 μm or more and 300 μm or less. The drain electrode plate 11, the source electrode plate 12, and the gate electrode plate 13 contain, for example, Cu.
[0014] Hereinafter, the structures of the source region, drain region, and gate region of the semiconductor chip 10 and the conductive layers 14, 15a, and 15b will be described. FIG. 4 is a cross-sectional view showing the semiconductor chip 10 and the conductive layers 14, 15a, and 15b in detail.
[0015] A conductive layer 14 is provided between the drain region of the semiconductor chip 10 and the drain electrode plate 11. An electrode layer Db is disposed under the drain region Da. The drain electrode plate 11 is disposed under the electrode layer Db via the conductive layer 14.
[0016] The drain region Da is, for example, an n-type semiconductor layer, that is, an n-type diffusion layer. The electrode layer Db includes, for example, any one of a stacked structure of Al / Ni / Au, a stacked structure of Al / Ni / Pd / Au, a stacked structure of Al / Cu, or a Cu single layer structure. The conductive layer 14 includes a conductive metal material or a sintered material (for example, a solder material or a sintered Ag material). Specifically, the conductive layer 14 includes, for example, at least any one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0017] The conductive layer 14 is joined or sintered between the electrode layer Db of the semiconductor chip 10 and the drain electrode plate 11 by being heated in a pressurized state or a non-pressurized state. The drain electrode plate 11 is electrically connected to the drain (that is, the electrode layer Db and the drain region Da) of the semiconductor chip 10 through the conductive layer 14.
[0018] A conductive layer 15a is provided between the source region Sa of the semiconductor chip 10 and the source electrode plate 12. An electrode layer Sb is disposed on the source region Sa. The source electrode plate 12 is disposed on the electrode layer Sb through the conductive layer 15a.
[0019] The source region Sa is, for example, an n-type semiconductor layer, that is, an n-type diffusion layer. The electrode layer Sb includes, for example, any one of a stacked structure of Al / Ni / Au, a stacked structure of Al / Ni / Pd / Au, a stacked structure of Al / Cu, or a Cu single layer structure. The conductive layer 15a includes a conductive metal material or a sintered material (for example, a solder material or a sintered Ag material). Specifically, the conductive layer 15a includes, for example, at least any one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0020] The conductive layer 15a is joined or sintered between the electrode layer Sb of the semiconductor chip 10 and the source electrode plate 12 by being heated in a pressurized state or a non-pressurized state. The source electrode plate 12 is electrically connected to the source (that is, the electrode layer Sb and the source region Sa) of the semiconductor chip 10 through the conductive layer 15a.
[0021] A conductive layer 15b is provided between the gate region of the semiconductor chip 10 and the gate electrode plate 13. An electrode layer Gb is placed on the gate region Ga. The gate electrode plate 13 is placed on the electrode layer Gb via the conductive layer 15b.
[0022] The gate region Ga is, for example, an n-type semiconductor layer, i.e., an n-type diffusion layer. The electrode layer Gb includes, for example, one of the following: an Al / Ni / Au multilayer structure, an Al / Ni / Pd / Au multilayer structure, an Al / Cu multilayer structure, or a Cu monolayer structure. The conductive layer 15b includes a conductive metallic material or a sintered material (for example, solder material or Ag sintered material). More specifically, the conductive layer 15b includes, for example, at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0023] The conductive layer 15b is heated under pressure or without pressure to bond or sinter between the electrode layer Gb of the semiconductor chip 10 and the gate electrode plate 13. The gate electrode plate 13 is electrically connected to the gate of the semiconductor chip 10 (i.e., the electrode layer Gb and the gate region Ga) via the conductive layer 15b.
[0024] Returning to Figure 3, the explanation continues. A mold layer 16 is provided on the drain electrode plate 11 and on the side surfaces of the source electrode plate 12 and the semiconductor chip 10. A mold layer 16 is also provided on the drain electrode plate 11 and on the side surfaces of the gate electrode plate 13 and the semiconductor chip 10. Furthermore, a mold layer 16 is also provided on the semiconductor chip 10 and between the source electrode plate 12 and the gate electrode plate 13. These mold layers 16 stably maintain the insulation state and arrangement between the semiconductor chip 10, the drain electrode plate 11, the source electrode plate 12, and the gate electrode plate 13 within the semiconductor device 1.
[0025] A coating film 17 is provided so as to cover the surfaces of the drain electrode plate 11, the source electrode plate 12, and the gate electrode plate 13. The coating film 17 covers all or part of the surfaces of these drain electrode plate 11, source electrode plate 12, and gate electrode plate 13. Specifically, the coating film 17 is provided on the lower and side surfaces of the drain electrode plate 11, the upper surface of the source electrode plate 12, and the upper surface of the gate electrode plate 13. When contact material (or wiring) is provided for connection to each of the drain electrode plate 11, source electrode plate 12, and gate electrode plate 13, a portion of the coating film 17 covering these surfaces is removed. This makes it possible to electrically connect the contact material to each of the drain electrode plate 11, source electrode plate 12, and gate electrode plate 13.
[0026] When the semiconductor device 1 is mounted on a substrate, such as a printed wiring board (or printed circuit board), the coating film 17 improves the adhesion between the drain electrode plate 11, the source electrode plate 12, and the gate electrode plate 13 and the layer provided around these electrode plates.
[0027] The coating film 17 may be a metal film, for example, a film containing Sn or Ni / Au, or a film containing Ni / Pd / Au, or it may contain an insulating film, for example, a rust inhibitor such as benzotriazole (BTA).
[0028] A coating film 18 is provided so as to cover the surface of the mold layer 16. The coating film 18 covers all or part of the surface of the mold layer 16. Specifically, the coating film 18 is provided on the upper and side surfaces of the mold layer 16. When the semiconductor device 1 is mounted on a substrate, such as a printed circuit board, the coating film 18 improves the adhesion between the mold layer 16 and the layers provided around the mold layer 16. The coating film 18 includes, for example, an insulating film.
[0029] The thickness of the semiconductor device 1 shown in Figure 3 in the Z direction is, for example, 500 μm or less, or 400 μm or less. That is, the thickness of the stacked structure in which the drain electrode plate 11, semiconductor chip 10, and source electrode plate 12 are arranged in that order is, for example, 500 μm or less, or 400 μm or less.
[0030] The main effects of the first embodiment are described below.
[0031] In the first embodiment described above, a drain electrode plate 11 connected to the drain of the semiconductor chip 10 is provided on the first surface of the semiconductor device 1, and a source electrode plate 12 and a gate electrode plate 13 connected to the source and gate of the semiconductor chip 10 are provided on the second surface of the semiconductor device 1 facing the first surface. According to the configuration of the first embodiment, since electrode plates are provided on the first and second surfaces of the semiconductor device 1, the semiconductor device 1 can be easily embedded in a printed circuit board having multilayer wiring (for example, double-sided wiring).
[0032] Furthermore, in the configuration of the first embodiment, the heat dissipation of the semiconductor device 1 can be improved by providing electrode plates, for example, thin plate-shaped (or sheet-shaped) electrode plates made of Cu, on the first and second surfaces of the semiconductor device 1. For example, by making the thickness of at least one of the drain electrode plate 11, source electrode plate 12, and gate electrode plate 13 50 μm or more (or 150 μm or more and 300 μm or less), the heat dissipation of the semiconductor device 1 can be significantly improved.
[0033] Furthermore, when the semiconductor device 1 is mounted on the printed circuit board, it is easy to form a wiring layer using Cu on the printed circuit board.
[0034] In the first embodiment, an example was described in which the semiconductor device 1 constitutes a MOSFET, but the semiconductor device 1 may also constitute other switching elements, such as an IGBT (insulated gate bipolar transistor) or a JFET (junction field effect transistor). When the semiconductor device 1 constitutes an IGBT, the source electrode plate 12 corresponds to the emitter electrode, and the drain electrode plate 11 corresponds to the collector electrode.
[0035] 2. Second Embodiment A semiconductor device of the second embodiment will now be described. The semiconductor device includes, for example, a MOSFET as a switching element. The MOSFET of the second embodiment has a source and gate on the first surface (or bottom surface, back surface) and a drain on the second surface (or top surface, front surface) opposite the first surface. The MOSFET is used in power conversion devices, such as DC-DC converters or inverters. The perspective view shown in the first embodiment will be omitted here. The second embodiment will mainly be described in terms of the differences from the first embodiment.
[0036] Figure 5 is a top view of the semiconductor device of the second embodiment. Figure 6 is a cross-sectional view of the semiconductor device shown in Figure 5 along the line VI-VI. Note that the peritoneum and mold layer, etc., are omitted in Figure 5.
[0037] As shown in Figures 5 and 6, the semiconductor device 2 comprises a semiconductor chip 20, a drain electrode plate 21, a source electrode plate 22, a gate electrode plate 23, conductive layers 24, 25a, 25b, a mold layer 26, and coating films 27 and 28.
[0038] The semiconductor chip 20 constitutes, for example, a MOSFET. The semiconductor chip 20 has a first surface orthogonal to the Z direction and a second surface opposite the first surface. The first surface is the bottom surface of the semiconductor chip 20 shown in Figure 6, and the second surface is the top surface of the semiconductor chip 20 shown in Figure 6. The semiconductor chip 20 has a source region and a gate region on the first surface and a drain region on the second surface.
[0039] The semiconductor chip 20 is provided between the source electrode plate 22 and the gate electrode plate 23 and the drain electrode plate 21. That is, the source electrode plate 22 is provided below the source region of the semiconductor chip 20. The gate electrode plate 23 is provided below the gate region of the semiconductor chip 20. Furthermore, the drain electrode plate 21 is provided on the drain region of the semiconductor chip 20.
[0040] The source electrode plate 22 is thin and includes, for example, a lead frame. The thickness of the source electrode plate 22 is, for example, 50 μm or more, or 150 μm to 300 μm. Similarly to the source electrode plate 22, the gate electrode plate 23 is thin and includes, for example, a lead frame. The thickness of the gate electrode plate 23 is, for example, 50 μm or more, or 150 μm to 300 μm. The drain electrode plate 21 is thin and includes, for example, a lead frame. The thickness of the drain electrode plate 21 is, for example, 50 μm or more, or 150 μm to 300 μm. The source electrode plate 22, the gate electrode plate 23, and the drain electrode plate 21 are made of, for example, Cu.
[0041] The following describes the structure of the source region, drain region, and gate region of the semiconductor chip 20 and the conductive layers 24, 25a, and 25b. Figure 7 is a detailed cross-sectional view of the semiconductor chip 20 and the conductive layers 24, 25a, and 25b.
[0042] A conductive layer 24 is provided between the drain region Da of the semiconductor chip 20 and the drain electrode plate 21. An electrode layer Db is placed on the drain region Da. The drain electrode plate 21 is placed on the electrode layer Db via the conductive layer 24.
[0043] The drain region Da is, for example, an n-type semiconductor layer, i.e., an n-type diffusion layer. The electrode layer Db includes, for example, one of the following: an Al / Ni / Au multilayer structure, an Al / Ni / Pd / Au multilayer structure, an Al / Cu multilayer structure, or a Cu monolayer structure. The conductive layer 24 includes a conductive metallic material or a sintered material (e.g., solder material or Ag sintered material). More specifically, the conductive layer 24 includes, for example, at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0044] The conductive layer 24 is heated under pressure or without pressure to bond or sinter the electrode layer Db of the semiconductor chip 20 with the drain electrode plate 21. The drain electrode plate 21 is electrically connected to the drain of the semiconductor chip 20 (i.e., the electrode layer Db and the drain region Da) via the conductive layer 24.
[0045] A conductive layer 25a is provided between the source region Sa of the semiconductor chip 20 and the source electrode plate 22. An electrode layer Sb is placed below the source region Sa. The source electrode plate 22 is placed below the electrode layer Sb via the conductive layer 25a.
[0046] The source region Sa is, for example, an n-type semiconductor layer, i.e., an n-type diffusion layer. The electrode layer Sb includes, for example, one of the following: an Al / Ni / Au multilayer structure, an Al / Ni / Pd / Au multilayer structure, an Al / Cu multilayer structure, or a Cu single-layer structure. The conductive layer 25a includes a conductive metallic material or a sintered material (for example, solder material or Ag sintered material). More specifically, the conductive layer 25a includes, for example, at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0047] The conductive layer 25a is heated under pressure or without pressure to bond or sinter between the electrode layer Sb of the semiconductor chip 20 and the source electrode plate 22. The source electrode plate 22 is electrically connected to the source of the semiconductor chip 20 (i.e., the electrode layer Sb and the source region Sa) via the conductive layer 25a.
[0048] A conductive layer 25b is provided between the gate region Ga of the semiconductor chip 20 and the gate electrode plate 23. An electrode layer Gb is placed below the gate region Ga. The gate electrode plate 23 is placed below the electrode layer Gb via the conductive layer 25b.
[0049] The gate region Ga is, for example, an n-type semiconductor layer, i.e., an n-type diffusion layer. The electrode layer Gb includes, for example, one of the following: an Al / Ni / Au multilayer structure, an Al / Ni / Pd / Au multilayer structure, an Al / Cu multilayer structure, or a Cu monolayer structure. The conductive layer 25b includes a conductive metallic material or a sintered material (e.g., solder material or Ag sintered material). More specifically, the conductive layer 25b includes, for example, at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
[0050] The conductive layer 25b is heated under pressure or without pressure to bond or sinter between the electrode layer Gb of the semiconductor chip 20 and the gate electrode plate 23. The gate electrode plate 23 is electrically connected to the gate of the semiconductor chip 20 (i.e., the electrode layer Gb and the gate region Ga) via the conductive layer 25b.
[0051] Returning to Figure 6, the explanation continues. A mold layer 26 is provided on the source electrode plate 22 and on the side surfaces of the drain electrode plate 21 and the semiconductor chip 20. A mold layer 26 is also provided on the side surfaces of the gate electrode plate 23, the semiconductor chip 20, and the drain electrode plate 21. These mold layers 16 stably maintain the insulation state and arrangement between the semiconductor chip 20, the drain electrode plate 21, the source electrode plate 22, and the gate electrode plate 23 within the semiconductor device 1.
[0052] A coating film 27 is provided so as to cover the surfaces of the drain electrode plate 21, the source electrode plate 22, and the gate electrode plate 23. The coating film 27 covers all or part of the surfaces of these drain electrode plate 21, source electrode plate 22, and gate electrode plate 23. When contact material (or wiring) is provided for connection to each of the drain electrode plate 21, source electrode plate 22, and gate electrode plate 23, a portion of the coating film 27 covering these surfaces is removed. This makes it possible to electrically connect the contact material to each of the drain electrode plate 21, source electrode plate 22, and gate electrode plate 23.
[0053] When the semiconductor device 1 is mounted on a substrate, such as a printed circuit board, the coating film 27 improves the adhesion between the drain electrode plate 21, the source electrode plate 22, and the gate electrode plate 23 and the layer provided around these electrode plates.
[0054] The coating film 27 may contain a metal film, for example, a multilayer film of Sn or Ni / Au or a multilayer film of Ni / Pd / Au, or it may contain an insulating film, for example, a rust inhibitor such as benzotriazole (BTA).
[0055] A coating film 28 is provided so as to cover the surface of the mold layer 26. The coating film 28 covers all or part of the surface of the mold layer 26. When the semiconductor device 1 is mounted on a substrate, such as a printed circuit board, the coating film 28 improves the adhesion between the mold layer 26 and the layers provided around the mold layer 26. The coating film 28 includes, for example, an insulating film.
[0056] The thickness of the semiconductor device 1 shown in Figure 6 in the Z direction is, for example, 500 μm or less, or 400 μm or less.
[0057] The main effects of the second embodiment are described below.
[0058] In the second embodiment described above, a source electrode plate 22 and a gate electrode plate 23 are provided on the first surface of the semiconductor device 2, connected to the source and gate of the semiconductor chip 20, respectively, and a drain electrode plate 21 is provided on the second surface of the semiconductor device 2, opposite the first surface, and connected to the drain of the semiconductor chip 20. According to the configuration of the second embodiment, since electrode plates are provided on the first and second surfaces of the semiconductor device 2, the semiconductor device 2 can be easily embedded in a printed circuit board having multilayer wiring (for example, double-sided wiring).
[0059] Furthermore, in the configuration of the second embodiment, the heat dissipation of the semiconductor device 2 can be improved by providing electrode plates, for example, thin plate-shaped (or sheet-shaped) electrode plates made of Cu, on the first and second surfaces of the semiconductor device 2. For example, by making the thickness of at least one of the drain electrode plate 21, source electrode plate 22, and gate electrode plate 23 50 μm or more (or 150 μm or more and 300 μm or less), the heat dissipation of the semiconductor device 2 can be significantly improved.
[0060] Furthermore, when the semiconductor device 2 is mounted on the printed circuit board, it is easy to form a wiring layer using Cu on the printed circuit board.
[0061] In the second embodiment, an example was described in which the semiconductor device 2 constitutes a MOSFET, but the semiconductor device 2 may also constitute other switching elements, such as an IGBT (insulated gate bipolar transistor) or a JFET (junction field effect transistor).
[0062] 3. Third Embodiment A power conversion device of the third embodiment will be described. In the third embodiment, a power conversion device comprising multiple semiconductor devices of the first embodiment will be described. Here, a DC-DC converter will be shown as an example of the power conversion device. In the third embodiment, the main differences from the first embodiment will be described.
[0063] First, the circuit configuration of the power converter according to the third embodiment will be described. Figure 8 is a circuit diagram of the power converter according to the third embodiment.
[0064] The power converter 3 comprises a plurality of semiconductor devices 1a and 1b, an inductor L1, and capacitors C1 and C2. Each of the semiconductor devices 1a and 1b corresponds to the semiconductor device 1 of the first embodiment and includes a MOSFET.
[0065] The following describes the connection relationships of the circuit elements constituting the power converter 3. The input terminal TIN is connected to the drain of the semiconductor device 1a. The input terminal TIN is also connected to the voltage VSS node via capacitor C1. The ground voltage VSS is supplied to the voltage VSS node.
[0066] The source of semiconductor device 1a is connected to the drain of semiconductor device 1b and the first terminal of inductor L1. The source of semiconductor device 1b is connected to a voltage VSS node. Gate drivers GD are connected to the gates of semiconductor devices 1a and 1b.
[0067] The second end of inductor L1 is connected to the output terminal TOUT. The second end of inductor L1 is also connected to the voltage VSS node via capacitor C2.
[0068] Next, the planar layout and cross-sectional structure of the power converter 3 of the third embodiment will be described. Figure 9 is a top view of the power converter of the third embodiment. Figure 10 is a cross-sectional view of the power converter shown in Figure 9 along line XX. Note that the cross-sectional view shown in Figure 10 includes not only the structure visible in the cross-section, but also structures such as through-holes and wiring layers that are visible through the cross-section. The power converter 3 has a structure in which semiconductor devices 1a and 1b are embedded in a printed circuit board 30. The printed circuit board 30 is a multilayer wiring board (for example, a double-sided wiring board) having a plurality of wiring layers, a plurality of insulating boards (or insulating layers), and a core material.
[0069] As shown in Figures 9 and 10, the power converter 3 includes a plurality of semiconductor devices 1a and 1b, a core material (or insulating material) 31, insulating plates (or insulating layers) 32 and 33, through-holes 34a, 34b, 34c, 34d, and 34e, wiring layers 35a, 35b, 36a, 36b, 36c, 36d, 37a, 37b, and 37c, an input terminal TIN, an output terminal TOUT, gate terminals TG1 and TG2, and a ground terminal TVSS (i.e., a voltage VSS node), an inductor L1, and capacitors C1 and C2. Capacitors C1 and C2 are provided in positions not shown. Each of the insulating plates 32 and 33 is, for example, in the form of a sheet and is an insulating material made of carbon fiber impregnated with a thermosetting resin.
[0070] As shown in Figure 10, semiconductor device 1a is provided between insulating plate 32 and insulating plate 33 in the Z direction, and between core materials 31 in the X and Y directions. Similarly, semiconductor device 1b is provided between insulating plate 32 and insulating plate 33 in the Z direction, and between core materials 31 in the X and Y directions.
[0071] In other words, semiconductor devices 1a and 1b are provided spaced apart on the insulating plate 32. An insulating plate 33 is provided on semiconductor devices 1a and 1b. Core material 31 is provided on the sides of semiconductor devices 1a and 1b. That is, the core material 31 is provided so as to cover the side of semiconductor device 1a. Similarly, the core material 31 is provided so as to cover the side of semiconductor device 1b.
[0072] An input terminal TIN, an output terminal TOUT, gate terminals TG1 and TG2, and a ground terminal TVSS are provided on the insulating plate 33.
[0073] Through-holes 34a and 34b are provided in the insulating plate 33 and the core material 31. Each of the through-holes 34a and 34b extends in the Z direction within the insulating plate 33 and the core material 31. Through-holes 34c, 34d, and 34e are provided in the insulating plate 33. The through-holes 34c, 34d, and 34e extend in the Z direction within the insulating plate 33.
[0074] A wiring layer 35a is provided between the drain electrode plate 11 and the insulating plate 32 of the semiconductor device 1a. The wiring layer 35a extends diagonally with respect to the X and Y directions. A wiring layer 36a is provided between the source electrode plate 12 and the insulating plate 33 of the semiconductor device 1a. The wiring layer 36a extends in the X direction.
[0075] A wiring layer 35b is provided between the drain electrode plate 11 and the insulating plate 32 of the semiconductor device 1b. The wiring layer 35b extends in the X and Y directions. A wiring layer 36b is provided between the source electrode plate 12 and the insulating plate 33 of the semiconductor device 1b. The wiring layer 36b extends in the X direction. Furthermore, wiring layers 37a, 37b, and 37c are provided on the insulating plate 33. The wiring layers 37a, 37b, and 37c extend in either the X or Y direction.
[0076] The input terminal TIN is connected to the through-hole 34a. The through-hole 34a is connected to the wiring layer 35a. Furthermore, the wiring layer 35a is connected to the drain electrode plate 11 of the semiconductor device 1a.
[0077] The source electrode plate 12 of the semiconductor device 1a is connected to the wiring layer 36a. The wiring layer 36a is connected to the through-hole 34b. The through-hole 34b is connected to the wiring layer 35b. Furthermore, the wiring layer 35b is connected to the drain electrode plate 11 of the semiconductor device 1b. The through-hole 34b is also connected to the first end of the inductor LI via the wiring layer 37a. The second end of the inductor LI is connected to the output terminal TOUT via the wiring layer 37b. The inductor L1 is surface-mounted, for example, on a printed circuit board 30.
[0078] The source electrode plate 12 of the semiconductor device 1b is connected to the wiring layer 36b. The wiring layer 36b is connected to the through-hole 34e. The through-hole 34e is connected to the terminal TVSS.
[0079] The gate electrode plate 13 of semiconductor device 1a is connected to a through-hole 34c via a wiring layer 36c. The through-hole 34c is connected to a gate terminal TG1. The gate electrode plate 13 of semiconductor device 1b is connected to a through-hole 34d via a wiring layer 36d. The through-hole 34d is connected to a gate terminal TG2 via a wiring layer 37c. Gate drivers GD are connected to gate terminals TG1 and TG2.
[0080] The main effects of the third embodiment are described below.
[0081] According to the configuration of the third embodiment described above, semiconductor devices 1a and 1b can be easily embedded and mounted on a printed circuit board, and a power conversion device, such as a DC-DC converter, can be formed in a small area. Other effects are the same as in the first embodiment.
[0082] 4. Fourth Embodiment A power conversion device of the fourth embodiment will be described. The fourth embodiment describes a power conversion device equipped with multiple semiconductor devices of the first and second embodiments. Here, as with the third embodiment, a DC-DC converter will be shown as an example. The fourth embodiment will mainly describe the differences from the first to third embodiments.
[0083] The power converter of the fourth embodiment has a semiconductor device 2a instead of semiconductor device 1b in the third embodiment. The other circuit configurations are the same as those of the third embodiment shown in Figure 8.
[0084] The planar layout and cross-sectional structure of the power converter according to the fourth embodiment will be described below. Figure 11 is a top view of the power converter according to the fourth embodiment. Figure 12 is a cross-sectional view of the power converter shown in Figure 11 along line XX. Note that the cross-sectional view shown in Figure 12 includes not only the structure visible in the cross-section, but also structures such as through-holes and wiring layers that are visible through the cross-section. The power converter 4 has a structure in which semiconductor devices 1a and 2a are embedded in a printed circuit board 40. The printed circuit board 40 is a multilayer wiring board having a plurality of wiring layers, a plurality of insulating boards (or insulating layers), and a core material.
[0085] As shown in Figures 11 and 12, the power converter 4 includes a plurality of semiconductor devices 1a and 2a, a core material (or insulating material) 41, insulating plates (or insulating layers) 42 and 43, through-holes 44a, 44b, 44c, 44d, and 44e, wiring layers 45a, 45b, 45c, 46a, 46b, 47a, and 47b, an input terminal TIN, an output terminal TOUT, gate terminals TG1 and TG2, and a ground terminal TVSS (i.e., a voltage VSS node), an inductor L1, and capacitors C1 and C2. Capacitors C1 and C2 are provided in positions not shown. Each of the insulating plates 42 and 43 is, for example, a sheet-like insulating material made of carbon fiber impregnated with a thermosetting resin.
[0086] As shown in Figure 12, semiconductor device 1a is provided between insulating plate 42 and insulating plate 43 in the Z direction, and between core materials 41 in the X and Y directions. Similarly, semiconductor device 2a is provided between insulating plate 42 and insulating plate 43 in the Z direction, and between core materials 41 in the X and Y directions.
[0087] In other words, semiconductor devices 1a and 2a are provided spaced apart on the insulating plate 42. An insulating plate 43 is provided on semiconductor devices 1a and 2a. Core material 41 is provided on the sides of semiconductor devices 1a and 2a. That is, the core material 41 is provided so as to cover the side of semiconductor device 1a. Similarly, the core material 41 is provided so as to cover the side of semiconductor device 2a.
[0088] An input terminal TIN, an output terminal TOUT, gate terminals TG1 and TG2, and a ground terminal TVSS are provided on the insulating plate 43.
[0089] Through-holes 44a, 44b, 44c, and 44d are provided within the insulating plate 43 and the core material 41. Each of the through-holes 44a, 44b, 44c, and 44d extends in the Z direction within the insulating plate 43 and the core material 41. A through-hole 44e is provided within the insulating plate 43. The through-hole 44e extends in the Z direction within the insulating plate 43.
[0090] A wiring layer 45a is provided between the drain electrode plate 11 and the insulating plate 42 of the semiconductor device 1a. The wiring layer 45a extends diagonally with respect to the X and Y directions. A wiring layer 46a is provided between the source electrode plate 12 and the insulating plate 43 of the semiconductor device 1a. The wiring layer 46a extends in the X direction. A wiring layer 46b is provided between the gate electrode plate 13 and the insulating plate 43 of the semiconductor device 1a. The wiring layer 46b extends in the Y direction.
[0091] A wiring layer 45b is provided between the source electrode plate 12 and the insulating plate 42 of the semiconductor device 2a. The wiring layer 45b extends in the X direction. A wiring layer 45c is provided between the gate electrode plate 13 and the insulating plate 42 of the semiconductor device 2a. The wiring layer 45c extends in both the X and Y directions. A wiring layer 46a is provided between the drain electrode plate 11 and the insulating plate 43 of the semiconductor device 2a. Furthermore, wiring layers 47a and 47b are provided on the insulating plate 43. The wiring layers 47a and 47b extend in the X direction.
[0092] The input terminal TIN is connected to the through-hole 44a. The through-hole 44a is connected to the wiring layer 45a. Furthermore, the wiring layer 45a is connected to the drain electrode plate 11 of the semiconductor device 1a.
[0093] The source electrode plate 12 of semiconductor device 1a is connected to wiring layer 46a. The wiring layer 46a is connected to through-hole 44c. The through-hole 44c is connected to the first end of inductor LI via wiring layer 47a. Furthermore, the wiring layer 46a is connected to the drain electrode plate 11 of semiconductor device 2a. The second end of inductor LI is connected to output terminal TOUT via wiring layer 47b.
[0094] The source electrode plate 12 of the semiconductor device 1b is connected to the wiring layer 45a. The wiring layer 45a is connected to the through-hole 44d. The through-hole 44d is connected to the terminal TVSS.
[0095] The gate electrode plate 13 of semiconductor device 1a is connected to a through-hole 44e via a wiring layer 46b. The through-hole 44e is connected to a gate terminal TG1. The gate electrode plate 13 of semiconductor device 2a is connected to a through-hole 44b via a wiring layer 45c. The through-hole 44b is connected to a gate terminal TG2. A gate driver GD is connected to gate terminals TG1 and TG2.
[0096] The main effects of the fourth embodiment are described below.
[0097] According to the configuration of the fourth embodiment described above, semiconductor devices 1a and 1b can be easily embedded and mounted on a printed circuit board, and a power conversion device, such as a DC-DC converter, can be formed in a small area. Other effects are the same as in the first embodiment.
[0098] 5. Fifth Embodiment A power conversion device of the fifth embodiment will be described. In the fifth embodiment, a power conversion device equipped with multiple surface-mount semiconductor devices, such as QFN (quad flat non-leaded package) type semiconductor devices, will be described. The fifth embodiment will mainly be described in terms of differences from the third embodiment.
[0099] The cross-sectional structure of the power converter according to the fifth embodiment will be described below. Figure 13 is a cross-sectional view of the power converter according to the fifth embodiment. Note that the cross-sectional view shown in Figure 13 includes not only the structure visible in the cross-section, but also structures such as through-holes and wiring layers that are visible through the cross-section. The power converter 5 has a structure in which semiconductor devices 6a and 6b are embedded in a printed circuit board 50. The printed circuit board 50 is a single-sided wiring board having a single-sided wiring layer, a plurality of insulating boards (or insulating layers), and a core material.
[0100] As shown in Figure 13, the power converter 5 has multiple semiconductor devices 6a and 6b, a core material (or insulating material) 51, insulating plates (or insulating layers) 52 and 53, through holes 54a, 54b, and 54c, wiring layers 55a, 55b, and 55c, a drain terminal 56a, a source terminal 56b, and a gate terminal 56c. Passive elements such as inductors and capacitors are omitted here. Each of the insulating plates 52 and 53 is, for example, in the form of a sheet and is an insulating material made by impregnating carbon fibers with a thermosetting resin.
[0101] Each of the semiconductor devices 6a and 6b comprises a semiconductor chip 10, a drain electrode layer 11a, a source electrode layer 12a, a gate electrode layer 13a, conductive layers 14 and 15, and a mold layer 16, as shown in Figure 13.
[0102] The semiconductor chip 10 constitutes, for example, a MOSFET. The semiconductor chip 10 has a first surface orthogonal to the Z direction and a second surface opposite the first surface. The first surface is the bottom surface of the semiconductor chip 10 shown in Figure 13, and the second surface is the top surface of the semiconductor chip 10 shown in Figure 13. The semiconductor chip 10 has a drain region on the first surface and a source region and a gate region on the second surface.
[0103] The semiconductor chip 10 is provided between the drain electrode layer 11a and the source electrode layer 12a and gate electrode layer 13a. That is, the drain electrode layer 11a is provided below the drain region of the semiconductor chip 10. The source electrode layer 12a is provided on the source region of the semiconductor chip 10. Furthermore, the gate electrode layer 13a is provided on the gate region of the semiconductor chip 10.
[0104] The drain electrode layer 11a has a thin plate shape and includes, for example, a lead frame. The thickness of the drain electrode layer 11a is, for example, 50 μm or more, or 150 μm to 300 μm. Similar to the drain electrode layer 11a, the source electrode layer 12a has a thin plate shape and includes, for example, a lead frame. The thickness of the source electrode layer 12a is, for example, 50 μm or more, or 150 μm to 300 μm. The gate electrode layer 13a has a thin plate shape and includes, for example, a lead frame. The thickness of the gate electrode layer 13a is, for example, 50 μm or more, or 150 μm to 300 μm. The drain electrode layer 11a, the source electrode layer 12a, and the gate electrode layer 13a contain, for example, Cu.
[0105] As shown in Figure 13, semiconductor device 6a is provided between insulating plate 52 and insulating plate 53 in the Z direction, and between core materials 51 in the X and Y directions. Similarly, semiconductor device 6b is provided between insulating plate 52 and insulating plate 53 in the Z direction, and between core materials 51 in the X and Y directions.
[0106] In other words, semiconductor devices 6a and 6b are provided spaced apart on the insulating plate 52. An insulating plate 53 is provided on semiconductor devices 6a and 6b. Core material 51 is provided on the sides of semiconductor devices 6a and 6b. That is, the core material 51 is provided so as to cover the side of semiconductor device 6a. Similarly, the core material 51 is provided so as to cover the side of semiconductor device 6b.
[0107] A drain terminal 56a, a source terminal 56b, and a gate terminal 56c are provided on the lower surface of the insulating plate 52.
[0108] Through-holes 54a, 54b, and 54c are provided within the insulating plate 52. Each of the through-holes 54a, 54b, and 54c extends in the Z direction within the insulating plate 52.
[0109] A wiring layer 55a is provided between the drain electrode layer 11a of the semiconductor device 6a and the insulating plate 52. The wiring layer 55a extends in either the X or Y direction. The source electrode layer 12a of the semiconductor device 6a is led to the lower surface of the semiconductor device 6a by a conductive layer. A wiring layer 55b is provided between the conductive layer of the source electrode layer 12a and the insulating plate 52. The wiring layer 55b extends in either the X or Y direction. The gate electrode layer 13a of the semiconductor device 6a is led to the lower surface of the semiconductor device 6a by a conductive layer. A wiring layer 55c is provided between the conductive layer of the gate electrode layer 13a and the insulating plate 52. The wiring layer 55c extends in either the X or Y direction.
[0110] The drain electrode layer 11a of the semiconductor device 6a is connected to the wiring layer 55a. The wiring layer 55a is connected to the drain terminal 56a via a through-hole 54a. The source electrode layer 12a of the semiconductor device 6a is connected to the wiring layer 55b via a conductive layer. The wiring layer 55b is connected to the source terminal 56b via a through-hole 54b. Furthermore, the gate electrode layer 13a of the semiconductor device 6a is connected to the wiring layer 55c via a conductive layer. The wiring layer 55c is connected to the gate terminal 56c via a through-hole 54c.
[0111] The configuration of semiconductor device 6b, including the members provided on the first surface, second surface, and side surface, is the same as that of semiconductor device 6a, and therefore its description is omitted.
[0112] According to the configuration of the fifth embodiment described above, the number of wiring layers used can be reduced by embedding the semiconductor devices 1a and 2a in a printed circuit board and drawing out the source, drain, and gate wiring onto a single wiring layer. In other words, it is possible to embed the semiconductor devices 1a and 2a in a single-sided printed circuit board. Other effects are the same as in the first embodiment.
[0113] 6. Others In the above embodiment, a DC-DC converter was used as an example of a power conversion device, but the method can be applied not only to DC-DC converters but also to other power conversion devices such as inverters.
[0114] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]
[0115] 1...Semiconductor device, 1a...Semiconductor device, 1b...Semiconductor device, 2...Semiconductor device, 2a...Semiconductor device, 3...Power converter, 4...Power converter, 5...Power converter, 6a...Semiconductor device, 6b...Semiconductor device, 10...Semiconductor chip, 11...Drain electrode plate, 11a...Drain electrode layer, 12...Source electrode plate, 12a...Source electrode layer, 13...Gate electrode plate, 13a...Gate electrode layer, 14...Conductive layer, 15a...Conductive layer, 15b...Conductive layer, 16...Mo 17...Coating layer, 18...Coating film, 20...Semiconductor chip, 21...Drain electrode plate, 22...Source electrode plate, 23...Gate electrode plate, 24...Conductive layer, 25a...Conductive layer, 25b...Conductive layer, 26...Molding layer, 27...Coating film, 28...Coating film, 30...Printed wiring board, 31...Core material, 32...Insulating board, 33...Insulating board, 34a...Through-hole, 34b...Through-hole, 34c...Through-hole, 34d...Through-hole, 34e...Through-hole 35a...Wiring layer, 35b...Wiring layer, 36a...Wiring layer, 36b...Wiring layer, 36c...Wiring layer, 36d...Wiring layer, 37a...Wiring layer, 37b...Wiring layer, 37c...Wiring layer, 40...Printed circuit board, 41...Core material, 42...Insulating board, 43...Insulating board, 44a...Through-hole, 44b...Through-hole, 44c...Through-hole, 44d...Through-hole, 44e...Through-hole, 45a...Wiring layer, 45b...Wiring layer, 45c...Wiring layer, 46a...Wiring layer 46b...Wiring layer, 47a...Wiring layer, 47b...Wiring layer, 50...Printed circuit board, 51...Core material, 52...Insulating board, 53...Insulating board, 54a...Through hole, 54b...Through hole, 54c...Through hole, 55a...Wiring layer, 55b...Wiring layer, 55c...Wiring layer, 56a...Drain terminal, 56b...Source terminal, 56c...Gate terminal, C1...Capacitor, C2...Capacitor, L1...Inductor, TG1...Gate terminal, TG2...Gate terminal.
Claims
1. A semiconductor chip having a drain region on a first surface and a source region and a gate region on a second surface facing the first surface, A drain electrode plate provided in the drain region, A source electrode plate provided in the source region, A gate plate provided in the gate region, A molded layer provided on the side surface of the semiconductor chip, the source electrode plate, and the gate electrode plate, The first coating film is provided on the lower surface and side surface of the drain electrode plate, the upper surface of the source electrode plate, and the upper surface of the gate electrode plate. A second coating film provided on the upper and side surfaces of the mold layer, A semiconductor device equipped with the following.
2. The semiconductor device according to claim 1, wherein each of the drain electrode plate, the source electrode plate, and the gate electrode plate contains Cu and has a thickness of 50 μm or more.
3. The semiconductor device according to claim 1, wherein each of the drain electrode plate, the source electrode plate, and the gate electrode plate contains Cu and has a thickness of 150 μm or more and 300 μm or less.
4. The semiconductor chip further comprises a first electrode layer provided between the drain region and the drain electrode plate, The semiconductor device according to claim 1, wherein the first electrode layer includes one of the following: a multilayer structure of Al, Ni, Au; a multilayer structure of Al, Ni, Pd, Au; a multilayer structure of Al, Cu; or a single-layer structure of Cu.
5. The first electrode layer and the drain electrode plate are further provided with a first conductive layer, The semiconductor device according to claim 4, wherein the first conductive layer comprises at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
6. The semiconductor chip further comprises a second electrode layer provided between the source region and the source electrode plate, and a third electrode layer provided between the gate region and the gate electrode plate of the semiconductor chip. The semiconductor device according to claim 1, wherein each of the second electrode layer and the third electrode layer includes one of the following: a laminated structure of Al, Ni, Au, a laminated structure of Al, Ni, Pd, Au, a laminated structure of Al, Cu, or a single-layer Cu structure.
7. The present invention further comprises a second conductive layer provided between the second electrode layer and the source electrode plate, and a third conductive layer provided between the third electrode layer and the gate electrode plate. The semiconductor device according to claim 6, wherein each of the second conductive layer and the third conductive layer comprises at least one of Ag, Cu, CuSn, AgSn, AuSn, and PbSn.
8. The semiconductor device according to claim 1, wherein the first coating film comprises benzotriazole (BTA).
9. The semiconductor device according to claim 1, wherein the first coating film is one of the following: a film containing Sn, a film containing Ni and Au, or a film containing Ni, Pd and Au.
10. The structure has a stacked configuration in which the drain electrode plate, the semiconductor chip, and the source electrode plate are arranged in that order. The semiconductor device according to claim 1, wherein the thickness of the laminated structure is 500 μm or less.