Tensile nitride deposition system and method

Abstract

An exemplary semiconductor processing method may include flowing a deposition gas, which may include a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas, into a substrate processing region of a substrate processing chamber. The flow ratio of the nitrogen-containing precursor to the silicon-containing precursor may be about 1:1 or greater. The method may further include generating a deposition plasma from the deposition gas to form a silicon- and nitrogen-containing layer on the substrate in the substrate processing chamber. The silicon- and nitrogen-containing layer may be treated with a treatment plasma. The treatment plasma is formed from a carrier gas that does not include the silicon-containing precursor. The flow rate of the carrier gas in the treatment plasma may be greater than the flow rate of the carrier gas in the deposition plasma.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 17 / 078,793, filed on October 23, 2020, entitled "TENSILE NITRIDE DEPOSITION SYSTEMS AND METHODS", the content of which is incorporated herein by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to semiconductor systems and processes. More specifically, this technology relates to deposition systems and methods by which a tensile silicon nitride layer can be formed.

Background Art

[0003]

[0003] Integrated circuits are enabled by a process of generating complexly patterned material layers on a substrate surface. To produce patterned materials on a substrate, a controlled method of forming and removing exposed materials is required. Material properties can affect how a device operates and can also affect how films are removed relative to each other. Plasma - enhanced deposition can produce films with certain properties. Many of the films formed require additional processing to adjust or improve the material properties of the film in order to provide suitable properties.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high - quality devices and structures. This technology addresses these needs and others.

Summary of the Invention

[0005]

[0005] Embodiments of the present technology include systems and methods for forming a tensile silicon nitride layer on a substrate. In some embodiments, the tensile nitride layer may act as an etching stop layer, a CMP stop layer, or a hard mask layer in a front-end-of-line or middle-end-of-line semiconductor manufacturing process. The high tensile stress of the nitride layer can reduce the line edge roughness (LER) and line width roughness (LWR) of holes, channels, trenches, and other types of openings formed in one or more patterning layers deposited above or below the tensile nitride layer. As the critical dimensions of semiconductor device structures such as nMOS transistors continue to shrink, the need for such precisely patterned openings is increasing.

[0006]

[0006] Embodiments of the present technology include a semiconductor processing method which may include introducing a deposition gas containing a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas into a substrate processing region of a substrate processing chamber. The flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be about 1:1 or greater. The method may further include generating a deposition plasma from the deposition gas to form a silicon-nitrogen-containing layer on a substrate in the substrate processing chamber. The silicon-nitrogen-containing layer may be processed with the processing plasma. The processing plasma is formed from a carrier gas that does not contain the silicon-containing precursor. The flow rate of the carrier gas in the processing plasma may be greater than the flow rate of the carrier gas in the deposition plasma.

[0007]

[0007] In exemplary embodiments, the nitrogen-containing precursor may contain ammonia, and the silicon-containing precursor may contain silane. The nitrogen-containing precursor may be characterized by a flow rate of about 100 sccm or more, and the silicon-containing precursor may be characterized by a flow rate of about 50 sccm or more. In additional embodiments, the carrier gas may contain at least one of molecular nitrogen (N2) and argon. The molecular nitrogen in the carrier gas may be characterized by a flow rate of about 5000 sccm or more, and the argon in the carrier gas may be characterized by a flow rate of about 2000 sccm or more. In yet additional embodiments, the processing chamber may be characterized by a deposition chamber pressure during the deposition of the silicon-nitrogen-containing layer that is lower than the processing chamber pressure during processing of the silicon-nitrogen-containing layer. In further embodiments, the deposition plasma may be generated by supplying plasma power of about 60 watts or less to the deposition gas. In further embodiments, the processing plasma may be generated by supplying plasma power of about 100 watts or more to a carrier gas that does not contain the silicon-containing precursor.

[0008]

[0008] In further exemplary embodiments, the silicon-nitrogen-containing layer may be formed at a deposition rate of about 10 Å / second or less. In further embodiments, the treatment method may produce a treated silicon-nitrogen-containing layer which is a silicon nitride layer characterized by a tensile stress of about 1 GPa or more and a wet etching rate of about 20 Å / min or less.

[0009]

[0009] Embodiments of the present technology may also include a semiconductor processing method comprising depositing a silicon-nitrogen-containing layer on a substrate in a substrate processing region of a substrate processing chamber. The silicon-nitrogen-containing layer may be deposited using a deposition plasma generated at a first plasma power from a deposition gas containing a nitrogen-containing precursor and a silicon-containing precursor. In some embodiments, the flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor is about 1:1 or greater. In additional embodiments, the silicon-nitrogen-containing layer may be formed at a deposition rate of about 10 Å / second or less. The method may further include processing the silicon-nitrogen-containing layer with a processing plasma. The processing plasma may be formed at a second plasma power greater than the first plasma power. This processing method may produce a silicon-nitrogen-containing layer characterized by a tensile stress of about 1 GPa or greater and a wet etching rate of about 20 Å / min or less.

[0010]

[0010] In exemplary embodiments, the processing plasma may be formed from a processing gas that does not contain a silicon-containing precursor or a nitrogen-containing precursor. In further embodiments, the processing plasma may be formed from a processing gas that contains molecular nitrogen (N2). In further embodiments, molecular nitrogen may be supplied to the semiconductor processing chamber at a nitrogen flow rate of about 10,000 sccm or more. This processing method can produce a silicon-nitrogen-containing layer, which is a silicon nitride layer characterized by about 3 atomic percent or less of hydrogen.

[0011]

[0011] Embodiments of the present technology include a semiconductor processing method which may include forming a silicon nitride layer in two or more cycles, which may include depositing a portion of the silicon nitride layer on a substrate in a substrate processing area of ​​a substrate processing chamber and processing a portion of the silicon nitride layer with a processing plasma. The portion of the silicon nitride layer may be deposited to a thickness of about 15 Å or less. In some embodiments, each portion of the silicon nitride layer may be formed at a deposition rate of about 10 Å / second. In additional embodiments, the processing step on each portion of the deposited silicon nitride layer may be carried out for about 15 seconds or less. The processing plasma may increase the tensile stress and wet etching rate of the processed portion of the silicon nitride layer compared to the portion when it was deposited. The processed portion of the silicon nitride layer may also be characterized by a hydrogen level of about 3 atomic% (at.%) or less.

[0012]

[0012] In exemplary embodiments, a portion of the silicon nitride layer may be deposited from a deposition plasma generated from a deposition gas supplied to a substrate processing chamber. The deposition gas may contain a nitrogen-containing precursor and a silicon-containing precursor. In some embodiments, the nitrogen-containing precursor may be characterized by a flow rate of about 200 sccm or less, and the silicon-containing precursor may be characterized by a flow rate of less than 100 sccm. This processing method can produce a silicon nitride layer characterized by a tensile stress of about 1 GPa or more and a wet etching rate of about 20 Å / min or less.

[0013]

[0013] Such techniques can offer numerous advantages over conventional systems and methods for forming silicon nitride layers. For example, in embodiments in which the carrier gas flow rate is increased when transitioning from deposition to processing, the tensile stress in the processed silicon-nitrogen-containing material deposited on the substrate can increase by a greater amount and in a shorter period of time than observed in conventional deposition and processing methods. In addition, in embodiments in which the amount of processing plasma power for generating the processing plasma is greater than the amount of deposition plasma power for generating the deposition plasma, the final tensile stress level in the silicon-nitrogen-containing material can also increase. In further embodiments, the technique can produce a silicon-nitrogen-containing layer with a lower atomic percentage of hydrogen than observed in conventional deposition and processing methods. A lower atomic percentage of hydrogen can further increase the tensile stress level and reduce the wet etching rate of the silicon-nitrogen-containing layer. Embodiments of the technique, along with many of their advantages and features, will be described in more detail below in conjunction with the accompanying drawings.

[0014]

[0014] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0015] [Figure 1A]

[0015] An exemplary top plan view of a processing system according to several embodiments of the present technology is shown. [Figure 1B]

[0016] A schematic cross-sectional view of an exemplary processing system according to several embodiments of this technology is shown. [Figure 2]

[0017] The following describes the steps of an exemplary method for semiconductor processing according to several embodiments of this technology. [Figure 3]

[0018] Figures A and B show cross-sectional views of exemplary semiconductor structures according to several embodiments of the present technology. [Modes for carrying out the invention]

[0016]

[0019] Some drawings are included as schematic diagrams. It should be understood that drawings are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0017]

[0020] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same kind may be distinguished according to their reference numerals by letters that distinguish similar components from each other. Where only the first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0018]

[0021] This technology includes embodiments of a system and processing method for forming a tensile silicon nitride layer on a semiconductor substrate. In particular, this tensile nitride layer addresses the difficulty of forming more precise channels, contacts, vias, trenches, and other types of openings in the patterning material on the substrate. Conventional low-stress nitride layers placed between the patterning material and the semiconductor material of the substrate lack the ability to highly align and maintain the smoothness of the sidewalls of the patterned openings. Therefore, patterning processes using such low-stress nitride layers result in rough openings characterized by large line-edge roughness (LER) and line-width roughness (LWR) along the sidewalls formed in the patterning material between the patterned photoresist layer and the nitride etching stop layer, or due to distortion of hard mask dimensions. As the critical dimensions of semiconductor devices such as nMOS transistors continue to decrease, the roughness of these openings becomes a greater problem. The degree of roughness of openings formed by such conventional methods often exceeds the tolerances of the critical dimensions of substrate features required for stable and functional integrated circuits.

[0019]

[0022] One technique to reduce the roughness of these openings is to form them on a silicon nitride layer with increased tensile stress. This increase in tensile stress improves the properties of the adjacent patterned material and reduces the tendency for the material to etch at a non-uniform rate in the lateral direction. Openings formed in the patterned material are characterized by reduced line edge roughness (LER) and line width roughness (LWR) along their sidewalls. Unfortunately, forming a silicon nitride layer with increased tensile stress is generally more difficult than forming a conventional low-stress nitride layer. Tensile stress can be increased in nitride layers deposited by plasma chemical vapor deposition of silicon-nitrogen-hydrogen-containing precursors by reducing the number of Si-H and NH bonds and increasing the number of Si-N bonds in the nitride layer when it is deposited. The reduction in the number of Si-H and NH bonds may be a result of hydrogen being removed from the layer when it is deposited. As Si and N atoms enter the spaces left by the removed hydrogen atoms and form more Si-N bonds, the overall tensile stress of the nitride layer increases. Forming nitride layers with high tensile stress presents an additional challenge: it requires an extra step to remove hydrogen atoms from the deposited layer.

[0020]

[0023] One method for treating a deposited silicon nitride layer to increase tensile stress is to expose the deposited layer to ultraviolet light. Unfortunately, UV treatment can have several drawbacks, including the low transmittance of UV light through the deposited layer and the need for additional equipment to generate and focus the light onto the substrate. Often, it is not practical to integrate the UV treatment equipment into the nitride deposition chamber, and the substrate with the nitride material deposited must be moved to a separate chamber for UV treatment. Since UV treatment equipment is generally designed to transmit less than about 5-10 Å through the deposited nitride, the substrate may have to travel back and forth between the nitride deposition chamber and the UV treatment chamber many times to fabricate the entire layer. This can significantly increase the time and complexity required to form a tensile silicon nitride layer on a substrate using the UV treatment process.

[0021]

[0024] Embodiments of the present technology address these and other problems with conventional systems and methods for forming a tensile silicon-nitrogen-containing layer by depositing and processing a silicon-nitrogen-containing layer on a substrate in a single processing chamber. Embodiments of the processing method include increasing the flow rate of a carrier gas between depositing a stress-free silicon-nitrogen-containing layer on a substrate and treating the deposited nitride with a processing plasma to form a silicon-nitrogen-containing layer having a tensile stress of about 1 GPa or more. In these embodiments, the flow rate of one or more deposition precursors is decreased or stopped while the flow rate of the carrier gas included in the deposition precursor is increased. In some embodiments, the carrier gas continuously flows into the processing chamber during the deposition and processing steps, and the carrier gas flow rate may be lower than the initial flow rate during the deposition step until the processing step is completed. In embodiments where the carrier gas flow rate increases between the deposition step and the processing step, the tensile stress in the processed silicon-nitrogen-containing layer can increase in a greater amount and in a shorter period than observed with conventional deposition and processing methods.

[0022]

[0025] In additional embodiments of the processing method, the plasma power can increase in the transition from a deposition plasma for depositing the silicon-nitrogen-containing layer to a processing plasma for increasing the tensile stress of the layer. In some embodiments, the plasma power may not be interrupted during the transition from the deposition plasma to the processing plasma. This can shorten the time for each deposition-treatment cycle for forming a silicon-nitrogen-containing layer with tensile stress. In embodiments where several deposition-treatment cycles are performed to complete the formation of the layer, a cumulative reduction in processing time can be significant. In further embodiments, as the plasma power increases, the tensile stress level in the fully formed silicon-nitrogen-containing layer can also increase.

[0023]

[0026] In further additional embodiments of this technology, tensile silicon-nitrogen-containing layers manufactured by the system and method embodiments may have a reduced hydrogen content compared to tensile layers manufactured by conventional methods. In embodiments, the tensile silicon-nitrogen-containing layers may have atomic hydrogen of about 3 atomic percent or less. Due to the low hydrogen level in the silicon-nitrogen-containing layers, the number of Si-H and NH bonds in the layer may decrease, while the number of Si-N bonds may increase. In embodiments, an increase in the molar ratio of Si-N bonds to Si-H and NH bonds may increase the amount of tensile stress in the layer. In further embodiments, an increase in the molar ratio may also decrease the wet etching rate of the silicon-nitrogen-containing layers. This makes these layers more effective as etching stop layers or hard masks in semiconductor manufacturing processes in some embodiments.

[0024]

[0027] After describing a general configuration of a chamber configured to perform operations according to embodiments of this technique in which plasma processing can be carried out, specific methodologies and component configurations may be described. Since this technique can be used to improve many film formation processes and can be applied to various processing chambers and operations, it should be understood that this technique is not intended to be limited to the specific films and processes described.

[0025]

[0028] Figure 1A is a top view of one embodiment of a processing system 10 including a deposition chamber, a processing chamber, an etching chamber, a baking chamber, and a curing chamber according to an embodiment. In the figure, a pair of front-opening unified pods 12 are received by a robot arm 14 and placed in a low-pressure holding area 16 before being placed in one of the substrate processing chambers 18a-f positioned in tandem sections 19a-c, supplying substrates of various sizes. A second robot arm 11 may be used to transfer the substrate wafer from the holding area 16 to and from the substrate processing chambers 18a-f. Each substrate processing chamber 18a-f can be equipped to perform some substrate processing operations including the formation of a stack of semiconductor materials described herein, in addition to other substrate processing such as plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and plasma processing, annealing, ashing, etc.

[0026]

[0029] The substrate processing chambers 18a-f can include one or more system components for depositing, plasma processing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers, such as 18c-d and 18e-f, are used to deposit a dielectric material on a substrate, and a third pair of processing chambers, such as 18a-b, can be used to process the deposited dielectric. In another configuration, all three pairs of chambers, such as 18a-f, can be configured to deposit and process a stack of dielectric films alternately arranged on a substrate. Any one or more of the described processes can be performed in a chamber separated from the manufacturing apparatus shown in different embodiments. It will be understood that additional configurations of deposition chambers, processing chambers, etching chambers, annealing chambers, and curing chambers for dielectric films are contemplated by the system 10.

[0027]

[0030] Figure 1B shows a cross-sectional view of an exemplary processing chamber 100 according to several embodiments of the present technology. This figure may illustrate an overview of a system that may be specifically configured to incorporate one or more aspects of the present technology and / or to perform one or more steps according to embodiments of the present technology. Additional details of the chamber 100 or the method performed may be described further below. While the chamber 100 may be used to form a tensile nitride film according to several embodiments of the present technology, it will be understood that the method may be similarly performed in any chamber in which film formation may take place. The processing chamber 100 may include a chamber body 102, a substrate support 104 disposed inside the chamber body 102, and a lid assembly 106 connected to the chamber body 102 and surrounding the substrate support 104 in the processing space 120. The substrate 103 may be provided to the processing space 120 through an opening 126, which may be conventionally sealed for processing using a slit valve or a door. The substrate 103 may be placed on the surface 105 of the substrate support during processing. The substrate support 104 may be rotatable along an axis 147 in which the shaft 144 of the substrate support 104 may be located, as indicated by the arrow 145. Alternatively, the substrate support 104 may be lifted to rotate as needed during the deposition process.

[0028]

[0031] The plasma profile modulator 111 may be located within the processing chamber 100 to control the plasma distribution across the substrate 103 placed on the substrate support 104. The plasma profile modulator 111 may include a first electrode 108 located adjacent to the chamber body 102, which can isolate the chamber body 102 from other components of the lid assembly 106. The first electrode 108 may be part of the lid assembly 106 or a separate sidewall electrode. The first electrode 108 may be an annular or ring-shaped member and may be a ring electrode. The first electrode 108 may be a continuous loop around the outer circumference of the processing chamber 100 surrounding the processing space 120, or may be discontinuous at selected locations if desired. The first electrode 108 may also be a perforated electrode, such as a perforated ring or mesh electrode, or a flat plate electrode, such as a secondary gas distributor.

[0029]

[0032] One or more isolators 110a, 110b, which may be dielectric materials such as ceramics or metal oxides, such as aluminum oxide and / or aluminum nitride, may contact the first electrode 108 to electrically and thermally isolate the first electrode 108 from the gas distributor 112 and the chamber body 102. The gas distributor 112 may define openings 118 for distributing the process precursor into the processing space 120. The gas distributor 112 may be connected to a first power source 142, such as an RF generator, an RF power supply, a DC power supply, a pulsed DC power supply, a pulsed RF power supply, or any other power supply that may be connected to the processing chamber. In some embodiments, the first power source 142 may be an RF power supply.

[0030]

[0033] The gas distributor 112 may be a conductive or non-conductive gas distributor. Furthermore, the gas distributor 112 may be formed from conductive and non-conductive components. For example, the body of the gas distributor 112 may be conductive while the faceplate of the gas distributor 112 is non-conductive. The gas distributor 112 may be powered by a first power source 142, such as the one shown in Figure 1, or, in some embodiments, the gas distributor 112 may be coupled with ground.

[0031]

[0034] The first electrode 108 may be connected to a first tuning circuit 128 that can control the grounding path of the processing chamber 100. The first tuning circuit 128 may include a first electronic sensor 130 and a first electronic controller 134. The first electronic controller 134 may be a variable capacitor or other circuit element, or may include one. The first tuning circuit 128 may be one or more inductors 132, or may include one. The first tuning circuit 128 may be any circuit that enables a variable or controllable impedance under the plasma conditions present in the processing space 120 during processing. In some embodiments as illustrated, the first tuning circuit 128 may include a first circuit leg and a second circuit leg connected in parallel between ground and the first electronic sensor 130. The first circuit leg may include a first inductor 132A. The second circuit leg may include a second inductor 132B connected in series with the first electronic controller 134. A second inductor 132B may be positioned between the first electronic controller 134 and a node that couples both the first and second circuit legs to the first electronic sensor 130. The first electronic sensor 130 is a voltage or current sensor connected to the first electronic controller 134 and may allow for some degree of closed-loop control of the plasma conditions inside the processing space 120.

[0032]

[0035] The second electrode 122 may be connected to the substrate support 104. The second electrode 122 may be embedded within the substrate support 104 or connected to the surface of the substrate support 104. The second electrode 122 may be a plate, a perforated plate, a mesh, a wire screen, or other distributed arrangement of conductive elements. The second electrode 122 may also be a tuning electrode and may be connected to a second tuning circuit 136 by a conduit 146, such as a cable with a selected resistance, such as 50 ohms, located within the shaft 144 of the substrate support 104. The second tuning circuit 136 may have a second electronic sensor 138 and a second electronic controller 140, the second electronic controller 140 may be a second variable capacitor. The second electronic sensor 138 is a voltage or current sensor and may be connected to the second electronic controller 140 to provide further control over the plasma conditions in the processing space 120.

[0033]

[0036] A third electrode 124, which may be a bias electrode and / or an electrostatic chuck electrode, may be connected to a substrate support 104. The third electrode is connected to a second power source 150 through a filter 148, which may be an impedance matching circuit. The second power source 150 may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second power source 150 may be RF bias power.

[0034]

[0037] The lid assembly 106 and substrate support 104 in Figure 1B can be used with any processing chamber for plasma or heat treatment. In operation, the processing chamber 100 may allow real-time control of plasma conditions within the processing space 120. The substrate 103 is placed on the substrate support 104, and process gas can be flowed through the lid assembly 106 using the inlet 114 according to any desired flow plan. The gas can exit the processing chamber 100 through the outlet 152. Power may be connected to a gas distributor 112 to establish plasma within the processing space 120. In some embodiments, the substrate may be electrically biased using a third electrode 124.

[0035]

[0038] When the plasma in the processing space 120 is excited, a potential difference can be established between the plasma and the first electrode 108. A potential difference can also be established between the plasma and the second electrode 122. Next, electronic controllers 134 and 140 can be used to adjust the flow characteristics of the ground path, represented by two tuning circuits 128 and 136. Setpoints can be provided for the first tuning circuit 128 and the second tuning circuit 136 to provide independent control of the deposition rate and the uniformity of the plasma density from the center to the edge. In embodiments where both electronic controllers are variable capacitors, electronic sensors can independently adjust the variable capacitors to maximize the deposition rate and minimize thickness non-uniformity.

[0036]

[0039] Each of the tuning circuits 128 and 136 may have a variable impedance that can be adjusted using their respective electronic controllers 134 and 140. If the electronic controllers 134 and 140 are variable capacitors, the capacitance range of each variable capacitor, and the inductances of the first inductor 132A and the second inductor 132B may be selected to provide an impedance range. This range depends on the frequency and voltage characteristics of the plasma, and there may be a minimum value in the capacitance range of each variable capacitor. Therefore, when the capacitance of the first electronic controller 134 is at its minimum or maximum, the impedance of the first tuning circuit 128 becomes high, which may result in a plasma shape with minimal air or lateral coverage on the substrate support. As the capacitance of the first electronic controller 134 approaches the value that minimizes the impedance of the first tuning circuit 128, the air coverage of the plasma may grow to its maximum, effectively covering the entire working area of ​​the substrate support 104. If the capacitance of the first electronic controller 134 deviates from the minimum impedance setting, the plasma shape may contract away from the chamber wall, reducing the air coverage of the substrate support. The second electronic controller 140 has a similar effect, and since the capacitance of the second electronic controller 140 can be changed, the air coverage of the plasma on the substrate support can be increased or decreased.

[0037]

[0040] Electronic sensors 130 and 138 may be used to tune their respective circuits 128 and 136 in a closed loop. Depending on the type of sensor used, a current or voltage setpoint may be set for each sensor, and control software may be provided to the sensors to determine the adjustments to their respective electronic controllers 134 and 140, minimizing deviations from the setpoint. As a result, the plasma shape may be selected and dynamically controlled during processing. The above discussion is based on electronic controllers 134 and 140, which may be variable capacitors, but it will be understood that any electronic component with adjustable characteristics may be used to provide tuning circuits 128 and 136 with adjustable impedance.

[0038]

[0041] Figure 2 shows exemplary steps in the deposition method 200 according to several embodiments of the present technology. The method can be performed in various processing chambers, including the processing chamber 100 described above. The method includes performing a purging step after deposition, which may limit particle deposition on the substrate. Method 200 may include a number of optional steps, which may or may not be particularly related to some embodiments of the method according to the present technology. For example, many of the steps are described to provide a broader range of structure formation, but may not be important to the present technology or may be performed by alternative methodologies that would be easily understood.

[0039]

[0042] Method 200 may include additional steps before commencing the listed steps. For example, the additional processing steps may include forming a structure on the semiconductor substrate, which may include both forming and removing material. The prior processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is brought into the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include supplying the semiconductor substrate to the processing area of ​​a semiconductor processing chamber such as the processing chamber 100 described above, or to the processing area of ​​another chamber which may include the components described above. The substrate may be a pedestal such as the substrate support 104, and may be deposited on the substrate support, which may be placed in the processing area of ​​a chamber such as the processing space 120 described above.

[0040]

[0043] Embodiments of the processing method 200 for forming a tensile silicon-nitrogen-containing layer may include introducing a deposition precursor into the substrate processing region of a substrate processing chamber 205. Embodiments of the deposition precursor may include at least one silicon-containing precursor and at least one nitrogen-containing precursor. Embodiments of the silicon-containing precursor may include, in particular, silane and disilane. Embodiments of the nitrogen-containing precursor may include, in particular, ammonia (NH3) and a mixture of molecular nitrogen and hydrogen (N2+H2). In further embodiments, the deposition precursor may also include at least one carrier gas. Embodiments of the carrier gas may include, in particular, molecular nitrogen (N2) and argon.

[0041]

[0044] In some embodiments, the nitrogen-containing deposition precursor may be introduced into the substrate processing area of ​​the processing chamber at a flow rate greater than or equal to the approximate flow rate of the silicon-containing deposition precursor. For example, the flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be about 1:1 or greater, about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, or greater. In additional examples, the flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be silicon-rich. In embodiments, the flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor may be about 1:5 or less, about 1:10 or less, or less. In further embodiments, the deposition carrier gas may be introduced into the substrate processing area of ​​the processing chamber at a flow rate greater than the combined flow rates of the nitrogen-containing and silicon-containing deposition precursors. For example, the flow rate ratio of the carrier gas to the nitrogen-containing and silicon-containing precursors may be about 30:1 or greater, about 40:1 or greater, about 50:1 or greater, about 60:1 or greater, about 70:1 or greater, or greater.

[0042]

[0045] In embodiments, the flow rate of one or more nitrogen-containing deposition precursors may be about 100 sccm or more, about 125 sccm or more, about 150 sccm or more, about 175 sccm or more, about 200 sccm or more, about 225 sccm or more, about 250 sccm or more, or more. In further embodiments, the flow rate of one or more silicon-containing deposition precursors may be about 100 sccm or less, about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, about 40 sccm or less, or less. In further embodiments, the flow rate of the carrier gas may be about 8000 sccm or more, about 9000 sccm or more, about 10,000 sccm or more, about 11,000 sccm or more, about 12,000 sccm or more, or more. In additional embodiments, the inflow of deposition precursors into the substrate processing chamber may increase the pressure in the chamber. In embodiments, the pressure in the substrate chamber while the deposition precursor flows may be characterized as about 1 Torr or more, about 2 Torr or more, about 3 Torr or more, about 4 Torr or more, about 5 Torr or more, about 6 Torr or more, about 7 Torr or more, or higher.

[0043]

[0046] Embodiments of processing method 200 may further include generating deposition plasma in the substrate processing region of processing chamber 210. The deposition plasma may be generated by supplying plasma power to a deposition precursor flowing into the substrate processing region. In some embodiments, the plasma power may be supplied by a radio frequency (RF) power source electrically connected to at least one electrode in the processing chamber. In embodiments, the RF power supply may power at least one electrode. This creates an electric field within the substrate processing region of the processing chamber, supplying energy to the deposition precursor and causing the deposition plasma to form. In further embodiments, the plasma power supplied to the deposition precursor may be about 60 watts or less, about 55 watts or less, about 50 watts or less, about 45 watts or less, about 40 watts or less, about 35 watts or less, about 30 watts or less, or less. In further embodiments, the frequency of the RF power supplied to the deposition precursor may be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power supplied to the deposition precursor may be continuously supplied, while in additional embodiments, the plasma power may be pulsed. In the pulsed embodiments, the supplied RF plasma power has a pulsed frequency which may be about 10 kHz or less, and may be about 9 kHz or less, about 8 kHz or less, about 7 kHz or less, about 6 kHz or less, about 5 kHz or less, about 4 kHz or less, about 3 kHz or less, about 2 kHz or less, about 1 kHz or less, or below. In some pulsed embodiments, the off portion of the duty cycle of the plasma power may allow for greater diffusion of plasma emitters in the silicon-nitrogen-containing material when deposited. In further embodiments, the longer the diffusion time of plasma emitters, the more uniformly the material may be formed when deposited.

[0044]

[0047] Embodiments of processing method 200 may further include depositing a silicon-nitrogen-containing material from a deposition plasma 215 onto a substrate in a substrate processing chamber. In some embodiments, the deposited silicon-nitrogen-containing material may be silicon nitride. In additional embodiments, the deposited silicon-nitrogen-containing material may be characterized by the amount of hydrogen incorporated. In embodiments, the amount of hydrogen incorporated into the deposited material may be about 5 atomic percent or more, about 6 atomic percent or more, about 7 atomic percent or more, about 8 atomic percent or more, about 9 atomic percent or more, about 10 atomic percent or more, or more. A large amount of hydrogen incorporated into the deposited silicon-nitrogen-containing material may contribute to the deposition of a low-stress material. In some embodiments, the deposited silicon-nitrogen-containing material may have tensile stresses of about 0.5 GPa or less, about 0.1 GPa or less, about 0.05 GPa or less, about 0.01 GPa or less, about -0.01 GPa or less, about -0.1 GPa or less, about -1 GPa or less, or less.

[0045]

[0048] In embodiments, the deposition of silicon-nitrogen-containing material on a substrate may be carried out at a deposition temperature that affects the deposition rate of the material. In additional embodiments, the semiconductor processing area of ​​the processing chamber may be characterized by a deposition temperature of about 550°C or less, about 500°C or less, about 475°C or less, about 450°C or less, about 425°C or less, about 400°C or less, about 375°C or less, about 350°C or less, or about 300°C or less, or lower. By depositing at a temperature of about 500°C or less, the technique can protect the thermal balance of the device compared to conventional high-temperature deposition. In further embodiments, the silicon-nitrogen-containing material may be deposited at a deposition rate of about 20 Å / sec or less, about 15 Å / sec or less, about 12 Å / sec or less, about 10 Å / sec or less, about 8 Å / sec or less, about 5 Å / sec or less, about 2 Å / sec or less, or lower.

[0046]

[0049] As will be further discussed below, embodiments of silicon-nitrogen-containing material deposition may include all of the material in the final silicon-nitrogen-containing layer, or a portion of the final silicon-nitrogen-containing layer less than the entire layer. In embodiments, the thickness of the silicon-nitrogen-containing material deposited on the substrate may be about 500 Å or less, about 400 Å or less, about 350 Å or less, about 300 Å or less, about 250 Å or less, about 200 Å or less, about 150 Å or less, about 100 Å or less, about 50 Å or less, about 40 Å or less, about 30 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, or less. In additional embodiments, the deposition process may take about 100 seconds or less, about 75 seconds or less, about 60 seconds or less, about 30 seconds or less, about 15 seconds or less, about 10 seconds or less, about 5 seconds or less, about 2 seconds or less, about 1 second or less, or less.

[0047]

[0050] Embodiments of the processing method 200 may additionally include introducing one or more processing precursors into the substrate processing area of ​​the substrate processing chamber 220. Embodiments of processing precursors may include nitrogen-containing precursors such as N2, and noble gas precursors such as helium, argon, and neon. In some embodiments, the processing precursors may not include helium. In additional embodiments, the processing precursors may include some or all of the carrier gases that were also used as deposited precursors. For example, embodiments include reducing or stopping the flow of nitrogen-containing and silicon-containing deposition precursors used during the deposition process while continuing to flow at least one of the carrier gases in the deposition precursors. In some embodiments, the flow rate of the carrier gases may increase during the transition from the deposition process to the processing process. In embodiments, the flow rate of the processing precursors into the substrate processing area of ​​the processing chamber may be about 20,000 sccm or more, about 22,500 sccm or more, about 25,000 sccm or more, about 27,500 sccm or more, about 30,000 sccm or more, or more. In additional embodiments, the treatment precursor may contain molecular nitrogen (N2) with a flow rate of about 15,000 sccm or more, about 16,000 sccm or more, about 17,000 sccm or more, about 18,000 sccm or more, about 19,000 sccm or more, about 20,000 sccm or more, or higher. Higher N2 flow rates may form additional Si-N bonds in the silicon-nitrogen-containing material. In embodiments, the number of Si-N bonds in the treated silicon-nitrogen-containing material may increase by about 1% or more, about 2% or more, about 3% or more, about 4% or more, about 5% or more, or higher compared to the material as it was deposited. In further embodiments, higher N2 flow rates may reduce the etching rate of the treated silicon-nitrogen-containing material. In embodiments, the etching rate of the N2-treated silicon-nitrogen-containing material can be reduced by about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 15% or more, or more, compared to the material as it was deposited.

[0048]

[0051] In many more embodiments, the treatment precursor may contain argon with a flow rate of about 3000 sccm or more, about 4000 sccm or more, about 5000 sccm or more, about 6000 sccm or more, about 7000 sccm or more, about 8000 sccm or more, or more. In embodiments, the etching rate of the argon-treated silicon-nitrogen-containing material may be reduced by about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 15% or more, or more, compared to the material as it was deposited.

[0049]

[0052] In additional embodiments, the inflow of the processing precursor into the substrate processing chamber can increase the pressure within the chamber. In some embodiments, the pressure within the processing chamber during the processing step can be greater than the pressure within the processing chamber during the deposition step. In embodiments, the pressure within the substrate chamber while the processing precursor is flowing can be characterized as about 3 Torr or more, about 4 Torr or more, about 5 Torr or more, about 6 Torr or more, about 7 Torr or more, about 8 Torr or more, about 9 Torr or more, about 10 Torr or more, or greater. In embodiments, an increase in chamber pressure can increase the stress on the processed silicon-nitrogen-containing material. In some embodiments, an increased chamber pressure can increase the stress on the processed silicon-nitrogen-containing material by about 2% or more, about 5% or more, about 10% or more, about 25% or more, about 50% or more, or greater than, compared to the material when deposited. In additional embodiments, an increased chamber pressure can also increase the etching rate of the processed silicon-nitrogen-containing material. In the embodiment, the increased chamber pressure can increase the etching rate in the treated silicon-nitrogen-containing material by about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 25% or more, or more, compared to the material as it was deposited.

[0050]

[0053] In embodiments, the flow rate of the treatment precursor is greater than the flow rate of the deposition precursor. For example, in embodiments where the treatment precursor contains one or more carrier gases in the deposition precursor, the flow rate of one or more carrier gases in the treatment precursor is greater than the flow rate of carrier gases in the deposition precursor. In embodiments, the flow rate ratio of the treatment precursor to the deposition precursor may be greater than 1:1, about 1.25:1 or greater, about 1.5:1 or greater, about 1.75:1 or greater, about 2:1 or greater, or greater. In embodiments where the precursor flow rate between the deposition and treatment processes is increased, the tensile stress in the treated silicon-nitrogen-containing layer may increase by a greater amount and in a shorter period of time than is observed in conventional deposition-treatment methods.

[0051]

[0054] Embodiments of processing method 200 may further include generating processing plasma in the substrate processing region of the processing chamber 225. Processing plasma may be generated by supplying plasma power to a processing precursor flowing into the substrate processing region. In some embodiments, processing plasma power may be supplied by the same source of radio frequency (RF) power used to supply deposition plasma power and through the same system electrodes. In additional embodiments, processing plasma power may be greater than the deposition plasma power supplying energy to the deposition plasma. In embodiments, processing plasma power may be greater than 60 watts, about 70 watts or more, about 80 watts or more, about 90 watts or more, about 100 watts or more, about 110 watts or more, about 120 watts or more, about 130 watts or more, about 140 watts or more, about 150 watts or more, or greater. Increasing plasma power may increase dissociation and the amount of radicals available for impact and distribution within the film. In further embodiments, the frequency of the RF power supplied to the processing precursor may be 13.56 MHz in one non-limiting example. In some embodiments, the plasma power supplied to the processing precursor may be supplied continuously, while in additional embodiments, the plasma power may be pulsed.

[0052]

[0055] In some embodiments, plasma power may be supplied as a continuous wave during the transition from deposition to treatment plasma. This can shorten the time of each dep-treat cycle for forming a silicon-nitrogen-containing layer with tensile stress. In embodiments where several dep-treat cycles are performed to complete layer formation, the cumulative reduction in treatment time may be significant. In further embodiments, increasing plasma power during the treatment process may also increase the tensile stress level in the fully formed silicon-nitrogen-containing layer.

[0053]

[0056] Embodiments of processing method 200 may further include processing the silicon-nitrogen-containing material deposited on a substrate in a substrate processing chamber with processing plasma 230. In some embodiments, the processing plasma exposure time may be about 1 second or more, about 2 seconds or more, about 5 seconds or more, about 10 seconds or more, about 15 seconds or more, about 30 seconds or more, about 45 seconds or more, about 60 seconds or more, or longer. In embodiments, the exposure time of the deposited silicon-nitrogen-containing material to the processing plasma may depend on the thickness of the material at the time of deposition. In additional embodiments, the exposure time may be about 0.1 seconds (0.1 sec / Å) or more per angstrom of deposited material. In further embodiments, the exposure time may be approximately 0.2 seconds / Å or longer, approximately 0.3 seconds / Å or longer, approximately 0.4 seconds / Å or longer, approximately 0.5 seconds / Å or longer, approximately 0.6 seconds / Å or longer, approximately 0.7 seconds / Å or longer, approximately 0.8 seconds / Å or longer, approximately 0.9 seconds / Å or longer, approximately 1 second / Å or longer, approximately 2 seconds / Å or longer, or longer.

[0054]

[0057] In embodiments, the processing of silicon-nitrogen-containing material on a substrate may be carried out at a processing temperature that affects the processing rate of the material. In additional embodiments, the semiconductor processing region of the processing chamber may be characterized by processing temperatures of about 550°C or less, about 500°C or less, about 475°C or less, about 450°C or less, about 425°C or less, about 400°C or less, about 375°C or less, about 350°C or less, or about 300°C or less, or below. In some embodiments, an increase in processing temperature may reduce the atomic proportion of hydrogen in the processed silicon-nitrogen-containing material. In embodiments, the atomic proportion of hydrogen in the processed silicon-nitrogen-containing material may decrease by about 1% or more, about 2.5% or more, about 5% or more, about 7.5% or more, about 10% or more, or more, compared to the material as it was deposited.

[0055]

[0058] In embodiments, the processing step can produce a tensile silicon-nitrogen-containing material. In further embodiments, the processed silicon-nitrogen-containing material may have a tensile stress of about 0.8 GPa or more, about 0.9 GPa or more, about 1 GPa or more, about 1.1 GPa or more, about 1.2 GPa or more, about 1.3 GPa or more, about 1.4 GPa or more, about 1.5 GPa or more, or higher. In embodiments, the processing step can also produce a processed silicon-nitrogen-containing material with a reduced level of incorporated hydrogen. In embodiments, the amount of incorporated hydrogen in the processed material may be about 3 atomic percent or less, 2 atomic percent or less, 1 atomic percent or less, 0.5 atomic percent or less, 0.2 atomic percent or less, 0.1 atomic percent or less, or lower. The reduced amount of incorporated hydrogen in the processed silicon-nitrogen-containing material may contribute to the deposition of material with increased tensile stress. In further embodiments, the reduced amount of incorporated hydrogen may also reduce the wet etching rate of the silicon-nitrogen-containing layer.

[0056]

[0059] In embodiments of this technology, plasma treatment of the deposited silicon-nitrogen-containing material in the deposition chamber eliminates the need to move the substrate to a UV treatment chamber and perform UV treatment on the material. By eliminating the UV treatment step, the complexity of the processing method and system for forming a tensile silicon-nitrogen-containing layer is reduced, and the processing time is shortened. These and other embodiments of this technology provide a faster, more productive, and more economical processing method and system for forming a tensile silicon-nitrogen-containing layer on a semiconductor substrate.

[0057]

[0060] The increased productivity achieved in embodiments of this technology may be a cumulative increase in embodiments in which the silicon-nitrogen-containing layer is formed in two or more cycles. These embodiments of the processing method 200 may further include forming a tensile silicon-nitrogen-containing layer in two or more cycles of depositing and processing the silicon-nitrogen-containing material. An additional cycle may begin by introducing an additional deposition precursor into the substrate processing area of ​​the substrate processing chamber, generating a deposition plasma from the deposition precursor 210, and depositing an additional portion of the silicon-nitrogen-containing material onto the substrate. An additional cycle may also include introducing one or more processing precursors into the substrate processing area of ​​the processing chamber, generating a processing plasma, and processing the deposited additional portion of the silicon-nitrogen-containing material to create an additional portion of the tensile silicon-nitrogen-containing layer.

[0058]

[0061] When a portion of the tensile silicon-nitrogen-containing layer is formed, it can be determined whether or not the formation of the tensile silicon-nitrogen-containing layer 235 is complete. If the portion of the tensile silicon-nitrogen-containing layer has completed its formation, the processing method can be terminated 240. If the portion of the tensile silicon-nitrogen-containing layer has not completed its formation, another cycle of depositing and processing the silicon-nitrogen-containing material can be started. In the embodiment, when the thickness of the layer reaches a thickness of approximately 50 Å or more, approximately 100 Å or more, approximately 150 Å or more, approximately 200 Å or more, approximately 250 Å or more, approximately 300 Å or more, approximately 400 Å or more, or greater, the tensile silicon-nitrogen-containing layer can be completely formed.

[0059]

[0062] Embodiments of the completed tensile silicon-nitrogen-containing layer produced by processing method 200 may include tensile stress levels of approximately 0.8 GPa or higher, approximately 0.9 GPa or higher, approximately 1 GPa or higher, approximately 1.1 GPa or higher, approximately 1.2 GPa or higher, approximately 1.3 GPa or higher, approximately 1.4 GPa or higher, approximately 1.5 GPa or higher, or higher. In additional embodiments, the completed tensile silicon-nitrogen-containing layer may have wet etching rates of approximately 20 Å / min or less, approximately 17.5 Å / min or less, approximately 15 Å / min or less, approximately 12.5 Å / min or less, approximately 10 Å / min or less, or lower. In embodiments, these properties of the tensile silicon-nitrogen-containing layer can make it an effective hard mask or silicon nitride etching stop layer that also provides support for forming precise openings in the adjacent patterning material. As described above, increasing the tensile stress of the nitride layer reduces the tendency for the adjacent patterning material to be etched at an uneven rate while openings are being formed in the material. As a result, the openings formed in the patterning material adjacent to the tensile nitride film are characterized by reduced line edge roughness (LER) and line width roughness (LWR) along the side walls of the openings, resulting in less overall roughness.

[0060]

[0063] Figures 3A and 3B show cross-sectional views of exemplary semiconductor structures 300 according to embodiments of the present technology. The embodiment of structure 300 includes a tensile silicon-nitrogen-containing layer 308 formed by the processing method and system according to embodiments of the present technology. In the embodiment shown in Figure 3A, structure 300 may also include a layer 302 of patterned photoresist material adjacent to a first layer 304 and a second layer 306 of patterned material. In the illustrated embodiment, the second layer 306 of patterned material is in direct contact with the tensile silicon-nitrogen-containing layer 308.

[0061]

[0064] In the embodiment of structure 300 shown in Figure 3A, a plurality of layers are shown on the opposite side of the tensile silicon-nitrogen-containing layer 308 from the patterned material layers 304 and 306. In the embodiment, these layers on the opposite side of layer 308 from the patterned material may include dielectric layers 310 that can be in direct contact with the tensile silicon-nitrogen-containing layer 308. The dielectric layer is characterized by a thickness of about 800 Å or more and may be characterized as a silicon-nitrogen-containing dielectric layer such as a silicon oxide layer. In a further embodiment, structure 300 may include a liner layer 312 adjacent to the dielectric layer 310. The liner layer 312 is characterized by a thickness of about 200 Å or more and may be a dense layer of dielectric material such as a silicon nitride layer deposited by atomic layer deposition. In a further embodiment, structure 300 may include a polysilicon layer 314 adjacent to the liner layer 312. The polysilicon layer is characterized by a thickness of approximately 900 Å or more and can act as a substrate for semiconductor device structures such as nMOS transistors (not shown).

[0062]

[0065] In the embodiment of structure 300 shown in Figure 3A, the patterned photoresist material 302 may be patterned to allow the formation of openings (not shown) in a first layer 304 and a second layer 306 of the patterned material. In the embodiment, these openings may extend through the first layer 304 of the patterned material. This layer may be a silicon-oxygen-carbon-containing layer characterized by a thickness of about 300 Å or more, which may be formed by a spin-on process. In a further embodiment, these openings may also extend through the second layer 306 of the patterned material. This layer may also be a silicon-oxygen-carbon-containing layer characterized by a thickness of about 500 Å or more, which may be formed by a chemical vapor deposition process. In an additional embodiment, a tensile silicon-nitrogen-containing layer 308 may function as an etching stop layer that can form the bottom side of the openings.

[0063]

[0066] Figure 3B shows another embodiment of structure 350 in which openings 316a-c are formed in the first layer 304 and the second layer 306 of the patterning material. These openings 316a-c may have sidewalls that are substantially perpendicular to the bottom side, including the exposed surface of the tensile silicon-nitrogen-containing layer 308. The sidewalls of the openings 316a-c may be characterized by line edge roughness having an average deviation of about 10 Å or less, about 5 Å or less, about 3 Å or less, about 1 Å or less, or less. The LER / LWR values ​​characterizing the sidewalls of the openings in embodiments of structure 350 may be at least 10% lower than the LER / LWR values ​​of openings formed in conventional structures with low-stress silicon nitride layers. The processing method and system of the present invention not only provide a tensile silicon-nitrogen-containing layer that does not require a time-consuming UV treatment process, but also provide semiconductor structures such as Structure 350 in which openings in the patterning material adjacent to the tensile silicon-nitrogen-containing layer are more precise and are characterized by a reduction in line edge roughness / line width roughness compared to openings formed in conventional structures.

[0064]

[0067] The above description provides numerous details for illustrative purposes to facilitate understanding of various embodiments of this technology. However, it will be apparent to those skilled in the art that certain embodiments can be implemented without some of these details, or with additional details.

[0065]

[0068] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the above description should not be construed as limiting the scope of the Art. Moreover, while methods or processes may be described sequentially or stepwise, it should be understood that actions may occur simultaneously or in an order different from that listed.

[0066]

[0069] Where a range of values ​​is given, unless explicitly stated otherwise in the context, each intervening value between the upper and lower limits of that range is understood to be specifically disclosed down to the smallest unit of the lower limit. This includes any narrower range between any stated or unstated intervening values ​​within the stated range, and any other stated or intervening values ​​within that stated range. The upper and lower limits of such narrower ranges may be individually included in or excluded from that range. Each range in which one, neither, or both of the limit values ​​are included is also included in the Art, provided that there are limit values ​​specifically excluded within the stated range. Where a stated range includes one or both of the limit values, it also includes ranges that exclude one or both of these included limit values.

[0067]

[0070] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” includes multiple such precursors, and “the layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0068]

[0071] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described feature, integer, component, or action, but not to exclude the presence or addition of one or more other features, integers, components, actions, activities, or groups.

Claims

1. A deposition gas containing a nitrogen-containing precursor, a silicon-containing precursor, and a carrier gas is introduced into the substrate processing area of ​​a substrate processing chamber, wherein the flow rate ratio of the nitrogen-containing precursor to the silicon-containing precursor is 1:1 or higher. In order to form a silicon-nitrogen-containing layer on the substrate in the substrate processing chamber, a deposition plasma is generated from the deposition gas, The silicon-nitrogen-containing layer is treated with a processing plasma, wherein the processing plasma is formed from a carrier gas that does not contain the silicon-containing precursor, and the flow rate of the carrier gas in the processing plasma is greater than the flow rate of the carrier gas in the deposition plasma. A semiconductor processing method, including the following.

2. The semiconductor processing method according to claim 1, wherein the nitrogen-containing precursor contains ammonia, and the ammonia has a flow rate of 100 sccm or more.

3. The semiconductor processing method according to claim 1, wherein the silicon-containing precursor contains silane, and the silane has a flow rate of 50 sccm or more.

4. The carrier gas is molecular nitrogen (N ２ The semiconductor processing method according to claim 1, comprising ) and argon, wherein the molecular nitrogen has a flow rate of 5000 sccm or more and the argon has a flow rate of 2000 sccm or more.

5. The semiconductor processing method according to claim 1, wherein the silicon-nitrogen-containing layer is formed at a deposition rate of 10 Å / second or less.

6. The semiconductor processing method according to claim 1, further comprising supplying plasma power of 60 watts or less to the deposition gas in order to generate the deposition plasma.

7. The semiconductor processing method according to claim 1, wherein the substrate processing chamber is characterized by a deposition chamber pressure during deposition of the silicon-nitrogen-containing layer that is lower than the processing chamber pressure during processing of the silicon-nitrogen-containing layer.

8. The semiconductor processing method according to claim 1, wherein the silicon-nitrogen-containing layer after processing includes a silicon nitride layer characterized by a tensile stress of 1 GPa or more and a wet etching rate of 20 Å / min or less.

9. The method involves depositing a silicon-nitrogen-containing layer on a substrate in the substrate processing region of a substrate processing chamber, wherein the silicon-nitrogen-containing layer is deposited using a deposition plasma generated from a deposition gas containing a nitrogen-containing precursor and a silicon-containing precursor, and the deposition plasma is formed with a first plasma power. The silicon-nitrogen-containing layer is treated with a processing plasma, wherein the processing plasma is formed with a second plasma power greater than the first plasma power, and the silicon-nitrogen-containing layer is characterized by a tensile stress of 1 GPa or more and a wet etching rate of 20 Å / min or less. A semiconductor processing method, including the following.

10. The semiconductor processing method according to claim 9, wherein the first plasma power is 60 watts or less, and the second plasma power is 100 watts or more.

11. The semiconductor processing method according to claim 9, wherein the silicon-nitrogen-containing layer includes a silicon nitride layer having a hydrogen level of 3 atomic percent or less.

12. The semiconductor processing method according to claim 9, wherein the processing plasma is formed from a processing gas that does not contain the silicon-containing precursor or the nitrogen-containing precursor.

13. The processing plasma contains molecular nitrogen (N ２ The semiconductor processing method according to claim 9, wherein the molecular nitrogen is formed from a processing gas containing ), and the molecular nitrogen is supplied to the substrate processing chamber at a nitrogen flow rate of 10,000 sccm or more.

14. The semiconductor processing method according to claim 9, wherein the silicon-nitrogen-containing layer is formed at a deposition rate of 10 Å / second or less.

15. Forming a silicon nitride layer A semiconductor processing method comprising, wherein the silicon nitride layer is A portion of a silicon nitride layer is deposited on a substrate in the substrate processing region of a substrate processing chamber, wherein the portion of the silicon nitride layer is deposited to a thickness of 15 Å or less. The process involves treating a portion of the silicon nitride layer with a processing plasma, wherein the processing plasma increases the tensile stress and wet etching rate of the treated portion of the silicon nitride layer compared to the portion when it was deposited, and the treated portion of the silicon nitride layer is characterized by a hydrogen level of 3 atomic percent or less. A semiconductor processing method formed by two or more cycles including [a specific component].

16. The semiconductor processing method according to claim 15, wherein the entire silicon nitride layer has a thickness of 300 Å or more.

17. The semiconductor processing method according to claim 15, wherein the portion of the silicon nitride layer is processed with the processing plasma for 15 seconds or less.

18. The semiconductor processing method according to claim 15, wherein the portion of the silicon nitride layer is deposited from a deposition plasma generated from a deposition gas supplied to the substrate processing chamber, the deposition gas comprises a nitrogen-containing precursor and a silicon-containing precursor, and further, the nitrogen-containing precursor has a flow rate of 200 sccm or less, and the silicon-containing precursor has a flow rate of less than 100 sccm.

19. The semiconductor processing method according to claim 15, wherein the portion of the silicon nitride layer is formed at a deposition rate of 10 Å / second or less.

20. The semiconductor processing method according to claim 15, wherein the entire silicon nitride layer is characterized by a tensile stress of 1 GPa or more and a wet etching rate of 20 Å / min or less.

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