Process integration to reduce contact resistance of semiconductor devices

Abstract

Provided herein is a method for forming a nanosheet field effect transistor (FET) device with reduced source / drain contact resistance. In some embodiments, the method for forming the FET device includes: etching a nanosheet stack of a nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions, the nanosheet stack including alternating layers of a nanosheet channel layer and a sacrificial nanosheet layer; depositing a silicide layer into the plurality of first source / drain regions at the ends of the nanosheet channel layer via a selective silicidation process to control the length of the nanosheet channel layer between the first source / drain regions; and performing a metal filling process to fill the plurality of first source / drain regions, the metal filling extending from the lowermost nanosheet channel layer to above the uppermost nanosheet channel layer, promoting the reduction of the source / drain contact resistance.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to semiconductor devices, and more particularly to nanosheet field effect transistor device structures.

Background Art

[0002] A transistor is often a circuit component or circuit element formed on a semiconductor device. Many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. An integrated circuit incorporates planar field-effect transistors (FETs), in which a current flows through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate. As device dimensions are shrinking, new device geometries, structures, and materials are facing the difficulty of maintaining switching speed without causing problems.

[0003] Some new technologies have emerged that enable chip designers to continue reducing the gate length. One particularly widespread technological change necessarily involves redesigning the structure of the FET from a planar device to a three-dimensional device, in which the semiconductor channel is replaced by fins that extend out from the plane of the substrate. In such devices, commonly referred to as FinFETs, the control gate surrounds three sides of the fin, thereby affecting the flow of current from three surfaces rather than one. The improved control achieved using 3D design results in faster switching performance and reduced leakage current.

[0004] The development of gate all-around FETs (GAA FETs) has extended the concept of FinFETs. In GAA FETs, the gate completely surrounds the channel, maximizing control over the current flowing through it. In GAA FETs, the channel can take the form of a cylindrical nanowire isolated from the substrate. Existing GAA FETs are horizontally oriented, and therefore the nanowires extend in a direction parallel to the surface of the semiconductor substrate.

[0005] The development of nanosheet FET devices has further extended the concept of FinFETs. Nanosheet FET devices are similar to the concept of cylindrical nanowires, except that the device channel comprises one or more nanosheet layers in a stacked configuration, and here, each nanosheet layer has a width substantially greater than the thickness of the nanosheet layer. Typical gate structures are formed above and below each nanosheet layer, and the increased width compared to nanowire structures facilitates an increase in drive current over a given footprint. However, as 3-D devices continue to shrink in size, the limited contact surface area between the source / drain regions and the corresponding metal contacts can lead to excessively high contact resistance in the source / drain regions of nanosheet device structures.

[0006] Accordingly, the inventors hereby provide embodiments of nanosheet FET devices having reduced source / drain contact resistance and methods for forming such devices. [Overview of the Initiative]

[0007] This specification provides a method for forming a nanosheet field-effect transistor (FET) device having reduced source / drain contact resistance. In some embodiments, the method for forming the FET device includes etching a nanosheet stack of a nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions, wherein the nanosheet stack comprises alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers; depositing silicon compound layers in the plurality of first source / drain regions at the sidewalls of the plurality of nanosheet channel layers via a selective siliconization process to control the channel length of the plurality of nanosheet channel layers between adjacent first source / drain regions; and carrying out a metal-filling process to fill the plurality of first source / drain regions, wherein the metal-filling process extends from the lowest nanosheet channel layer of the plurality of nanosheet channel layers to above the uppermost nanosheet channel layer of the plurality of nanosheet channel layers, thereby facilitating a reduction in source / drain contact resistance.

[0008] In some embodiments, a method for forming a nanosheet field-effect transistor (FET) device having reduced source / drain contact resistance involves forming a nanosheet stack on a substrate, wherein the nanosheet stack comprises alternating layers of nanosheet channel layers and sacrificial nanosheet layers; etching the nanosheet stack of the nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions; applying a hard mask over the plurality of second source / drain regions; depositing silicon compound layers within the plurality of first source / drain regions at the sidewalls of the nanosheet channel layers via a selective siliconization process to control the channel length of the nanosheet channel layers between the first source / drain regions; and performing a metal-filling process to fill the plurality of first source / drain regions. The present invention comprises: performing a metal-filling process in which the metal filler extends from the lowest nanosheet channel layer to above the uppermost nanosheet channel layer to facilitate a reduction in source / drain contact resistance; applying a hard mask over the metal filler in a plurality of first source / drain regions; depositing silicon compound layers in a plurality of second source / drain regions at the sidewalls of nanosheet channel layers exposed to the plurality of second source / drain regions via a selective siliconization process to control the length of the nanosheet channel layers between adjacent second source / drain regions; and performing a second metal-filling process to fill the plurality of second source / drain regions, in which the second metal-filler extends from the lowest nanosheet channel layer to above the uppermost nanosheet channel layer to facilitate a reduction in source / drain contact resistance.

[0009] In some embodiments, a nanosheet field-effect transistor (FET) device includes a nanosheet stack comprising a plurality of nanosheet channel layers, and a source / drain region in contact with the edge portions of the plurality of nanosheet channel layers, wherein the source / drain region is filled with a metal filler extending below the uppermost nanosheet channel layer among the plurality of nanosheet channel layers, and a silicon compound layer is disposed between the metal filler and the sidewalls of the plurality of nanosheet channel layers.

[0010] Other and further embodiments of this disclosure are described below.

[0011] The embodiments of this disclosure, briefly outlined above and discussed in more detail below, can be understood by referring to the exemplary embodiments of this disclosure depicted in the accompanying drawings. However, since this disclosure may also allow for other equally effective embodiments, the accompanying drawings illustrate only typical embodiments of this disclosure and should therefore not be considered limiting in scope. [Brief explanation of the drawing]

[0012] [Figure 1] This flowchart shows a method for forming a nanosheet field-effect transistor (FET) device according to at least some embodiments of the present disclosure. [Figure 2] This is a schematic isometric view showing a nanosheet FET device with multiple source / drain regions. [Figure 3] This is a cross-sectional view showing a portion of a nanosheet FET device according to at least some embodiments of the present disclosure. [Figure 4] This is a cross-sectional view showing a portion of a nanosheet FET device according to at least some embodiments of the present disclosure. [Modes for carrying out the invention]

[0013] For ease of understanding, the same reference numerals are used where possible to specify identical elements common to the figures. The figures are not drawn to exact scale and may be simplified for clarity. Elements and features of one embodiment may be usefully incorporated into other embodiments without further mention.

[0014] This specification provides embodiments of nanosheet FET devices having reduced source / drain contact resistance and methods for forming such devices. The methods provided herein increase the contact area between the source / drain regions of the nanosheet FET device and their respective metal contacts, and advantageously reduce the contact resistance between the source / drain regions of the nanosheet FET device and their respective metal contacts, thereby improving the performance of the device. The methods provided herein further advantageously facilitate the adjustment of the channel length via controlled deposition techniques to optimize the performance of the device.

[0015] Figure 1 shows a flowchart of a method for forming a nanosheet field-effect transistor (FET) device having reduced source / drain contact resistance according to at least some embodiments of the present disclosure. In 102, method 100 comprises forming a nanosheet stack on a substrate (e.g., substrate 218), the nanosheet stack comprising alternating layers of nanosheet channel layers (e.g., a plurality of nanosheet channel layers 206) and sacrificial nanosheet layers (e.g., a plurality of sacrificial nanosheet layers 212). The nanosheet stack of the nanosheet FET device may be etched to form trenches (e.g., trenches 304) defining a plurality of first source / drain regions (e.g., a plurality of first source / drain regions 202) and a plurality of second source / drain regions (e.g., a plurality of second source / drain regions 204). The etching process may be anisotropic dry etching, wet etching, or other suitable etching process. In some embodiments, the etching process etches the exposed portions of the nanosheet stack perpendicular to the substrate. In some embodiments, the etching process vertically etches the exposed portions of the nanosheet stack and a portion of the substrate, in other words, etching the lower part of the upper surface of the substrate.

[0016] In 104, method 100 optionally includes adding a hard mask (e.g., hard mask 238) on top of a plurality of second source / drain regions. In some embodiments, the hard mask is deposited on top of the plurality of second source / drain regions before any deposition or filling process is carried out in the plurality of first source / drain regions, such as depositing silicon compound layers in the plurality of first source / drain regions. In some embodiments, method 100 includes forming inner spacers (e.g., inner spacers 226) in the plurality of first source / drain regions adjacent to the plurality of nanosheet channel layers. In some embodiments, the spacers are formed of a dielectric material, such as silicon nitride (SiN) or any suitable dielectric material.

[0017] For example, Figure 2 shows a schematic isometric view of a nanosheet FET device or device 200 having multiple source / drain regions according to at least some embodiments of the present disclosure. In some embodiments, the multiple source / drain regions 201 may generally include multiple first source / drain regions 202 and multiple second source / drain regions 204. In some embodiments, the multiple first source / drain regions 202 correspond to p-channel metal-oxide semiconductor (pMOS) areas of device 200. In some embodiments, the multiple second source / drain regions 204 correspond to n-channel metal-oxide semiconductor (nMOS) areas of device 200. Figure 1 shows the multiple second source / drain regions 204 filled with material and covered with a hard mask 238, and the multiple first source / drain regions 202 in an unfilled intermediate step, ready for the subsequent deposition and packing processes. Multiple first source / drain regions 202 and multiple second source / drain regions 204 may be separated by an insulating layer 230 containing a low-K dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonite (SiOCN), or silicon oxycarbide (SiOC). A gate region 242 may be located above the multiple source / drain regions 201.

[0018] The device 200 generally comprises a plurality of nanosheet channel layers 206 alternating with a plurality of sacrificial nanosheet layers 212 deposited or disposed on a substrate 218 (e.g., a stacked configuration or stacked layers). In some embodiments, the plurality of nanosheet channel layers 206 have a thickness of about 5 nanometers to about 15 nanometers per layer. In some embodiments, the plurality of sacrificial nanosheet layers 212 have a thickness of about 5 nanometers to about 15 nanometers per layer. In some embodiments, the substrate 218 may be a semiconductor substrate formed of silicon (Si), silicon germanium (SiGe), or any other suitable semiconductor substrate material. In some embodiments, the plurality of nanosheet channel layers 206 include exactly three channel layers, which are stacked, a first channel layer 220, a second channel layer 222, and a third channel layer 224, separated by layers of the plurality of sacrificial nanosheet layers 212. However, the device 200 may also include more or fewer nanosheet channel layers than three. In some embodiments, multiple nanosheet channel layers 206 and multiple sacrificial nanosheet layers 212 are grown alternately and sequentially via an epitaxial growth process.

[0019] In some embodiments, the plurality of nanosheet channel layers 206 are substantially made of silicon (Si), and the plurality of sacrificial nanosheet layers 212 are substantially made of silicon germanium (SiGe) having a desired Ge concentration. In some embodiments, the plurality of nanosheet channel layers 206 are substantially made of silicon germanium (SiGe) having a desired Ge concentration, and the plurality of sacrificial nanosheet layers 212 are substantially made of silicon (Si). In some embodiments, the desired Ge concentration is from about 15 volume percent to about 40 volume percent. In some embodiments, the plurality of nanosheet channel layers 206 and the plurality of sacrificial nanosheet layers 212 include a single-crystal semiconductor material, such as single-crystal silicon. In some embodiments, the plurality of sacrificial nanosheet layers 212 are then etched away in a manner selective to the material of the plurality of nanosheet channel layers 206, freeing up the plurality of nanosheet channel layers 206 for subsequent metal filling. The plurality of first source / drain regions 202 may include inner spacers 226 adjacent to the plurality of sacrificial nanosheet layers 212.

[0020] Referring again to Figure 1, in 106, Method 100 includes depositing silicon compound layers (e.g., silicon compound layer 322) within a plurality of first source / drain regions at the edges of the nanosheet channel layers via a selective siliconization process to control the length of the nanosheet channel layer between the first source / drain regions. The silicon compound layers function as contacts for the first source / drain regions and further as a material that reduces contact resistance. In some embodiments, the silicon compound layers include at least one of titanium, nickel, palladium, ruthenium, molybdenum, platinum, osmium, or iridium. In some embodiments, the silicon compound layers include titanium silicide for the nMOS area and molybdenum or ruthenium for the pMOS area.

[0021] In some embodiments, as depicted in Figure 3, before depositing silicon compound layers in a plurality of first source / drain regions, Method 100 includes performing a controlled epitaxial growth process to deposit silicon or silicon germanium on the exposed sidewalls (e.g., sidewall 350) of the nanosheet channel layer, and further, to partially fill the plurality of second source / drain regions before depositing silicon compound layers in the plurality of second source / drain regions. In some embodiments, the controlled epitaxial growth process advantageously forms gaps (e.g., gaps 344) between the opposing sidewalls of the nanosheet channel layer to prevent epitaxial integration in the plurality of first source / drain regions. The silicon compound layer is deposited on the epitaxial growth layer (e.g., epitaxial material 306). The channel length 318 of the device 200 extending between adjacent metal fillers (e.g., metal filler 310) can be advantageously controlled by controlling the thickness of the epitaxial material deposited on the exposed nanosheet channel layer and by controlling the thickness of the silicon compound layer.

[0022] Figure 3 shows a cross-sectional view of a portion of a nanosheet FET device 200 according to at least some embodiments of the present disclosure. Each of a plurality of first source / drain regions 202 may be defined by a trench 304. In some embodiments, an inner spacer 226 may be formed in or adjacent to the trench 304 by a process of laterally removing material from the sidewalls of a plurality of sacrificial nanosheet layers 212, so that the sidewalls 334 of the plurality of sacrificial nanosheet layers 212 are recessed relative to the sidewalls 350 of the plurality of nanosheet channel layers 206 adjacent to the plurality of first source / drain regions 202. For example, this lateral etching may be carried out using a wet etching process or dry plasma etching with an etching solution that selectively etches the plurality of sacrificial nanosheet layers 212 with respect to the material of the plurality of nanosheet channel layers 206. The size of the lateral recess may be controlled through timed etching. In some embodiments, a dielectric material may be selectively deposited in the lateral recess to form the inner spacer 226. In some embodiments, conformal layers of dielectric material may be deposited within a plurality of first source / drain regions 202, including recesses, which are then etched again to remove excess material. In some embodiments, the width of the recesses is substantially equal to the thickness of the inner spacer 226.

[0023] In some embodiments, multiple nanosheet channel layers 206 can be isolated from gate electrodes 348 deposited above the multiple nanosheet channel layers 206 via their respective upper spacers 320. In some embodiments, the upper spacers 320 are formed from the same material as the inner spacers 226. In some embodiments, conformal layers of dielectric material can form both the inner spacers 226 and the upper spacers 320.

[0024] In some embodiments, the epitaxial material 306 grows and extends from the sidewalls 350 of the plurality of nanosheet channel layers 206, such as, for example, the first channel layer 220, the second channel layer 222, and the third channel layer 224. The epitaxial material 306 can similarly grow from the bottom surface 338 of the trench 304. In some embodiments, the epitaxial material 306 grows from the bottom surface 338 to a position directly below the uppermost nanosheet channel layer among the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 grows from the bottom surface 338 to a position directly below the lowermost nanosheet channel layer among the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 growing from the sidewalls 350 of the plurality of nanosheet channel layers 206 forms a bulbous shape. In some embodiments, the epitaxial material 306 adjacent to one of the nanosheet channel layers 206 among the plurality of nanosheet channel layers 206 is not integrated with the epitaxial material 306 extending from any of the remaining channels of the plurality of nanosheet channel layers 206. In some embodiments, the epitaxial material 306 can include epitaxial silicon (Si) or silicon germanium (SiGe) doped with a dopant suitable for forming an nMOS area or a pMOS area.

[0025] In some embodiments, a silicon compound layer 322 is deposited over the epitaxial material 306 and conforms to the epitaxial material 306. A metal fill 310 is disposed in the remaining portion of the trench 304 not occupied by one or more of the epitaxial material 306 and the silicon compound layer 322. The contact interface 380 between the metal fill 310 and the epitaxial material 306 or the silicon compound layer 322 is larger than a conventional interface, and advantageously, the contact resistance between the metal fill 310 and the epitaxial material 306 or the silicon compound layer 322 is reduced.

[0026] In some embodiments, the gate spacer 312 can be disposed around the metal fill 310 within the gate region 242. The gate spacer 312 can be made of a dielectric material. In some embodiments, a second gate spacer 314 is disposed between the gate spacer 312 and the gate electrode 348 to assist in adjusting the conductivity of the device 200. In some embodiments, the gate spacer 312 is made of a material different from that of the second gate spacer 314. In some embodiments, the gate spacer 312 is made of a low-K material and the second gate spacer 314 is made of a high-K material. In some embodiments, the second gate spacer 314 is consumed during processing and can create a larger volume for the gate electrode 348.

[0027] Figure 4 shows a cross-sectional view of a portion of a nanosheet FET device according to at least some embodiments of the present disclosure. In some embodiments, a silicon compound layer 408 is deposited or formed in the trench 304 directly on the lower surface 338 of the trench 304 and on the side walls 350 of the multiple nanosheet channel layers 206, without using the epitaxial material 306 discussed above in relation to Figure 3. In some embodiments, the silicon compound layer 408 has a thickness 410 greater than the thickness of the silicon compound layer 322. In some embodiments, the thickness is about 1 nanometer to about 4 nanometers. In some embodiments, the thickness 410 optimizes the performance of the device and, on the other hand, minimizes the short-channel effect. A metal filler 310 is disposed in the remaining portion of the trench 304 not occupied by the silicon compound layer 408. In some embodiments, the metal filler 310 extends below the multiple nanosheet channel layers 206. The channel length 420 can include the length of each of the multiple nanosheet channel layers 206, and in addition, the thickness 410 of the silicon compound layer 408 at both ends of each layer. The channel length 420 can be controlled by controlling the thickness 410 to tune the device 200 for optimal performance. In some embodiments, the channel length of the device 200 is about 10 nanometers to about 15 nanometers. The contact interface 480 between the metal filler 310 and the silicon compound layer 408 is larger than that of conventional interfaces, which is advantageous in that it reduces the contact resistance between the metal filler 310 and the silicon compound layer 408. The device in Figure 4 further advantageously does not require a source / drain injection and activation step, reducing cost and thermal budget.

[0028] Referring again to Figure 1, in 108, Method 100 includes performing a metal-filling process to fill a plurality of first source / drain regions, where the metal filler (e.g., metal filler 310) extends from the lowest nanosheet channel layer (e.g., third channel layer 224) to above the uppermost nanosheet channel layer (e.g., first channel layer 220), thereby facilitating a reduction in source / drain contact resistance. The metal filler reduces the epitaxial material (e.g., epitaxial material 306) disposed within the source / drain regions, thereby reducing epitaxial strain. However, the benefits of the reduced source / drain contact resistance through the metal-filling process described herein can also offset the drawback of the reduced epitaxial strain. In some embodiments, Method 100 includes adjusting the metal filler to improve channel stress and compensate for any performance loss due to the reduced epitaxial strain.

[0029] In some embodiments, Method 100 includes applying a hard mask over metal fillers in a plurality of first source / drain regions. In some embodiments, Method 100 includes performing similar process steps for a plurality of second source / drain regions after applying a hard mask over metal fillers in a plurality of first source / drain regions. For example, in some embodiments, the Method includes performing a controlled epitaxial growth process to deposit silicon or silicon germanium on the exposed sidewalls of nanosheet channel layers in a plurality of second source / drain regions, and further to partially fill the plurality of second source / drain regions. In some embodiments, silicon compound layers are deposited in a plurality of second source / drain regions, and then metal filling is performed. In some embodiments, the second metal filler extends from the lowest nanosheet channel layer to above the uppermost nanosheet channel layer to facilitate a reduction in source / drain contact resistance. In some embodiments, an inner spacer is formed in a plurality of second source / drain regions before the silicon compound layers are deposited in the plurality of second source / drain regions. In some embodiments, after the filling process of this method, an appropriate middle end-of-line (MEOL) process or back end-of-line (BEOL) process may be performed on the device 200.

[0030] While the foregoing applies to embodiments of the present disclosure, other and further forms of the present disclosure can be devised without departing from the fundamental scope of the present disclosure. For ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in the accompanying drawings. Any such layers, structures, and / or regions not explicitly shown may be present in actual semiconductor device structures. Furthermore, with respect to semiconductor processing techniques, the descriptions provided herein are not intended to encompass all processing procedures that may be required to form a functional semiconductor integrated circuit device.

Claims

1. A method for forming a nanosheet field-effect transistor (FET) device having reduced source / drain contact resistance, Etching a nanosheet stack of a nanosheet FET device to form a plurality of first source / drain regions and a plurality of second source / drain regions, wherein the nanosheet stack comprises alternating layers of a plurality of nanosheet channel layers and a plurality of sacrificial nanosheet layers. To control the channel length of the plurality of nanosheet channel layers between adjacent first source / drain regions, a silicon compound layer is deposited in the plurality of first source / drain regions at the sidewalls of the plurality of nanosheet channel layers via a selective siliconization process, The process includes carrying out a metal-filling process for filling the plurality of first source / drain regions, wherein the metal filler of the metal-filling process extends from the lowest nanosheet channel layer of the plurality of nanosheet channel layers to above the uppermost nanosheet channel layer of the plurality of nanosheet channel layers, thereby promoting a reduction in the source / drain contact resistance. A method in which the silicon compound layer is deposited or formed directly on the lower surface of the plurality of first source / drain regions and directly on the side walls of the plurality of nanosheet channel layers.

2. The method according to claim 1, wherein the plurality of first source / drain regions correspond to the pMOS areas of the nanosheet FET device, and the plurality of second source / drain regions correspond to the nMOS areas of the nanosheet FET device.

3. The method according to claim 1, further comprising applying a hard mask over the plurality of second source / drain regions before depositing the silicon compound layer in the plurality of first source / drain regions.

4. The method according to claim 1, wherein the silicon compound layer comprises at least one of titanium, nickel, palladium, molybdenum, platinum, osmium, or iridium.

5. The method according to claim 1, wherein the nanosheet channel layer is made of silicon and the sacrificial nanosheet layer is made of silicon germanium.

6. A silicon compound layer is deposited on the sidewalls of the plurality of nanosheet channel layers disposed within the plurality of second source / drain regions via a selective siliconization process, The present invention relates to carrying out a second metal-filling process for filling the plurality of second source / drain regions, wherein the metal filler of the second metal-filling process extends from the lowest nanosheet channel layer to above the uppermost nanosheet channel layer, thereby promoting a reduction in the source / drain contact resistance. The method according to claim 1, further comprising:

7. The method according to claim 6, further comprising carrying out a controlled epitaxial growth process to deposit silicon or silicon germanium on the exposed sidewalls of the plurality of nanosheet channel layers disposed within the plurality of second source / drain regions, before depositing the silicon compound layer within the plurality of second source / drain regions, and further to partially fill the plurality of second source / drain regions.

8. Forming the nanosheet stack on the substrate before etching the nanosheet stack, Applying a hard mask over the plurality of second source / drain regions before performing the metal filling process to fill the plurality of first source / drain regions, Applying a hard mask over the metal filler in the plurality of first source / drain regions, In order to form a lateral recess, the sacrificial nanosheet layer is etched laterally, By selectively depositing material in the lateral recesses of the sacrificial nanosheet layer in the plurality of second source / drain regions, a spacer is formed. To control the length of the nanosheet channel layer between adjacent second source / drain regions, after forming the spacer, a silicon compound layer is deposited in the plurality of second source / drain regions at the sidewalls of the nanosheet channel layer exposed to the plurality of second source / drain regions via a selective siliconization process, The present invention relates to carrying out a second metal-filling process for filling the plurality of second source / drain regions, wherein the metal filler of the second metal-filling process extends from the lowest nanosheet channel layer to above the uppermost nanosheet channel layer, thereby promoting a reduction in the source / drain contact resistance. The method according to claim 1, further comprising:

9. Before depositing the silicon compound layer in the plurality of second source / drain regions, a controlled epitaxial growth process is carried out to deposit silicon or silicon germanium on the exposed sidewalls of the nanosheet channel layer, and furthermore, to partially fill the plurality of second source / drain regions. The method according to claim 8, further comprising:

10. A nanosheet field-effect transistor (FET) device, A nanosheet stack comprising multiple nanosheet channel layers, A source / drain region in contact with the end portions of the plurality of nanosheet channel layers, wherein the source / drain region is filled with a metal filler extending below the uppermost nanosheet channel layer among the plurality of nanosheet channel layers, and a silicon compound layer is disposed between the metal filler and the side walls of the plurality of nanosheet channel layers, Equipped with, The silicon compound layer is deposited or formed directly on the lower surface of the source / drain region and directly on the side walls of the plurality of nanosheet channel layers. Nanosheet field-effect transistor (FET) device.

11. The nanosheet FET device according to claim 10, wherein the silicon compound layer has a thickness of about 1 nanometer to about 4 nanometers.

12. The nanosheet FET device according to claim 10, wherein the plurality of nanosheet channel layers include exactly three stacked layers.

13. The nanosheet FET device according to claim 10, wherein the channel length of the nanosheet FET device is approximately 10 nanometers to approximately 15 nanometers.

14. The nanosheet FET device according to claim 10, wherein the silicon compound layer comprises at least one of titanium, nickel, palladium, molybdenum, platinum, osmium, or iridium.

15. The nanosheet FET device according to claim 10, wherein the plurality of nanosheet channel layers are made of single-crystal silicon.

Images